CA1255782A - Microprocessor controlled circuit breaker trip unit - Google Patents
Microprocessor controlled circuit breaker trip unitInfo
- Publication number
- CA1255782A CA1255782A CA000491504A CA491504A CA1255782A CA 1255782 A CA1255782 A CA 1255782A CA 000491504 A CA000491504 A CA 000491504A CA 491504 A CA491504 A CA 491504A CA 1255782 A CA1255782 A CA 1255782A
- Authority
- CA
- Canada
- Prior art keywords
- current
- circuit
- circuit breaker
- trip
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/093—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means
- H02H3/0935—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means the timing being determined by numerical means
Abstract
MICROPROCESSOR CONTROLLED CIRCUIT
BREAKER TRIP UNIT
ABSTRACT OF THE DISCLOSURE
A microprocessor based trip unit for a circuit breaker is disclosed. The instantaneous current magnitudes in each phase and in the neutral of the circuit being pro-tected are simultaneously and sequentially sampled by re-spective sample and hold circuits. The measured values are then applied to a respective analog-to-digital converter and the digitized values are sequentially applied to a microprocessor. The microprocessor calculates true RMS
current and sums the signals of all phases and neutral to determine presence and magnitude of a ground fault current.
To permit use of an 8-bit microprocessor, while maintaining high resolution of measured current over a large range, novel automatic scale adjustment is provided. The memory of prior thermal history of the circuit breaker is provided electronically by a capacitor circuit which is discharged at a rate representative of the rate of cooling of the cir-cuit breaker. The output of he capacitor circuit is loaded into the microprocessor when the circuit breaker comes back onto the line after a prior opening operation. Any desired number of trip units can be remotely located from a switch-board frame containing a respective plurality of circuit breakers without local trip units.
BREAKER TRIP UNIT
ABSTRACT OF THE DISCLOSURE
A microprocessor based trip unit for a circuit breaker is disclosed. The instantaneous current magnitudes in each phase and in the neutral of the circuit being pro-tected are simultaneously and sequentially sampled by re-spective sample and hold circuits. The measured values are then applied to a respective analog-to-digital converter and the digitized values are sequentially applied to a microprocessor. The microprocessor calculates true RMS
current and sums the signals of all phases and neutral to determine presence and magnitude of a ground fault current.
To permit use of an 8-bit microprocessor, while maintaining high resolution of measured current over a large range, novel automatic scale adjustment is provided. The memory of prior thermal history of the circuit breaker is provided electronically by a capacitor circuit which is discharged at a rate representative of the rate of cooling of the cir-cuit breaker. The output of he capacitor circuit is loaded into the microprocessor when the circuit breaker comes back onto the line after a prior opening operation. Any desired number of trip units can be remotely located from a switch-board frame containing a respective plurality of circuit breakers without local trip units.
Description
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, MICROPROCESSOR CON~ROLLED CIRCUI~
_ _ BREAKER ~RIP UNI~
BACKGROUND OF ~HE INVEN~ION
~his invention relates to a trip unit for a cir-cuit breaker and more specifically relates to a micropro-cessor-based trip unit.
~rip units for circuit breakers are used to auto-matically operate the circuit breaker under fault current conditions. rhe time required for the circuit breaker to open will depend on the fault current magnitude and nature.
~rip units, for many years, employed a bimetal member which responded in a predetermined manner to relatively low fault current and an electromagnetic trip member which responded to higher fault current magnitudes.
~ rip units which employ digital electronic cir-cuits and microprocessors to simulate the behavior of bi-metal and electromagnetic trip units are also known. ~rip units of these types are typically shown, for e~ample, in U.S. Patents 4,423,459, dated December 27, 1983, in the name of Frederick A. Stich and Conrad F. Williams; and 4,338,647, dated July 6, 1982, in the name of Wilson et al.
Digital and microprocessor based trip units of the prior art use combinations of analog and digital circuitry.
~he units, however, do not perform a true RMS load current measurement, and require additional circuits and transfor-mer components to perform ground~ fault current analysis.
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~oreover, prior units have limited accuracy over the full current measurement range and do not take accurate account of the prior thermal history of the circuit breaker.
Prior art current sensing systems for electronic trip units employ a current transformer in each phase and in the neutral, if a neutral is used. ~he current trans-former outputs are applied to respective full-wave, bridge-connected rectifiers. ~he rectif~ed output of each line is ttlen filtered and applied to a level detection circuit~
rhe measured peak level is then scaled to 0.707 to produce an output which, supposedly, is related to the RMS current of each respective line. A signal related to the measured RMS current is then applied to timing circuits which cause circuit breaker tripping when measured current of a given magnitude e~ists for given times.
A major problem in prior art electronic trip units is that the RMS current measured is correct only if the current wave shapes measured are perfect sine waves. If tbe wave shape is non-sinusoidal, the scali~g factor is wrong. For example, in circuits having appreciable line capacitance, such as inverter drives, the current wave shape contains substantial distortion from the sinusoidal shape. In circuits containing transformers, a third har-monic component is present in the wave ~hape, making it ~5 non-sinusoidal. Other sources of distortion of the current wave shape from the sinusoidal shape are well known. As a result of this inaccuracy, the circuit breaker may trip falsely and unnecessarily on too low a line current, or the circuit breaker may not trip when it should, because of the inaccurate measurement.
Circuits are known, which correct the above inac-curate measurement. For example, the output of the measur-ing current transformer can be connected to a resistor and the temperature of the resistor can be measured, to obtain a true RMS reading. Such a system is expensive and re-~ ~Z .) 5 ~
sponds too slowly to current changes to be use~ul for elec-tronic trip units.
Commercially available semiconductor chips exist which produce an RMS output. Such chips, ho~ever, are too expensiYe for use in electronic trip units for circuit brea~ers.
Sampling systems are also known, in which the in-stantaneous amplitude of a wave is periodically measured.
By measuring a sufficient number of samples each cycle and s4uaring the value of each sample, and then summing and taking the square root of the sum of the squares, the RMS
measurement can be obtained, its accuracy increasing with the number of samples taken. ~he effective number of sam-ples can be increased by phase shifting the beginning of the measuring point for each sample in each subsequent half cycle. Suc.h asynchronous sampling can be used to obtain the RMS value of any periodic wave shape. However, when this technique is applied to electronic trip units, the circuits become comple~ and e~pensive, since the measure-ment must be made separately for each of the phases and the neutral, if a neutral is provided.
As will be seen, the present invention provides a simple and inexpensive circuit for true RMS current mea-surement.
Another problem with e~isting electronic trip units is that they require intermediate current transfor-mers for each phase and for the neutral circuit. ~ypic-ally, these transformers are connected in wye, and are needed to produce a ground fault signal. Such current transformers are expensive and occupy considerable volume in the control housing.
As will be seen, the need for such separate inter-mediate transformers is eliminated by the present invention.
Another problem with prior art microprocessor based systems is that measurement resolution is poor, ~ ~ ~ss~
! RMD-1268 ~ - 4 -c'r~ , re4uiring relatively large microprocessors. By way of ecample, it is desirable to use an 8-bit microprocessor because of lts low cost. lf, ho~ever, it is desired to be ~ I able to discriminate currents from one-fourth full load .~ I S (for grouad fault detection) to ten times full load current, tùe current range is 1 to 40. If full load current is 600 <~ ¦ amperes, the difference between ten times full load current anq one-fourth full load current is (6,000-150) = 5850 am-~eres. An 8-bit microprocessor provides 256 unique 8 bit combinations. Thus, the individual steps are: 6,000l256 =
23.4~ amperes. This provides a resolution of abo~t 23.44A/
lSOA = 16~ where the 150 amperes is 25~ of 600 amperes.
However, 8 resolution of abou, 5~ or less is desired.
Therefore, a simple 8-bit microprocessor cannot be used, lS ~hile still having appropriate resolution.
As wlll be later seen, the invention provides a no~el automatic scale adjustment to permit requisite accu-racy, while using an 8-bit microprocessor.
~ A furtber problem with escisting digital circuits .. ~ 20 is in the means for providing thermal memory. Thus, in a .~ standard circuit breaker trip unlt, the history of prior heating of the breaker due to prior lnterruption operation, or prior heating caused by closlng on capaciti~e loads, and the like, stays with the brea`.cer. In prior art digital ~,-9 25 Systems, the effect of the thermal his~ory of the breaker was lost after the breaker opens. As ~ill be seen, the ~` ~ present inventlon provides circuit means for retaining thermal memory.
Still another problem in e~isting trip systems is that the trlp ~inding of the magnetlc latch of tbe clrcuit ~ breaker has a large number o turns and thus high lnduc-;` ~ tance. Therefore~ it is hard to dellver a trip slgnal rap-' ~ ~ idly to the coil because the trip circuit Uith the coil has a lar~e time constant. Accordlngly, ~hen the breaker is oyera~ed ~lth very high speed currcnt llmiting breakers, it ~, _ ~ ~s hard to coordinate the pert'ormance of the breakrrs.
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-- s BRI EF DESCRIP~ION OF ~HE INVEN~ION
In accordance with the present invention, a novel microprocessor based trip unit is provided, which employs, as maJor components, a power supply, a sample and hold cir-cuit for each line, an analog-to-digital converter, a mi-croprocessor, and configuration switches for setting the adjustment parameters of the trip unit. ~he circuit is applicable to both three and four wire systems. Opening of the circuit breaker is accomplished by a conventional mech-anical mechanism which is activated by an electromagneticlatching mechanism triggered by the electronic trip unit.
~ he po~er supply provides full-~ave, rectified current from the three phase lines and neutral. It then generates a ~5 volt power source for all logic circuits, and also produces a positive reference voltage for the an-alo~-to-digital (A/D) converter. ~he positive reference voltage is either +l volt or ~5 volts, depending on the state of a control si~nal from the microcomputer. ~he power supply is capable of delivering 25 milliamperes when the line current is only 25% of its rated load current, which rated current may, for e~ample, be 600 amperes.
Signals representative of the line and neutral current are derived from the lines by the same current transformers, and are converted to voltage waveforms, using ~5 high precision resistors. ~he signal values are inverted and are in the range of O to +5 volts, with +5 volts repre-senting 20 times the frame rated current.
In accordance with one important aspect of this invention, all four signals (if a neutral is present) are sampled repetitively and simultaneously, and the sampled signals are used to charge respective capacitors. A sample is taken about every 1,500 microseconds (about ll samples/
cycle for a 60 Hz. line), and continues for about 100 cy-cles to produce about 1,100 samples for each RMS measure-ment cycle. Sequentially, the output of the sample and .. . .. . ..
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hold circuit for each line is read out into a single A/D
converter. ~he conversion to a digital value takes about 100 microseconds, using an 8-bit converter having an QCCU-racy of +1 least significant bit.
~he simultaneously sampled signals of each line are then sequentially applied to the microcomputer which, using a conventional program, calculates the true RMS cur-rent for each line.
~he microcomputer also uses the processed simulta-neously sampled signals to calculate a ground fault cur-rent. ~hat is, if the sum of ~he line and neu$ral currents is not zero, there must be a ground fault. Since signals of the three phases and neutral are simultaneously sampled, and accurate RUS values are available, ground ~ault current can be calculated from the information in the microcompu-ter.
In order to adjustably set the parameters of cur-rent rating, instantaneous trip current, ground fault pick-up current and ground fault delay time, respectlve e~ter-nally adjustable binary coded decimal switches are providedwhich can be addressed individually, and read by the micro-computer. Based on the settings of these switches, and the readings from the A/D converter, the microcomputer calcu-lates a time to trip the circuit breaker. If the current ~5 does not decrease, and the calculated time arrives, the microcomputer issues a trip signal.
From the above, it is seen that the novel system of the invention employs true RMS current measurement.
Moreover, ground fault current is accurately calculated in the microcomputer, since simult~neously measured line and neutral current values are available, eliminating the need for intermediate current transformers.
~ he system employs an 8-bit microprocessor, yet carries out these operations with high resolution by scale switching. ~hus, one current scale is used for currents less than, for example, one and a half times rated current.
If rated current is 600 amperes, over the gO0 ampere range, there are 900/256=3.52 amperes per bit. For a ground fault current of one-fourth rated current (150 amperes), the res-olution is 3.52/150=2.3X. It is, in fact, ~ 1.2% which isvery satisfactory resolution.
At currents greater than 900 amperes, current scale is dynamically switched so t~at, for ten times load current, the amperes per bit is 6,000/256, which yields the same minimum accuracy.
rhe novel trip unit of the present invention also has simulated thermal memory. rhe memory consists of ther-mistors fi~ed on the bus bars which act as the primary windings of the current transformer pick-ups for the sys-tem. rhe thermistors are negative temperature coefficient devices, and their resistance will be related to the amount of heat (I2t) stored in the circuit breaker. rheir resis-tance is thus used to preset the current level and time-out functions of the microprocessor.
Alternatively, the thermal memory may employ a capacitive storage circuit and a separate A/D converter channel. ~he heating effect on the circuit breaker due to high current is taken into account by charging the capaci-tor to a level related to the breaker energy (I2t). ~hen the b`reaker trips, the charge on the capacitor bleeds off at a rate related to the cooling rate of the breaker. When the breaker is again closed, the capacitor level is read through the A/D converter channel, and the value measured is used to preset the energy level and time-out functions of the microprocessor.
rhe magnetic latch of the circuit breaker using the trip unit of the invention has a novel split winding structure. rhus, present windings for trip latches have a large number of turns, for example, ~,500 turns of 40 gauge wire. rhis coil has high inductance so that the trip cir-cuit containing the coil has a long time constant, for ex-~s~
ample, 8 to 10 milliseconds. In many applications, for example, those using a current limiting breaker, the magnetic latch mus-t trip within 3 to 4 milliseconds. If the magnetic latch is too slow, the high speed current limiting breaker will trip before the magnetic latch reacts. The novel split winding of the invention provides a continuous magnetic latch winding with two sections, a 6,600 turn section and a 110 turn section. When high speed operation is called for, a high trip voltage is available. The large turn winding is then bypassed and sufficient current flows through the 110 turn section to provide enough ampere turns to trip the latch in a very short time.
A further feature of the invention is the use of an EPRO~ with the microprocessor with a switch for selecting certain predetermined trip characteristics which are applied to the main microprocessor.
Also provided for the breaker is a thermal override, such that the magnetic latch of the operating mechanism is released if the unit temperature exceeds 85C.
The novel trip unit of the invention can be packaged ~ compactly and housed with its respective circuit breaker.
Alternatively, the trip unit can be mounted remotely of the cir-cuit breaker. For example, for switchboard frames containing a plurality of circuit breakers, the circuit breaker trip units can be contained in a single control location with appropri-ate input and output lines interconnecting the breakers with their respective trip units. In arrangements such as this, the )S7B~
local trip units can share certain common parts, such as common power supplies, data processing and the like.
Thus, in accordance with a broad aspect of the invention, there is provided a microprocessor based circuit breaker trip unit comprising, in combination:
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said 1~ circuit breaker;
respective signal conversion means connected to said plur-ality of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetively and simultaneously sampling and holding sample analog values of each o~ said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produeed in said sample and hold circuit after said pre-~3 determined number of samples of a corresponding digitial value;
a microprocessor means coupled to each of said analog-to-digital converters for computing a true RMS value of the current of each of said line from said predetermined number of samples;
and an output circuit means connected between said micro-eomputer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions.
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In accordance with another broad aspect of the invention there is provided a microprocessor based circuit breaker trip unit comprising, in combination:
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective circuit breaker poles;
a trip mechanism energizable to open said circuit breaker poles;
respective signal conversion means connected to said plural-ity of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after each of said predetermined number of samples to a corresponding digital ~a value;
a microcomputer means coupled to each of said analog-to-digital converters for computing a true RMS value of the currents of each of said lines;
an output circuit means connected between said microcomputer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions; and -8b-:~S~7B;~
autoscaling circuit means connected -to said microcomputer for dividing a given current range into a first small range and a second larger range in values of amperes per bit of said microprocessor.
In accordance with another broad aspect of the invention there is provided a microprocessor based circuit breaker trip unit comprising, in combination:
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plura-lity of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after each of said predetermined number of samples to a corresponding digital value;
a microcomputer means coupled to each of said analog-to-digital converters for computing a true RMS value of the currents of each of said lines;
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said microcomputer includes means for computing ground fault current from the simultaneous samples of current in said lines;
an output circuit means connected between said microcomputer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions and;
autoscaling circuit means connected to said microcomputer for dividing a given current range into a first small range and a second larger range in values of amperes per bit of said microcomputer.
In accordance with another broad aspect of the invention there is provided a process for operating a trip unit of a multipole a-c circuit breaker which protects a circuit having a plurality of a-c lines; said process comprising the steps of producing a current signal for each of said lines which is proportional to the instantaneous current in said line; conver-ting each of said current signals to respective voltage signals which are proportional to said current signals; simultaneously, ~`.
and repetitively measuring the amplitudes of each of said voltage ~0 signals for relatively short sampling time; converting the ana-log value of the amplitudes of said voltage signal to a digital value; and separately calculating the true RMS value of each of said voltage signals by taking the square root of the sum of the s~uares of each of the digital values measured.
In accordance with another broad aspect of the invention there is provided a trip unit for a circuit breaker comprising, in combination:
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a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plurality of current transformers for converting the current output of said current transformers to respective voltage signals;
an output circuit means connected between said current trans~
formers and said trip mechanism for operating said trip mechanism in response to predetermined current conditions;
said trip mechanism including a magnetic latch and a semiconductor switching device; said magentic latch containing a latch operating winding which is connected in series with said semiconductor switching device;
said semiconductor switching device having a control electrode connected to said output circuit means to be switched into conduction in response to a given output from said output eireuit means;
said winding consisting of a series connected large turn, high resistance section and relatively low turn, relatively low resistance section; and bypass switching means connected from the node of said series connected sections to said semiconductor switching device whereby, when the output voltage in series with said winding and said switching device exceeds a given value, said bypass switehing devlce conducts and shortcircuits said large turn, -8e-~S5t7~;~
high resistance section.
In accordance with another broad aspect of the invention there is provided a method of operating a circuit breaker trip unit with the use of a microprocessor comprising the steps of:
providing said microprocessor with predetermined current data for said trip unit;
initiating a sample interval timer in said microprocessor upon the start or the sampling period to sequence the samples taken by a plurality of sample and hold circuits;
constantly determining the voltage of each sample and hold circuit at the end of each sample interval;
constantly providing the microprocessor with a digitally converted signal voltage and current samples unit the end of the sampling period;
repetitively storing the microprocessor the sampled current value for 1100 sample times to calculate the total current during the sampling period;
repetitively comparing in the microprocessor the sample time ~alculated with the root-mean-square equation and said elapsed time; and opening the circuit breaker trip unit when the calculated true RMS value indicates an occurrence of at least a predetermined current condition.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of the novel microprocessor implemented electronic trip unit of the present invention.
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Figures 2A and 2B together form a flow chart for the microprocessor of the block diagram of Figure 1.
Figures 3A, 3B, 3C and 3D are parts of an overall schematic diagram of the detailed circuit and microprocessor of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
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Referring to Figure 1, there is first schematically illustrated a three-phase a-c power line containing phases A,B and C and a neutral line N which may or may not be provided 1~ in the circuit. The circuit breaker 20 is schematically illus-trated as having four poles for the phases A,s, C and the neutral N, respectively. Circuit breaker 20 may be a conventional circuit breaker of relatively low voltage and having a rated current, for example, of 600 amperes. Obviously, any desired rating can be used for the circuit breaker. Circuit breaker 20 can be contained in metal insulated switchgear along with any desired number of other circuit breakers having the same and different ratings.
Circuit breaker 20 contains a trip mechanism 21 which ~a can be a conventional type of electromagnetic trip mechanism, operable in response to a current through the trip coil 22 of the trip mechanism 21. Trip coil 22 can be energized from a positive voltage supplied by rectifier device 34 upon the firing of a silicon controlled rectifier (SCR) 23 which is in series with the coil 22. Trip coil 22 can be the split coil of a magnetic latch, as will be later described. A thermal trip circuit 24 can also be provided to cause a switching action in parallel with SCR 23 1~Z55~7~3~
-9a-when the temperature of circuit breaker 20 exceeds some preset value, for example 85C.
The purpose of the present invention is to apply a trip signal to the gate electrode 25 of SCR 23 under certain eireuit eonditions in the circuit protected by the circuit breaker 20.
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Conventional current transformers 30, 31, 32 and 33 are provided on phases ~, B, C and neutral N, respec-tively. ~he outputs of these transformers arg applied to an appropriate rectifier device 3~ ~hich conventionallY
consists of respective single-phase full-wave bridge con-nected rectifier circuits for each of windings 30-33, re-spectively. rhis arrangement will be described later in more detail.
~he output of rectifier 34 is connected to po~er supply circuit 35. Power supply circuit 35 produes a 5-volt control power output for controlling components of the trip mechanism, as well as the logic circuit components to be later described. Power supply 35 also puts out a posi-tive 12 volts to the reference circuit 35A that supplies a voltage Vref which is adjustable, using Vref control, be-twèen at least two values, for e~ample 3.5 volts and .56 volt to the input +Vref of an analog to digital converter to be described. ~his circuit operates to switch the ref-erence voltage Vref to provide automatic scaling, as will later be described. Switchover can occur, for e~ample, at a measured current of 1.5 times the rated current of the circuit breaker 20. Switching the reference level produces an automatic scaling type operation, so that relatively high resolution in the measuring circuit is obtained at a low current scale region, making it possible to use 8-bit microprocessors with the requisite accuracy of current mea-surement at critical current levels.
~ he output of rectifier 34 is also applied through signal converter circuits 36 ~hich individually convert the output current signals of rectifier 34 to respective vol-tage signals. ~he output of signal converter circuits 36 are ~hen applied to the analog inverter 37 ~hich inverts their polarity from a negative to positive.
Each of the individual signals derived from lines A, B, C and N are then applied to a simultaneous sample-and-hold circuit 38. ~he simultaneous samp]e and hold circuit 38 takes a sample simultaneously from each of the outputs of current transformers 30-33 once every 1500 mi-croseconds, or 11 times in each cycle of a 60 Hz system.
At the time the simultaneous samples are taken, each signal A, B, C and N charges a respective capacitor to a voltage level representative of each respective instanta-neous phase current. ~he charge of each capacitor is then sampled sequentially and convqrted, by the analog to digi-tal converter 3g t to a digital value representative of the instantaneous current of that phase which is then sent to the microcomputer 41. ~he address and ~ecode circuit 40 coordinates this activity which is ultimately controlled by the microcomputer 41. Appro~imately every 100 cycles, the RMS current is computed arithmetically from these samples.
A data bus 42 interconnects the microcomputer 41 with the analog-to-digital converter 39 and with switch buffer circuits 43, which are, in turn, connected to four respective configuration switches for setting values of current rating, instantaneous trip, ground fault pickup and ground fault delay, respectively. Any desired number of configuration switches can be used, for a~y desired respec-tive parameters. ~hese switches are binary coded decimal switches which are located e~ternally of the control cir-cuits so that they can be easily manually adjusted. Also provided, as shown in Figure 1, is a crystal oscillator 45 and a switch address decoder circuit 46 connected between the microcomputer 41 and the switch buffers 43.
Also provided in Figure 1 is a thermal 0emory de-vice 50 which may be a thermistor or capacitive circuit.
When using a capacitive circuit, ~hich is charged just be~
fore tripping by the microcomputer 41 to a value represent-ative of the thermal condition of the circuit breaker, dis-charge circuit means are provided within device ~0, such that, when the circuit breaker is open and its parts cool, the capacitive or other structure within thermal memory ~S5~7~
device 50 is discharged or cools at the same rate. When the circuit breaker is reclosed, the output remaining in the thermal memory device 50 is read back into the system and all trip levels are appropriately adjusted to take into consideration the prior thermal history of the circuit breaker. When using thermistors for the thermal memory, they are preferably negative temperature devices mounted on the main bus bars within the circuit breaker, and are read by the microprocessor as described above.
Outputs from the milcrocomputer 41 include the +Vref 1~ control output, which is applied to reference circuit 35A in order to adjust the +Vref level to obtain the desired automatic scaling of the reference output.
A trip signal is derived from port 1 of the micro-computer 41, which is the trip signal to be applied to ~CR
23 under appropriate computed circumstances. A start A/D signal is also derivedfrom microcomputer 41, which signal is applied to the analog-to-digital converter 39 so that samples are taken from the simultaneous sample and hold circuits.
Figures 2A and 2B together form a flow chart for -the microcomputer of Figure 1. This same flow chart is applicable to the circuit of Figures 3A, 3B and 3C, which shall be later de-scribed.
The flow chart analysis may begin with the start at the right of Figure 2A. Following the start operation, the system is initialized, including initialization of timer memory, input/output ports and interrupts. Thereafter, the thermistor 1~5~
values in the thermal memory device 50 are read and the RMS
trip values are preset in accordance with the thermal history of the breaker as determined by the thermistor values. The set up switches connected to the switch buffers 43 are then read and the trip parameters appropriately set. Thereafter, the ports and status are set and the analog to digital converter 39 is started.
A measurement ist~en made as to whether the ground fault circuit is enabled. If not, a determination is made as to whether the RMS calculate instruction has been enabled. If not, a determination is made as to whether the reference voltage is at its high level. If not, a subroutine comes back to the determination of a ground fault enabling condition.
In the above sequence, if it was determined -that the ground fault was enabled, the flow chart moves to the second column to the left in Figure 2A and a determination is made of the largest phase current. From this is subtracted the current measured in the other two phases and the neutral current and the result is placed in storage. This is a ground fault current sample. Thereafter, a calculation is made of the ground fault average over 1/4 cycle and a decislon is then made as to whether the ground fault average current is less than the ground fault pick-up current.
If the ground fault average is less than the ground fault pick-up, the trip flags, which are displayed in the beginning, are cleared so that the circuit can continue in its operation as will be later described. If, however, the ~S5 ~ ~
ground fault average is found to be not less than ground fault pick-up the delay is calculated and a determination is made of whether the delay is greater than that of the counter.
If it is, the trip flags are immediately set. If not, the value is loaded into the timer circuit and the timer is started so that the trip flags will be set after a given length of time.
Returning to the right column of Figure 2A, starting with the start, it is noted that if it is found that the voltage reference is high, an output to numeral 3 is applied. This output is found in the lowermost righ-t hand column of Figure 2B
and it is seen that a determination is made as to whether all flags are clear. If they are, then it is possible to switch to the low voltage reference. If not, an output numeral 4 is pro-duced corresponding to the indicated location in the right hand column in Figure 2A.
Returning to the right column of the flow chart of Figure 2A, and the position where determination is made of whethe~r-^RMS calculation is enabled, if it is enabled, the flow chart proceeds in the central column of Figure 2A. Thus, for each phase, the microprocessor will square the sample measured add it to the sum and then increment the count. A determination is then made of whether the count is less than 256. If not, an RMS calculation is made in which the RMS value is divided by 256. It is then determined whether the reference voltage is high and, if so, high parameters are used, and if not, low voltage reference parameters are used.
Thereafter, a determination is made as to whether the l~S5~
RMS current measured is less than or equal to 115% of the full load current. If not, the over curren-t sum is made equal to the over current sum plus the RMS value minus the cooling factor and the trip flags are set. A decision is then made as to whether the over current sum is less than the sum RMS constant value. If not, the breaker is tripped and the sequence is ended. If the RMS value was found to be less than or equal to 115% of full load current, a determination is made as to whether the over current sum equals the over current sum minus the cooling factor.
mhereafter, the trip flags are cleared when the over current sum is equal to zero. In this condition, or if the over current sum is found less than an RMS current, there is an output to the central column of the chart, where a decision is made as to whether the reference is high and the flow chart proceeds as previously described.
When the breaker is tripped and the sequencing is ended, it will be noted that trip flags are also set. These same trip flags may be set by the interrupt service routine
, MICROPROCESSOR CON~ROLLED CIRCUI~
_ _ BREAKER ~RIP UNI~
BACKGROUND OF ~HE INVEN~ION
~his invention relates to a trip unit for a cir-cuit breaker and more specifically relates to a micropro-cessor-based trip unit.
~rip units for circuit breakers are used to auto-matically operate the circuit breaker under fault current conditions. rhe time required for the circuit breaker to open will depend on the fault current magnitude and nature.
~rip units, for many years, employed a bimetal member which responded in a predetermined manner to relatively low fault current and an electromagnetic trip member which responded to higher fault current magnitudes.
~ rip units which employ digital electronic cir-cuits and microprocessors to simulate the behavior of bi-metal and electromagnetic trip units are also known. ~rip units of these types are typically shown, for e~ample, in U.S. Patents 4,423,459, dated December 27, 1983, in the name of Frederick A. Stich and Conrad F. Williams; and 4,338,647, dated July 6, 1982, in the name of Wilson et al.
Digital and microprocessor based trip units of the prior art use combinations of analog and digital circuitry.
~he units, however, do not perform a true RMS load current measurement, and require additional circuits and transfor-mer components to perform ground~ fault current analysis.
_, . ~ . ...
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~oreover, prior units have limited accuracy over the full current measurement range and do not take accurate account of the prior thermal history of the circuit breaker.
Prior art current sensing systems for electronic trip units employ a current transformer in each phase and in the neutral, if a neutral is used. ~he current trans-former outputs are applied to respective full-wave, bridge-connected rectifiers. ~he rectif~ed output of each line is ttlen filtered and applied to a level detection circuit~
rhe measured peak level is then scaled to 0.707 to produce an output which, supposedly, is related to the RMS current of each respective line. A signal related to the measured RMS current is then applied to timing circuits which cause circuit breaker tripping when measured current of a given magnitude e~ists for given times.
A major problem in prior art electronic trip units is that the RMS current measured is correct only if the current wave shapes measured are perfect sine waves. If tbe wave shape is non-sinusoidal, the scali~g factor is wrong. For example, in circuits having appreciable line capacitance, such as inverter drives, the current wave shape contains substantial distortion from the sinusoidal shape. In circuits containing transformers, a third har-monic component is present in the wave ~hape, making it ~5 non-sinusoidal. Other sources of distortion of the current wave shape from the sinusoidal shape are well known. As a result of this inaccuracy, the circuit breaker may trip falsely and unnecessarily on too low a line current, or the circuit breaker may not trip when it should, because of the inaccurate measurement.
Circuits are known, which correct the above inac-curate measurement. For example, the output of the measur-ing current transformer can be connected to a resistor and the temperature of the resistor can be measured, to obtain a true RMS reading. Such a system is expensive and re-~ ~Z .) 5 ~
sponds too slowly to current changes to be use~ul for elec-tronic trip units.
Commercially available semiconductor chips exist which produce an RMS output. Such chips, ho~ever, are too expensiYe for use in electronic trip units for circuit brea~ers.
Sampling systems are also known, in which the in-stantaneous amplitude of a wave is periodically measured.
By measuring a sufficient number of samples each cycle and s4uaring the value of each sample, and then summing and taking the square root of the sum of the squares, the RMS
measurement can be obtained, its accuracy increasing with the number of samples taken. ~he effective number of sam-ples can be increased by phase shifting the beginning of the measuring point for each sample in each subsequent half cycle. Suc.h asynchronous sampling can be used to obtain the RMS value of any periodic wave shape. However, when this technique is applied to electronic trip units, the circuits become comple~ and e~pensive, since the measure-ment must be made separately for each of the phases and the neutral, if a neutral is provided.
As will be seen, the present invention provides a simple and inexpensive circuit for true RMS current mea-surement.
Another problem with e~isting electronic trip units is that they require intermediate current transfor-mers for each phase and for the neutral circuit. ~ypic-ally, these transformers are connected in wye, and are needed to produce a ground fault signal. Such current transformers are expensive and occupy considerable volume in the control housing.
As will be seen, the need for such separate inter-mediate transformers is eliminated by the present invention.
Another problem with prior art microprocessor based systems is that measurement resolution is poor, ~ ~ ~ss~
! RMD-1268 ~ - 4 -c'r~ , re4uiring relatively large microprocessors. By way of ecample, it is desirable to use an 8-bit microprocessor because of lts low cost. lf, ho~ever, it is desired to be ~ I able to discriminate currents from one-fourth full load .~ I S (for grouad fault detection) to ten times full load current, tùe current range is 1 to 40. If full load current is 600 <~ ¦ amperes, the difference between ten times full load current anq one-fourth full load current is (6,000-150) = 5850 am-~eres. An 8-bit microprocessor provides 256 unique 8 bit combinations. Thus, the individual steps are: 6,000l256 =
23.4~ amperes. This provides a resolution of abo~t 23.44A/
lSOA = 16~ where the 150 amperes is 25~ of 600 amperes.
However, 8 resolution of abou, 5~ or less is desired.
Therefore, a simple 8-bit microprocessor cannot be used, lS ~hile still having appropriate resolution.
As wlll be later seen, the invention provides a no~el automatic scale adjustment to permit requisite accu-racy, while using an 8-bit microprocessor.
~ A furtber problem with escisting digital circuits .. ~ 20 is in the means for providing thermal memory. Thus, in a .~ standard circuit breaker trip unlt, the history of prior heating of the breaker due to prior lnterruption operation, or prior heating caused by closlng on capaciti~e loads, and the like, stays with the brea`.cer. In prior art digital ~,-9 25 Systems, the effect of the thermal his~ory of the breaker was lost after the breaker opens. As ~ill be seen, the ~` ~ present inventlon provides circuit means for retaining thermal memory.
Still another problem in e~isting trip systems is that the trlp ~inding of the magnetlc latch of tbe clrcuit ~ breaker has a large number o turns and thus high lnduc-;` ~ tance. Therefore~ it is hard to dellver a trip slgnal rap-' ~ ~ idly to the coil because the trip circuit Uith the coil has a lar~e time constant. Accordlngly, ~hen the breaker is oyera~ed ~lth very high speed currcnt llmiting breakers, it ~, _ ~ ~s hard to coordinate the pert'ormance of the breakrrs.
~'~'. ~ ~
,~ ` , ,, . . .. _ . ' S'7~
-- s BRI EF DESCRIP~ION OF ~HE INVEN~ION
In accordance with the present invention, a novel microprocessor based trip unit is provided, which employs, as maJor components, a power supply, a sample and hold cir-cuit for each line, an analog-to-digital converter, a mi-croprocessor, and configuration switches for setting the adjustment parameters of the trip unit. ~he circuit is applicable to both three and four wire systems. Opening of the circuit breaker is accomplished by a conventional mech-anical mechanism which is activated by an electromagneticlatching mechanism triggered by the electronic trip unit.
~ he po~er supply provides full-~ave, rectified current from the three phase lines and neutral. It then generates a ~5 volt power source for all logic circuits, and also produces a positive reference voltage for the an-alo~-to-digital (A/D) converter. ~he positive reference voltage is either +l volt or ~5 volts, depending on the state of a control si~nal from the microcomputer. ~he power supply is capable of delivering 25 milliamperes when the line current is only 25% of its rated load current, which rated current may, for e~ample, be 600 amperes.
Signals representative of the line and neutral current are derived from the lines by the same current transformers, and are converted to voltage waveforms, using ~5 high precision resistors. ~he signal values are inverted and are in the range of O to +5 volts, with +5 volts repre-senting 20 times the frame rated current.
In accordance with one important aspect of this invention, all four signals (if a neutral is present) are sampled repetitively and simultaneously, and the sampled signals are used to charge respective capacitors. A sample is taken about every 1,500 microseconds (about ll samples/
cycle for a 60 Hz. line), and continues for about 100 cy-cles to produce about 1,100 samples for each RMS measure-ment cycle. Sequentially, the output of the sample and .. . .. . ..
~5~
hold circuit for each line is read out into a single A/D
converter. ~he conversion to a digital value takes about 100 microseconds, using an 8-bit converter having an QCCU-racy of +1 least significant bit.
~he simultaneously sampled signals of each line are then sequentially applied to the microcomputer which, using a conventional program, calculates the true RMS cur-rent for each line.
~he microcomputer also uses the processed simulta-neously sampled signals to calculate a ground fault cur-rent. ~hat is, if the sum of ~he line and neu$ral currents is not zero, there must be a ground fault. Since signals of the three phases and neutral are simultaneously sampled, and accurate RUS values are available, ground ~ault current can be calculated from the information in the microcompu-ter.
In order to adjustably set the parameters of cur-rent rating, instantaneous trip current, ground fault pick-up current and ground fault delay time, respectlve e~ter-nally adjustable binary coded decimal switches are providedwhich can be addressed individually, and read by the micro-computer. Based on the settings of these switches, and the readings from the A/D converter, the microcomputer calcu-lates a time to trip the circuit breaker. If the current ~5 does not decrease, and the calculated time arrives, the microcomputer issues a trip signal.
From the above, it is seen that the novel system of the invention employs true RMS current measurement.
Moreover, ground fault current is accurately calculated in the microcomputer, since simult~neously measured line and neutral current values are available, eliminating the need for intermediate current transformers.
~ he system employs an 8-bit microprocessor, yet carries out these operations with high resolution by scale switching. ~hus, one current scale is used for currents less than, for example, one and a half times rated current.
If rated current is 600 amperes, over the gO0 ampere range, there are 900/256=3.52 amperes per bit. For a ground fault current of one-fourth rated current (150 amperes), the res-olution is 3.52/150=2.3X. It is, in fact, ~ 1.2% which isvery satisfactory resolution.
At currents greater than 900 amperes, current scale is dynamically switched so t~at, for ten times load current, the amperes per bit is 6,000/256, which yields the same minimum accuracy.
rhe novel trip unit of the present invention also has simulated thermal memory. rhe memory consists of ther-mistors fi~ed on the bus bars which act as the primary windings of the current transformer pick-ups for the sys-tem. rhe thermistors are negative temperature coefficient devices, and their resistance will be related to the amount of heat (I2t) stored in the circuit breaker. rheir resis-tance is thus used to preset the current level and time-out functions of the microprocessor.
Alternatively, the thermal memory may employ a capacitive storage circuit and a separate A/D converter channel. ~he heating effect on the circuit breaker due to high current is taken into account by charging the capaci-tor to a level related to the breaker energy (I2t). ~hen the b`reaker trips, the charge on the capacitor bleeds off at a rate related to the cooling rate of the breaker. When the breaker is again closed, the capacitor level is read through the A/D converter channel, and the value measured is used to preset the energy level and time-out functions of the microprocessor.
rhe magnetic latch of the circuit breaker using the trip unit of the invention has a novel split winding structure. rhus, present windings for trip latches have a large number of turns, for example, ~,500 turns of 40 gauge wire. rhis coil has high inductance so that the trip cir-cuit containing the coil has a long time constant, for ex-~s~
ample, 8 to 10 milliseconds. In many applications, for example, those using a current limiting breaker, the magnetic latch mus-t trip within 3 to 4 milliseconds. If the magnetic latch is too slow, the high speed current limiting breaker will trip before the magnetic latch reacts. The novel split winding of the invention provides a continuous magnetic latch winding with two sections, a 6,600 turn section and a 110 turn section. When high speed operation is called for, a high trip voltage is available. The large turn winding is then bypassed and sufficient current flows through the 110 turn section to provide enough ampere turns to trip the latch in a very short time.
A further feature of the invention is the use of an EPRO~ with the microprocessor with a switch for selecting certain predetermined trip characteristics which are applied to the main microprocessor.
Also provided for the breaker is a thermal override, such that the magnetic latch of the operating mechanism is released if the unit temperature exceeds 85C.
The novel trip unit of the invention can be packaged ~ compactly and housed with its respective circuit breaker.
Alternatively, the trip unit can be mounted remotely of the cir-cuit breaker. For example, for switchboard frames containing a plurality of circuit breakers, the circuit breaker trip units can be contained in a single control location with appropri-ate input and output lines interconnecting the breakers with their respective trip units. In arrangements such as this, the )S7B~
local trip units can share certain common parts, such as common power supplies, data processing and the like.
Thus, in accordance with a broad aspect of the invention, there is provided a microprocessor based circuit breaker trip unit comprising, in combination:
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said 1~ circuit breaker;
respective signal conversion means connected to said plur-ality of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetively and simultaneously sampling and holding sample analog values of each o~ said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produeed in said sample and hold circuit after said pre-~3 determined number of samples of a corresponding digitial value;
a microprocessor means coupled to each of said analog-to-digital converters for computing a true RMS value of the current of each of said line from said predetermined number of samples;
and an output circuit means connected between said micro-eomputer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions.
-8a-.~55', ~X
In accordance with another broad aspect of the invention there is provided a microprocessor based circuit breaker trip unit comprising, in combination:
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective circuit breaker poles;
a trip mechanism energizable to open said circuit breaker poles;
respective signal conversion means connected to said plural-ity of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after each of said predetermined number of samples to a corresponding digital ~a value;
a microcomputer means coupled to each of said analog-to-digital converters for computing a true RMS value of the currents of each of said lines;
an output circuit means connected between said microcomputer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions; and -8b-:~S~7B;~
autoscaling circuit means connected -to said microcomputer for dividing a given current range into a first small range and a second larger range in values of amperes per bit of said microprocessor.
In accordance with another broad aspect of the invention there is provided a microprocessor based circuit breaker trip unit comprising, in combination:
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plura-lity of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after each of said predetermined number of samples to a corresponding digital value;
a microcomputer means coupled to each of said analog-to-digital converters for computing a true RMS value of the currents of each of said lines;
-8c-~' ~S5,~
said microcomputer includes means for computing ground fault current from the simultaneous samples of current in said lines;
an output circuit means connected between said microcomputer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions and;
autoscaling circuit means connected to said microcomputer for dividing a given current range into a first small range and a second larger range in values of amperes per bit of said microcomputer.
In accordance with another broad aspect of the invention there is provided a process for operating a trip unit of a multipole a-c circuit breaker which protects a circuit having a plurality of a-c lines; said process comprising the steps of producing a current signal for each of said lines which is proportional to the instantaneous current in said line; conver-ting each of said current signals to respective voltage signals which are proportional to said current signals; simultaneously, ~`.
and repetitively measuring the amplitudes of each of said voltage ~0 signals for relatively short sampling time; converting the ana-log value of the amplitudes of said voltage signal to a digital value; and separately calculating the true RMS value of each of said voltage signals by taking the square root of the sum of the s~uares of each of the digital values measured.
In accordance with another broad aspect of the invention there is provided a trip unit for a circuit breaker comprising, in combination:
-8d-l~S5~7~;~
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plurality of current transformers for converting the current output of said current transformers to respective voltage signals;
an output circuit means connected between said current trans~
formers and said trip mechanism for operating said trip mechanism in response to predetermined current conditions;
said trip mechanism including a magnetic latch and a semiconductor switching device; said magentic latch containing a latch operating winding which is connected in series with said semiconductor switching device;
said semiconductor switching device having a control electrode connected to said output circuit means to be switched into conduction in response to a given output from said output eireuit means;
said winding consisting of a series connected large turn, high resistance section and relatively low turn, relatively low resistance section; and bypass switching means connected from the node of said series connected sections to said semiconductor switching device whereby, when the output voltage in series with said winding and said switching device exceeds a given value, said bypass switehing devlce conducts and shortcircuits said large turn, -8e-~S5t7~;~
high resistance section.
In accordance with another broad aspect of the invention there is provided a method of operating a circuit breaker trip unit with the use of a microprocessor comprising the steps of:
providing said microprocessor with predetermined current data for said trip unit;
initiating a sample interval timer in said microprocessor upon the start or the sampling period to sequence the samples taken by a plurality of sample and hold circuits;
constantly determining the voltage of each sample and hold circuit at the end of each sample interval;
constantly providing the microprocessor with a digitally converted signal voltage and current samples unit the end of the sampling period;
repetitively storing the microprocessor the sampled current value for 1100 sample times to calculate the total current during the sampling period;
repetitively comparing in the microprocessor the sample time ~alculated with the root-mean-square equation and said elapsed time; and opening the circuit breaker trip unit when the calculated true RMS value indicates an occurrence of at least a predetermined current condition.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of the novel microprocessor implemented electronic trip unit of the present invention.
i~S5~1'8~
Figures 2A and 2B together form a flow chart for the microprocessor of the block diagram of Figure 1.
Figures 3A, 3B, 3C and 3D are parts of an overall schematic diagram of the detailed circuit and microprocessor of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
.
Referring to Figure 1, there is first schematically illustrated a three-phase a-c power line containing phases A,B and C and a neutral line N which may or may not be provided 1~ in the circuit. The circuit breaker 20 is schematically illus-trated as having four poles for the phases A,s, C and the neutral N, respectively. Circuit breaker 20 may be a conventional circuit breaker of relatively low voltage and having a rated current, for example, of 600 amperes. Obviously, any desired rating can be used for the circuit breaker. Circuit breaker 20 can be contained in metal insulated switchgear along with any desired number of other circuit breakers having the same and different ratings.
Circuit breaker 20 contains a trip mechanism 21 which ~a can be a conventional type of electromagnetic trip mechanism, operable in response to a current through the trip coil 22 of the trip mechanism 21. Trip coil 22 can be energized from a positive voltage supplied by rectifier device 34 upon the firing of a silicon controlled rectifier (SCR) 23 which is in series with the coil 22. Trip coil 22 can be the split coil of a magnetic latch, as will be later described. A thermal trip circuit 24 can also be provided to cause a switching action in parallel with SCR 23 1~Z55~7~3~
-9a-when the temperature of circuit breaker 20 exceeds some preset value, for example 85C.
The purpose of the present invention is to apply a trip signal to the gate electrode 25 of SCR 23 under certain eireuit eonditions in the circuit protected by the circuit breaker 20.
.
~s~
Conventional current transformers 30, 31, 32 and 33 are provided on phases ~, B, C and neutral N, respec-tively. ~he outputs of these transformers arg applied to an appropriate rectifier device 3~ ~hich conventionallY
consists of respective single-phase full-wave bridge con-nected rectifier circuits for each of windings 30-33, re-spectively. rhis arrangement will be described later in more detail.
~he output of rectifier 34 is connected to po~er supply circuit 35. Power supply circuit 35 produes a 5-volt control power output for controlling components of the trip mechanism, as well as the logic circuit components to be later described. Power supply 35 also puts out a posi-tive 12 volts to the reference circuit 35A that supplies a voltage Vref which is adjustable, using Vref control, be-twèen at least two values, for e~ample 3.5 volts and .56 volt to the input +Vref of an analog to digital converter to be described. ~his circuit operates to switch the ref-erence voltage Vref to provide automatic scaling, as will later be described. Switchover can occur, for e~ample, at a measured current of 1.5 times the rated current of the circuit breaker 20. Switching the reference level produces an automatic scaling type operation, so that relatively high resolution in the measuring circuit is obtained at a low current scale region, making it possible to use 8-bit microprocessors with the requisite accuracy of current mea-surement at critical current levels.
~ he output of rectifier 34 is also applied through signal converter circuits 36 ~hich individually convert the output current signals of rectifier 34 to respective vol-tage signals. ~he output of signal converter circuits 36 are ~hen applied to the analog inverter 37 ~hich inverts their polarity from a negative to positive.
Each of the individual signals derived from lines A, B, C and N are then applied to a simultaneous sample-and-hold circuit 38. ~he simultaneous samp]e and hold circuit 38 takes a sample simultaneously from each of the outputs of current transformers 30-33 once every 1500 mi-croseconds, or 11 times in each cycle of a 60 Hz system.
At the time the simultaneous samples are taken, each signal A, B, C and N charges a respective capacitor to a voltage level representative of each respective instanta-neous phase current. ~he charge of each capacitor is then sampled sequentially and convqrted, by the analog to digi-tal converter 3g t to a digital value representative of the instantaneous current of that phase which is then sent to the microcomputer 41. ~he address and ~ecode circuit 40 coordinates this activity which is ultimately controlled by the microcomputer 41. Appro~imately every 100 cycles, the RMS current is computed arithmetically from these samples.
A data bus 42 interconnects the microcomputer 41 with the analog-to-digital converter 39 and with switch buffer circuits 43, which are, in turn, connected to four respective configuration switches for setting values of current rating, instantaneous trip, ground fault pickup and ground fault delay, respectively. Any desired number of configuration switches can be used, for a~y desired respec-tive parameters. ~hese switches are binary coded decimal switches which are located e~ternally of the control cir-cuits so that they can be easily manually adjusted. Also provided, as shown in Figure 1, is a crystal oscillator 45 and a switch address decoder circuit 46 connected between the microcomputer 41 and the switch buffers 43.
Also provided in Figure 1 is a thermal 0emory de-vice 50 which may be a thermistor or capacitive circuit.
When using a capacitive circuit, ~hich is charged just be~
fore tripping by the microcomputer 41 to a value represent-ative of the thermal condition of the circuit breaker, dis-charge circuit means are provided within device ~0, such that, when the circuit breaker is open and its parts cool, the capacitive or other structure within thermal memory ~S5~7~
device 50 is discharged or cools at the same rate. When the circuit breaker is reclosed, the output remaining in the thermal memory device 50 is read back into the system and all trip levels are appropriately adjusted to take into consideration the prior thermal history of the circuit breaker. When using thermistors for the thermal memory, they are preferably negative temperature devices mounted on the main bus bars within the circuit breaker, and are read by the microprocessor as described above.
Outputs from the milcrocomputer 41 include the +Vref 1~ control output, which is applied to reference circuit 35A in order to adjust the +Vref level to obtain the desired automatic scaling of the reference output.
A trip signal is derived from port 1 of the micro-computer 41, which is the trip signal to be applied to ~CR
23 under appropriate computed circumstances. A start A/D signal is also derivedfrom microcomputer 41, which signal is applied to the analog-to-digital converter 39 so that samples are taken from the simultaneous sample and hold circuits.
Figures 2A and 2B together form a flow chart for -the microcomputer of Figure 1. This same flow chart is applicable to the circuit of Figures 3A, 3B and 3C, which shall be later de-scribed.
The flow chart analysis may begin with the start at the right of Figure 2A. Following the start operation, the system is initialized, including initialization of timer memory, input/output ports and interrupts. Thereafter, the thermistor 1~5~
values in the thermal memory device 50 are read and the RMS
trip values are preset in accordance with the thermal history of the breaker as determined by the thermistor values. The set up switches connected to the switch buffers 43 are then read and the trip parameters appropriately set. Thereafter, the ports and status are set and the analog to digital converter 39 is started.
A measurement ist~en made as to whether the ground fault circuit is enabled. If not, a determination is made as to whether the RMS calculate instruction has been enabled. If not, a determination is made as to whether the reference voltage is at its high level. If not, a subroutine comes back to the determination of a ground fault enabling condition.
In the above sequence, if it was determined -that the ground fault was enabled, the flow chart moves to the second column to the left in Figure 2A and a determination is made of the largest phase current. From this is subtracted the current measured in the other two phases and the neutral current and the result is placed in storage. This is a ground fault current sample. Thereafter, a calculation is made of the ground fault average over 1/4 cycle and a decislon is then made as to whether the ground fault average current is less than the ground fault pick-up current.
If the ground fault average is less than the ground fault pick-up, the trip flags, which are displayed in the beginning, are cleared so that the circuit can continue in its operation as will be later described. If, however, the ~S5 ~ ~
ground fault average is found to be not less than ground fault pick-up the delay is calculated and a determination is made of whether the delay is greater than that of the counter.
If it is, the trip flags are immediately set. If not, the value is loaded into the timer circuit and the timer is started so that the trip flags will be set after a given length of time.
Returning to the right column of Figure 2A, starting with the start, it is noted that if it is found that the voltage reference is high, an output to numeral 3 is applied. This output is found in the lowermost righ-t hand column of Figure 2B
and it is seen that a determination is made as to whether all flags are clear. If they are, then it is possible to switch to the low voltage reference. If not, an output numeral 4 is pro-duced corresponding to the indicated location in the right hand column in Figure 2A.
Returning to the right column of the flow chart of Figure 2A, and the position where determination is made of whethe~r-^RMS calculation is enabled, if it is enabled, the flow chart proceeds in the central column of Figure 2A. Thus, for each phase, the microprocessor will square the sample measured add it to the sum and then increment the count. A determination is then made of whether the count is less than 256. If not, an RMS calculation is made in which the RMS value is divided by 256. It is then determined whether the reference voltage is high and, if so, high parameters are used, and if not, low voltage reference parameters are used.
Thereafter, a determination is made as to whether the l~S5~
RMS current measured is less than or equal to 115% of the full load current. If not, the over curren-t sum is made equal to the over current sum plus the RMS value minus the cooling factor and the trip flags are set. A decision is then made as to whether the over current sum is less than the sum RMS constant value. If not, the breaker is tripped and the sequence is ended. If the RMS value was found to be less than or equal to 115% of full load current, a determination is made as to whether the over current sum equals the over current sum minus the cooling factor.
mhereafter, the trip flags are cleared when the over current sum is equal to zero. In this condition, or if the over current sum is found less than an RMS current, there is an output to the central column of the chart, where a decision is made as to whether the reference is high and the flow chart proceeds as previously described.
When the breaker is tripped and the sequencing is ended, it will be noted that trip flags are also set. These same trip flags may be set by the interrupt service routine
2~ shown in the left column in Figure 2B. In this column, the interrupt service routine begins to step a pointer from a peak sum equal to a peak value sum minus a cooling factor. This is then applied to the input of the analog to digital converter which samples the instantaneous value being delivered. The sample is then stored at the pointer and a calculation is made of -the peak average over 1/~ cycle.
1~5~
Thereafter, the next analog to digital conversion cycle is started and a decision is made as to whether the voltage reference is ]ow. If the voltage reference is high, then a second decision is made as to whether the peak average current is less than the peak pick-up. If not, a decision is made as to whether the peak sum is greater than some constant value. If it is/ the trip flags are set and the breaker is tripped. If not, a routine is initiated which follows the routine shown in the central column in Figure 2B. This same routine is initiated if the voltage reference is found to be low.
In the routine shown in the central column of Figure 2B, a decision is made as to whether the peak average is less than some predetermined high value. If not, the system switches to the high reference voltage value. Thereafter, a determination is made of whether the pointer is not equal to 3.
If not, then the RMS samples are stored and the enabled RMS cal-culation flag is raised. The next decision made is whether the total currents measured are zero. If not, there is a ground faul~t and the ground fault samples are stored and the enabled ~0 ~round fault calculation flag is raised. This terminates the interrupt sequence.
The sequence shown to the very right hand side of Figure 2B starts with a timer interrupt which initiates reloading and starting of the timer. Thereafter, a decision is made as to whether the ground fault current trip system is cleared. If it ~;~S~'7~i~
is, the interrupt routine ends. If it is not cleared, there is a countdown and a decision is made of whether the count is greater than zero. If it is not, an output to numeral 5 is taken to the central column in Figure 2A, which initiates the tripping of the breaker.
In carrying out the above process with the micro-computer 41, it will be clear that the desired program will be stored, for example, in a dedicated mlcroprocessor or an E PROM
or RO~. The switch table data and timing data may also be stored in a suitable ROM.
There is next described, the detailed circuit arrange-ment of the present invention, shown in Figures 3A, 3B, 3C and 3D. Figures 3A, 3B, 3C, and 3D are parts of a single circuit diagram but are shown on separate drawing sheets for clarity.
The interconnecting lines are correspondingly marked.
The rectifier 34 of Figure~l is shown in more detail in Fi~ure 3B as including the four single phase full wave bridges 60, 61, 62 and 63. These bridges receive inputs from the current transormers 30, 31, 32 and 33 for phases A, B, C and ~a neutral N, respectively. The positive output terminal of each of the bridges 60-63 is connected to the positive output line 64 which leads to the power supply circuit of Figure 3A.
Figure 3A shows the power supply circuit and the schematically illustrated electromagnetic circuit breaker trip structure. The power supply circuit inclues a Darlington arranged transistor switch 65, which can be type 2N6533 arranged ~25~7~;~
-17a-to bleed off excess power which might be produced within the power supply. A transistor 66 is also provided which may be a type MPSA06 which is connected in circuit relation with Zener diodes 67 an 68 which may be types lN5261B and lN5240B, respectively.
Zener diode 67 clamps line 64 to 47 volts maximum, while Zener ~iode 68 clamps the voltage to 10 volts. A filter capacitor 69 (1.5 microfarads) is also provided. Resistor 73 (lK) connects the anode of Zener 68 to the digital ground.
Also connected to positive line 64 is the main magnetic latch coil 80 of the circuit breaker and a shunt trip circuit 81 ror the circuit breaker. Magnetic latch coil 80 is connected in series with diode 75 (type lN4004) and SCR 82, which may be a type C103B, which is connected to the power supply ~round circuit. The gate circuit of SCR 82 has a resistor 83 which may be a lK resistor, and capacitor 84, which may be a 0.1 microarad capacitor, connected thereto. A thermostat 85 is connected in parallel with the SCR 82 and may be type SCCRP85CS, which closes when the circuit breaker temperature exceeds 85C, thus initiating a trip of the circuit breaker independently of tha operation of the SCR 82.
An input trip signal is applied through diode 87 (lN4148) to the gate of SCR 82 over the trip signal line 86 which is derived from the microprocessor control of Figures 3C and 3D
às will be later described.
Coil 80 consists of a winding having a 6650 turn winding section 80a, of 40 gauge wire and a 110 turn winding section 80b of 33 gauge wire. The resistances of windings 80a and ~S~ 8~
-17b-and 80b are 1150 ohms and 4.4 ohms, respectively. The windings are connected in series, and their connection point is connected to the anode of SCR 82 through Zener diode 80c, which is a type 5A26A Tra~3~4~ made by General Semiconductor, and capable of high current conduction, for example, 11 amperes. The use of separate wire sections 80a and 80b with Zener 80c permits the by-pass of coil section 80a in the presence of a high voltage at line 64 which occurs during a high fault condition. Under this situation, the latch coil 80 should operate the latch in
1~5~
Thereafter, the next analog to digital conversion cycle is started and a decision is made as to whether the voltage reference is ]ow. If the voltage reference is high, then a second decision is made as to whether the peak average current is less than the peak pick-up. If not, a decision is made as to whether the peak sum is greater than some constant value. If it is/ the trip flags are set and the breaker is tripped. If not, a routine is initiated which follows the routine shown in the central column in Figure 2B. This same routine is initiated if the voltage reference is found to be low.
In the routine shown in the central column of Figure 2B, a decision is made as to whether the peak average is less than some predetermined high value. If not, the system switches to the high reference voltage value. Thereafter, a determination is made of whether the pointer is not equal to 3.
If not, then the RMS samples are stored and the enabled RMS cal-culation flag is raised. The next decision made is whether the total currents measured are zero. If not, there is a ground faul~t and the ground fault samples are stored and the enabled ~0 ~round fault calculation flag is raised. This terminates the interrupt sequence.
The sequence shown to the very right hand side of Figure 2B starts with a timer interrupt which initiates reloading and starting of the timer. Thereafter, a decision is made as to whether the ground fault current trip system is cleared. If it ~;~S~'7~i~
is, the interrupt routine ends. If it is not cleared, there is a countdown and a decision is made of whether the count is greater than zero. If it is not, an output to numeral 5 is taken to the central column in Figure 2A, which initiates the tripping of the breaker.
In carrying out the above process with the micro-computer 41, it will be clear that the desired program will be stored, for example, in a dedicated mlcroprocessor or an E PROM
or RO~. The switch table data and timing data may also be stored in a suitable ROM.
There is next described, the detailed circuit arrange-ment of the present invention, shown in Figures 3A, 3B, 3C and 3D. Figures 3A, 3B, 3C, and 3D are parts of a single circuit diagram but are shown on separate drawing sheets for clarity.
The interconnecting lines are correspondingly marked.
The rectifier 34 of Figure~l is shown in more detail in Fi~ure 3B as including the four single phase full wave bridges 60, 61, 62 and 63. These bridges receive inputs from the current transormers 30, 31, 32 and 33 for phases A, B, C and ~a neutral N, respectively. The positive output terminal of each of the bridges 60-63 is connected to the positive output line 64 which leads to the power supply circuit of Figure 3A.
Figure 3A shows the power supply circuit and the schematically illustrated electromagnetic circuit breaker trip structure. The power supply circuit inclues a Darlington arranged transistor switch 65, which can be type 2N6533 arranged ~25~7~;~
-17a-to bleed off excess power which might be produced within the power supply. A transistor 66 is also provided which may be a type MPSA06 which is connected in circuit relation with Zener diodes 67 an 68 which may be types lN5261B and lN5240B, respectively.
Zener diode 67 clamps line 64 to 47 volts maximum, while Zener ~iode 68 clamps the voltage to 10 volts. A filter capacitor 69 (1.5 microfarads) is also provided. Resistor 73 (lK) connects the anode of Zener 68 to the digital ground.
Also connected to positive line 64 is the main magnetic latch coil 80 of the circuit breaker and a shunt trip circuit 81 ror the circuit breaker. Magnetic latch coil 80 is connected in series with diode 75 (type lN4004) and SCR 82, which may be a type C103B, which is connected to the power supply ~round circuit. The gate circuit of SCR 82 has a resistor 83 which may be a lK resistor, and capacitor 84, which may be a 0.1 microarad capacitor, connected thereto. A thermostat 85 is connected in parallel with the SCR 82 and may be type SCCRP85CS, which closes when the circuit breaker temperature exceeds 85C, thus initiating a trip of the circuit breaker independently of tha operation of the SCR 82.
An input trip signal is applied through diode 87 (lN4148) to the gate of SCR 82 over the trip signal line 86 which is derived from the microprocessor control of Figures 3C and 3D
às will be later described.
Coil 80 consists of a winding having a 6650 turn winding section 80a, of 40 gauge wire and a 110 turn winding section 80b of 33 gauge wire. The resistances of windings 80a and ~S~ 8~
-17b-and 80b are 1150 ohms and 4.4 ohms, respectively. The windings are connected in series, and their connection point is connected to the anode of SCR 82 through Zener diode 80c, which is a type 5A26A Tra~3~4~ made by General Semiconductor, and capable of high current conduction, for example, 11 amperes. The use of separate wire sections 80a and 80b with Zener 80c permits the by-pass of coil section 80a in the presence of a high voltage at line 64 which occurs during a high fault condition. Under this situation, the latch coil 80 should operate the latch in
3 to 4 milliseconds. To get this high speed operation, however, it is ~ ~S5t, ~
necessary to bypass coil sec~ion 80a; thereby to substan-tially reduce the time cons~ant of the circuit. Since a high voltage is available, there are sufficient ampere turns provided from the high rate of rise of current in the 110 turn winding 80b to trip the magentic latch~
Also provided in Figure 3A is a transistorized voltage regulator 90 which may be a type LM340LA50. Capac-i tors 91 and 92 are connected to pins 1 and 2 of the vo l-tage regulator 90 and may be 15 microfarads and 1.5 micro-farad, respectively. ~he regulated 5 volt output appears at pin 3 of regulator 90 and is used throughout the system where a 5 volt power supply is necessary. A 10 volt output is taken from pin l of regulator 90.
~he 5 volt output is also connected to resistors ~5 and 96 which may have values of 2.7K and lOK, respec-tivèly, of the dual voltage reference circuit used for scale change. ~he node of resistors 95 and 96 is connected to positive pin 3 of operational amplifier (LM358AN) sec-tion 95a. Pins 1 and 2 of section 95a are connected through diode 96 (lN4148) to resistors 97a and 97b which are lK and 6.2K resistors, respectively. ~he node of re-sistors 97a and 97b is connected to pin 6 of operational ampli fier section 95b. Pin 7 of section 95b is then con-nected, through diode 98 (lN4148) and resistor 99 (2.7K) to trip signal input line 86. ~he input system voltage at node 50 is applied to resistor 51 (lK) and then to resistor 52 (6.2K~ and capacitor 52a (0.1 microfarad).
~here is ne~t described the arrangement of Figure 3~ and the signal conditioners 36 of Figure 1, the analog inverter 37 of Figure 1 and the simultaneous sample and hold circuits 38 of Figure 1. Referring to Figure 3B, it will be noted that the negative signal on bridge connected rectifiers 60, 61, 62 and 63 is connected to precision re-sistors 100, 101, 102 and 103, respectively. Each of these resistors is a low value resistor, for example, 2.5 ohms at 5~
2 watts with 1% accuracy. rhey may, for e~ample, be beryl-lium o~ide core resistors and are used to convert the cur-rent signal detected by the bridge connected recti ~iers 60-63 into a voltage signal.
rhe signal on these signal resistors 100-103, how-ever, is inverted and is below ground. Since the micropro-cessor to be described needs input signals which are inver-ted and above ground, the signals from the resistors 100-103 are connected to respective sections of operational ampli fier U1 which inverts the signals. Operational ampli-fier U1 may be a type L~d2243. rwO resistor networks llOa, 110b, 110c, 110d and 111a, lllb, lllc, llld, which may each be type 4308SIP, which contains 10K resistors, are inter-posed between resistors 100 and 103 and the operational ampli fier U1, as shown, and provide the necessary biases to operate the operational ampli fier U1 correctly.
~he outputs on the circui t lines 115, 116, 117 and 118 then correspond to inverted voltage outputs related to the instantaneous current in phases A, B, C and in the neu-tral N respectively of the circuit of Figure 1. In other words, these signals are directly related to the signals derived from current transformers 30, 31, 32 and 33, re-spectively. ~hese signals are then applied to the OR cir-cuit containing diodes 112a, 112b, 112c and 112d, respec-~5 tively (lN4148), which are connected to node 50, ~he sig-nals are also applied to a quad bilateral switch U2 which contains four separate swi tches which are operable to sam-ple the instantaneous value of the four signals on lines 115, 116, 117 and 11~, respectively. Device U2 may be a 30 device type CD4066.
In accordance wi th one aspect of the invention, these samples are simultaneously taken. ~hus, the bi lat-eral switches are closed to take a sample in each line sim-ultaneously, by the control line 120 which comes ~rom pin 35 34 (P1-7) of the microprocessor to be later described in 31 ~S~78;~
~ nd 3 ~, connec~ion with Figure 3CJ Line 120, when, activated will initiate a sampling operation of all four switches of U2 over the control input lines which are connected together at pins 12, 13, 5 and 6 of the switching device U2. Note that the lines 115, 116, 117 and 118 are connected to in-put/output pins 1, 4, 8 and 11, respectively of U2. The control line 120 is operated in such a manner that the switches of the switching device U2 are turned on and off every 1500 microseconds (approximately 11 times per cycle in a 60 cycle system). ~his sampling is repeated ~or 100 cycles to produce 1100 simultaneous samples for each of lines A, B, C and N in a given cycling interval.
~ he sampled signals are then applied to respective capacitors 130, 131, 132 and 133, corresponding tc phase 15 lines A, B, C and N, respectively. Capacitors 130-133 may each be 1000 picofarad capacitors. Each time one of the switches of switch unit U2 closes, it will be apparent that the appropriate capacitor 130 to 133 will charge. Respec-tive sections of an operational amplifier U3 are connected to the outputs of the switches of switch unit U2. ~hese act as voltage followers and serve to prevent e~cessive discharge of capacitors 130 to 133 during the sampling op-eration.
At the end of a complete sampling cycle, the net ~5 charge on each capacitor 130 to 133 will be related to the instantaneous current which was measured by current trans-formers 30-33, respectively. Note also that these measure-ments were made at simultaneous instants so that the data can be processed, not only to give true RMS data for each line, but also to calculate the ground fault current.
As will be seen in connection with Figure 3C, the outputs of voltage follower U3 are digitized and then ap-plied to the microprocessor of RMS and ground fault cur-rent.
~S5 ~ ~
Reference is ne~t made to the components of Figures ~nd 3 o 3C~ Figure 3C first shows the main microprocessor U4. In a preferred embodiment of the invention, microprocessor U4 is a type 80C49NEC in which the program for the system is "masked-in". Alternatively, the microprocessor may be the commercially available 8049~EC with an appropriate E PROM
for providing a program which can be switch-selected to provide any desired trip characteristic.
A 6 ~Hz crystal Y1 is connected to pins 2 and 3 and reference voltage is connected to pins 4 and 5 through the resistor 150, resistor 151, and capacitor 152, ~hich are lOK, lOK and 0.1 microfarads~ respectively. Pin 7 is connected to ground. Control line 120 which operates switches U2 of Figure 3B is connected to pin 34 of micro-processor U4. Pin 31 is connected to line 160 and throughinverter U6. ~he output of U6 is used to switch the vol-ta~e reference circuit as will be described~
A first jumper switch connected to pin 1 of micro-processor U4 allows the pin to be connected to 5 volts or ~round for ground fault or no ground fault measurement, respectively. A second jumper, connected to pin 39, allows instantaneous trip or no instantaneous trip, respectively.
Figure 3C ne~t contains an analog to digital con-verter U5, which is preferably a type ADC0809. ~he output lines from pins 8, 14, 1 and ? of converter U5 of Figure 3B
are connected to pins 26, 1, 28 and 27, respectively, of converter U5. A digital value, representative of the ana log voltage of the above input pins is output to micropro-cessor from pins DBO to DB7. An end of conversion signal EOC is output from pin 7 of converter U5, through a section of inverter U6 (a 74HC04 He~ inverter) to pin 6 of micro-processor U4. ~he start signal of U4 at pin 6 ls derived from pin 29 of microprocessor U4. All other pin connec-tions between microprocessor U4 and converter U5 are made as shown.
~s~
A 3 to 8 line decoder U9 (Figure 3D) is next provided and may be any desired type, for example, a type 74HC138. Also provided are two octal tri-state buffers U10 and Ull which are each type 7 4~C244.
Next provided in Figure 3D are four 10 position binary coded decimal switches Sl, S2, S3 and S4 which may each be type 230102GBBCD and which are operable for setting ground fault delay, ground fault pickup, instantaneous trip level and current setting, respectively. Resistor networks RN3, RN4, RN5 and RN6 are provided in the connectors between switches 51 to 54 and buffers U10 and Ull so that an open swi-tch pulls down the signal.
There is finally provided in Figure 3C a circuit for providing thermal memory ~hich includes thermistors NTCl, 2 and 3, which may each be type 05DC103J-EC. These are mounted, preferably, on the conductors within the circuit breaker which serve as the primary windings of current trans-formers 30, 31 and 32, respectively. The thermistors are connected in series with resistors 220, 221 and 222, respectively, which may each be 30K. Signals representative of the thermal ~ condition of the circuit breaker are then connected to the converter U5 and their digital value is loaded into microprocessor U4 to appropriately modify the trip characteristics of the breaker in accordance with its prior thermal history.
Next, shown in Figure 3D is the novel dual reference voltage circuit. This circuit consists of the voltage divider having resistors 260 and 261 (6 and 14K, respectively) which l~S~7~
_2~-are connected to the output at the lead 160. The node oE
resistors 260 and 261 is connected to pin 3 of operational amplifier U7 (a dual op-amp type LM358AN). Resistors 265 and 266 (12K and 1.5K, respectively) of a second voltage divider are also connected to 5 volts and their node is connected to pin 5 of a respective section of dual op-amp U7. Output pins
necessary to bypass coil sec~ion 80a; thereby to substan-tially reduce the time cons~ant of the circuit. Since a high voltage is available, there are sufficient ampere turns provided from the high rate of rise of current in the 110 turn winding 80b to trip the magentic latch~
Also provided in Figure 3A is a transistorized voltage regulator 90 which may be a type LM340LA50. Capac-i tors 91 and 92 are connected to pins 1 and 2 of the vo l-tage regulator 90 and may be 15 microfarads and 1.5 micro-farad, respectively. ~he regulated 5 volt output appears at pin 3 of regulator 90 and is used throughout the system where a 5 volt power supply is necessary. A 10 volt output is taken from pin l of regulator 90.
~he 5 volt output is also connected to resistors ~5 and 96 which may have values of 2.7K and lOK, respec-tivèly, of the dual voltage reference circuit used for scale change. ~he node of resistors 95 and 96 is connected to positive pin 3 of operational amplifier (LM358AN) sec-tion 95a. Pins 1 and 2 of section 95a are connected through diode 96 (lN4148) to resistors 97a and 97b which are lK and 6.2K resistors, respectively. ~he node of re-sistors 97a and 97b is connected to pin 6 of operational ampli fier section 95b. Pin 7 of section 95b is then con-nected, through diode 98 (lN4148) and resistor 99 (2.7K) to trip signal input line 86. ~he input system voltage at node 50 is applied to resistor 51 (lK) and then to resistor 52 (6.2K~ and capacitor 52a (0.1 microfarad).
~here is ne~t described the arrangement of Figure 3~ and the signal conditioners 36 of Figure 1, the analog inverter 37 of Figure 1 and the simultaneous sample and hold circuits 38 of Figure 1. Referring to Figure 3B, it will be noted that the negative signal on bridge connected rectifiers 60, 61, 62 and 63 is connected to precision re-sistors 100, 101, 102 and 103, respectively. Each of these resistors is a low value resistor, for example, 2.5 ohms at 5~
2 watts with 1% accuracy. rhey may, for e~ample, be beryl-lium o~ide core resistors and are used to convert the cur-rent signal detected by the bridge connected recti ~iers 60-63 into a voltage signal.
rhe signal on these signal resistors 100-103, how-ever, is inverted and is below ground. Since the micropro-cessor to be described needs input signals which are inver-ted and above ground, the signals from the resistors 100-103 are connected to respective sections of operational ampli fier U1 which inverts the signals. Operational ampli-fier U1 may be a type L~d2243. rwO resistor networks llOa, 110b, 110c, 110d and 111a, lllb, lllc, llld, which may each be type 4308SIP, which contains 10K resistors, are inter-posed between resistors 100 and 103 and the operational ampli fier U1, as shown, and provide the necessary biases to operate the operational ampli fier U1 correctly.
~he outputs on the circui t lines 115, 116, 117 and 118 then correspond to inverted voltage outputs related to the instantaneous current in phases A, B, C and in the neu-tral N respectively of the circuit of Figure 1. In other words, these signals are directly related to the signals derived from current transformers 30, 31, 32 and 33, re-spectively. ~hese signals are then applied to the OR cir-cuit containing diodes 112a, 112b, 112c and 112d, respec-~5 tively (lN4148), which are connected to node 50, ~he sig-nals are also applied to a quad bilateral switch U2 which contains four separate swi tches which are operable to sam-ple the instantaneous value of the four signals on lines 115, 116, 117 and 11~, respectively. Device U2 may be a 30 device type CD4066.
In accordance wi th one aspect of the invention, these samples are simultaneously taken. ~hus, the bi lat-eral switches are closed to take a sample in each line sim-ultaneously, by the control line 120 which comes ~rom pin 35 34 (P1-7) of the microprocessor to be later described in 31 ~S~78;~
~ nd 3 ~, connec~ion with Figure 3CJ Line 120, when, activated will initiate a sampling operation of all four switches of U2 over the control input lines which are connected together at pins 12, 13, 5 and 6 of the switching device U2. Note that the lines 115, 116, 117 and 118 are connected to in-put/output pins 1, 4, 8 and 11, respectively of U2. The control line 120 is operated in such a manner that the switches of the switching device U2 are turned on and off every 1500 microseconds (approximately 11 times per cycle in a 60 cycle system). ~his sampling is repeated ~or 100 cycles to produce 1100 simultaneous samples for each of lines A, B, C and N in a given cycling interval.
~ he sampled signals are then applied to respective capacitors 130, 131, 132 and 133, corresponding tc phase 15 lines A, B, C and N, respectively. Capacitors 130-133 may each be 1000 picofarad capacitors. Each time one of the switches of switch unit U2 closes, it will be apparent that the appropriate capacitor 130 to 133 will charge. Respec-tive sections of an operational amplifier U3 are connected to the outputs of the switches of switch unit U2. ~hese act as voltage followers and serve to prevent e~cessive discharge of capacitors 130 to 133 during the sampling op-eration.
At the end of a complete sampling cycle, the net ~5 charge on each capacitor 130 to 133 will be related to the instantaneous current which was measured by current trans-formers 30-33, respectively. Note also that these measure-ments were made at simultaneous instants so that the data can be processed, not only to give true RMS data for each line, but also to calculate the ground fault current.
As will be seen in connection with Figure 3C, the outputs of voltage follower U3 are digitized and then ap-plied to the microprocessor of RMS and ground fault cur-rent.
~S5 ~ ~
Reference is ne~t made to the components of Figures ~nd 3 o 3C~ Figure 3C first shows the main microprocessor U4. In a preferred embodiment of the invention, microprocessor U4 is a type 80C49NEC in which the program for the system is "masked-in". Alternatively, the microprocessor may be the commercially available 8049~EC with an appropriate E PROM
for providing a program which can be switch-selected to provide any desired trip characteristic.
A 6 ~Hz crystal Y1 is connected to pins 2 and 3 and reference voltage is connected to pins 4 and 5 through the resistor 150, resistor 151, and capacitor 152, ~hich are lOK, lOK and 0.1 microfarads~ respectively. Pin 7 is connected to ground. Control line 120 which operates switches U2 of Figure 3B is connected to pin 34 of micro-processor U4. Pin 31 is connected to line 160 and throughinverter U6. ~he output of U6 is used to switch the vol-ta~e reference circuit as will be described~
A first jumper switch connected to pin 1 of micro-processor U4 allows the pin to be connected to 5 volts or ~round for ground fault or no ground fault measurement, respectively. A second jumper, connected to pin 39, allows instantaneous trip or no instantaneous trip, respectively.
Figure 3C ne~t contains an analog to digital con-verter U5, which is preferably a type ADC0809. ~he output lines from pins 8, 14, 1 and ? of converter U5 of Figure 3B
are connected to pins 26, 1, 28 and 27, respectively, of converter U5. A digital value, representative of the ana log voltage of the above input pins is output to micropro-cessor from pins DBO to DB7. An end of conversion signal EOC is output from pin 7 of converter U5, through a section of inverter U6 (a 74HC04 He~ inverter) to pin 6 of micro-processor U4. ~he start signal of U4 at pin 6 ls derived from pin 29 of microprocessor U4. All other pin connec-tions between microprocessor U4 and converter U5 are made as shown.
~s~
A 3 to 8 line decoder U9 (Figure 3D) is next provided and may be any desired type, for example, a type 74HC138. Also provided are two octal tri-state buffers U10 and Ull which are each type 7 4~C244.
Next provided in Figure 3D are four 10 position binary coded decimal switches Sl, S2, S3 and S4 which may each be type 230102GBBCD and which are operable for setting ground fault delay, ground fault pickup, instantaneous trip level and current setting, respectively. Resistor networks RN3, RN4, RN5 and RN6 are provided in the connectors between switches 51 to 54 and buffers U10 and Ull so that an open swi-tch pulls down the signal.
There is finally provided in Figure 3C a circuit for providing thermal memory ~hich includes thermistors NTCl, 2 and 3, which may each be type 05DC103J-EC. These are mounted, preferably, on the conductors within the circuit breaker which serve as the primary windings of current trans-formers 30, 31 and 32, respectively. The thermistors are connected in series with resistors 220, 221 and 222, respectively, which may each be 30K. Signals representative of the thermal ~ condition of the circuit breaker are then connected to the converter U5 and their digital value is loaded into microprocessor U4 to appropriately modify the trip characteristics of the breaker in accordance with its prior thermal history.
Next, shown in Figure 3D is the novel dual reference voltage circuit. This circuit consists of the voltage divider having resistors 260 and 261 (6 and 14K, respectively) which l~S~7~
_2~-are connected to the output at the lead 160. The node oE
resistors 260 and 261 is connected to pin 3 of operational amplifier U7 (a dual op-amp type LM358AN). Resistors 265 and 266 (12K and 1.5K, respectively) of a second voltage divider are also connected to 5 volts and their node is connected to pin 5 of a respective section of dual op-amp U7. Output pins
4 and 7 of U7 are connected to diodes 270 and 271, respectively, (each lN4148) to output lead 272 which is connected to pin 12 of converter U5.
The potential at the node of resistors 260 and 261 is 3.5 volts, and the potential at the node of resistors 265 and 266 is 0.556 volts. If the voltage on line 160 from micro-processor U4 is 5 volts/ the output on lead 272 is 3.5 volts, through diode 270. If, however, microprocessor U4 calls for a voltage reference change, the voltage on line 162 is zero and the output on line 272 is then 0.556 volts through diode 271.
A number of test points are provided throughout the circuit of Figures 3A, B and C. These test points, 14 in number, are labeled TPl to TP14 and are as follows:
TPl -- (-) A Phase TP2 -- (-) B Phase TP3 -- (-) C Phase TP4 -- (-) N Phase TP5 -- (-) Mag. Latch TP10 -- + Mag. Latch TPll -- + N Phase TP12 -- + C Phase TP13 -- + B Phase TP14 -- + A Phase
The potential at the node of resistors 260 and 261 is 3.5 volts, and the potential at the node of resistors 265 and 266 is 0.556 volts. If the voltage on line 160 from micro-processor U4 is 5 volts/ the output on lead 272 is 3.5 volts, through diode 270. If, however, microprocessor U4 calls for a voltage reference change, the voltage on line 162 is zero and the output on line 272 is then 0.556 volts through diode 271.
A number of test points are provided throughout the circuit of Figures 3A, B and C. These test points, 14 in number, are labeled TPl to TP14 and are as follows:
TPl -- (-) A Phase TP2 -- (-) B Phase TP3 -- (-) C Phase TP4 -- (-) N Phase TP5 -- (-) Mag. Latch TP10 -- + Mag. Latch TPll -- + N Phase TP12 -- + C Phase TP13 -- + B Phase TP14 -- + A Phase
5 ~ 8~
-23a-It is now possible to describe the operation of the novel system of Figures 3A, B, C and D and particularly to describe the processing of signals derived from capacitors 130, 131, 132 and 133. The flow chart of Figure 2 is applicable to Figures 3A, B, C and D.
In order to start the system operation, the circuit breaker is closed but the microprocessor operation is prevented until the reference signal voltages are developed. Once the re~erence signal voltages are developed, the microprocessor reads the condition of the switches Sl, ~5~7~
S2, S3 and S4 which correspond to ground fault delay set-ting, ground fault pick-up setting, instantaneous plck-up setting and continuous current settings, respectlvely.
~hese signals are applied from pins 1, 3, 4 and 6 of switches S1, S2, S3 and S4, respectively, to the input pins of tristate buffers U10 and U11. ~he outputs of the tri-state buffers U10 through ~11 are sequentially read at micrOproceSsor pins 12, 13, 14 and 15, respectively and tbe desired trip characteristics for the device are ~ppropri-ately set. Similarly, the outputs of the thermistors N~C1,N~C2 and N~C3 are read into the pins 4, 3 and ~, respec-tively, of converter U5 which converts the analog outputs o~ the thermistors into a digital signal on the output pins 17, 14, 15, 8, 18, 19, 20 and 21 of converter U5 into the corresponding pins of the microprocessor. ~he microproces-sor then employs this thermal history information to appro-priately adjust the points at which the circuit breaker will be tripped relative to the points at ~hich a cold cir-cuit breaker will trip.
Assuming now that the power supply is up aad the breaker is successfully reclosed and remains closed, it will be assumed that a fault condition occurs on the A
~hase of the circuit breaker. Under this situation, a rel-atively high current will flow through bridge connected rectifier 60 of Fig. 3B through the darlington switch 65 to return to the other terminal of rectifier 60 through the ~round circuit and resistor 100. ~he voltage across resis-tor 100 is inverted by the operational amplifier U1 with unity gain and is applie~ through diode 112a.
If the signal is so high that instantaneous trip override is required, the fault current will flow through resistor 51 to pin 5 of operational amplifier ~5b and ~ill cause an output at pin 7 sufficient to cause thyristor 82 to fire, thus operating the magnetic latch structure. If, however, the signal output through diode 112a ls not suffl-~s~
ciently bigh to operate the operational amplifier 95b asdescribed above, the output signal will appear at pin 1 of switch SWA of the quadbilateral switch U2. Note that all of the swi tches of the quadbilateral swi tch U2 open and 5 close simultaneously in response to an output signal on line 120 taken from pin 31 of microprocessor U4.
~ hen the switches U2 are closed, capacitors 130 to 133 charge to values related to the input s,~gnals coming from respective sections of operational ampli fier U1.
10 Since a fault current existed in phase A, capacitor 130 is more highly charged than the other capacl tors 131, 132 or 133. When line 120 causes all of the switches U~ to open, the signal on capaci tors 130 to 133 are applied through the voltage follower consisting of the operational ampli fier lS sections U3. Operational amplifier U3 has unity gain to substantially limi t the current drain on the capaci tors 130 to 133.
~ he analog to digi ~al converter U5 can do only one conversion at a time. rhe microprocessor U4 selects which 20 of the phases or neutral is to be converted, for example, in an orderly sequence of phase A, phase B, phase C and neutral.
Once the analog to digi tal conversion is performed on the phase A signal in its turn, the microprocessor reads ~5 out an 8-bi t value from converter U5, which corresponds to the voltage on the capacitor 130. In sequence, the micro-~rocessor reads and stores all of the values from converter U5 which were simultaneously input from the operational ampli fier U3. ~hereafter, under the influence of the pro-30 gram, the microprocessor U4 adds all four values taken fromphases A, B, C and neutral and calculates the ground fault current, if any. I f a ground fault current beyond a given magnitude is measured, the microprocessor puts out a signal to ini tiate the firing of thyristor 82. Note that the 35 microprocessor in performing the analysis will examine the ~5~
individual values to determine peak average value for the short time trip operation.
~ he microprocessor U4 also uses the measured val-ues as individual samples to calculate true RMS values for the long time over current trip function. Two hundred fifty-si~ samples are required to produce a single ~MS
value, In turn, several RNS values must be measured before a trip operation can be init~ated. rhe calculation of a single RMS value with ~he system of the present invention takes appro~imately 1.2 seconds.
Once the microprocessor decides for any reason to fire the thyristor 82, an output signal is applied to pin 30 (Pl-3) which signal is applied through U6 to the gate of thyristor 82.
Note that when the circuit is first started, a start conversion signal is needed. ~his start signal is taken from pin 29 of microprocessor U4. ~he end of conver-sion signal is produced by converter U5 at pin 7 which cau-ses the generation of a new start signal from the micro-processor pin 29 to start a new conversion signal.
~ he voltage reference signal from operational amp-lifier U7 is applied over line 272 to the pin 12 of conver-ter U5. rhe microprocessor U4 will make a decision as to whether this reference voltage should be high or low, de-pending UpOD the current value being measured during thefault condition. rhus, microprocessor U4 ~ill put out an appropriate signal on pin 30 through inverter U6 over line 160 in order to switch the Yoltage reference in the desired manner, thus producing the novel scaling operation of the present invention which has been previously described.
~ he circuit connected to pins 5 and 6 of micropro-cessor U4 contains resistors and capacitors which provide the necessary reset function. ~hus, when the breaker first ~ closes and the power supply ~ not yet reached its normal output, the reset will be held for appro~imatey 1 millisec-ond and until power is available.
~l~SS'78~
~ he operation of the microprocessor will be u~der the control of a suitable program. One program whlch has been used successfully is appended hereto.
Although the present inventlon has been described in connection with a preferred embodiment thereof, many variations and modifications will now become apparent to those skilled in the art. It is preferred, therefore, that the present inve~tion be limited not by the specific dis-closure herein, but only by the appended claims.
-23a-It is now possible to describe the operation of the novel system of Figures 3A, B, C and D and particularly to describe the processing of signals derived from capacitors 130, 131, 132 and 133. The flow chart of Figure 2 is applicable to Figures 3A, B, C and D.
In order to start the system operation, the circuit breaker is closed but the microprocessor operation is prevented until the reference signal voltages are developed. Once the re~erence signal voltages are developed, the microprocessor reads the condition of the switches Sl, ~5~7~
S2, S3 and S4 which correspond to ground fault delay set-ting, ground fault pick-up setting, instantaneous plck-up setting and continuous current settings, respectlvely.
~hese signals are applied from pins 1, 3, 4 and 6 of switches S1, S2, S3 and S4, respectively, to the input pins of tristate buffers U10 and U11. ~he outputs of the tri-state buffers U10 through ~11 are sequentially read at micrOproceSsor pins 12, 13, 14 and 15, respectively and tbe desired trip characteristics for the device are ~ppropri-ately set. Similarly, the outputs of the thermistors N~C1,N~C2 and N~C3 are read into the pins 4, 3 and ~, respec-tively, of converter U5 which converts the analog outputs o~ the thermistors into a digital signal on the output pins 17, 14, 15, 8, 18, 19, 20 and 21 of converter U5 into the corresponding pins of the microprocessor. ~he microproces-sor then employs this thermal history information to appro-priately adjust the points at which the circuit breaker will be tripped relative to the points at ~hich a cold cir-cuit breaker will trip.
Assuming now that the power supply is up aad the breaker is successfully reclosed and remains closed, it will be assumed that a fault condition occurs on the A
~hase of the circuit breaker. Under this situation, a rel-atively high current will flow through bridge connected rectifier 60 of Fig. 3B through the darlington switch 65 to return to the other terminal of rectifier 60 through the ~round circuit and resistor 100. ~he voltage across resis-tor 100 is inverted by the operational amplifier U1 with unity gain and is applie~ through diode 112a.
If the signal is so high that instantaneous trip override is required, the fault current will flow through resistor 51 to pin 5 of operational amplifier ~5b and ~ill cause an output at pin 7 sufficient to cause thyristor 82 to fire, thus operating the magnetic latch structure. If, however, the signal output through diode 112a ls not suffl-~s~
ciently bigh to operate the operational amplifier 95b asdescribed above, the output signal will appear at pin 1 of switch SWA of the quadbilateral switch U2. Note that all of the swi tches of the quadbilateral swi tch U2 open and 5 close simultaneously in response to an output signal on line 120 taken from pin 31 of microprocessor U4.
~ hen the switches U2 are closed, capacitors 130 to 133 charge to values related to the input s,~gnals coming from respective sections of operational ampli fier U1.
10 Since a fault current existed in phase A, capacitor 130 is more highly charged than the other capacl tors 131, 132 or 133. When line 120 causes all of the switches U~ to open, the signal on capaci tors 130 to 133 are applied through the voltage follower consisting of the operational ampli fier lS sections U3. Operational amplifier U3 has unity gain to substantially limi t the current drain on the capaci tors 130 to 133.
~ he analog to digi ~al converter U5 can do only one conversion at a time. rhe microprocessor U4 selects which 20 of the phases or neutral is to be converted, for example, in an orderly sequence of phase A, phase B, phase C and neutral.
Once the analog to digi tal conversion is performed on the phase A signal in its turn, the microprocessor reads ~5 out an 8-bi t value from converter U5, which corresponds to the voltage on the capacitor 130. In sequence, the micro-~rocessor reads and stores all of the values from converter U5 which were simultaneously input from the operational ampli fier U3. ~hereafter, under the influence of the pro-30 gram, the microprocessor U4 adds all four values taken fromphases A, B, C and neutral and calculates the ground fault current, if any. I f a ground fault current beyond a given magnitude is measured, the microprocessor puts out a signal to ini tiate the firing of thyristor 82. Note that the 35 microprocessor in performing the analysis will examine the ~5~
individual values to determine peak average value for the short time trip operation.
~ he microprocessor U4 also uses the measured val-ues as individual samples to calculate true RMS values for the long time over current trip function. Two hundred fifty-si~ samples are required to produce a single ~MS
value, In turn, several RNS values must be measured before a trip operation can be init~ated. rhe calculation of a single RMS value with ~he system of the present invention takes appro~imately 1.2 seconds.
Once the microprocessor decides for any reason to fire the thyristor 82, an output signal is applied to pin 30 (Pl-3) which signal is applied through U6 to the gate of thyristor 82.
Note that when the circuit is first started, a start conversion signal is needed. ~his start signal is taken from pin 29 of microprocessor U4. ~he end of conver-sion signal is produced by converter U5 at pin 7 which cau-ses the generation of a new start signal from the micro-processor pin 29 to start a new conversion signal.
~ he voltage reference signal from operational amp-lifier U7 is applied over line 272 to the pin 12 of conver-ter U5. rhe microprocessor U4 will make a decision as to whether this reference voltage should be high or low, de-pending UpOD the current value being measured during thefault condition. rhus, microprocessor U4 ~ill put out an appropriate signal on pin 30 through inverter U6 over line 160 in order to switch the Yoltage reference in the desired manner, thus producing the novel scaling operation of the present invention which has been previously described.
~ he circuit connected to pins 5 and 6 of micropro-cessor U4 contains resistors and capacitors which provide the necessary reset function. ~hus, when the breaker first ~ closes and the power supply ~ not yet reached its normal output, the reset will be held for appro~imatey 1 millisec-ond and until power is available.
~l~SS'78~
~ he operation of the microprocessor will be u~der the control of a suitable program. One program whlch has been used successfully is appended hereto.
Although the present inventlon has been described in connection with a preferred embodiment thereof, many variations and modifications will now become apparent to those skilled in the art. It is preferred, therefore, that the present inve~tion be limited not by the specific dis-closure herein, but only by the appended claims.
Claims (18)
PROPERTY OR PRIVIELGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A microprocessor based circuit breaker trip unit comprising, in combination:
a plurality of current transformers connected to corresponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plurality of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after said predetermined number of samples of a corresponding digital value;
a microprocessor means coupled to each of said analog-to-digital converters for computing a true RMS value of the current of each of said line from said predetermined number of samples;
and an output circuit means connected between said microcomputer and said trip mechanism for operating said trip mechanism in res-ponse to predetermined current conditions.
a plurality of current transformers connected to corresponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plurality of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after said predetermined number of samples of a corresponding digital value;
a microprocessor means coupled to each of said analog-to-digital converters for computing a true RMS value of the current of each of said line from said predetermined number of samples;
and an output circuit means connected between said microcomputer and said trip mechanism for operating said trip mechanism in res-ponse to predetermined current conditions.
2. The trip unit of claim 1, wherein said microcomputer is an 8-bit circuit.
3. The trip unit of claim 2, wherein said microcomputer further includes means for computing ground fault current from the simultaneous samples of current in said lines.
4. The trip unit of claim 1, wherein one of said lines is a neutral.
5. The trip unit of claim 2, wherein one of said lines is a neutral.
6. The trip unit of claim 2 or 5, wherein said micro-computer further includes means for computing ground fault current from the simultaneous samples of current in said lines.
7. The trip unit of claim 1 which further includes thermal memory means coupled between said lines and said analog-to-digital converter means; said thermal memory means producing an output related to the instantaneous thermal energy stored in said circuit breaker and circuit means coupling the digital output of said analog-to-digital converter, which is related to said output of said thermal memory means to said microcomputer for modifying the trip timing operating of said trip unit after said circuit breaker is closed, to account for its prior thermal history.
8. The trip unit of claim 7, wherein said thermal mem-ory means includes first, second and third thermistors fixed to the conductors of respective poles of said circuit breaker.
9. The trip unit of claim 1, wherein said sample and hold circuits include respective switch circuit means and res-pective capacitor means, whereby each time said lines are sampled, all of said switch circuit means for each of said lines simultaneously closes, and adds charge to its respective said capacitor means of a value related to the voltage signal amplitude during the sampling instant.
10. The trip unit of claim 1 wherein said trip mechanism includes a magnetic latch and a semiconductor switching device, said magnetic latch containing a latch operating winding which is connected in series with said semiconductor switching device, said semiconductor switching device having a control electrode connected to said output circuit means to be switched into conduction in response to a given output from said output circuit means; said winding consisting of a series connected large turn, high resistance section and a relatively low turn, relatively low resistance section; and bypass switching means connected from the node of said series connected sections to said semiconductor switching device whereby, when the output voltage in series with said winding and said switching device exceeds a given value, said bypass switching device conducts and short-circuits said large turn, high resistance section.
11. A microprocessor based circuit breaker trip unit comprising, in combination:
a plurality of current transformers connected to corresponding lines of a multiphase circuit which are connected to respective circuit breaker poles;
a trip mechanism energizable to open said circuit breaker poles;
respective signal conversion means connected to said plurality of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after each of said predetermined number of samples to a corresponding digital value;
a microcomputer means coupled to each of said analog-to-digital converters for computing a true RMS value of the currents of each of said lines;
an output circuit means connected between said micro-computer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions; and autoscaling circuit means connected to said microcomputer for dividing a given current range into a first small range and a second larger range in values of amperes per bit of said microprocessor.
a plurality of current transformers connected to corresponding lines of a multiphase circuit which are connected to respective circuit breaker poles;
a trip mechanism energizable to open said circuit breaker poles;
respective signal conversion means connected to said plurality of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after each of said predetermined number of samples to a corresponding digital value;
a microcomputer means coupled to each of said analog-to-digital converters for computing a true RMS value of the currents of each of said lines;
an output circuit means connected between said micro-computer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions; and autoscaling circuit means connected to said microcomputer for dividing a given current range into a first small range and a second larger range in values of amperes per bit of said microprocessor.
12. The trip unit of claim 11 which further includes thermal memory means coupled between said lines and said analog-to-digital converter means; said thermal memory means producing an output related to the thermal energy stored in said circuit breaker and circuit means coupling the digital output of said analog-to-digital converter, which is related to said output of said thermal memory means to said microcomputer for modifying the trip timing operation of said trip unit after said circuit breaker is closed, to account for its prior thermal history.
13. The trip unit of claim 12, wherein said sample and hold circuits include respective switch circuit means and respective capacitor means, whereby each time said lines are sampled, all of said switch circuit means for each of said lines simultaneously closes, and adds charge to its respective said capacitor means of a value related to the voltage signal amplitude during the sampling instant.
14. The trip unit of claim 12, wherein said thermal memory means includes first, second and third thermistors fixed to the conductors of respective poles of said circuit breaker.
15. A microprocessor based circuit breaker trip unit comprising, in combination:
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plurality of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after each of said predetermined number of samples to a corresponding digital value;
a microcomputer means coupled to each of said analog-to-digital converters for computing a true RMS value of the currents of each of said lines;
said microcomputer includes means for computing ground fault current from the simultaneous samples of current in said lines;
an output circuit means connected between said micro-computer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions and;
autoscaling circuit means connected to said microcomputer for dividing a given current range into a first small range and a second larger range in values of amperes per bit of said microcomputer.
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plurality of current transformers for converting the current output of said current transformers to respective voltage signals;
respective sample and hold circuits for repetitively and simultaneously sampling and holding sample analog values of each of said voltage signals for a predetermined number of samples;
analog-to-digital converter means connected to each of said respective sample and hold circuits for converting the analog value produced in said sample and hold circuit after each of said predetermined number of samples to a corresponding digital value;
a microcomputer means coupled to each of said analog-to-digital converters for computing a true RMS value of the currents of each of said lines;
said microcomputer includes means for computing ground fault current from the simultaneous samples of current in said lines;
an output circuit means connected between said micro-computer and said trip mechanism for operating said trip mechanism in response to predetermined current conditions and;
autoscaling circuit means connected to said microcomputer for dividing a given current range into a first small range and a second larger range in values of amperes per bit of said microcomputer.
16. A process for operating the trip unit of a multi-pole a-c circuit breaker which protects a circuit having a plurality of a-c lines; said process comprising the steps of producing a current signal for each of said lines which is pro-portional to the instantaneous current in said line; converting each of said current signals to respective voltage signals which are proportional to said current signals; simultaneously, and repetitively measuring the amplitudes of each of said voltage signals for relatively short sampling time, converting the analog value of the amplitudes of said voltage signal to a digital value; and separately calculating the true RMS
value of each of said voltage signals by taking the square root of the sum of the squares of each of the digital values measured.
value of each of said voltage signals by taking the square root of the sum of the squares of each of the digital values measured.
17. A trip unit for a circuit breaker comprising, in combination:
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plurality of current transformers for converting the current out-put of said current transformers to respective voltage signals;
an output circuit means connected between said current transformers and said trip mechanism for operating said trip mechanism in response to predetermined current conditions;
said trip mechanism including a magnetic latch and a semiconductor switching device; said magnetic latch containing a latch operating winding which is connected in series with said semiconductor switching device;
said semiconductor switching device having a control electrode connected to said output circuit means to be switched into conduction in response to a given output from said output circuit means;
said winding consisting of a series connected large turn, high resistance section and relatively low turn, relatively low resistance section; and bypass switching measn connected from the node of said series connected sections to said semiconductor switching device whereby, when the output voltage in series with said winding and said switching device exceeds a given value, said bypass switching device conducts and shortcircuits said large turn, high resistance section.
a plurality of current transformers connected to corres-ponding lines of a multiphase circuit which are connected to respective poles of said circuit breaker;
a trip mechanism energizable to open said poles of said circuit breaker;
respective signal conversion means connected to said plurality of current transformers for converting the current out-put of said current transformers to respective voltage signals;
an output circuit means connected between said current transformers and said trip mechanism for operating said trip mechanism in response to predetermined current conditions;
said trip mechanism including a magnetic latch and a semiconductor switching device; said magnetic latch containing a latch operating winding which is connected in series with said semiconductor switching device;
said semiconductor switching device having a control electrode connected to said output circuit means to be switched into conduction in response to a given output from said output circuit means;
said winding consisting of a series connected large turn, high resistance section and relatively low turn, relatively low resistance section; and bypass switching measn connected from the node of said series connected sections to said semiconductor switching device whereby, when the output voltage in series with said winding and said switching device exceeds a given value, said bypass switching device conducts and shortcircuits said large turn, high resistance section.
18. A method of operating a circuit breaker trip unit with the use of a microprocess comprising the steps of:
providing said microprocessor with predetermined current data for said trip unit;
initiating a sample interval timer in said microprocessor upon the start or the sampling period to sequence the samples taken by a plurality of sample and hold circuits;
constantly determining the voltage of each sample and hold circuit at the end of each sample interval;
constantly providing the microprocessor with a digitally converted signal voltage and current samples until the end of the sampling period;
repetitively storing in the microprocessor the sampled current value for 1100 sample times to calculate the total current during the sampling period;
repetitively comparing in the microprocessor the sample time calculated with the root-mean-square equation and said elapsed time; and opening the circuit breaker trip unit when the calculated true RMS value indicates an occurrence of at least a predetermined current condition.
providing said microprocessor with predetermined current data for said trip unit;
initiating a sample interval timer in said microprocessor upon the start or the sampling period to sequence the samples taken by a plurality of sample and hold circuits;
constantly determining the voltage of each sample and hold circuit at the end of each sample interval;
constantly providing the microprocessor with a digitally converted signal voltage and current samples until the end of the sampling period;
repetitively storing in the microprocessor the sampled current value for 1100 sample times to calculate the total current during the sampling period;
repetitively comparing in the microprocessor the sample time calculated with the root-mean-square equation and said elapsed time; and opening the circuit breaker trip unit when the calculated true RMS value indicates an occurrence of at least a predetermined current condition.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US655,152 | 1984-09-27 | ||
| US06/655,152 US4631625A (en) | 1984-09-27 | 1984-09-27 | Microprocessor controlled circuit breaker trip unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1255782A true CA1255782A (en) | 1989-06-13 |
Family
ID=24627739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000491504A Expired CA1255782A (en) | 1984-09-27 | 1985-09-25 | Microprocessor controlled circuit breaker trip unit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4631625A (en) |
| EP (1) | EP0179017A3 (en) |
| JP (1) | JPS61224228A (en) |
| CA (1) | CA1255782A (en) |
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|---|---|---|---|---|
| JPS4118427Y1 (en) * | 1964-03-11 | 1966-08-27 | ||
| JPS5087759A (en) * | 1973-12-07 | 1975-07-15 | ||
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| JPS5952383B2 (en) * | 1975-09-23 | 1984-12-19 | 株式会社横河電機製作所 | RMS conversion circuit |
| JPS54137649A (en) * | 1978-04-18 | 1979-10-25 | Tokyo Electric Power Co Inc:The | Digital protective relay device |
| US4250532A (en) * | 1979-02-12 | 1981-02-10 | Gould Inc. | Electronic overcurrent detection and tripping circuit |
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| US4377837A (en) * | 1980-04-15 | 1983-03-22 | Westinghouse Electric Corp. | Circuit interrupter with overtemperature trip device |
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| US4347541A (en) * | 1981-01-14 | 1982-08-31 | Gte Laboratories Incorporated | Circuit breaker |
| DE3137496C2 (en) * | 1981-09-21 | 1990-01-25 | Siemens AG, 1000 Berlin und 8000 München | Digital overcurrent release |
| JPS5876910A (en) * | 1981-10-30 | 1983-05-10 | Konishiroku Photo Ind Co Ltd | Abnormal state detecting device |
| US4423459A (en) * | 1982-04-05 | 1983-12-27 | Siemens-Allis, Inc. | Solid state circuit protection system and method |
| US4432031A (en) * | 1982-05-03 | 1984-02-14 | General Electric Company | Method for overcurrent protection |
| US4550360A (en) * | 1984-05-21 | 1985-10-29 | General Electric Company | Circuit breaker static trip unit having automatic circuit trimming |
-
1984
- 1984-09-27 US US06/655,152 patent/US4631625A/en not_active Expired - Lifetime
-
1985
- 1985-09-25 CA CA000491504A patent/CA1255782A/en not_active Expired
- 1985-09-27 EP EP85730133A patent/EP0179017A3/en not_active Ceased
- 1985-09-27 JP JP60214452A patent/JPS61224228A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61224228A (en) | 1986-10-04 |
| US4631625A (en) | 1986-12-23 |
| EP0179017A2 (en) | 1986-04-23 |
| EP0179017A3 (en) | 1987-04-22 |
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