CA1258894A - Sequential data transmission system - Google Patents
Sequential data transmission systemInfo
- Publication number
- CA1258894A CA1258894A CA000475716A CA475716A CA1258894A CA 1258894 A CA1258894 A CA 1258894A CA 000475716 A CA000475716 A CA 000475716A CA 475716 A CA475716 A CA 475716A CA 1258894 A CA1258894 A CA 1258894A
- Authority
- CA
- Canada
- Prior art keywords
- parallel
- data
- channel element
- digital data
- operatively connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
Abstract
ABSTRACT OF THE INVENTION
The present invention relates to a data transmission system, for transmitting information from a first end-user device to a second end-user device, which comprises a plurality of channel elements, each channel element having an input and an output terminal adapted to receive and transmit, respectively, serial digital data having a predetermined format. Each channel element also has a plurality of parallel input terminals and a plurality of parallel output terminals adapted to receive and transmit, respectively parallel digital data. The parallel output terminals of each of the channel elements is operatively connected to the parallel input terminals of a next adjacent channel element thereby connecting the channel elements in a ring configuration. Each channel element receives the serial digital data from a plurality of associated end-user devices and transmits the serial digital data in parallel to the next adjacent channel element until the parallel digital data has traversed the entire ring, at which time newly received serial digital data at each channel element is inserted onto the ring.
The parallel digital data transferred around the ring is examined by each channel element to extract the parallel digital data determined to be addressed to the channel element.
The present invention relates to a data transmission system, for transmitting information from a first end-user device to a second end-user device, which comprises a plurality of channel elements, each channel element having an input and an output terminal adapted to receive and transmit, respectively, serial digital data having a predetermined format. Each channel element also has a plurality of parallel input terminals and a plurality of parallel output terminals adapted to receive and transmit, respectively parallel digital data. The parallel output terminals of each of the channel elements is operatively connected to the parallel input terminals of a next adjacent channel element thereby connecting the channel elements in a ring configuration. Each channel element receives the serial digital data from a plurality of associated end-user devices and transmits the serial digital data in parallel to the next adjacent channel element until the parallel digital data has traversed the entire ring, at which time newly received serial digital data at each channel element is inserted onto the ring.
The parallel digital data transferred around the ring is examined by each channel element to extract the parallel digital data determined to be addressed to the channel element.
Description
~ZS8~39~
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~ he pre~ent inven~ion relate6 to a transmi~ion system, and more particularly, to a digit~l tr~n~mission ~ystem for transmitting packets of information over a loop between devices 10 coupled to the 130p.
In tran~mi sion ~y6tem~ having a plurallty o~ devices, such a~ telephone~, terminals, controllers and proces~ors coupled to a transmis~ion carrier, ~ome form of dialog or communication exchan~e generally takes place between these device~ vi~ the 15 tran~mission carrier. In order to provide for an orderly exchange of information between devicefi~ variou~ networ architectures and ~cheme~ have been devifieds however, many o~ the exi~ting ~ran~ml~ion ~yatems are complex, lnefficient, and require large amounts of co~plex hardware. Thi~ i~ especially true with transmission 8y8tem8 u~ilizing packet switching schemes. Such schemes require the use of at least one ho~t p~oce~or, a nunber of communication proce~sor~ (or front end processors), the ~oftw~re a~soci~ted with each of the proces~or~
- which is generally very large and very complex, and communication interace deYices which interface or couple a u~er device with the transmis~ion carrier, The transmission carrier generally tranC~er~ the in~ormation in a berial fa~hion.
~ 1--CS01~704 02/20/84 ~ Z S~ ~9~
Hence, it is highly desirable to provide a 'cransmis~ion 8y8tem for interdevice co~munication which i5 high speed and overcomes the di6advantage~ and limitations of the existing ~ystems. The data transmission ~ystem of the present invention transfers packets of information in a parallel fashion via a ring, which ~orms the transmission carrier of the present invention, thereby overcoming the capacity of speed limitations of the pre~ent ~witching network schemes.
1 0 =~9~
Therefore, there iE supplied by the present invention a data transmission ~ys~em implementing a communica~ions scheme between a plurality of devices. The data transmission system which tran~mit~ information from a first end-user device to a second end-user device comprises a plurality of channel elements, each channel element having an input and an output terminal adap~ed to receive and tran~mit, respectively, ~erial digital data having a predetermined f ormat. Each cha~nel element al80 has a plurali~y of parall~l input terminals and a plurality of parallel output terminals adapted to receive and transmit, respectively, parallel digital data. The parallel outpu~ terminals of each of the channel el~ments i8 operatively connected to the parallel input terminal~ o~ a next adjacent channel element thereby connecting the channel elements in a ring configura ion~ Each channel element receives the ~erial digital data ~rom a plurality of C50~0704 02/20/84 ~5~
-3- 6~159-791 associated end~use~devices and transmits the serial digital data in parallel to the next adjacent channel element until the parallel digital data has traversed the entire ring, at which time newly received serial digital data at each channel element is inserted onto the ring. The parallel digital data transferred around the ring is examined by each channel elem-ent to extract the parallel digital data determined to be addressed to the channel element.
~ccordingly, it is an object of the present invention to provide a transmission system for transferring information between devices.
It is still another object of the present invention to provide a transmission system for transferring information between devices coupled to a transmission carrier.
It is a further object of the present invention to provide a transmission system for transferring information between devices coupled to a transmission carrier, wherein the transmission carrier is in the form of a parallel ring.
In accordance with the present invention, there is provided a data transmission system, for transmitting information rom a first end-user device to a second end-user device, comprising: (a) a plurality of channel elements, each channel element having a first input and a first output terminal adapted to receive and transmit, respectively, serial digital data having a predetermined format, the first input and first output terminals of each channel element being ~3 ~ ~2~8~9~
operatively connected to at least one corresponding end-user device, and each channel element further having a plurality of second input terminals and a plurality of second output term-inals adapted to receive and transmit, respectively, parallel digital data, wherein said channel element compriseso (i) router means, operatively connected to said second input terminals and operatively connected to said second output ter-minals, and further operatively connected to said ~irst term-inal, for coupling a new block of serial digital data onto said second output terminals at a predetermined time, other-wise coupling the parallel digital data received on said second input terminals to said second output terminals, and further examining the parallel digital data received on said second input terminals to generate a control signal when the parallel digital data is addressed to the channel element;
(ii) memory means, operatively connected to said second out-put terminals, for storing the parallel digital data on said second output terminals in response to the control signal gen-erated by said router means; and (iii) converter means, operatively connected to said memory means and operatively connected to said f irst output term-inal, for converting the parallel digital data stored in said memory means to serial digital data having said predetermined format, the serial digital data being coupled to said output first terminal; and (b) a plurality of parallel data lines, wherein each of said parallel data lines operatively connects the second output terminals of one oE said channel elements to the second input terminals of a next adjacent channel element, thereby connect ing the channel elements in a ring configuration forming a , ~3~ 1258~
ring, for causing the serial digital data received by each channel element from the corresponding end-user device to be transmitted in parallel around the ring, each channel element causing the data received via the second input terminals to be outputted serially on the first output terminal when it is determined that the data contains an address corresponding to the channel element.
In accordance with the present invention, there is further provided a data transmission system, for transmitting information from a first end-user device to a second end user device, comprising: a plurality of channel element means, each channel element means having a first input and a first output terminal adapted to receive and transmit, respectively, serial digital data having a predetermined format, and each channel element means further having a plurality of second input term-inals and a plurality of second output terminals adapted to receive and transmit, respectively, parallel digital data; and wherein the second output terminals of each of said channel element means is operatively connected to the second input terminals of a next adjacent channel element means thereby connecting the channel element means in a ring configuration forming a ring, each channel element means for receiving said serial digital data from a plurality of associated end-user devices and transmitting the serial digital data in parallel to the next adjacent channel element means until the parallel digital data has traversed the entire ring at which time newly received serial digital data at each channel element means is inserted onto the ring, the parallel digital data transferred around the ring being examined by each channel element means to extract the parallel digital data determined to be -3~ S~8~
addressed to it, wherein said channel element means comprlses:
(a) router means, operatively connected to said second input terminals and operatively connected to said second output ter-minals, and further operatively connected to said irst input terminal, for coupling a new block of serial digital data onto said second output terminals, otherwise coupling the parallel digital data received on said second input terminals to said second output terminals, and further examining the parallel digital data received on said second input terminals to deter-mine whether the parallel digital data addressed to the chan-nel element means is to be extracted;
(b) memory means, operatively connected to said second output terminals, for storing the parallel digital data extracted by said router means; and (c) converter means, operatively connected to said memory means and operatively connected to said first output terminal, for converting the parallel digital data stored in said memory means to serial digital data having said predetermined format, the serial digital data being coupled to said first output terminal.
In accordance with the present invention, there is further provided a data transmission system, for transmitting information ~rom a sending end-user device to a receiving end-user device, comprising: a plurality of channel elements connected in a ring configuration forming a xing, each channel element having a Eirst input terminal and a irst output term-inal for receiving and transmitting, respectively, serial information, the serial information having a predetermined format which includes data and address information of the _3~ Z5~4 receiving end-user device, and while the serial information i8 being received by each channel element from corresponding end-user devices operatively connected thereto, a block of parallel data is being transmitted in parallel by each channel element to a next adjacent channel element, said block of parallel data being a predetermined ~uantum of serial infor-mation, such that when the block of parallel data has traversed the entire ring a new block of parallel data made up of newly received serial information is completed loading into each channel element, and said new block of parallel data of each channel element is transferred around the ring, and fur-ther, while the block of parallel data is being transmitted around the ring, each channel element extracts parallel data which it determines it is addressed to it, wherein each chan-nel element compriseæ:
(a) router means, having a plurality of second input term-inals adapted to receive the block of parallel data and having a plurality of second output terminals adapted to transmit the block o~ parallel data, and operatively connected to said first input terminal, for coupling said new block of parallel data onto said second output terminals at a predetermined time, otherwise coupling the block of parallel data received on said second input terminals to said second output term-inals, the block of parallel data received on said second input terminals being examined to determine whether to extract the block of parallel data received by the channel element;
(b) memory means, operatively connected to said second output terminals, for storing the block of parallel data as deter-mi~ed by said router means; and (c) converter means, operatively connected to said memory ~3~ S 8 ~9 ~
means and operatively connected to said first output terminal, for converting the block of parallel data stored in said memory means to serial information having said predetermined format, the serial information being coupled to said first output terminal.
These and other objects of the present invention will become more apparent when taken in conjunction with the following description and attached drawings, wherein like characters indicate like parts, and which drawings form a part of the present application.
i~
~ .
~s~s~a Fig. 1 ~how~ a functional block diagram of the preferred embodiment of the tran~mifision system of the present invention;
Fig. 2 shows the format of the information transmitted, in ~he preferred embodiment of the present invention, via a link be~ween a concentrator and a central router;
Fig, 3 show~ a functional block diagram of a channel elemen~
of the preferred embodi~ent of the present invention;
Fig/ 4 shows a timing diagram of data beiny transmitted aroun~ a loop of the present invention;
Fig. 5 shows a functional logic block diagram of a router of the preferred embodimen~ of the pre~ent invention;
Fig. 6 ~hows a logic block diagram of the memory elements of the channel element of the preferred embodiment of the present invention;
Fig. 7 show~ a logic block diagram of the read logic of the memory element~ of the preferred embodiment of the present invention, and Fig. 8 ~how~ a timing di~gram of the read logic of the memory 20 element~ of ~ig. 7.
C5010~0~ 02/20/84 .~2~889~1L
~C~E~
Figure 1 shows a functional block diagram of the preferred embodimen~ of the transmis~ion system of the present invention, A central router 10 contains a plurality o~ channel elements 20, 20 ', 20 ", connected in a ring conf iguration via a loop 26 .
(NOTE: There exists a difference between a ring and a loop. The difference between a loop and a ring is that a loop generally uses s~IIL~ ~d control (with one station ac~ing a8 a polling primary and the others as ~econdaries), while a ring uses Li~ k~ control (with all station sharing control as peers). On a loop, generally the ~econdaries do not communicate with each o~her: traffic i8 exchanged only between the primary and secondarie6. On a ring, any station can communicate directoy with any other station. Although the term ring and loop are used interchangeably herein, it will be apparent that the present invention operates as a ring~ Each channel element (C~A~ ELE~) 20 has it~ output connected to the input o~ the next channel element 20' in the loop; hence, the output of channel element ~1 20 i~ connected to the input of channel element ~2 20', ..., the output of channel element ~80 ~not: shown) iB connected ~o the input of channel element ~81 20 ", and ~inally the output of channel element #81 20 " is connected to the input o~ channel element ~1 200 The control element (CONTROL) 22 generates the clocking signal~ tCLR), and timing ~ignal~, including CLR81 which 2S form~ the synchronizing signal, SYNC. Each channel element 20 inter~aces with a corresponding concentrator 30 (or sometimes ~ 2 S~
referred to as herein as the formatter). Thus, channel element ~1 20 interfaces with concentrator (CONC) ~1 30, channel element #2 20' interfaces wi~h concentrator ~2 30', ..., and channel element ~81 interfaces with concentrator t81 30~O The interface between the respective channel elements 20 and concentrators 30 i~ via a corresponding link 32, 32', 32'l. The central router 10 inter~aces with each link 32, 32', 32 " via the corresponding port 24, 24', 24 ". Each port 24 of the central router 10 also has a port number which corresponds to the channel element number. Thus, channel element ~1 interfaces with port 1, channel element t2 interfaces with port 2, ..~, and channel element #81 in~erfaces with port 81. Each concentrator 30 interface~ with a plurality of end user devices (or more simply devices) such as telephones, terminals, processors, computers, (not shown) ....
Each concentrator 30 formats the data received from the end user device~ attached ~hereto into a predetermined format for transmission to its respective channel element 20, and further causes data received from the channel element 20 to be transmitted to a speci~ied destinat~on end user device. CL~l is coupled to each concentrator 30 to permit the concentrator 30 to eynchronize the data ~ran6mitted to its corresponding channel element 20. The conc~ntrator 30 append a destination address to packets ori ginating f rom sources not having the capability of attaching the destination address. The concenta~ors 30 may take many forms depending upon the da~a devices coupled to the concentrator, one form including a microprocessor. Concentrators ~5010704 02/20/84 1258~g~
are generally well known in the art and wiil not be di~cu~sed further since it forms no part of the present invention and is not necefi~ary for an understanding of the precent invention.
Referring to Yigure 2, there is shown the formats of the information transmitted via links 32 to and from the concentrators 30. Two formats are utilized by the preferred embodiment of he pre~ent invention, format 1 being ~hown in Fig.
2A and format 2 being shown in Fig. 2B. Each format can be though~ of as an 81 bit word. ~it 0 i the multiplex data bit 10 which defin2s the format. If bit 0 is a 1, then format 1 word is defined. If bit ~ is a ~ then forma~ 2 i8 defined, The format 1 word is divided into three fieldz of 27 bit~ each, field ~ (or data 0) i8 contained in bit ~ - ~6, field 1 (or data 1) is contained in bits 27 - 53, and field 2 (or data 2) is contained in bits 54 - 80. When a 1 is present in bit 0 defining format 1 and the addre6~ portion cnntains a valid address, data is contained in at least field p. Data may or may not be present in fields 1 and 2. Thu~, for format 1 data, bits 27 and 54 are utilized to define if data i8 present in the re~pec~ive ~ield~.
A one in bi~ 27 will indicate if data is present in field 1, and a one in bit 54 will indicate data is pre6ent in ~ield 2. For field 0, bit~ 1 - 16 indicate the destination addres~ for the data contained in bits 17 - 26. Likewise, for field 1, bit~ 28 -43 indicate the destination address for the data contained in bits 44 - 53 and for field 2, bits 55 - 70 indi~ate the destination address for the data contained in bit~ 71-80. For ~ 9 ~
format 2 word~, bite 1 - 16 indicate a destination addres6 for the data contained in bits 17 - 80. For both formats 1 and 2, the address por~ion i~ divided into a port addres~ portion ~bits 1 - 7) and a device addre~ portion (bits 8 - 16), the port addrees being utilized by the central router 10 to cause the data to be transferred to the correct port 24 and the device address being utilized by the concen~rator 30 to transmit the data ~o the addre~ed device. Since a format 1 or format 2 word is transmitted via link 32 every 81 clock period~ in the preferred embodiment of the present invention, there can be times when no data is present. No data i~ indicated by a NULL charac~er which, in the preferred embodiment of ~he pre~ent invention, is a predetermined invalid port address.
Referring to Fig. 3, there i~ shown a functional block cliagram of the channel element 20 of the preferred embodiment of the present invention. The channel element 20 is comprised of a router element 200 and a memory elemen~ 202. The roun~er element 200 of a preferred embodiment of the present invention i~
comprised of 3 router chip~ ~or more 8i~ply router) RC0 201, RCl 201' and RC2 201''. ~ach router 20:L is coupled to receive input data from th~ previous channel equipment 20 from the respective 27 data lines 26l, 26 " , 26 "', whlch in part comprise the loop 26. The router el~ment 200 al~o receive serial data from the concentrator 30O In the preferred embodlment of the present inv~ntion the ~erial data is shi~ted into the ~outer chip~ 201 ~uch tha~ a~ter 81 clock cycles the fir~t 27 bit~ of the data ~S3~39~
word will re~ide in RCp 201, the next 27 bits of the data word will re5ide in RCl 201', and the laRt 27 bits of the data word will reside in RC2 201 ". Since each field of the format 1 data word is 27 bits, each route chip 201 will have stored therein a single field o~ data.
~ t the end of 81 clock cycle~ the router chip 201 select6 the data residing in the router chip 201 ju~ received from the concentrator 30 and place~ tha~ data on the loop 26. Thus, 81 bits of serial data just received i~ tran~mitted on loop 26 in parallel as a block of data. The data is shifted in parallel to the next channel element 20 each clock cycle (or clock period).
At the ~nd of 81 clock cycle~ the data will have looped back to the router chip 201 which originally placed the data on the loop~
at which ~ime new data is placed on the loop by the router chip 201. During the 6hifting of data around the loop 26, the router chip 201 i~ decoding the port address portion (bits 1 - 7) of the destination addre~ portion (bi~s 1 - 16) of the data word. If the port addre~s indicates an addresR for that channel element 20, the data i8 transferred to the memory element 202. Memory element 202 of the preferred embodiment of the presen~ invention i~ comprised of thre2 FIFO memoriezv memory ~ 203, memory 1 203' and memory 2 203'l. Memory ~ 203 is operatively coupled to the 27 output data lines 26' of router chip 201, memory 1 203' is operatively coupled to the 27 output data lines 26 " o~ ~Cl 201', and memory 2 203 " iB opera~ively coupled to ~he 27 output data l~ne~ 26''l of RC2 201''. The output o~ memory ~ 203, memory 1 - ~Z5i~38~
203', and memory 2 203 " is coupled to a multiplexer (MUX) 204 which sequentially read~ the data from each memory. The output of the MUX 204 is coupled to a parallel/~erial converter 205 which transmits the data (SERIAL DATA OUT) to the concentrator 30.
Although the preferred embodiment shows 81 channel elements 20, the data word format i8 compri ed of 3 data fields, the router chip 201 is divided to handle 27 bits and interfaces with a corresponding memory unit, i~ will be understood by those skilled in the art that other combina~ions may be implemented without departing from ~he true spirit and ~cope of the present invention.
The data tran~mission around the loop 26 is de~cribed in further detail below in conjunction with Fig~ ~. Referring to Fig. 4, the clock ~ignal CLR is shown, along with timing signals CLRl, CLK2, and CLK81. Timing signal CLRl define~ the firs~ time period, or s~art of a complete transmission cycle, the complete tran~mission cycle comprising 81 clock pèriods. During the fir~t clock period, data received from concentrator ~1 by channel element #1 is inserted onto the loop 26 via the router element 200 associated with channel element ~ ikewise data received f rom concentra~or ~2 by channel element #2 i5 inserted onto the loop 26 via the router element 200 associated with the channel element ~2, and 90 on. Thufi, the data received via the channel element rom it6 respective concentrator is in~erted onto the loop via the router element associated with the respective C501070~ 02/20/84 ~L~58~9~
channel element. During each clock period, the data contained in each channel element i~ tran~mitted to the next channel element, i.e., the channel element connected to the outputs of the channel element in the loop configuration. Therefore, during clock period 2, channel element ~1 receives the concentrator 81 data, channel element ~2 receive~ the concentrator ~1 data, ... and finally the channel element 81 receives the concentrator 80 data. Likewise, during clock period 3, channel element ~1 receives the concentrator 80 data, which was the data contained in channel element ~81 during clock period 2. As can be ~een from the Fig. 4, the data from concentrator ~1 i. transmi~ted to each channel element in the loop during each re~pective clock period until finally ~he concentra~or 1 dat~ has reached channel element ~81 during clock period 81. Likewi~e, the data ~rom every concentator ha~ traversed the loop in the 81 clock period~
forming a complete transmission cycle~ Qn the next clock period the transmi sion cycle repea~s i~self with the da~a received by each router element 200 inserted onto the loop during clock period 1. During ~he 81 clock periods that the data is 20 traversing the loop, the next data Erom the concentrator i8 being loaded into the respective router element 200, the loading proce~s which will be discussed in further detail hgreinunder.
Re~errin~ to Fig. 5, there i~ ~hown a functional logic block diagram of the router chip 201 of the preferred embodiment of the present invention. The DATA IN terminal provide~ for the inputting of 27 da~a lines (26', 26 " ~ or 26 "') o~ loop 26. The C501070~ 02/20/84 i ~ 5~ ~9~
data transmitted around the loop 26 i~ held in a loop latch 301 during a clock perlod. AB de~cribed above a SERIAL DATA IN
terminal receiv~s data ~rom the associated concentr~tor 30, the serial data having the format a8 described abo~e. The serial data is shifted into a ~erial/parallel (S/P) converter 302, which in the preferred embodiment is a 27 bit wide register. A SERIAL
DATA OUT terminal of S/P converter 302 of RC2 201 " is coupled to the next router chip RC1 201', and likewise the SERIAL D~TA OUT
of the n~x~ router chip 201' i~ coupled to 8till another router chip RC0 201, thereby achieving a cerial to parallel conver~ion of 81 bits wide sufficient to handle a data word of the t~an~mi~ion ~ystem of the pre~ent invention. As discu~ed above, in the preferr~d embodiment of the present invention, the router element 200 is implemen ed with three router chips 201, each router chip 201 of the router element 200 handling 27 of the 81 ~it da~a word. A~ter 81 clock periods, the serial/parallel conver~er 302 of each router chip 201 cont~ins the correct 27 bits of a data word an~ is trans~erred in parallel into an input latch 303. The output of the input la~ch 303 and the output of the loop latch 3~1 are coupled to an OUTPUT MUX 304. The output of the OUlP~T MUX 304, DATA O~JT i ( i 0 f or RC,0 ~01, i = 1 f or RCl 201'~ and i = 2 for ~C2 201 "3, is ~he data from loop latch 301. ~owever, at the end of the 81st clock period as discussed above, the OUTPUT MUX 304 i~ switched to selec~ the data ~rom the input latch 303 r thereby inserting the data received f rom the ~ssociated concentrator 30 and the tran~mission of the received data around the loop 26 i~ started.
l~S~3~9'~
Each router element 200 ha~ an ID number which i~ a~sociated with the channel elem~nt 20. Thus, channel element ~1 has an ID
of 1 , ch~nnel elemenk ~2 has an ID of 2 , . ~ ., and channel element ~81 has an ~D of 81. This ID al60 correspond~ to the port 5 number.
Each router chip 201 of a router element 200 has the ~ame ID
wired in. Thus, RCp, RCl, and RC2 for router element 200 a~sociated with channel element tl has an ID o~ , and RC0, RCl, and RC2 for router elemen~ 200 associated with channel element ~81 has an ID of 81. The ID is inputted to a fir~t input of a first comparator 305 and the fir~t inpu~ of a second comparator 30fii The second input of ~ir~t comparator 305 is operatively connected to the output of input latch 303. The ~econd input of second comparator 306 i~ operativaly connected to the output of loop latch 301. During clock periods~ 2-81 the output of second comparator 306 will output a write control ~iynal when the port address portion o~ the data word in the loop latch 301 is equal to the ID. During clock period 1 the output of fir~t comparator 305 will ou~put a writ~ control signal when the port address portion of the data word in input ~atch 303 is equal to the ID. This permits da~a just written in the input latch 303 ~rom the as~ociated ~/P convester 302 and concentrator 30 to be elected when the data is addLessed to tha~ port. The output of first comparator 305 and the outpu~ of second comparator 306 i coupled to the DATA MUX 307 which ~;elects the output of tha comparators in accordance with the clock period, C~010704 0~/20/8 ~58i~4 thereby insuring the proper generation of the write control signal. The output of data MUX 307 i5 the MEMORY W~ITE signal tWRi). That data is then wri'c'cen into the memory element 202 for subsequent tran~mission to ~he concentrator 30.
The extrac~ion of the data from the loop 26 will now be described in conjunction with Fig. 6. Router element 200 of the preferred embodiment is shown comprising the three router chips RC0 201, RC1 201' and RC2 201 " , and as de~cribed above the output of the router chips is DATA0, DATAl, and DATA2, re~pectively. Also, each router chip 201 outputs a write control signal WR~, WR1, and ~2. DATA0 compri~es the bits ~ - 26 of the data word, DATAl compri~e~ bits 27 - 53 of the data word and DATA2 comprises bit~ 54 - 80 of the data woxd. DATA0 is transmitted on ~he fir~t 27 data lines 26 ' o:E loop 26, DATAl is transmitted on the second 27 data lines 26 " of loop 26, and DATA2 is transmitted on the ~hird 27 data line~ 26 ' " of loop 26. DATA0 is coupled to memory ~ 203, DATAl iE coupled to memory 1 203 ', and DATA2 is coupled to memory 2 203''. RAM 402 of ~he preferred embodiment of the present invention can be comprised o~
Monolithic Memorie~ integrated ci~cuit chip 67401.
~ach memory unit 203 contain~ a MUX 401 and a 27 bit wide RAM
402. The ~one" input of PlUX0 401 i~ coupled to D~TA~, the "one"
input of MUXl 401' is coupled to DAT~l, and the ~one~ input o~
MUX2 ~01 " is coupled to DATA2. ~he ~zero~ inpu~ of MUX 401 i5 a null character which i~ switchable into the port addre~s portion of the addre~s field. ~ence, for MUX~ 401 the null character is ~14-C5010704 02/~0/8 :~LZ5~3~39~
switchable into bit~ 1-7, for MUXl 401' the null character is ~witchable into bit~ 28-34, and for MUX2 401 " the null character is switchable into bits 55-61. The ~one~ input of the MUX 401 i~
fielected when the control input C i8 a logic 1. The output of each MUX 401 i8 coupled to the data input D of the respective RAM
402. ~owever, no data is written into the RAM 402 unless a write control signal is pre~ent at the write terminal WRT of the RAM
402.
The write control ~ignal for the RAM 402 is generated by the remaining logic of memory 203 shown in Fig. 6. A null character of the preferred embodiment of the present inven~ion iR an invalid address, i.e., bit 1 and bit 2 of a 7 bit field i8 a logic 1 ~ignifying a port address of 96. Since comparators 305, 306, o~ e~ch router chip 201 inhibit the generation of the corresponding write control signal for invalid addresses, no check i8 performed on bit~ 1 and 2 by the logic of the memory 203 in the preferred embodiment of the present invention. For a format 2 data word, bit ~ is a logic p which is coupled to an inverting input of gate 405. If the port adddre6~ portion of the data field in router element 200 equal~ the ID, RC0 201 generates the write address signal WR~ which ully qualifies ~ND gate 405.
The output of AND gate 405 i8 coupled to OR gatQ 406 and to OR
gate 407 of memory 0 203, to OR ga~e 410 and to OR gate 411 of memory 1 203', and to O~ gate 420 and to OR gate 421 of memory 2 203 ". As a result of the output of AND gate 405 ~eing a logic 1, each MUX 401 select~ the respective data input and the ~RT
5 ~ ~g ~
input of eaoh R~M 402 i8 enabled thereby writing the full 81 bit data word ~hat is ~hen present on the loop 26 into memory element 202.
When a format 1 aa~a word is pre~ent on loop 26, bit 0 is a logic 1~ AND gate 409 will be partially enabled, and gate 405 will be di8abled. (Bit ~ ic coupled to AND gate 409, to AND gate 412, and to AND gate 422.) If DATA0 has a port address of the channel element (field 0 of a forma~ word 1 ha~ the port addre s of ~he channel element) WR0 will be a logic 1, and AND gate 409 will be fully enabled thereby causing MUXp ~01 to selec~ DATAp, and further cau~ing write signal to be present at ~AM~ 402. The write ~ign~l will al~o be present at RA~l 402' and RAM2 402 ".
However, if bit 27 is not a logic 1 and ~he write signal WRl is not present (that is not a logic 1), AND gate 412 will not be enabled cau~ing a null character to be written into RAMl 402'.
~imilarly, AND gate 422 will cause the null character to be writ~en into RAM2 402' ' if the addre#s portion of field 2 (or DA~A2) is not equal to the channel element number, and the data present bit~ bit 54, i8 not a logic lo If, for a ~ormat 1 da~a word field 0 has valid data but does not contain the port address number o~ the channel element, WR0 will be a logic 0 and ~h~ output of AND gate 40g will be a logic p~ ~ence, MUXp 401 will select th~ null character. No writing into RAM~ 402 will occur unles~ there i8 a write into the other RAMS. Further, if field 1 contains valid data (bit 27 is a logic 1) and al80 contain~ the port address of the channel element, 8~
then WRl will be a logic 1 enabling AND gate 412. Thiæ cause~
memory 1 to select data 1. Since the output of AND gate 412 is coupled to OR gate 411, OR gate 421, and OR gate 407, a write operation will occur for RAM0, RA~l, and RAM2. However, only RAMl 402' will extract the data (D~Al) from data lines 26'' and be written into RAMl 402'. RA~0 and RAM2 will write the null character.
Similarly, for a format 1 data word, if field 2 contains valid data and also contains a port addre~ of the channel element, DATA2 will be written into RAM2 and a null character will be written into RAM0 and RAMl. However, if ~he port address of the channel element i~ contained in more than one field, tho~e fields will generate the corre~ponding WRi and ~he da~ will be written into the respective RAMS.
lS Figure 7 shows a logic block diagram of the read logic of the memory elements 203 of the preferred embodiment of the pre~ent invention. Figure 8 show~ a timing diagram of the read logic of the memory elements 203.
While there has been shown what i8 considered ~o be the preferred embodiment of the invention, it will be mani~est that many ohanges and modification~ can be made therein without departing from the e~ential ~piri~ and scope of the inYen~ion.
It is intended, therefore, in the annexed claims, to cover ~11 ~uch change~ and modifica~ion~ which fall within the true 6cope 25 of ~he invention.
C501070~ 02/20~8
~LI~
~ he pre~ent inven~ion relate6 to a transmi~ion system, and more particularly, to a digit~l tr~n~mission ~ystem for transmitting packets of information over a loop between devices 10 coupled to the 130p.
In tran~mi sion ~y6tem~ having a plurallty o~ devices, such a~ telephone~, terminals, controllers and proces~ors coupled to a transmis~ion carrier, ~ome form of dialog or communication exchan~e generally takes place between these device~ vi~ the 15 tran~mission carrier. In order to provide for an orderly exchange of information between devicefi~ variou~ networ architectures and ~cheme~ have been devifieds however, many o~ the exi~ting ~ran~ml~ion ~yatems are complex, lnefficient, and require large amounts of co~plex hardware. Thi~ i~ especially true with transmission 8y8tem8 u~ilizing packet switching schemes. Such schemes require the use of at least one ho~t p~oce~or, a nunber of communication proce~sor~ (or front end processors), the ~oftw~re a~soci~ted with each of the proces~or~
- which is generally very large and very complex, and communication interace deYices which interface or couple a u~er device with the transmis~ion carrier, The transmission carrier generally tranC~er~ the in~ormation in a berial fa~hion.
~ 1--CS01~704 02/20/84 ~ Z S~ ~9~
Hence, it is highly desirable to provide a 'cransmis~ion 8y8tem for interdevice co~munication which i5 high speed and overcomes the di6advantage~ and limitations of the existing ~ystems. The data transmission ~ystem of the present invention transfers packets of information in a parallel fashion via a ring, which ~orms the transmission carrier of the present invention, thereby overcoming the capacity of speed limitations of the pre~ent ~witching network schemes.
1 0 =~9~
Therefore, there iE supplied by the present invention a data transmission ~ys~em implementing a communica~ions scheme between a plurality of devices. The data transmission system which tran~mit~ information from a first end-user device to a second end-user device comprises a plurality of channel elements, each channel element having an input and an output terminal adap~ed to receive and tran~mit, respectively, ~erial digital data having a predetermined f ormat. Each cha~nel element al80 has a plurali~y of parall~l input terminals and a plurality of parallel output terminals adapted to receive and transmit, respectively, parallel digital data. The parallel outpu~ terminals of each of the channel el~ments i8 operatively connected to the parallel input terminal~ o~ a next adjacent channel element thereby connecting the channel elements in a ring configura ion~ Each channel element receives the ~erial digital data ~rom a plurality of C50~0704 02/20/84 ~5~
-3- 6~159-791 associated end~use~devices and transmits the serial digital data in parallel to the next adjacent channel element until the parallel digital data has traversed the entire ring, at which time newly received serial digital data at each channel element is inserted onto the ring. The parallel digital data transferred around the ring is examined by each channel elem-ent to extract the parallel digital data determined to be addressed to the channel element.
~ccordingly, it is an object of the present invention to provide a transmission system for transferring information between devices.
It is still another object of the present invention to provide a transmission system for transferring information between devices coupled to a transmission carrier.
It is a further object of the present invention to provide a transmission system for transferring information between devices coupled to a transmission carrier, wherein the transmission carrier is in the form of a parallel ring.
In accordance with the present invention, there is provided a data transmission system, for transmitting information rom a first end-user device to a second end-user device, comprising: (a) a plurality of channel elements, each channel element having a first input and a first output terminal adapted to receive and transmit, respectively, serial digital data having a predetermined format, the first input and first output terminals of each channel element being ~3 ~ ~2~8~9~
operatively connected to at least one corresponding end-user device, and each channel element further having a plurality of second input terminals and a plurality of second output term-inals adapted to receive and transmit, respectively, parallel digital data, wherein said channel element compriseso (i) router means, operatively connected to said second input terminals and operatively connected to said second output ter-minals, and further operatively connected to said ~irst term-inal, for coupling a new block of serial digital data onto said second output terminals at a predetermined time, other-wise coupling the parallel digital data received on said second input terminals to said second output terminals, and further examining the parallel digital data received on said second input terminals to generate a control signal when the parallel digital data is addressed to the channel element;
(ii) memory means, operatively connected to said second out-put terminals, for storing the parallel digital data on said second output terminals in response to the control signal gen-erated by said router means; and (iii) converter means, operatively connected to said memory means and operatively connected to said f irst output term-inal, for converting the parallel digital data stored in said memory means to serial digital data having said predetermined format, the serial digital data being coupled to said output first terminal; and (b) a plurality of parallel data lines, wherein each of said parallel data lines operatively connects the second output terminals of one oE said channel elements to the second input terminals of a next adjacent channel element, thereby connect ing the channel elements in a ring configuration forming a , ~3~ 1258~
ring, for causing the serial digital data received by each channel element from the corresponding end-user device to be transmitted in parallel around the ring, each channel element causing the data received via the second input terminals to be outputted serially on the first output terminal when it is determined that the data contains an address corresponding to the channel element.
In accordance with the present invention, there is further provided a data transmission system, for transmitting information from a first end-user device to a second end user device, comprising: a plurality of channel element means, each channel element means having a first input and a first output terminal adapted to receive and transmit, respectively, serial digital data having a predetermined format, and each channel element means further having a plurality of second input term-inals and a plurality of second output terminals adapted to receive and transmit, respectively, parallel digital data; and wherein the second output terminals of each of said channel element means is operatively connected to the second input terminals of a next adjacent channel element means thereby connecting the channel element means in a ring configuration forming a ring, each channel element means for receiving said serial digital data from a plurality of associated end-user devices and transmitting the serial digital data in parallel to the next adjacent channel element means until the parallel digital data has traversed the entire ring at which time newly received serial digital data at each channel element means is inserted onto the ring, the parallel digital data transferred around the ring being examined by each channel element means to extract the parallel digital data determined to be -3~ S~8~
addressed to it, wherein said channel element means comprlses:
(a) router means, operatively connected to said second input terminals and operatively connected to said second output ter-minals, and further operatively connected to said irst input terminal, for coupling a new block of serial digital data onto said second output terminals, otherwise coupling the parallel digital data received on said second input terminals to said second output terminals, and further examining the parallel digital data received on said second input terminals to deter-mine whether the parallel digital data addressed to the chan-nel element means is to be extracted;
(b) memory means, operatively connected to said second output terminals, for storing the parallel digital data extracted by said router means; and (c) converter means, operatively connected to said memory means and operatively connected to said first output terminal, for converting the parallel digital data stored in said memory means to serial digital data having said predetermined format, the serial digital data being coupled to said first output terminal.
In accordance with the present invention, there is further provided a data transmission system, for transmitting information ~rom a sending end-user device to a receiving end-user device, comprising: a plurality of channel elements connected in a ring configuration forming a xing, each channel element having a Eirst input terminal and a irst output term-inal for receiving and transmitting, respectively, serial information, the serial information having a predetermined format which includes data and address information of the _3~ Z5~4 receiving end-user device, and while the serial information i8 being received by each channel element from corresponding end-user devices operatively connected thereto, a block of parallel data is being transmitted in parallel by each channel element to a next adjacent channel element, said block of parallel data being a predetermined ~uantum of serial infor-mation, such that when the block of parallel data has traversed the entire ring a new block of parallel data made up of newly received serial information is completed loading into each channel element, and said new block of parallel data of each channel element is transferred around the ring, and fur-ther, while the block of parallel data is being transmitted around the ring, each channel element extracts parallel data which it determines it is addressed to it, wherein each chan-nel element compriseæ:
(a) router means, having a plurality of second input term-inals adapted to receive the block of parallel data and having a plurality of second output terminals adapted to transmit the block o~ parallel data, and operatively connected to said first input terminal, for coupling said new block of parallel data onto said second output terminals at a predetermined time, otherwise coupling the block of parallel data received on said second input terminals to said second output term-inals, the block of parallel data received on said second input terminals being examined to determine whether to extract the block of parallel data received by the channel element;
(b) memory means, operatively connected to said second output terminals, for storing the block of parallel data as deter-mi~ed by said router means; and (c) converter means, operatively connected to said memory ~3~ S 8 ~9 ~
means and operatively connected to said first output terminal, for converting the block of parallel data stored in said memory means to serial information having said predetermined format, the serial information being coupled to said first output terminal.
These and other objects of the present invention will become more apparent when taken in conjunction with the following description and attached drawings, wherein like characters indicate like parts, and which drawings form a part of the present application.
i~
~ .
~s~s~a Fig. 1 ~how~ a functional block diagram of the preferred embodiment of the tran~mifision system of the present invention;
Fig. 2 shows the format of the information transmitted, in ~he preferred embodiment of the present invention, via a link be~ween a concentrator and a central router;
Fig, 3 show~ a functional block diagram of a channel elemen~
of the preferred embodi~ent of the present invention;
Fig/ 4 shows a timing diagram of data beiny transmitted aroun~ a loop of the present invention;
Fig. 5 shows a functional logic block diagram of a router of the preferred embodimen~ of the pre~ent invention;
Fig. 6 ~hows a logic block diagram of the memory elements of the channel element of the preferred embodiment of the present invention;
Fig. 7 show~ a logic block diagram of the read logic of the memory element~ of the preferred embodiment of the present invention, and Fig. 8 ~how~ a timing di~gram of the read logic of the memory 20 element~ of ~ig. 7.
C5010~0~ 02/20/84 .~2~889~1L
~C~E~
Figure 1 shows a functional block diagram of the preferred embodimen~ of the transmis~ion system of the present invention, A central router 10 contains a plurality o~ channel elements 20, 20 ', 20 ", connected in a ring conf iguration via a loop 26 .
(NOTE: There exists a difference between a ring and a loop. The difference between a loop and a ring is that a loop generally uses s~IIL~ ~d control (with one station ac~ing a8 a polling primary and the others as ~econdaries), while a ring uses Li~ k~ control (with all station sharing control as peers). On a loop, generally the ~econdaries do not communicate with each o~her: traffic i8 exchanged only between the primary and secondarie6. On a ring, any station can communicate directoy with any other station. Although the term ring and loop are used interchangeably herein, it will be apparent that the present invention operates as a ring~ Each channel element (C~A~ ELE~) 20 has it~ output connected to the input o~ the next channel element 20' in the loop; hence, the output of channel element ~1 20 i~ connected to the input of channel element ~2 20', ..., the output of channel element ~80 ~not: shown) iB connected ~o the input of channel element ~81 20 ", and ~inally the output of channel element #81 20 " is connected to the input o~ channel element ~1 200 The control element (CONTROL) 22 generates the clocking signal~ tCLR), and timing ~ignal~, including CLR81 which 2S form~ the synchronizing signal, SYNC. Each channel element 20 inter~aces with a corresponding concentrator 30 (or sometimes ~ 2 S~
referred to as herein as the formatter). Thus, channel element ~1 20 interfaces with concentrator (CONC) ~1 30, channel element #2 20' interfaces wi~h concentrator ~2 30', ..., and channel element ~81 interfaces with concentrator t81 30~O The interface between the respective channel elements 20 and concentrators 30 i~ via a corresponding link 32, 32', 32'l. The central router 10 inter~aces with each link 32, 32', 32 " via the corresponding port 24, 24', 24 ". Each port 24 of the central router 10 also has a port number which corresponds to the channel element number. Thus, channel element ~1 interfaces with port 1, channel element t2 interfaces with port 2, ..~, and channel element #81 in~erfaces with port 81. Each concentrator 30 interface~ with a plurality of end user devices (or more simply devices) such as telephones, terminals, processors, computers, (not shown) ....
Each concentrator 30 formats the data received from the end user device~ attached ~hereto into a predetermined format for transmission to its respective channel element 20, and further causes data received from the channel element 20 to be transmitted to a speci~ied destinat~on end user device. CL~l is coupled to each concentrator 30 to permit the concentrator 30 to eynchronize the data ~ran6mitted to its corresponding channel element 20. The conc~ntrator 30 append a destination address to packets ori ginating f rom sources not having the capability of attaching the destination address. The concenta~ors 30 may take many forms depending upon the da~a devices coupled to the concentrator, one form including a microprocessor. Concentrators ~5010704 02/20/84 1258~g~
are generally well known in the art and wiil not be di~cu~sed further since it forms no part of the present invention and is not necefi~ary for an understanding of the precent invention.
Referring to Yigure 2, there is shown the formats of the information transmitted via links 32 to and from the concentrators 30. Two formats are utilized by the preferred embodiment of he pre~ent invention, format 1 being ~hown in Fig.
2A and format 2 being shown in Fig. 2B. Each format can be though~ of as an 81 bit word. ~it 0 i the multiplex data bit 10 which defin2s the format. If bit 0 is a 1, then format 1 word is defined. If bit ~ is a ~ then forma~ 2 i8 defined, The format 1 word is divided into three fieldz of 27 bit~ each, field ~ (or data 0) i8 contained in bit ~ - ~6, field 1 (or data 1) is contained in bits 27 - 53, and field 2 (or data 2) is contained in bits 54 - 80. When a 1 is present in bit 0 defining format 1 and the addre6~ portion cnntains a valid address, data is contained in at least field p. Data may or may not be present in fields 1 and 2. Thu~, for format 1 data, bits 27 and 54 are utilized to define if data i8 present in the re~pec~ive ~ield~.
A one in bi~ 27 will indicate if data is present in field 1, and a one in bit 54 will indicate data is pre6ent in ~ield 2. For field 0, bit~ 1 - 16 indicate the destination addres~ for the data contained in bits 17 - 26. Likewise, for field 1, bit~ 28 -43 indicate the destination address for the data contained in bits 44 - 53 and for field 2, bits 55 - 70 indi~ate the destination address for the data contained in bit~ 71-80. For ~ 9 ~
format 2 word~, bite 1 - 16 indicate a destination addres6 for the data contained in bits 17 - 80. For both formats 1 and 2, the address por~ion i~ divided into a port addres~ portion ~bits 1 - 7) and a device addre~ portion (bits 8 - 16), the port addrees being utilized by the central router 10 to cause the data to be transferred to the correct port 24 and the device address being utilized by the concen~rator 30 to transmit the data ~o the addre~ed device. Since a format 1 or format 2 word is transmitted via link 32 every 81 clock period~ in the preferred embodiment of the present invention, there can be times when no data is present. No data i~ indicated by a NULL charac~er which, in the preferred embodiment of ~he pre~ent invention, is a predetermined invalid port address.
Referring to Fig. 3, there i~ shown a functional block cliagram of the channel element 20 of the preferred embodiment of the present invention. The channel element 20 is comprised of a router element 200 and a memory elemen~ 202. The roun~er element 200 of a preferred embodiment of the present invention i~
comprised of 3 router chip~ ~or more 8i~ply router) RC0 201, RCl 201' and RC2 201''. ~ach router 20:L is coupled to receive input data from th~ previous channel equipment 20 from the respective 27 data lines 26l, 26 " , 26 "', whlch in part comprise the loop 26. The router el~ment 200 al~o receive serial data from the concentrator 30O In the preferred embodlment of the present inv~ntion the ~erial data is shi~ted into the ~outer chip~ 201 ~uch tha~ a~ter 81 clock cycles the fir~t 27 bit~ of the data ~S3~39~
word will re~ide in RCp 201, the next 27 bits of the data word will re5ide in RCl 201', and the laRt 27 bits of the data word will reside in RC2 201 ". Since each field of the format 1 data word is 27 bits, each route chip 201 will have stored therein a single field o~ data.
~ t the end of 81 clock cycle~ the router chip 201 select6 the data residing in the router chip 201 ju~ received from the concentrator 30 and place~ tha~ data on the loop 26. Thus, 81 bits of serial data just received i~ tran~mitted on loop 26 in parallel as a block of data. The data is shifted in parallel to the next channel element 20 each clock cycle (or clock period).
At the ~nd of 81 clock cycle~ the data will have looped back to the router chip 201 which originally placed the data on the loop~
at which ~ime new data is placed on the loop by the router chip 201. During the 6hifting of data around the loop 26, the router chip 201 i~ decoding the port address portion (bits 1 - 7) of the destination addre~ portion (bi~s 1 - 16) of the data word. If the port addre~s indicates an addresR for that channel element 20, the data i8 transferred to the memory element 202. Memory element 202 of the preferred embodiment of the presen~ invention i~ comprised of thre2 FIFO memoriezv memory ~ 203, memory 1 203' and memory 2 203'l. Memory ~ 203 is operatively coupled to the 27 output data lines 26' of router chip 201, memory 1 203' is operatively coupled to the 27 output data lines 26 " o~ ~Cl 201', and memory 2 203 " iB opera~ively coupled to ~he 27 output data l~ne~ 26''l of RC2 201''. The output o~ memory ~ 203, memory 1 - ~Z5i~38~
203', and memory 2 203 " is coupled to a multiplexer (MUX) 204 which sequentially read~ the data from each memory. The output of the MUX 204 is coupled to a parallel/~erial converter 205 which transmits the data (SERIAL DATA OUT) to the concentrator 30.
Although the preferred embodiment shows 81 channel elements 20, the data word format i8 compri ed of 3 data fields, the router chip 201 is divided to handle 27 bits and interfaces with a corresponding memory unit, i~ will be understood by those skilled in the art that other combina~ions may be implemented without departing from ~he true spirit and ~cope of the present invention.
The data tran~mission around the loop 26 is de~cribed in further detail below in conjunction with Fig~ ~. Referring to Fig. 4, the clock ~ignal CLR is shown, along with timing signals CLRl, CLK2, and CLK81. Timing signal CLRl define~ the firs~ time period, or s~art of a complete transmission cycle, the complete tran~mission cycle comprising 81 clock pèriods. During the fir~t clock period, data received from concentrator ~1 by channel element #1 is inserted onto the loop 26 via the router element 200 associated with channel element ~ ikewise data received f rom concentra~or ~2 by channel element #2 i5 inserted onto the loop 26 via the router element 200 associated with the channel element ~2, and 90 on. Thufi, the data received via the channel element rom it6 respective concentrator is in~erted onto the loop via the router element associated with the respective C501070~ 02/20/84 ~L~58~9~
channel element. During each clock period, the data contained in each channel element i~ tran~mitted to the next channel element, i.e., the channel element connected to the outputs of the channel element in the loop configuration. Therefore, during clock period 2, channel element ~1 receives the concentrator 81 data, channel element ~2 receive~ the concentrator ~1 data, ... and finally the channel element 81 receives the concentrator 80 data. Likewise, during clock period 3, channel element ~1 receives the concentrator 80 data, which was the data contained in channel element ~81 during clock period 2. As can be ~een from the Fig. 4, the data from concentrator ~1 i. transmi~ted to each channel element in the loop during each re~pective clock period until finally ~he concentra~or 1 dat~ has reached channel element ~81 during clock period 81. Likewi~e, the data ~rom every concentator ha~ traversed the loop in the 81 clock period~
forming a complete transmission cycle~ Qn the next clock period the transmi sion cycle repea~s i~self with the da~a received by each router element 200 inserted onto the loop during clock period 1. During ~he 81 clock periods that the data is 20 traversing the loop, the next data Erom the concentrator i8 being loaded into the respective router element 200, the loading proce~s which will be discussed in further detail hgreinunder.
Re~errin~ to Fig. 5, there i~ ~hown a functional logic block diagram of the router chip 201 of the preferred embodiment of the present invention. The DATA IN terminal provide~ for the inputting of 27 da~a lines (26', 26 " ~ or 26 "') o~ loop 26. The C501070~ 02/20/84 i ~ 5~ ~9~
data transmitted around the loop 26 i~ held in a loop latch 301 during a clock perlod. AB de~cribed above a SERIAL DATA IN
terminal receiv~s data ~rom the associated concentr~tor 30, the serial data having the format a8 described abo~e. The serial data is shifted into a ~erial/parallel (S/P) converter 302, which in the preferred embodiment is a 27 bit wide register. A SERIAL
DATA OUT terminal of S/P converter 302 of RC2 201 " is coupled to the next router chip RC1 201', and likewise the SERIAL D~TA OUT
of the n~x~ router chip 201' i~ coupled to 8till another router chip RC0 201, thereby achieving a cerial to parallel conver~ion of 81 bits wide sufficient to handle a data word of the t~an~mi~ion ~ystem of the pre~ent invention. As discu~ed above, in the preferr~d embodiment of the present invention, the router element 200 is implemen ed with three router chips 201, each router chip 201 of the router element 200 handling 27 of the 81 ~it da~a word. A~ter 81 clock periods, the serial/parallel conver~er 302 of each router chip 201 cont~ins the correct 27 bits of a data word an~ is trans~erred in parallel into an input latch 303. The output of the input la~ch 303 and the output of the loop latch 3~1 are coupled to an OUTPUT MUX 304. The output of the OUlP~T MUX 304, DATA O~JT i ( i 0 f or RC,0 ~01, i = 1 f or RCl 201'~ and i = 2 for ~C2 201 "3, is ~he data from loop latch 301. ~owever, at the end of the 81st clock period as discussed above, the OUTPUT MUX 304 i~ switched to selec~ the data ~rom the input latch 303 r thereby inserting the data received f rom the ~ssociated concentrator 30 and the tran~mission of the received data around the loop 26 i~ started.
l~S~3~9'~
Each router element 200 ha~ an ID number which i~ a~sociated with the channel elem~nt 20. Thus, channel element ~1 has an ID
of 1 , ch~nnel elemenk ~2 has an ID of 2 , . ~ ., and channel element ~81 has an ~D of 81. This ID al60 correspond~ to the port 5 number.
Each router chip 201 of a router element 200 has the ~ame ID
wired in. Thus, RCp, RCl, and RC2 for router element 200 a~sociated with channel element tl has an ID o~ , and RC0, RCl, and RC2 for router elemen~ 200 associated with channel element ~81 has an ID of 81. The ID is inputted to a fir~t input of a first comparator 305 and the fir~t inpu~ of a second comparator 30fii The second input of ~ir~t comparator 305 is operatively connected to the output of input latch 303. The ~econd input of second comparator 306 i~ operativaly connected to the output of loop latch 301. During clock periods~ 2-81 the output of second comparator 306 will output a write control ~iynal when the port address portion o~ the data word in the loop latch 301 is equal to the ID. During clock period 1 the output of fir~t comparator 305 will ou~put a writ~ control signal when the port address portion of the data word in input ~atch 303 is equal to the ID. This permits da~a just written in the input latch 303 ~rom the as~ociated ~/P convester 302 and concentrator 30 to be elected when the data is addLessed to tha~ port. The output of first comparator 305 and the outpu~ of second comparator 306 i coupled to the DATA MUX 307 which ~;elects the output of tha comparators in accordance with the clock period, C~010704 0~/20/8 ~58i~4 thereby insuring the proper generation of the write control signal. The output of data MUX 307 i5 the MEMORY W~ITE signal tWRi). That data is then wri'c'cen into the memory element 202 for subsequent tran~mission to ~he concentrator 30.
The extrac~ion of the data from the loop 26 will now be described in conjunction with Fig. 6. Router element 200 of the preferred embodiment is shown comprising the three router chips RC0 201, RC1 201' and RC2 201 " , and as de~cribed above the output of the router chips is DATA0, DATAl, and DATA2, re~pectively. Also, each router chip 201 outputs a write control signal WR~, WR1, and ~2. DATA0 compri~es the bits ~ - 26 of the data word, DATAl compri~e~ bits 27 - 53 of the data word and DATA2 comprises bit~ 54 - 80 of the data woxd. DATA0 is transmitted on ~he fir~t 27 data lines 26 ' o:E loop 26, DATAl is transmitted on the second 27 data lines 26 " of loop 26, and DATA2 is transmitted on the ~hird 27 data line~ 26 ' " of loop 26. DATA0 is coupled to memory ~ 203, DATAl iE coupled to memory 1 203 ', and DATA2 is coupled to memory 2 203''. RAM 402 of ~he preferred embodiment of the present invention can be comprised o~
Monolithic Memorie~ integrated ci~cuit chip 67401.
~ach memory unit 203 contain~ a MUX 401 and a 27 bit wide RAM
402. The ~one" input of PlUX0 401 i~ coupled to D~TA~, the "one"
input of MUXl 401' is coupled to DAT~l, and the ~one~ input o~
MUX2 ~01 " is coupled to DATA2. ~he ~zero~ inpu~ of MUX 401 i5 a null character which i~ switchable into the port addre~s portion of the addre~s field. ~ence, for MUX~ 401 the null character is ~14-C5010704 02/~0/8 :~LZ5~3~39~
switchable into bit~ 1-7, for MUXl 401' the null character is ~witchable into bit~ 28-34, and for MUX2 401 " the null character is switchable into bits 55-61. The ~one~ input of the MUX 401 i~
fielected when the control input C i8 a logic 1. The output of each MUX 401 i8 coupled to the data input D of the respective RAM
402. ~owever, no data is written into the RAM 402 unless a write control signal is pre~ent at the write terminal WRT of the RAM
402.
The write control ~ignal for the RAM 402 is generated by the remaining logic of memory 203 shown in Fig. 6. A null character of the preferred embodiment of the present inven~ion iR an invalid address, i.e., bit 1 and bit 2 of a 7 bit field i8 a logic 1 ~ignifying a port address of 96. Since comparators 305, 306, o~ e~ch router chip 201 inhibit the generation of the corresponding write control signal for invalid addresses, no check i8 performed on bit~ 1 and 2 by the logic of the memory 203 in the preferred embodiment of the present invention. For a format 2 data word, bit ~ is a logic p which is coupled to an inverting input of gate 405. If the port adddre6~ portion of the data field in router element 200 equal~ the ID, RC0 201 generates the write address signal WR~ which ully qualifies ~ND gate 405.
The output of AND gate 405 i8 coupled to OR gatQ 406 and to OR
gate 407 of memory 0 203, to OR ga~e 410 and to OR gate 411 of memory 1 203', and to O~ gate 420 and to OR gate 421 of memory 2 203 ". As a result of the output of AND gate 405 ~eing a logic 1, each MUX 401 select~ the respective data input and the ~RT
5 ~ ~g ~
input of eaoh R~M 402 i8 enabled thereby writing the full 81 bit data word ~hat is ~hen present on the loop 26 into memory element 202.
When a format 1 aa~a word is pre~ent on loop 26, bit 0 is a logic 1~ AND gate 409 will be partially enabled, and gate 405 will be di8abled. (Bit ~ ic coupled to AND gate 409, to AND gate 412, and to AND gate 422.) If DATA0 has a port address of the channel element (field 0 of a forma~ word 1 ha~ the port addre s of ~he channel element) WR0 will be a logic 1, and AND gate 409 will be fully enabled thereby causing MUXp ~01 to selec~ DATAp, and further cau~ing write signal to be present at ~AM~ 402. The write ~ign~l will al~o be present at RA~l 402' and RAM2 402 ".
However, if bit 27 is not a logic 1 and ~he write signal WRl is not present (that is not a logic 1), AND gate 412 will not be enabled cau~ing a null character to be written into RAMl 402'.
~imilarly, AND gate 422 will cause the null character to be writ~en into RAM2 402' ' if the addre#s portion of field 2 (or DA~A2) is not equal to the channel element number, and the data present bit~ bit 54, i8 not a logic lo If, for a ~ormat 1 da~a word field 0 has valid data but does not contain the port address number o~ the channel element, WR0 will be a logic 0 and ~h~ output of AND gate 40g will be a logic p~ ~ence, MUXp 401 will select th~ null character. No writing into RAM~ 402 will occur unles~ there i8 a write into the other RAMS. Further, if field 1 contains valid data (bit 27 is a logic 1) and al80 contain~ the port address of the channel element, 8~
then WRl will be a logic 1 enabling AND gate 412. Thiæ cause~
memory 1 to select data 1. Since the output of AND gate 412 is coupled to OR gate 411, OR gate 421, and OR gate 407, a write operation will occur for RAM0, RA~l, and RAM2. However, only RAMl 402' will extract the data (D~Al) from data lines 26'' and be written into RAMl 402'. RA~0 and RAM2 will write the null character.
Similarly, for a format 1 data word, if field 2 contains valid data and also contains a port addre~ of the channel element, DATA2 will be written into RAM2 and a null character will be written into RAM0 and RAMl. However, if ~he port address of the channel element i~ contained in more than one field, tho~e fields will generate the corre~ponding WRi and ~he da~ will be written into the respective RAMS.
lS Figure 7 shows a logic block diagram of the read logic of the memory elements 203 of the preferred embodiment of the pre~ent invention. Figure 8 show~ a timing diagram of the read logic of the memory elements 203.
While there has been shown what i8 considered ~o be the preferred embodiment of the invention, it will be mani~est that many ohanges and modification~ can be made therein without departing from the e~ential ~piri~ and scope of the inYen~ion.
It is intended, therefore, in the annexed claims, to cover ~11 ~uch change~ and modifica~ion~ which fall within the true 6cope 25 of ~he invention.
C501070~ 02/20~8
Claims (7)
1. A data transmission system, for transmitting infor-mation from a first end-user device to a second end-user device, comprising: (a) a plurality of channel elements, each channel element having a first input and a first output term-inal adapted to receive and transmit, respectively, serial digital data having a predetermined format, the first input and first output terminals of each channel element being oper-atively connected to at least one corresponding end-user device, and each channel element further having a plurality of second input terminals and a plurality of second output term-inals adapted to receive and transmit, respectively, parallel digital data, wherein said channel element comprises:
(i) router means, operatively connected to said second input terminals and operatively connected to said second output ter-minals, and further operatively connected to said first term-inal, for coupling a new block of serial digital data onto said second output terminals at a predetermined time, other-wise coupling the parallel digital data received on said second input terminals to said second output terminals, and further examining the parallel digital data received on said second input terminals to generate a control signal when the parallel digital data is addressed to the channel element;
(ii) memory means, operatively connected to said second out-put terminals, for storing the parallel digital data on said second output terminals in response to the control signal gen-erated by said router means; and (iii) converter means, operatively connected to said memory means and operatively connected to said first output term-inal, for converting the parallel digital data stored in said memory means to serial digital data having said predetermined format, the serial digital data being coupled to said output first terminal; and (b) a plurality of parallel data lines, wherein each of said parallel data lines operatively connects the second output terminals of one of said channel elements to the second input terminals of a next adjacent channel element, thereby connect-ing the channel elements in a ring configuration forming a ring, for causing the serial digital data received by each channel element from the corresponding end-user device to be transmitted in parallel around the ring, each channel element causing the data received via the second input terminals to be outputted serially on the first output terminal when it is determined that the data contains an address corresponding to the channel element.
(i) router means, operatively connected to said second input terminals and operatively connected to said second output ter-minals, and further operatively connected to said first term-inal, for coupling a new block of serial digital data onto said second output terminals at a predetermined time, other-wise coupling the parallel digital data received on said second input terminals to said second output terminals, and further examining the parallel digital data received on said second input terminals to generate a control signal when the parallel digital data is addressed to the channel element;
(ii) memory means, operatively connected to said second out-put terminals, for storing the parallel digital data on said second output terminals in response to the control signal gen-erated by said router means; and (iii) converter means, operatively connected to said memory means and operatively connected to said first output term-inal, for converting the parallel digital data stored in said memory means to serial digital data having said predetermined format, the serial digital data being coupled to said output first terminal; and (b) a plurality of parallel data lines, wherein each of said parallel data lines operatively connects the second output terminals of one of said channel elements to the second input terminals of a next adjacent channel element, thereby connect-ing the channel elements in a ring configuration forming a ring, for causing the serial digital data received by each channel element from the corresponding end-user device to be transmitted in parallel around the ring, each channel element causing the data received via the second input terminals to be outputted serially on the first output terminal when it is determined that the data contains an address corresponding to the channel element.
2. A data transmission system, according to claim 1 wherein said router means comprises:
(a) input converter means, operatively connected to said first input terminal, for converting said serial digital data to parallel digital data;
(b) register means, operatively connected to said second input terminals, for receiving said parallel digital data from the channel element operatively connected to said second input terminals;
(c) comparator means, operatively connected to said input converter means and to said register means, for deter-mining when said parallel digital data is addressed to the channel element; and (d) selector means, operatively connected to said input converter means and to said register means, and further oper-atively connected to said second output terminals, for coup-ling said parallel digital data from said input converter means to said second output terminals in response to a sync signal, otherwise coupling said parallel digital data from said register means to said second output terminals.
(a) input converter means, operatively connected to said first input terminal, for converting said serial digital data to parallel digital data;
(b) register means, operatively connected to said second input terminals, for receiving said parallel digital data from the channel element operatively connected to said second input terminals;
(c) comparator means, operatively connected to said input converter means and to said register means, for deter-mining when said parallel digital data is addressed to the channel element; and (d) selector means, operatively connected to said input converter means and to said register means, and further oper-atively connected to said second output terminals, for coup-ling said parallel digital data from said input converter means to said second output terminals in response to a sync signal, otherwise coupling said parallel digital data from said register means to said second output terminals.
3.
A data transmission system, for transmitting infor-mation from a first end-user device to a second end-user device, comprising: a plurality of channel element means, each channel element means having a first input and a first output terminal adapted to receive and transmit, respectively, serial digital data having a predetermined format, and each channel element means further having a plurality of second input term-inals and a plurality of second output terminals adapted to receive and transmit, respectively, parallel digital data; and wherein the second output terminals of each of said channel element means is operatively connected to the second input terminals of a next adjacent channel element means thereby connecting the channel element means in a ring configuration forming a ring, each channel element means for receiving said serial digital data from a plurality of associated end-user devices and transmitting the serial digital data in parallel to the next adjacent channel element means until the parallel digital data has traversed the entire ring at which time newly received serial digital data at each channel element means is inserted onto the ring, the parallel digital data transferred around the ring being examined by each channel element means to extract the parallel digital data determined to be addressed to it, wherein said channel element means comprises:
(a) router means, operatively connected to said second input terminals and operatively connected to said second output terminals, and further operatively connected to said first input terminal, for coupling a new block of serial digital data onto said second output terminals, otherwise coupling the parallel digital data received on said second input terminals to said second output terminals, and further examining the parallel digital data received on said second input terminals to determine whether the parallel digital data addressed to the channel element means is to be extracted;
(b) memory means, operatively connected to said second output terminals, for storing the parallel digital data extracted by said router means; and (c) converter means, operatively connected to said memory means and operatively connected to said first output terminal, for converting the parallel digital data stored in said memory means to serial digital data having said predeter-mined format, the serial digital data being coupled to said first output terminal.
A data transmission system, for transmitting infor-mation from a first end-user device to a second end-user device, comprising: a plurality of channel element means, each channel element means having a first input and a first output terminal adapted to receive and transmit, respectively, serial digital data having a predetermined format, and each channel element means further having a plurality of second input term-inals and a plurality of second output terminals adapted to receive and transmit, respectively, parallel digital data; and wherein the second output terminals of each of said channel element means is operatively connected to the second input terminals of a next adjacent channel element means thereby connecting the channel element means in a ring configuration forming a ring, each channel element means for receiving said serial digital data from a plurality of associated end-user devices and transmitting the serial digital data in parallel to the next adjacent channel element means until the parallel digital data has traversed the entire ring at which time newly received serial digital data at each channel element means is inserted onto the ring, the parallel digital data transferred around the ring being examined by each channel element means to extract the parallel digital data determined to be addressed to it, wherein said channel element means comprises:
(a) router means, operatively connected to said second input terminals and operatively connected to said second output terminals, and further operatively connected to said first input terminal, for coupling a new block of serial digital data onto said second output terminals, otherwise coupling the parallel digital data received on said second input terminals to said second output terminals, and further examining the parallel digital data received on said second input terminals to determine whether the parallel digital data addressed to the channel element means is to be extracted;
(b) memory means, operatively connected to said second output terminals, for storing the parallel digital data extracted by said router means; and (c) converter means, operatively connected to said memory means and operatively connected to said first output terminal, for converting the parallel digital data stored in said memory means to serial digital data having said predeter-mined format, the serial digital data being coupled to said first output terminal.
4. A data transmission system, according to claim 3, wherein said router means comprises:
(a) input converter means, operatively connected to said first input terminal, for converting said serial digital data to parallel digital data;
(b) register means, operatively connected to said second input terminals, for receiving said parallel digital data from the channel element operatively connected to said second input terminals;
(c) comparator means, operatively connected to said input converter means and to said register means, for deter-mining when to cause said parallel digital data to be extracted; and (d) selector means, operatively connected to said input converter means and to said register means, and further oper-atively connected to said second output terminals, for coup-ling said parallel digital data from said input converter means to said second output terminals in response to a sync signal, otherwise coupling said parallel digital data from said register means to said second output terminals.
(a) input converter means, operatively connected to said first input terminal, for converting said serial digital data to parallel digital data;
(b) register means, operatively connected to said second input terminals, for receiving said parallel digital data from the channel element operatively connected to said second input terminals;
(c) comparator means, operatively connected to said input converter means and to said register means, for deter-mining when to cause said parallel digital data to be extracted; and (d) selector means, operatively connected to said input converter means and to said register means, and further oper-atively connected to said second output terminals, for coup-ling said parallel digital data from said input converter means to said second output terminals in response to a sync signal, otherwise coupling said parallel digital data from said register means to said second output terminals.
5. A data transmission system, for transmitting infor-mation from a sending end-user device to a receiving end-user device, comprising: a plurality of channel elements connected in a ring configuration forming a ring, each channel element having a first input terminal and a first output terminal for receiving and transmitting, respectively, serial information, the serial information having a predetermined format which includes data and address information of the receiving end-user device, and while the serial information is being received by each channel element from corresponding end-user devices operatively connected thereto, a block of parallel data is being transmitted in parallel by each channel element to a next adjacent channel element, said block of parallel data being a predetermined quantum of serial information, such that when the block of parallel data has traversed the entire ring a new block of parallel data made up of newly received serial information is completed loading into each channel element, and said new block of parallel data of each channel element is transferred around the ring, and further, while the block of parallel data is being transmitted around the ring, each channel element extracts parallel data which it deter-mines it is addressed to it, wherein each channel element comprises:
(a) router means, having a plurality of second input terminals adapted to receive the block of parallel data and having a plurality of second output terminals adapted to transmit the block of parallel data, and operatively connected to said first input terminal, for coupling said new block of parallel data onto said second output terminals at a predeter-mined time, otherwise coupling the block of parallel data received on said second input terminals to said second output terminals, the block of parallel data received on said second input terminals being examined to determine whether to extract the block of parallel data received by the channel element;
(b) memory means, operatively connected to said second output terminals, for storing the block of parallel data as determined by said router means; and (c) converter means, operatively connected to said memory means and operatively connected to said first output terminal, for converting the block of parallel data stored in said memory means to serial information having said predeter-mined format, the serial information being coupled to said first output terminal.
(a) router means, having a plurality of second input terminals adapted to receive the block of parallel data and having a plurality of second output terminals adapted to transmit the block of parallel data, and operatively connected to said first input terminal, for coupling said new block of parallel data onto said second output terminals at a predeter-mined time, otherwise coupling the block of parallel data received on said second input terminals to said second output terminals, the block of parallel data received on said second input terminals being examined to determine whether to extract the block of parallel data received by the channel element;
(b) memory means, operatively connected to said second output terminals, for storing the block of parallel data as determined by said router means; and (c) converter means, operatively connected to said memory means and operatively connected to said first output terminal, for converting the block of parallel data stored in said memory means to serial information having said predeter-mined format, the serial information being coupled to said first output terminal.
6. A data transmission system, according to claim 5.
wherein said router means comprises:
(a) input converter means, operatively connected to said first input terminal, for converting said serial information to said block of parallel data;
(b) register means, operatively connected to said second input terminals, for receiving said block of parallel data from the channel element operatively connected to said second input terminals;
(c) comparator means, operatively connected to said input converter means and to said register means, for deter-mining when to cause said block of parallel data to be extracted and (d) selector means, operatively connected to said input converter means and to said register means, and further operatively connected to said second output terminals, for coupling said block of parallel data from said input converter means to said second output terminals in response to a sync signal, otherwise coupling said block of parallel data from said register means to said second output terminals.
wherein said router means comprises:
(a) input converter means, operatively connected to said first input terminal, for converting said serial information to said block of parallel data;
(b) register means, operatively connected to said second input terminals, for receiving said block of parallel data from the channel element operatively connected to said second input terminals;
(c) comparator means, operatively connected to said input converter means and to said register means, for deter-mining when to cause said block of parallel data to be extracted and (d) selector means, operatively connected to said input converter means and to said register means, and further operatively connected to said second output terminals, for coupling said block of parallel data from said input converter means to said second output terminals in response to a sync signal, otherwise coupling said block of parallel data from said register means to said second output terminals.
7. A data transmission system, according to claim 6, wherein said block of parallel data includes at least one field of data and address information, said memory mean comprising:
(a) logic means, operatively connected to said second output terminals and operatively connected to said comparator means, for selectively transmitting said field of data and address information in response to at least one write control signal; and (b) memory means, operatively connected to said logic means and operatively connected to said converter means, wherein said memory means is of the type First In-First Out (FIFO), for storing said field of data and address information selectively transmitted by said logic means.
(a) logic means, operatively connected to said second output terminals and operatively connected to said comparator means, for selectively transmitting said field of data and address information in response to at least one write control signal; and (b) memory means, operatively connected to said logic means and operatively connected to said converter means, wherein said memory means is of the type First In-First Out (FIFO), for storing said field of data and address information selectively transmitted by said logic means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/586,154 US4612635A (en) | 1984-03-05 | 1984-03-05 | Sequential data transmission system |
| US586,154 | 1984-03-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1258894A true CA1258894A (en) | 1989-08-29 |
Family
ID=24344528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000475716A Expired CA1258894A (en) | 1984-03-05 | 1985-03-04 | Sequential data transmission system |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4612635A (en) |
| AU (1) | AU564724B2 (en) |
| CA (1) | CA1258894A (en) |
| SE (1) | SE461561B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB8623310D0 (en) * | 1986-09-27 | 1986-10-29 | Int Computers Ltd | Multi-node data processing system |
| US4942574A (en) * | 1988-03-31 | 1990-07-17 | American Telephone And Telegraph Company, At&T Bell Laboratories | Concurrent resource request resolution mechanism |
| JPH0624378B2 (en) * | 1988-06-30 | 1994-03-30 | 株式会社東芝 | Data transmission / reception method between networks |
| US7298975B2 (en) * | 2000-07-13 | 2007-11-20 | L-3 Communications Integrated Systems L.P. | Synchronous collapsed ring architecture for real-time signal switching and distribution |
| WO2002030047A2 (en) * | 2000-10-04 | 2002-04-11 | Vitesse Semiconductor Corporation | A data communication network switching unit having a systolic ring structure |
| US7702405B2 (en) * | 2004-06-02 | 2010-04-20 | Standard Microsystems Corporation | System and method for transferring non-compliant packetized and streaming data into and from a multimedia device coupled to a network across which compliant data is sent |
| US9351077B1 (en) | 2014-12-11 | 2016-05-24 | L-3 Communications Integrated Systems Lp | Systems and methods for independent and control-isolated audio processing (ICIAP) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS534761B2 (en) * | 1971-12-10 | 1978-02-21 | ||
| US3787627A (en) * | 1971-12-15 | 1974-01-22 | Adaptive Tech | Central address distributor |
| US3919483A (en) * | 1973-12-26 | 1975-11-11 | Ibm | Parallel multiplexed loop interface for data transfer and control between data processing systems and subsystems |
| US3919484A (en) * | 1974-03-01 | 1975-11-11 | Rca Corp | Loop controller for a loop data communications system |
| FR2275944A1 (en) * | 1974-06-21 | 1976-01-16 | Suchard Jean | MESSAGE TRANSMISSION SYSTEM BETWEEN SEVERAL STATIONS |
| GB1530405A (en) * | 1975-03-24 | 1978-11-01 | Okura Denki Co Ltd | Loop data highway communication system |
| US4199662A (en) * | 1978-07-17 | 1980-04-22 | Lowe Charles S Jr | Hybrid control of time division multiplexing |
| US4237553A (en) * | 1978-12-26 | 1980-12-02 | Bell Telephone Laboratories, Incorporated | Data packet multiplexing in a staggered fashion |
| US4383314A (en) * | 1981-01-12 | 1983-05-10 | Burroughs Corporation | Circular access linkage loop configuration for system communication |
-
1984
- 1984-03-05 US US06/586,154 patent/US4612635A/en not_active Expired - Lifetime
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1985
- 1985-02-28 AU AU39245/85A patent/AU564724B2/en not_active Expired
- 1985-03-01 SE SE8501019A patent/SE461561B/en not_active IP Right Cessation
- 1985-03-04 CA CA000475716A patent/CA1258894A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| AU3924585A (en) | 1985-09-12 |
| SE461561B (en) | 1990-02-26 |
| AU564724B2 (en) | 1987-08-20 |
| SE8501019D0 (en) | 1985-03-01 |
| US4612635A (en) | 1986-09-16 |
| SE8501019L (en) | 1985-09-06 |
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