CA1260147A - Remote reset circuit - Google Patents
Remote reset circuitInfo
- Publication number
- CA1260147A CA1260147A CA000517416A CA517416A CA1260147A CA 1260147 A CA1260147 A CA 1260147A CA 000517416 A CA000517416 A CA 000517416A CA 517416 A CA517416 A CA 517416A CA 1260147 A CA1260147 A CA 1260147A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- bits
- reset
- rxd
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
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- 230000001360 synchronised effect Effects 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 239000003985 ceramic capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 241001481828 Glyptocephalus cynoglossus Species 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- NLZUEZXRPGMBCV-UHFFFAOYSA-N Butylhydroxytoluene Chemical compound CC1=CC(C(C)(C)C)=C(O)C(C(C)(C)C)=C1 NLZUEZXRPGMBCV-UHFFFAOYSA-N 0.000 description 1
- 101150002998 LCAT gene Proteins 0.000 description 1
- 241001163743 Perlodes Species 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007519 figuring Methods 0.000 description 1
- XGFJCRNRWOXGQM-UHFFFAOYSA-N hot-2 Chemical compound CCSC1=CC(OC)=C(CCNO)C=C1OC XGFJCRNRWOXGQM-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
ABSTRACT
A remote reset circuit acts as a stand-alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference characters When a match occurs, the remote reset circuit activates the system's hardware reset line.
The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients.
A remote reset circuit acts as a stand-alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference characters When a match occurs, the remote reset circuit activates the system's hardware reset line.
The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients.
Description
RE~SOTE RESET CIRCUIT
BACKGROUND OF THE _INVENT ION
The present inYention relate~ generally to a computer remote reset ~y~tem and in particular to a software independent re~ot~ rese~ cireuit.
5Computer systems based o~ a common bus, ~uch as S-lOO, V~E, ~r Multibu~ ~T~ are widely used in the industry for a variety of applications ranging from control systems to softwarè deYelopment stations. In addition, many home and per~onal computers are based on ~i~ilar bu~es Often it 10i~ convenien~, and sometime~ necessary, ~o physically ~epara~e ~he sys~em's terminal or te~ainal~ rom the computer. For example, in a sy~e~ u~d for &oftware development or user ~ervice~ the user may Wi5~ to ~ave acce6s t~rough t~e telephone or long dista~ce lines. In 15control application~ tbe ~o~puter ~y~tem may be located in a har~h environmen~ and ~u~t be i~olated fro~ t~e operator. If t~e user i~ near the ~ys~e~, a re~et is just a pus~ of ehe ~witch. If, ~owe~er, the u~er i5 at a re~ote terminal or co~unicating throug~ a tel~phon~ lin~, 20a reliable reset is d~fficult.~o pro~ide.
In some ~omputer ~ys~ems the operating ~y~e~ ~o twar~
~upport~ a reset fro~ a re~ote ter~inal. In many sase~, a7 howe~er, the software under ~evelopment may cause the system's software to crash. ~s a result, the computer may fail to respond to the terminal, thus rendering the software supported reset function useless.
It is therefore an object of the present invention to pro-~ide a remote reset circuit that is completely independent of software.
It is another object of the present invention to provide a stand-alone remote reset circuit that is independent of other system hardware such as the UART or other terminal communication devices.
It is yet another object of the present invention to provide a remote reset circuit for which a system crash will not affect the availability of a user initiated system reset.
SUMMARY ~F THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the apparatus of this invention may comprise a remote reset circuit acting as a stand~alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line.
The remote reset circuit is hardware based and designed around mono-stable multivibrators. As such, it is unaffected by system crashes, partial serial transmissions, or power supply transients.
Thus broadly, the invention contemplates a remote reset circuit for remotely resetting a digital system with the remote reset circuit accepting a receiver data (RxD) signal and generating a reset signal upon receiving the correct RxD reset signal, which comprises, in combination, an adjustable one-shot means triggered by the RxD signal for providing a timed pulse output long enough in duration to permit the clocking in of a desired number of bits transmitted at a predetermined baud rate from the source of the RxD signal, a timing means triggered by the timed pulse output of the adjustable one-shot means for providing a synchronous clock signal (Tsync), a counting means triggered by the Tsync clock 2a signal for counting the desired number of bits clocked in from the source of the RxD signal, a means for presetting a desired reset pattern of bits, a means for comparing the bits in the desired number of bits clocked in from the source of the RxD
signal with the desired reset pattern of bits and for providing a match signal when the desired number of bits clocked in from the source of the RxD signal compares in pattern with the desired reset pattern of bits, and a means for generating a signal to reset the digital system upon receipt of the match signal from the means for comparing.
In another embodiment, the invention provides a remote reset circuit for remotely resetting a digital system with the remote reset circuit accepting a receiver data (RxD) signal and generating a reset signal upon receiving the correct RxD signal, which comprises, in combination, a one-shot means triggered by the RxD signal for providing a timed pulse output long enough in duration to permit the clocking in of a desired number of bits transmitted from the source of the RxD signal, an adjustable timing means triggered by the timed pulse output of the one-shot means for providing an approximately square-wave synchronous clock signal (Tsync) having adjustable duration, a counting means triggered by the Tsync clock signal for counting the desired number of bits clocked in from the source of the RxD signal, a means for pre-setting a desired reset pattern of bits, a means for comparing the bits in the desired number of bits clocked in from the source of the RxD signal with the desired reset pattern of bits and for providing a match signal when the desired number of bits clocked in from the source of the RxD signal compares in pattern with the desired reset pattern of bits, and a means for generating a signal to reset the digital system upon receipt of the match signal from the means for comparing.
An advantage of the present invention is that the remote reset circuit is hardware oriented and does not require software con-figuring or initialization.
Another advantage of the present invention is that the remote reset circuit has an easily selectable reset character.
Additional objects, advantages and novel ~eatureg of ~he invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in ~he art upon examination of the following or may be learned by practice of the invention. The objects and advantages o~ the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorpora~ed in and form a part of the specificatio~, illustra~e the embodiment~s) of the present inveYltion and, together with the descrip~ion, serve to explain t~e principles of the invenSion. In the drawin~s:
FIGURES lA and lB together form a logic diagra~ of an embodiment of remo~e rese~ circuit of the present invention:
FIGURE 2 is a layout diagram for the embodiment of Figures lA and lB: .
FIGURE 3 is a logic diagram illustrating a method for input~ing ~e embodime~t of Figures lA and lB from RS-Z32 ~onnectors: and FI5URE 4 is a timing diagram for the remote rese~
circuit of Figure~ lA and lB.
DETAIL D~SCRIPTION OF THF PREFERRED EMB~DIMENT
For the purpose of this description, a tilde ~-) before a signal name indicates the in~er~ed version of that signal, e.g., ~Tsync is the inverse of Tsy~c. A
slash (~) a~ter a signal name indi~ates tha~ the signal is active low, e.q., R~SET~ is active, or asserted at a low logic level.
To und~rstand th2 op~rat10n of th~ lnv~ntlon, a~sum~ that the mult1b~s comput~r systQm romat~ res~t clrcu1t, see Flgures lA and lB, has had no 1nput for ~n ~rbltrar11y lon~ t1me. W~th no 1nput, the RxD 11ne ls h19h. RxD ls brought 1n at lnput connect1cn lQ, lnvcrted in 1nv~rter 11 and log kally AND0d in AND g~te 1~ w~th the clear slgn~l (CLR) as 1nvert~d by lnv~rt~r 15. The CLR (Tl) 1s proYlded from a one-shot I~, And ~s normatly low. Assum~n~ that the on~-shot 1~ ha~ tlmed DUt, and that CLR 1s ind~ed low, RxD 1s s~nt thr~ugh AND
gate 1~ and tnverter 12 to ~h1~t r~9iStQr ~l dat~ tnput INA and to a lo second one-shot ~5. A fall1n~ edge of RxD lndicates a start ~it, and tr~gers the second one-shot 2~- ThQ actlYe h~gh output Q of the second one-shot 2~ enables and synchronizes t~mer ~ to prov~de an QUtpUt of the ~sync clock. The ~sync clock output provides the clk input for shift reglster ~1 and is 1nverted by 1nvert~r 3D to provide th~ .Tsync ~lock whlch 1s fed through AND gat~ 3~ ~nd ~P4 to the B
lnput of on~-shot 1~ c~us~ of the duratlcn (T?) ~f the second one-~hot ~, the Tsyno clock wlll b~ enabled long en~ugh to clock ln th~ start blt and ~11 7 data blts. Tsync ls fed lnto the shift re~1st~r 21 and .Tsyno lnto the blt counter ~. Slnce the shlft r~ er ~ olocks d~ta ln on th~ r~slng ~dge o~ Tsync, bits are sampl~d ln the approxlmatQ centar. ~hls allows fbr settl~ng tlme, The bit count~r ~ co~ ts th~ number of samples (r~sin~ edges of Tsync, fallin~ edges D~ .Tsync) ~nd sets thQ QD output of b1S count~r h1~h when lt counts to 8. ~hls QD output of b~t c~unter ~5 ~nabl~s .~sync tu thc B ~nput oP tha flrst on~-sh~t ~. ~he next falllng edge of Tsync ~r1s1ng ~ e o~ .Tsync), aftQr the 8th sample, trlgg~rs the flrst one-shot l~ to prov~d~ th~ CLR pulse. CLR clears the b~t count~r ~ and blocks ~xO. By blockln~
RxD, a false state canno~ occur at the fall of bi~ number 7, parity bi~s, stop bits, or noise at the end of the character. ~CL,R from second one-shot 2S clears the T2 pulse before time-outr Time-out is provided, howe~er, prevent hang-up in the PYent of partial transmission or transmissioD errors. In addition, ~he second one-shot 25 is used for T2 to ensure powering up in a known state.
The fall of CLR indicates the end of ~he character, and the remote re~e~ circuit of the present invention waits for the next fall of RxD. Returning now to shift regist~r 21, the parallel date is brought out to two magnitude comparators 27 and 29 and is compared to the reference character set by ~witches Sl - S7. The 8~h bit of the reference character is tied high ~B3 of 29), and the QD
output of bit counter 25 is tied to A3 of magnitude comparator 29. This assures that a match cannot be found until all bits have been clocked in. (The start bit is thrown away, so the comparison is done between the reference character plus one high bi~ and the seven transmitted bits plus QD of bi~ counter 23.) If no match is found, ~he character is ignored, and no reset is generated. If a match is found, the A=B outpu~ of magnitude comparator 29 goes high and ~riggers timer through inverter 33. Timer 31 i~ a 555 timer se~ up in monostable mode~ with a pulse time of approximately lO ms. This lO ms pulse is fed through an open collector inv~r~er 35 to provide the rese~ pulse, RESET/.
The remote reset circuit of ~he present invention above dascribed for Multibus based systems may be embodied in several implementations. The circuit may be implsmented on a. logic card, see Figure 2, which plugs into the system bus. The da-~a inpu~ may be taken from a RS-232 jumper, or from the input ~o the system's U~RT.
3L~ 7 The loglc card n~ed not be a full sl~ board sln~ th~ loglc occup~es ltttle space and ne~s acces~ to only th~ bus power (VCC~, ground, and hardware reset 11nes. Otherwlss, th~ l~gic card c~n b~ plug~ed ~nto ~I bus, other than Multlbus, w~th Qlther a ~S-232 or TT~
compat1ble data lnpu~. Th@ lo~lc may also be lncorporated ~s a part of the CPU or er~al eomm~lnlcatlons pr~nted circult bDard. ~nally~
the lo~c m~y be lncorporate~ a~ a p~rt of thç sQr~al commul)lcat~on ~ntegrated c~rcu~t (UA2T or USART).
If the data ~s T~L datal the UART ~xD T~L tnput may be lnputt~d 0 dir~ctly ~ the RxD inpuS lQ- Alternat~vely data ~y b~ pulle~ from RS-232 ~.onnectors and fed through an ~nv~rter 37 to the RxD ~nput IO, s~e f~gure 3.
The remote reset clrcu~t of the present ~n\lent1on m~y be se~ for use at any rate from 300 to 9600 8al~d ~n th~ above-descr~bed embodi~ents. Th~ follow~ng Baud rate tlm~ng ~d~ustments must be made:
T~ync c~ock ~ust be set for the Baud r~te fr~qu~ncy; e.~., for 30D ~aud, set Ts~nc fQr 300 ~Iz; Cl2ar pulse (T~) must be set to 1.5 X ~sync p~r~od, X 20%; and ~nable puls~ (T2~ mu~t b~ set to IO X Tsync perlod, % 20X; se~ F1~ura 4.
With ref~reno~ again t~ Flgur~ I, the BalJd r te ~s set by first removlng the ~umper plug JPI and tylng t1m~r ~Z RS~ term~nal high ~+5 volts). While observe ~sync on t~mer ~ OUT ~orminal ad~ust RI and R2 for a square w~ve ~f tho Balld rat~ frequ~n~y. Prefer~bly the t1mer ~2 is an NE555 ttmer. ln some cases C3 w111 also have to be chan~d ~o ach~eve thQ dQslrQd square wave fre~uen~y.
S~cond, replace iumP~r plu~ JPI and r~move ~umper plugs JP2 ~nd ~P3. ~hen ~onnect a TT~ squar~ wave ~nerator w1th a per~od of ~0 X
~sync per~od to the one shot ~ at lnput A and tie the one-~hot 2 cl ~ar (CLR) hi~h (+5 volts). At the falling edge of the signal at one-shot 25 input A, observe an active low pulse at test point TPl. Set R3 and C6 such that the low pulse is equal in duration to time Tl.
Remove JP4 and connect a TTL square wave generator with a period of approximately 20 X Tsync period to one-shot 17 input B. A rising edge of the siynal on one-shot 17 input B initiates an active low pulse at one-shot 17 output Q. Set R4 and C5 æo that the duration of the low pulse at one-s~ot 17 output Q is equal to time T2. Then, remove the signal generator, and replace jumper plugs JP2, JP3, and JP4.
Select the character to be used as a reset character, and set switches Sl - S7. Although any 7-bit ASCII
character rnay be used as the reset character, an unassigned control key sequence is suggested. This helps prevent uninten~ional resets. The open position ~ets the bit to a "1" and the closed position sets i~ to a "0", thus Sl - S7 is set to the binary representation of the reset charac~er. Sl se~s bit 0, S2 bit 1, and so forth.
If the remote reset circuit is implemented on a logi~
board, plug the board into an unused bus slot and connect the data input ~o the appropriate point in ~he system.
This may be a connector to the RS 232 input, or a jumper to the TTL RxD inpu~ of the sy6~em UART as above deæ~ribed.
To use the remo~e reset control, simply type the selected reset charac~er on a terminal keyboard and observe the system reset.
In the pre~erred embodiment, componen~s and elements may be selected as follows:
COMPO~ENT PART # D RIPTION
27 N~555 Timer 31 N~555 Timer 17, 25 74LS221 Dual One-Shot 11, 15, 19, 74LS05 Hex Open Collector 30. 33. 35 Inverter 23 74LSZ93 4-Bit Binary Counter Zl 74LS164 8-Bit Parallel Output Shift Register 13, 34 74LS08 ~uad AND Ga~e
BACKGROUND OF THE _INVENT ION
The present inYention relate~ generally to a computer remote reset ~y~tem and in particular to a software independent re~ot~ rese~ cireuit.
5Computer systems based o~ a common bus, ~uch as S-lOO, V~E, ~r Multibu~ ~T~ are widely used in the industry for a variety of applications ranging from control systems to softwarè deYelopment stations. In addition, many home and per~onal computers are based on ~i~ilar bu~es Often it 10i~ convenien~, and sometime~ necessary, ~o physically ~epara~e ~he sys~em's terminal or te~ainal~ rom the computer. For example, in a sy~e~ u~d for &oftware development or user ~ervice~ the user may Wi5~ to ~ave acce6s t~rough t~e telephone or long dista~ce lines. In 15control application~ tbe ~o~puter ~y~tem may be located in a har~h environmen~ and ~u~t be i~olated fro~ t~e operator. If t~e user i~ near the ~ys~e~, a re~et is just a pus~ of ehe ~witch. If, ~owe~er, the u~er i5 at a re~ote terminal or co~unicating throug~ a tel~phon~ lin~, 20a reliable reset is d~fficult.~o pro~ide.
In some ~omputer ~ys~ems the operating ~y~e~ ~o twar~
~upport~ a reset fro~ a re~ote ter~inal. In many sase~, a7 howe~er, the software under ~evelopment may cause the system's software to crash. ~s a result, the computer may fail to respond to the terminal, thus rendering the software supported reset function useless.
It is therefore an object of the present invention to pro-~ide a remote reset circuit that is completely independent of software.
It is another object of the present invention to provide a stand-alone remote reset circuit that is independent of other system hardware such as the UART or other terminal communication devices.
It is yet another object of the present invention to provide a remote reset circuit for which a system crash will not affect the availability of a user initiated system reset.
SUMMARY ~F THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the apparatus of this invention may comprise a remote reset circuit acting as a stand~alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line.
The remote reset circuit is hardware based and designed around mono-stable multivibrators. As such, it is unaffected by system crashes, partial serial transmissions, or power supply transients.
Thus broadly, the invention contemplates a remote reset circuit for remotely resetting a digital system with the remote reset circuit accepting a receiver data (RxD) signal and generating a reset signal upon receiving the correct RxD reset signal, which comprises, in combination, an adjustable one-shot means triggered by the RxD signal for providing a timed pulse output long enough in duration to permit the clocking in of a desired number of bits transmitted at a predetermined baud rate from the source of the RxD signal, a timing means triggered by the timed pulse output of the adjustable one-shot means for providing a synchronous clock signal (Tsync), a counting means triggered by the Tsync clock 2a signal for counting the desired number of bits clocked in from the source of the RxD signal, a means for presetting a desired reset pattern of bits, a means for comparing the bits in the desired number of bits clocked in from the source of the RxD
signal with the desired reset pattern of bits and for providing a match signal when the desired number of bits clocked in from the source of the RxD signal compares in pattern with the desired reset pattern of bits, and a means for generating a signal to reset the digital system upon receipt of the match signal from the means for comparing.
In another embodiment, the invention provides a remote reset circuit for remotely resetting a digital system with the remote reset circuit accepting a receiver data (RxD) signal and generating a reset signal upon receiving the correct RxD signal, which comprises, in combination, a one-shot means triggered by the RxD signal for providing a timed pulse output long enough in duration to permit the clocking in of a desired number of bits transmitted from the source of the RxD signal, an adjustable timing means triggered by the timed pulse output of the one-shot means for providing an approximately square-wave synchronous clock signal (Tsync) having adjustable duration, a counting means triggered by the Tsync clock signal for counting the desired number of bits clocked in from the source of the RxD signal, a means for pre-setting a desired reset pattern of bits, a means for comparing the bits in the desired number of bits clocked in from the source of the RxD signal with the desired reset pattern of bits and for providing a match signal when the desired number of bits clocked in from the source of the RxD signal compares in pattern with the desired reset pattern of bits, and a means for generating a signal to reset the digital system upon receipt of the match signal from the means for comparing.
An advantage of the present invention is that the remote reset circuit is hardware oriented and does not require software con-figuring or initialization.
Another advantage of the present invention is that the remote reset circuit has an easily selectable reset character.
Additional objects, advantages and novel ~eatureg of ~he invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in ~he art upon examination of the following or may be learned by practice of the invention. The objects and advantages o~ the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorpora~ed in and form a part of the specificatio~, illustra~e the embodiment~s) of the present inveYltion and, together with the descrip~ion, serve to explain t~e principles of the invenSion. In the drawin~s:
FIGURES lA and lB together form a logic diagra~ of an embodiment of remo~e rese~ circuit of the present invention:
FIGURE 2 is a layout diagram for the embodiment of Figures lA and lB: .
FIGURE 3 is a logic diagram illustrating a method for input~ing ~e embodime~t of Figures lA and lB from RS-Z32 ~onnectors: and FI5URE 4 is a timing diagram for the remote rese~
circuit of Figure~ lA and lB.
DETAIL D~SCRIPTION OF THF PREFERRED EMB~DIMENT
For the purpose of this description, a tilde ~-) before a signal name indicates the in~er~ed version of that signal, e.g., ~Tsync is the inverse of Tsy~c. A
slash (~) a~ter a signal name indi~ates tha~ the signal is active low, e.q., R~SET~ is active, or asserted at a low logic level.
To und~rstand th2 op~rat10n of th~ lnv~ntlon, a~sum~ that the mult1b~s comput~r systQm romat~ res~t clrcu1t, see Flgures lA and lB, has had no 1nput for ~n ~rbltrar11y lon~ t1me. W~th no 1nput, the RxD 11ne ls h19h. RxD ls brought 1n at lnput connect1cn lQ, lnvcrted in 1nv~rter 11 and log kally AND0d in AND g~te 1~ w~th the clear slgn~l (CLR) as 1nvert~d by lnv~rt~r 15. The CLR (Tl) 1s proYlded from a one-shot I~, And ~s normatly low. Assum~n~ that the on~-shot 1~ ha~ tlmed DUt, and that CLR 1s ind~ed low, RxD 1s s~nt thr~ugh AND
gate 1~ and tnverter 12 to ~h1~t r~9iStQr ~l dat~ tnput INA and to a lo second one-shot ~5. A fall1n~ edge of RxD lndicates a start ~it, and tr~gers the second one-shot 2~- ThQ actlYe h~gh output Q of the second one-shot 2~ enables and synchronizes t~mer ~ to prov~de an QUtpUt of the ~sync clock. The ~sync clock output provides the clk input for shift reglster ~1 and is 1nverted by 1nvert~r 3D to provide th~ .Tsync ~lock whlch 1s fed through AND gat~ 3~ ~nd ~P4 to the B
lnput of on~-shot 1~ c~us~ of the duratlcn (T?) ~f the second one-~hot ~, the Tsyno clock wlll b~ enabled long en~ugh to clock ln th~ start blt and ~11 7 data blts. Tsync ls fed lnto the shift re~1st~r 21 and .Tsyno lnto the blt counter ~. Slnce the shlft r~ er ~ olocks d~ta ln on th~ r~slng ~dge o~ Tsync, bits are sampl~d ln the approxlmatQ centar. ~hls allows fbr settl~ng tlme, The bit count~r ~ co~ ts th~ number of samples (r~sin~ edges of Tsync, fallin~ edges D~ .Tsync) ~nd sets thQ QD output of b1S count~r h1~h when lt counts to 8. ~hls QD output of b~t c~unter ~5 ~nabl~s .~sync tu thc B ~nput oP tha flrst on~-sh~t ~. ~he next falllng edge of Tsync ~r1s1ng ~ e o~ .Tsync), aftQr the 8th sample, trlgg~rs the flrst one-shot l~ to prov~d~ th~ CLR pulse. CLR clears the b~t count~r ~ and blocks ~xO. By blockln~
RxD, a false state canno~ occur at the fall of bi~ number 7, parity bi~s, stop bits, or noise at the end of the character. ~CL,R from second one-shot 2S clears the T2 pulse before time-outr Time-out is provided, howe~er, prevent hang-up in the PYent of partial transmission or transmissioD errors. In addition, ~he second one-shot 25 is used for T2 to ensure powering up in a known state.
The fall of CLR indicates the end of ~he character, and the remote re~e~ circuit of the present invention waits for the next fall of RxD. Returning now to shift regist~r 21, the parallel date is brought out to two magnitude comparators 27 and 29 and is compared to the reference character set by ~witches Sl - S7. The 8~h bit of the reference character is tied high ~B3 of 29), and the QD
output of bit counter 25 is tied to A3 of magnitude comparator 29. This assures that a match cannot be found until all bits have been clocked in. (The start bit is thrown away, so the comparison is done between the reference character plus one high bi~ and the seven transmitted bits plus QD of bi~ counter 23.) If no match is found, ~he character is ignored, and no reset is generated. If a match is found, the A=B outpu~ of magnitude comparator 29 goes high and ~riggers timer through inverter 33. Timer 31 i~ a 555 timer se~ up in monostable mode~ with a pulse time of approximately lO ms. This lO ms pulse is fed through an open collector inv~r~er 35 to provide the rese~ pulse, RESET/.
The remote reset circuit of ~he present invention above dascribed for Multibus based systems may be embodied in several implementations. The circuit may be implsmented on a. logic card, see Figure 2, which plugs into the system bus. The da-~a inpu~ may be taken from a RS-232 jumper, or from the input ~o the system's U~RT.
3L~ 7 The loglc card n~ed not be a full sl~ board sln~ th~ loglc occup~es ltttle space and ne~s acces~ to only th~ bus power (VCC~, ground, and hardware reset 11nes. Otherwlss, th~ l~gic card c~n b~ plug~ed ~nto ~I bus, other than Multlbus, w~th Qlther a ~S-232 or TT~
compat1ble data lnpu~. Th@ lo~lc may also be lncorporated ~s a part of the CPU or er~al eomm~lnlcatlons pr~nted circult bDard. ~nally~
the lo~c m~y be lncorporate~ a~ a p~rt of thç sQr~al commul)lcat~on ~ntegrated c~rcu~t (UA2T or USART).
If the data ~s T~L datal the UART ~xD T~L tnput may be lnputt~d 0 dir~ctly ~ the RxD inpuS lQ- Alternat~vely data ~y b~ pulle~ from RS-232 ~.onnectors and fed through an ~nv~rter 37 to the RxD ~nput IO, s~e f~gure 3.
The remote reset clrcu~t of the present ~n\lent1on m~y be se~ for use at any rate from 300 to 9600 8al~d ~n th~ above-descr~bed embodi~ents. Th~ follow~ng Baud rate tlm~ng ~d~ustments must be made:
T~ync c~ock ~ust be set for the Baud r~te fr~qu~ncy; e.~., for 30D ~aud, set Ts~nc fQr 300 ~Iz; Cl2ar pulse (T~) must be set to 1.5 X ~sync p~r~od, X 20%; and ~nable puls~ (T2~ mu~t b~ set to IO X Tsync perlod, % 20X; se~ F1~ura 4.
With ref~reno~ again t~ Flgur~ I, the BalJd r te ~s set by first removlng the ~umper plug JPI and tylng t1m~r ~Z RS~ term~nal high ~+5 volts). While observe ~sync on t~mer ~ OUT ~orminal ad~ust RI and R2 for a square w~ve ~f tho Balld rat~ frequ~n~y. Prefer~bly the t1mer ~2 is an NE555 ttmer. ln some cases C3 w111 also have to be chan~d ~o ach~eve thQ dQslrQd square wave fre~uen~y.
S~cond, replace iumP~r plu~ JPI and r~move ~umper plugs JP2 ~nd ~P3. ~hen ~onnect a TT~ squar~ wave ~nerator w1th a per~od of ~0 X
~sync per~od to the one shot ~ at lnput A and tie the one-~hot 2 cl ~ar (CLR) hi~h (+5 volts). At the falling edge of the signal at one-shot 25 input A, observe an active low pulse at test point TPl. Set R3 and C6 such that the low pulse is equal in duration to time Tl.
Remove JP4 and connect a TTL square wave generator with a period of approximately 20 X Tsync period to one-shot 17 input B. A rising edge of the siynal on one-shot 17 input B initiates an active low pulse at one-shot 17 output Q. Set R4 and C5 æo that the duration of the low pulse at one-s~ot 17 output Q is equal to time T2. Then, remove the signal generator, and replace jumper plugs JP2, JP3, and JP4.
Select the character to be used as a reset character, and set switches Sl - S7. Although any 7-bit ASCII
character rnay be used as the reset character, an unassigned control key sequence is suggested. This helps prevent uninten~ional resets. The open position ~ets the bit to a "1" and the closed position sets i~ to a "0", thus Sl - S7 is set to the binary representation of the reset charac~er. Sl se~s bit 0, S2 bit 1, and so forth.
If the remote reset circuit is implemented on a logi~
board, plug the board into an unused bus slot and connect the data input ~o the appropriate point in ~he system.
This may be a connector to the RS 232 input, or a jumper to the TTL RxD inpu~ of the sy6~em UART as above deæ~ribed.
To use the remo~e reset control, simply type the selected reset charac~er on a terminal keyboard and observe the system reset.
In the pre~erred embodiment, componen~s and elements may be selected as follows:
COMPO~ENT PART # D RIPTION
27 N~555 Timer 31 N~555 Timer 17, 25 74LS221 Dual One-Shot 11, 15, 19, 74LS05 Hex Open Collector 30. 33. 35 Inverter 23 74LSZ93 4-Bit Binary Counter Zl 74LS164 8-Bit Parallel Output Shift Register 13, 34 74LS08 ~uad AND Ga~e
2~ 74LS85 4-Bi~ ~agnitude Comparator 29 74LS85 4 Bit Magnitude Comparator 37 DS1~89 RS-2~2 to TTL Conv~rter (optional) Sl - S7 Dip Switch Rl - R4 100K Trim Po~, 10 ~urn R5, R18 10K 1/4 ~att Resistor R6 - R10 5,lK 1/~ Watt Resistor Rll - R17 3.3K 1/4 Watt Resistor Cl, C6 luf Ceramic Capacitor, C2, C4 6800ph Ceramic Capacitor, 35 WVDC
C3 O.luf Ceramic Capacitor~
~5 WVDC
C5 ~.47uf Ceramic Capaci~or, 35 WVDC
The foregoing description of the preferred embodiment of the inven~ion have been presented for pur~oses of illu~tra~ion and description. It i5 no~ intended to be exhaustive or to limit the invention to the precise form di closed, and obviously many modifications and variation6 are possible in light of the abo~e ~eaching. The embodimen~ was chosen and described in order to bes~
explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and wit~
variou modifications as ar@-~uited to the particular use contemplated. I~ is intended that the scope of the invention be definsd by the claims appended hereto.
C3 O.luf Ceramic Capacitor~
~5 WVDC
C5 ~.47uf Ceramic Capaci~or, 35 WVDC
The foregoing description of the preferred embodiment of the inven~ion have been presented for pur~oses of illu~tra~ion and description. It i5 no~ intended to be exhaustive or to limit the invention to the precise form di closed, and obviously many modifications and variation6 are possible in light of the abo~e ~eaching. The embodimen~ was chosen and described in order to bes~
explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and wit~
variou modifications as ar@-~uited to the particular use contemplated. I~ is intended that the scope of the invention be definsd by the claims appended hereto.
Claims (2)
1. A remote reset circuit for remotely resetting a digital system, the remote reset circuit accepting a receiver data (RxD) signal and generating a reset signal upon receiving the correct RxD reset signal, the remote resetting circuit comprising in combination:
adjustable one-shot means triggered by the RxD signal for providing a timed pulse output long enough in duration to permit the clocking in of a desired number of bits transmitted at a predetermined baud rate from the source of the RxD signal;
timing means triggered by the timed pulse output of said adjustable one-shot means for providing a synchronous clock signal (Tsync);
counting means triggered by the Tsync clock signal for counting the desired number of bits clocked in from the source of the RxD
signal;
means for presetting a desired reset pattern of bits;
means for comparing the bits in the desired number of bits clocked in from the source of the RxD signal with the desired reset pattern of bits and for providing a match signal when the desired number of bits clocked in from the source of the RxD signal compares in pattern with the desired reset pattern of bits; and means for generating a signal to reset the digital system upon receipt of the match signal from said means for comparing.
adjustable one-shot means triggered by the RxD signal for providing a timed pulse output long enough in duration to permit the clocking in of a desired number of bits transmitted at a predetermined baud rate from the source of the RxD signal;
timing means triggered by the timed pulse output of said adjustable one-shot means for providing a synchronous clock signal (Tsync);
counting means triggered by the Tsync clock signal for counting the desired number of bits clocked in from the source of the RxD
signal;
means for presetting a desired reset pattern of bits;
means for comparing the bits in the desired number of bits clocked in from the source of the RxD signal with the desired reset pattern of bits and for providing a match signal when the desired number of bits clocked in from the source of the RxD signal compares in pattern with the desired reset pattern of bits; and means for generating a signal to reset the digital system upon receipt of the match signal from said means for comparing.
2. A remote reset circuit for remotely resetting a digital system, the remote reset circuit accepting a receiver data (RxD) signal and generating a reset signal upon receiving the correct RxD
signal, the remote resetting circuit comprising in combination:
one-shot means triggered by the RxD signal for providing a timed pulse output long enough in duration to permit the clocking in of a desired number of bits transmitted from the source of the RxD signal;
adjustable timing means triggered by the timed pulse output of said one-shot means for providing an approximately square-wave synchronous clock signal (Tsync) having adjustable duration;
counting means triggered by the Tsync clock signal for counting the desired number of bits clock in from the source of the RxD
signal;
means for presetting a desired reset pattern of bits means for comparing the bits in the desired number of bits clocked in from the source of the RxD signal with the desired reset pattern of bits and for providing a match signal when the desired number of bits clocked reset pattern of bits; and in pattern with the desired reset pattern of bits; and means for generating a signal to reset the digital system upon receipt of the match signal from said means for comparing.
signal, the remote resetting circuit comprising in combination:
one-shot means triggered by the RxD signal for providing a timed pulse output long enough in duration to permit the clocking in of a desired number of bits transmitted from the source of the RxD signal;
adjustable timing means triggered by the timed pulse output of said one-shot means for providing an approximately square-wave synchronous clock signal (Tsync) having adjustable duration;
counting means triggered by the Tsync clock signal for counting the desired number of bits clock in from the source of the RxD
signal;
means for presetting a desired reset pattern of bits means for comparing the bits in the desired number of bits clocked in from the source of the RxD signal with the desired reset pattern of bits and for providing a match signal when the desired number of bits clocked reset pattern of bits; and in pattern with the desired reset pattern of bits; and means for generating a signal to reset the digital system upon receipt of the match signal from said means for comparing.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US775,547 | 1985-09-12 | ||
| US06/775,547 US4686526A (en) | 1985-09-12 | 1985-09-12 | Remote reset circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1260147A true CA1260147A (en) | 1989-09-26 |
Family
ID=25104751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000517416A Expired CA1260147A (en) | 1985-09-12 | 1986-09-03 | Remote reset circuit |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4686526A (en) |
| CA (1) | CA1260147A (en) |
| GB (1) | GB2180967B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5241402A (en) * | 1989-12-04 | 1993-08-31 | Xerox Corporation | Concurrent modem control in a reprographic machine |
| CA2072178A1 (en) * | 1991-06-24 | 1992-12-25 | Said S. Saadeh | Innate bus monitor for computer system manager |
| DE69230306T2 (en) * | 1991-09-09 | 2000-04-13 | Compaq Computer Corp | Remote bootstrap system and method for bootstrapping a computer system |
| WO1993010615A1 (en) * | 1991-11-15 | 1993-05-27 | Server Technology, Inc. | Systeme for protecting and restarting computers and peripherals at remote sites which are accessible by telephone communication |
| GB9214198D0 (en) * | 1992-07-03 | 1992-08-12 | Texas Instruments Ltd | Method of resetting coupled modules and a system using the method |
| US5430865A (en) * | 1992-10-13 | 1995-07-04 | Astro Sciences Corporation | Hardware remote reset circuit |
| US5652837A (en) * | 1993-03-22 | 1997-07-29 | Digital Equipment Corporation | Mechanism for screening commands issued over a communications bus for selective execution by a processor |
| US5379341A (en) * | 1993-06-16 | 1995-01-03 | Odessa Engineering, Inc. | Device for remotely resetting electronic appliances in response to telephone rings |
| DE19712372A1 (en) * | 1997-03-25 | 1998-10-01 | Deutsche Telekom Ag | Device for remotely resetting computing systems, in particular microcomputers |
| FR2766594B1 (en) * | 1997-07-24 | 2000-01-28 | Sgs Thomson Microelectronics | EXTERNAL CONTROL RESET FOR A NON-VOLATILE MEMORY IN AN INTEGRATED CIRCUIT |
| JP5535766B2 (en) * | 2010-05-27 | 2014-07-02 | ラピスセミコンダクタ株式会社 | Timer circuit |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1805463B2 (en) * | 1968-10-26 | 1971-10-14 | BLOCK SYNCHRONIZATION METHOD FOR TIME MULTIPLEX SYSTEMS WITH PULSE CODE MODULATION | |
| US3796995A (en) * | 1972-12-15 | 1974-03-12 | Johnson Service Co | Remote coded dual state controller apparatus |
| US3813531A (en) * | 1973-01-02 | 1974-05-28 | Honeywell Inf Systems | Diagnostic checking apparatus |
| IT1047329B (en) * | 1975-09-30 | 1980-09-10 | C Olivetto E C S P A Ing | REMOTE IGNITION AND INITIALIZATION DEVICE OF A TERMINAL |
| JPS6039189B2 (en) * | 1979-05-23 | 1985-09-04 | テクトロニツクス・インコ−ポレイテツド | signal measurement device |
| DE2930586A1 (en) * | 1979-07-27 | 1981-02-12 | Siemens Ag | CIRCUIT ARRANGEMENT FOR SYNCHRONIZING A SUBordinate DEVICE, IN PARTICULAR A DIGITAL SUBSCRIBER STATION, BY A SUPERIOR DEVICE, IN PARTICULAR A DIGITAL SWITCHING CENTER OF A PCM REMOTE |
| DE2939159C3 (en) * | 1979-09-27 | 1982-03-25 | Siemens AG, 1000 Berlin und 8000 München | Method for the synchronization of key devices that are operated as part of a packet network |
| US4481574A (en) * | 1982-02-18 | 1984-11-06 | Pinetree Systems, Inc. | Programmable interface between remote terminals and a computer |
| JPS59221047A (en) * | 1983-05-30 | 1984-12-12 | Victor Co Of Japan Ltd | Synchronizing signal detecting circuit for digital signal transmission |
| US4535198A (en) * | 1983-07-18 | 1985-08-13 | At&T Information Systems Inc. | Digital terminal keyboard dialing |
-
1985
- 1985-09-12 US US06/775,547 patent/US4686526A/en not_active Expired - Fee Related
-
1986
- 1986-09-03 GB GB8621221A patent/GB2180967B/en not_active Expired
- 1986-09-03 CA CA000517416A patent/CA1260147A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB8621221D0 (en) | 1986-10-08 |
| US4686526A (en) | 1987-08-11 |
| GB2180967B (en) | 1989-03-15 |
| GB2180967A (en) | 1987-04-08 |
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