CA1278101C

CA1278101C - Paged virtual cache system

Info

Publication number: CA1278101C
Application number: CA000525688A
Authority: CA
Inventors: Thomas F. Joyce; Forrest M. Phillips; Ming T. Miu; Jian-Kuo Shen
Original assignee: Honeywell Bull Inc
Current assignee: Bull HN Information Systems Inc
Priority date: 1985-12-19
Filing date: 1986-12-18
Publication date: 1990-12-18
Anticipated expiration: 2007-12-18
Also published as: US4785398A; EP0232526A3; KR870006471A; ES2039351T3; AU6647886A; EP0232526A2; AU595846B2; KR920005280B1; DE3688192D1; EP0232526B1; DE3688192T2

Abstract

ABSTRACT OF THE DISCLOSURE

A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes.
Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories f or processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.

Description

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The present invention relates to computer systems and more particularly to a cache system for use in such S systems.

P~ig~

More and more computer systems include processors which are capable of executing instructions at higher and higher rates as compared with the speed 4f high capacity main memory system~. To improve instruction execution speed, these systems utilize low capacity, high speed cache memories. The cache m~mories are used - to store a limited num~er of instruction~ and/or data blocks. For each memory read operation, the processor ch~cks ~he cache memory to determine if the information is stored there (a hit occurred). When there is a hit condition, the information will be read out from cache memory; otherwise (a miss condition), it will be fetched from main memory.
With such higher and higher processor instruction execu~ion ra~e~, the cache hit rate becomes extremely important in terms of both processor and system perfonmance. That is, a hit rate les~ than 95 percent can re~ult in a sub~tantial decrease in overall system 25 performance. This is partlcularly true in the case of multiprocessing systemq.
Normally, the proceq~or addresses the main and cache memorie~ using a virtual address defining a relative memory location. The real or physical address ~.;;27~

defining an actual memory location is obtained by translating the virtual address. The virtual address normally includes segment, page and word address bits.
The word address bits are not translated but the 5 segment and page address bits are translated by an address translation buf~er (ATB) or a memory management unit (MMU).
Since main memory is much larger than the cache memory, there are several common mapping techniques 10 used for efficiently mapping information from main memory into the cache memory. A number of these techniques are described in an article by C. J. Conti entitled, "Concepts for Buff er Storage, n published in the March 1969 issue o~ IEEE Computer Group News. One 15 technique is the sector technique in which the cache and main memories are divided into a number of sectisns or pages, each of which consists of a large number of blocks. A main memory sector or page is mapped into any one of the sectors of the cache memory a block at a 20 time. Each block resident in the cache memory has a tag associated with it for determining when the block is in cache memory. The cache memory is capable of holding only 2 small number of sector~, and each cache sector, at any given time, can contain only blocks from 25 the same main memory sector. The search in the sector organized cache is fully associative in that any block potentially can be found in any one of the cache sector 8.
While the system requires only one tag per sectar 30 and one validity bit per block, all of the tags of all of the blocks stored in the cache memory must be searched which is time-consuming or requires additional hardware.

In another technique, that of set associative~ the cache and main m~mories are divided into a plurality of sets of blocks. A main memory block may be mapped into any one of the cache blocks in one set. While this technique reduces the amount of hardware required by the fully associative technique, it still requires a tag for each stored block. Therefore, the number of entries within a set is increased. This is accompanied by a factorial increase in comparison hardware.
In another technique, that of direct mapping, any main memory block can be placed in only one cache block. That is, each main memory block is preassigned a certain cache memory location. Thereore, searching is faster and requires a small amount of hardware.
15 While the arrangement has these advantages, it is said to lack flexibility. Therefore, the set associative technique has been employed using a limited number of entries per set.
In order to provide a balance between the extremes 20 in cache organizations in transferring too much data or requiring a large number of tags, one system employs a set associative sector cache. This system is disclosed in U. S~ Patent No. 4,493,026. While efficiency is achieved over the fully associative technique, the 25 system still limits the number of entries per set and limits the amount of blocks of data which can be stored~
It i8 accordinyfy a primary object of this invention to provide an improved page or sector cache 30 uni~.
It i~ a further object of thi~ invention to provide a cache unit for a processing unlt which requires a small number of tag~ thus minimizing the ~mount of hardware circuits and cost.

51~-02220 Tt is another further object of the present invention to provide a cache unit which can be used for storing instructions or data and is usable in a multiprocessing systemO
S It i~ still a further object of the present invention to provide a fast access cache unit capable of storing data for a number of pages with great flexibility.

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The ~oregoing objects are achieved according to the present invention by a cache memory having a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions 15 on a page basis. More particularly, an input QM in response to an address generated by an associated processing unit (CPU), provides a cache address including a page level number which identifies where all of the required information resides in the other 20 memories for proces~lng the request relating to the specified page~ This organization permits the efficient processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both 25 con~istency and synonym problems.
A consistency or coherence problem can occur vla multicache memory system when data inconsistency exists in the private cache memories and main memory~ That is, po~entially, the content3 of the same main memory 30 block can appear in several cache memorieR at the same ~ 2~ 510-02220 time~ When suf~icient steps are not taken, the multiple copies of that block storsd in the cache memories can differ with one another and with main memory.
The cache memory of the present invention utilizes a physical address CAM which is coupled to respond to the addresses of data being written into main memory by any other processing unit. The CAM operates to generate a page level number which can be utiliæed by one o~ the remaining memories storing block address information to invalidate the affected block if stored in the cache memory.
Because of the random relationship existing between a virtual ~logical) and its translated 15 physical tabsolute) address, two virtual addresses may be mapped into the same physical a~dress. This results in a synonym problem. The same physical address CAM is also used to detect potential synonym problems. That i5, the physical address CAM operates to detect any 20 comparison between the VMMn new physical address and a previously stored valid physical address. Upon such detection, the page level number provided by the physical address CAM is used to store the new virtual address in the input CAM at the specified level. This 25 eliminates the need to reload the same page as well as eliminating the synonym problem.
The use of a common cache address ~page level number) for accessing all of the required informatiQn pertaining to a page reduces the compl~xity and 30 enhances the overall performance of the cache memory.
The cache organization also permits address translation to be overlapped with the interrogation of the input 6 7~43~-40 CAM. As illustrated in the different embodiments of the pr~sen-t invention, thls same oryani~ation can be utilized for both instruction and data cache memories.
Addi-tionally, the cache memory of the present invention can be used to process either virtual or physical addresses. That is, the common cache address will be generated in the same manner in response to either a virtual or physical addres3.
The oryanizatlon of the cache memory permlts the use of like VLSI memory elements, further reducing costs and enhanciny speed of operation.
In accordance the present invention provides a cache memory for use in a multiprocesslng systam ln ~hich a number of processing units connect in common to share a main memory, said main memory being divided into a number of segments in whlch each segment includes a plurality of pages, each containing a plurality of blocks, each of which has a plurality of words, said cache memory being coupled to one of saLd processing units for providlng fast access information fetched from said main memory in response to requests for information received from said one processiny unit, each request includiny an input address for identifying the information words to be accessed from saicl cache memory, said cache memory comprising, a plurality of content addressable memories, each contain:LncJ a plurality of loca~ions for storing address information pertaining to each of a predetermined number of said plurality of pages, a first one of sald content addressable memories being coupled to receive said input address from said one processing unit; a plurality of directly addressable random access memories, each containiny a plurality of locatlons Eor :~2~

6a 72434-40 storing address, control and da~a information pertaining ~o each of said plurality of pages; a common int2rnal bus connecting each of content addressable and directly addressable memories .ln common; and, cache control means coupled to re~ei~e said requests from said one processlng unik, said cache control means belng operative in response to each request ~or information to apply a first portion o~ said input address corresponding to an effective address to said first one of said content addressable memories, said flrst content addre~sable memory being operative upon detectiny a hik condition indlcatlng that the page containing the requested infoxmation resides in cache memory to generate a page level number value on said bus identifying where information is stored in said content addressable and directly addressable memories pertinen~
to said page, sald cache control means applying sald page level number value together with other portlons of sald input address as a cache address to other ones of said memories as required for readlng out the requested informatlon words to said one processing unit.
In accordance the present invention also provides a cache memory for use with a processincJ unit which connects to a main memory, said main memory being divided into a number o~
paSies~ each containing a plurality of blocks, each of which has a plurality o~ words, said aache memory providiny fast access information fetched from said main memory in response to requests for information received from sald processing unit, each request including an input address for identifyiny the information words to be accessed from said cache memory, said cache memory comprising, a plurality of content addressable memories, each containing a plurality of locations for storiny a first type oi informati.on pertaining to each of a number of said plurality of pages, a first one of said conten~

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6b 7243~-40 addressable memories being coupled to recelve said input address from ~aid processing unit; a plurality of directly addressable random access memories, each containing a plurality of locations for storing other types o~ inEorma~ion pertalning to each of said plurality of payes; a common internal bus connecting each of content addressable and directly addresæable memories in common; and cache control means coupled to receive said requests frorn said processing unit, said cache control means being operative in xesponse to each request for information to apply a first por~ion of said input address to said first one of said content addressable memories, said first content addressable memory being operative upon detecting a hit condition indicaking that the page containing the requested information resides in cache memory to generate a page level number value on said bus identifying where said other types of information is stored in said content addressable and directly addressable memories associated wlth said page, said cache control means applying said page level number value together wlth other portions of said input address as a cache address to other ones of said memories for accessing the reque~ted information words.
The novel features which are belleved to be characteristic of the invention both as to its or~anization and method of operation, together with further ob~ects and advantages will be better understood from the Eollowing descrlption when considered in connectlon with the accompanying drawings. It is to be expressly understood, however, that each of the drawings are given for the purpose of illustration and description only and are not intended as a definition of the limits of the present invention.

6c 72434-40 BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a multiproces~ing system which includes the apparatus of tha present invention.
Figures 2 and 3 respectively are block dlagrams of data and lnstruc-tion cache memories which are constructed according to the present invention.
Figures ~a through 4e are diagrams illuskrating the loyical organizations of the different memorles which are included in the cache memorie~ of Figures 2 and 3.

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Figures 5a through 5d are diagrams illustrating the types of addresses utilized in the cache memories of Figures 2 and 3.
Figures 6a and 6b are flow diagrams used in 5 describing the operation of the data cache memory of Figure 2.
FigureS 7a and 7b are flow diagrams used in describing the operation of the instruction cache memory of E'igure 3.

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Figure 1 shows a multiprocessing system lO which includes a plurality of subsystems 14 through 32 coupled in common to a system bus 12. The subsystems include a plurality of central subsystems 14 through 15 16, a plurality of memory subsystems 20 through 28 and a number of input/output peripheral subsystems 30 through 38. Each subsystem includes an interface area (not shown) which enables the associated unit or units to transmit or receive requests in the form of data, 20 addresses and commands to or from system bus 12.
The organization of each central subsystem is the same. Each central subsystem includes a pipelined central processing unit (CPU) such as 14-2 which couple~ to a cache unit such as 14 4. For the purpose 25 of the present invention, each CPU can be considered convention~l in design and may be implemented using 32-bit microprocessor chips capable o~ proces~ing virtual and phy si cal addresses.
Each cache unit includes a data cache memory and 30 an instruction cache memory which are shown in detail in Figures 2 and 3. Both cache memories are organized ~7~ 510-02220 in the same manner, the major difference being that the cache memory of Figure 2 processes data and the cache memory of Figure 3 processes instructions. Therefore, the same description for Figure 2 will not be repeated 5 for Figure 3.

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Referring to Figure 2, it is seen that data cache memory 14~40 includes a virtual memory management unit (VMM:U) 14-400 for translating CPU 32-bit virtual 10 addresses into physical addresses. The CPU addresses are received and initially stored in a 32-bit address regis~er ~AR) 14-402.
For the purpose of the present invention, the VMMU
14-400 can be constructed from conventional integrated 15 circuit chips. VMMU 14-400 is capable of operation in a virtual address mode and a physical address mode as a function of a mode signal provided by the cache control circuits of block 14-404. When operated in virtual address mode, VM~U 14-400 converts the virtual address segment and page number bits of Figure 5a into ~he physical address page frame number bits of Figure 5b.
When operated in ph~sic~l address mode, VMMU 14-400 inhibits translation and the CPU address bits are transferred for direct use.
In a`ddition to the translation circuits, VMMU
14-400 includes other clrcuits. For example, it inGludes a 4-bit word counter used for designating word addresses during cache write operations.
The cache control circuits of block 14-404 operate 30 to decode the cache requests it receives Prom CPU
14;2. In response to such requests, it generates the ~'7~

g required sequence of control signals in addition to command signals which are applied via the command portion of system bus 12 for directing the transfer of data into and out of data cache memory 14-40 based upon 5 the input signals it receives from CPU 14-2 and other units within cache memory 14 40 as explaine~ herein.
For eaae of programming, the control circuits take the form of a microprogrammed control unit.
As shown, cache memory 14-40 includes content 10 addressable memorie~, such as cache address CAM (CAC) memory 14-406 and physical address CAM ~PAC) memory 14~408 in addition to directly addressable memories, such as Page RAM (PGR) memory 14-410, Physical Address RAM (PAR) memory 14-412, Block Tag Array (BTA3 memory 15 14-414 and Page Tag Array (PTA~ memory 14-416.
According to the teachings of the present invention, all of these memories connect in common to an internal common bus 14-420 as shown. The cache control circuits of block 14-404 by applying enable signals to the 20 different memories, establishes which memory is to serve as the source of page level number signals.
As explained herein, this organizational structure permits all of the related information pertaining to a given page to be directly mapped into the same level in 25 each of the memories where the related information is to be ~tored. Thus, simultaneous direct access to all of this information i5 readily obtained by applying a single cache address page level number value to bus 14-420. This minimizes complexity, reduces C08~l 30 enhances speed of operation, and provid~s added flexability.

Additional inputs to PGR memory 14-410 include the output of a four position selector switch 14-430, the page level number from bus 14-420 and a clear input sign~ from control circuits 14-404. The switch 14-430 5 receives address signals from four sources selected under the control of cache control circuits 14-404 in re~ponse to coded signals SWl. The address register 14-402 applies block and word number address signals to positlon 3, VMMU 14-400 applies PAL and CT~ address 10 bitg to position 2, BTA memory 14-414 applies block number bits to position 1 and a 10-bit offset register 14~432 and incrementor 14-434 apply block and word number bits to position 0. PGR m~mory 14-410 connects to a data bus of CPU 14-2 and to the data lines of 15 system bus 12 via a data FIFO array 14-436. The FIFO
array 14-436 contains eight 36-bit register locations for storing data words transferred between memory PGR
14-410 and system bus 12. The FIFO 14-436 can be considered conventional in design and could take the 20 form of the FIFO circuits disclosed in U.S. Patent No.
4,195,340.
The same four sources that connect to switch 14-430 also connect to a second switch 14-440 as shown. The output of switch 14-440 from the source 25 selected in r~sponse to coded signals SW2 is applied as one of the inputs to a 30-bit output memory address register 14-442. Register 14-442 receives 20 physical address bits from PAR memory 14-412 which it applies to the address bus oE system bus 12 along with the 10 30 address bits from switch 14-440 and parity bits.
A two-position selector switch 14-444 receives block number (BN) address signals from address register 14-402 and offset register 14-432 selected in response ~27~

to signal SW3. The output of switch 14-444 is applied as an input to BTA memory 14-414. The BTA memory 14~414 also is connected to receive block number (BN) address signals from the address bus of system bus 12 5 which have been previously stored in a snoop register of block 14-450 in response to a bus write command.
The BTA memory 14 414 also receives consistency page number level sign~ s and a hit signal from PAC memory 14--40 8 r As shown, PAC memory 14-408 couples to the command and address buses of system bus 12 through the "Snoop"
register and decode circuits of block 14-450. As explained herein~ these connections to system bus 12 permits use of the PAC memory 14-408 in maintaining 15 data consistency. Additionally, PAC memory 14-408 receives the upper 29 physical address bits (PAU) from VMMU 14-400.
Another unit which also connects to common bus 14-420 is the level replacement circuits (LRU) 14-422.
20 These circuits in response to a miss signal from CAC
14-406 generate a page level number code on bus 14-420 specifying where the related information pertaining to the n~w page is to be stored. The LRU 14-422 includes a replace array which stores information for defining 25 the leas~ recently used page level for replacement.
LRU 14~422 may be constructed uslng conventional register chips. A preferred embodi~ent of LRU 14-422 i5 disclosed in the copending~ patent application of Ming T. Miu, et al., entitled, ~Least Recently Used 0 ~eplacement Level Generating Apparatus~" seri~ number filed on even date and assigned to the same assignee as named herein.

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The organizations of the different CAM and RAM
memories are shown in Figures 4a through 4e. The CAC
memory 14-406 is a 32 locations by 21-bit content addressable memory (CAM) array~ That is, its locations 5 are identified or addressed by their contents. As such~ CAC memory 14-406 in addition to including 32, 21-bit register locations has 3~ comparison circuits whose outputs feed a priority encoder circuit. An idenkical comparison or match between the valid 20-bit 10 contents of any location and the 20-bit effective page number (EPN~ address of Figure 5c produces a hit signal which is encoded into a 5-bit page level number value by the priority encoder circuit. In order to detect the occurrence of both segment and page hits, segment 15 and page address bits are compared separately. The priority encoder circuit is used to signal an illegal occurrence of more than one hit signal and for selecting the highest priority binary ONE input in that situation. The CAC memory 14-406 as well as the other 20 CAM memories of Figure 2 can be constructed from standard integrated circuit chips using well known techniques~
As seen from Figure 4a, each 20-bits of CAC memory 14-406 stores a 20-bit effective page number ~EPN) 25 value and a valid bit (VN). The EPN values represent the 32 most recently used pages resident in PGR memory 14-410 at any given instant and their validity status . The EPN values usually represent virtual addresses which consist of a 10-bit segment number value and a 30 10-bit page number value derived from a 32-bit CPU
virtual address as illustrated by a comparison of Figures 5a and Sc.

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In the system of the preferred embodiment, main memory is logica~ly divided into a number of ~qual segments which corresponds to the larges~ subdivision of memory spaceO Each segment is given a unique 5 identification by the user for specifying the collection of information associated with the execution of a process. Main memory ha~ 210 or 1024 segments as established by the size of the segment number portion of the virtual address of Figure 5a.
Each segment is subdivided into smaller units called pages. All of the pages of a segment are of the same size. Ther~ are 210 or 1024 page~ as established by the size of the page number portion of the virtual address of Figure 5a. Each page has a size of 26 or 64 15 blocks and each block has 24 or 16 words or 8 double words. The~e values are established by the ~izes of the block and word number portions of the virtual address of Figure 5a. Each word has 16 bits which corresponds to 2, 8-bit data bytes~
Access to segments is controlled by a ring mechanism which is established by a 2-bit ring number portion of each virtual address (see Figure Sa~.
Segment and page addressing is accomplished through the use of segment de~criptor tables and pages tables. For 25 further information about these mechanisms, reference may be made to the text entitled, "The Multics System~
An Examination of Its Structure," by Elliott I.
Organick, Copyrigh~ 1972.
When the EPN values represent physical addresses, 30 they consist of a 20-bit page frame number derived from a 30-bi~ CPU physical addre~s as seen from a compariqon of Figures 5b and 5c. From the point of view of CAC
memory 14-406, there is no difference in operation from ~i~7~

that of virtual addresses- In either Ca~ef CAC memory 14-406 provides a page level number which is combined with the block and word number values derived from the CPU virtual address or offset value of the CPU physical 5 address to form the cache address of Figure 5d.
Figure 4b discloses the organizations of PAC
memory 14-408 and PAR memory 14-412. Both memories contain 32 register locations for storing the 32 most recently u~ed page frame number values (i.e., the upper 10 20 bits of the physical addre~s) generated by VMMU
14-400. However, PAC memory 14-408 also contains a valid bit ~VB) location ln each r2gister location. The contents of PAC memory 14-408 are addressable by any 20-bit page frame number ~PFN) portion of a memory 15 physical address of a write command applied to system bus 12 by another one o~ the other subsystems of Figure Comparison circuits within the memory 14-408 operate to generate a hit- signal when an identical 20 comparison in page frame numbers is detected. This maintains con~istency by permitting the invalidation of those copies of bloeks stored in PGR memory 14-410 which have been altered by other subsystems/devices through BTA memory 14-414. That is, PAC memory 14-408 25 through its comparison priority encoder circuits generates a hit signal and a page level number value which is used to accomplish the required invalidation.
In a similar fashion, PAC memory 14-408 detects synonym problems in response to a new page frame number 30 generated by VMMU 14-400. When virtual add~ess page number values have been mapped into the same physical address frame number, PAC memory 14-408 generates a hit signal which is applied to control circuits 14-404 and a page level number value which is applied to bus 14-420. Thi~ in turn results in the invalidation of the appropriate virtual address page in CAC memory 1~-406.
The PAR memory 14-412 serves as mapping unit in that it provides the required physical add~ess page frame number values in the case of a cache miss.
Because PAR memory 14-412 stores the same page frame n~mber values as stored in PAC memory 14~408, it may be 10 possible to combine the two memories in some manner to share a set of common memory registers. However, for reasons of clarity and slmplicity, both memories are shown separately.
Figure 4c shows the organization of BTA memory 15 14-~14. It has 32 levels, each having 64, 2-bit wide directly addressable register locations. This memory is used track the valid and written status o~ the blocks within each of the 32 pages stored in PG~ memory 14-410. The written bit (~B) locations are used during 20 write back or siphon operations to identify blocks which have been altered by CPU 14-2. For this purpose, BTA memory 14-414 further includes a priority encoder circuit for detecting the presence of written blocks denoted by binary ONES when a number of locations are 25 accessed in parallel. The valid bit (VB) location is used to maintain data consistency as discussed earlier.
Figure qd shows the organization of PGR memory 14-410. This memory serves as the data store and holds up to 32 pages, each two kilobytes in size. As shown, 30 each page i5 subdivided into 64 blocks, each block having 8 double words or 16 words or 32 bytes.

L 5lo-o222o Figure 4e shows the organization of PTA memory 14-416. This memory maintains status for each of the 32 paqes stored in PGR memory 14-410 which the data cache 14-40 uses to make control decisions regarding S the pages. ~s shown, memory 14-416 has 32, 2-bit locations. The first bit location stores a private bit which when set indicates that only the current process will use that pageO The second bit location stores a modiied bit which when set indicates that the shared 10 memory image of a page in main memory has been altered since it was last retrieved from virtual store ~e.g.
I/O disk ~torage).

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As seen from Figure 3, the instruction cache 15 memory 14-53 is organized in the same manner as data cache memory 14-40. Similar reference numerals are used to designate like blocks in Figures 2 and 3 (e.gO
14-400, 14-500 and 14-410, 14-510, etc.). The differences are those changes required for efficient 20 and high speed instruction processing. For this reason, a combination of page registers 14-535A, 14-535B and instruction address registers 14-534A, 14-534B are utilized in place of offset register 14-432 for the storage of paye level number and offse~ values, 2S resp4ctively.
As shown, the outputs of the page registers 14-535A and 14-535B connect to different positions of a two-position selector switch 14-533. Th~ outputs of instruction address registers 14-532A and 14-532B
30 connect to the 0 and 1 positions of selector switch ~17-14 530. The instruction address registers 14-532A and 14-532B also include increment circuits 14-534A and 14-534B~
The pairs of page and instruction address 5 registers 14-535A and 14-535B and 14-532A and 14-532B
permit the concurrent processing of instructions from two blocks of instructions. Briefly, when an instruction f etch request is received by cache memory 14-50, the virtual address of~set value consisting of 10 the block number and double word number is loaded into the instruction address register not being used (e.g~
IAR2). At the same time, the corresponding page register (e.g. PRl) is loaded with the page level number value. Thereafter, under the control of signals 15 from the cache control circuits 14-504, the first positions of selector switch circuits 14-530 and 14-533 are enabled for transferring signals representative of the offset and page level number values. Each time CPU
14-2 accesses an instruction, the contents of the 20 instructiOn addr~ss register (e.g. IAR2) are incremented by one and returned to the register.
It will be noted that since cache memory 14-50 is dedicated to processing CPU requests for instructions rather than data, it can be simplified in certain 25 respects. That i9, the modified bit positions of BTA
memory 14-414 shown in Figure 4c and the priority encoder can be eliminated. Also, PTA memory 14-416 can b~ eliminated~

~t~ 510-02220 12~.S5;.~1P.~Flg~_Q~_QP~ QE_5;~ Q~Y_1~=4Q

With reference to Figures 1, 2, 4a through 4e~ and Sa through 5d, the operation of cache memory 14-40 will now be described in connection with the flow diagrams 5 of Figures 6a and 6b. It is assumed that cache memory 14-40 receive5 a reques~ for data. The re~uest includes signals specifying the type o request together with a virtual address having the format o~
Figure 5a. As seen Erom Figure 6a, prior to processing 10 request~, the cache memory 14-40 will have been previously inltialized to a known state following the system of Figure 1 having been powered up (i.e., block 602).
From Figure 6b, it is seen that during 15 initialization, the cache control circuits 14-404 initialize CAC memory 14-406, PAC memory 14-408, BTA
memory 14-414 and PTA memory 14-416 via a clear signal applied to the clear input terminals of each memory (i.e~, block 602-2). This results in the valid ~it 20 tVB) positions within the CAC and PAC memories 14-406 and 14-408 of Figures 4a and 4b, the valid and written bit position~ of BTA memory 14-414 of Figure 4c and private and modif ied bit positions of the PTA memory 14-416 of Figure 4e all being cleared to binarv ZEROS.
Also, as shown in block 602-4, the replace~ent control ~ircuits 14-422, in response to the clear signal, set up 32 locations with initial level values in its array. The locations are assigned values 0 through 31 wherein the value 31 is the most recently 30 used and value 0 is the least recently used. The locations are updated in a round robin fashion to ~78~ 510-02220 provide the replacement of pages on a least recently used basi Next, the cache address registers 14-432 and 14-442 are cleared to ZEROS (i.e., block 602 6~.
Now, cache memory 14-40 is ready to process CPU
requests (i.e., block 604) and monitor bus write requests received from other subsystems of Figure 1 (i.e., block 608) .
As previously mentioned, PAC memory 14-408 perorms a bus watch or monitoring function in the 10 manner illustrated by blocks 608-2 through 608-8. More specifically, the snoop register and decode circuits 14-450 monitor the requests applied to system bus 12 by other subsystems. Upon detecting a write to memory request, the circuits 14-450 generate an output write 15 signal which is applied to PAC memory 14-408. This causes the 20 physical address page frame nu~ber bits of that request to be loaded into the snoop register part of block 14-450. Th~ write signal also causes PAC
memory 14 408 to interrogate its contents using the - 20 page frame number bits. If no match or hit is detected, the above operations are repeated.
When a hit is detPcted, PAC memory 14-408 applies a hit signal as an input to the cache control circuits 14-404. It also applies a page level number value as 25 an input to BTA memory 14-414 together with the block number of the write request previously stored by circuits 14-450. Under control of the circuits 14-404, the valid bit of the designated block at the specified level is reset to a binary ZERO. Only the presence of 30 a write request or command generated by another subsystem will be detected by the circuits of block 14-450. As seen from block 608-8, after the invalidation operation, monitoring continues. It will be noted that through the use of the page level number value, cache memory 14-40 maintains data consistency in a fast and efficient manner~
In parallel, with maintalning bus consistenGy, cache memory 14-40 processes CPU data reques~s. The occurrence of a data r~quest results in the performance of the sequence operations shown in blocks 604-2 through 604 18 o sheet 2 of Figure 6b. As shown, in 10 response to a CPU data request, virtual address register 14-402 is loaded with a virtual address formatted as shown in Flgure 5a. Using the 20-bit effective address number tEpN) bits (Figure Sc), the contents o~ CAC memory 14-406 are interrogated. If CAC
15 memory 14-406 detects an identical match between the EPN bits and the segment and page number bit contents of one of the CAC memory locations, it operates to generate a hit signal and a page level number value on internal bus 14-420.
The cache address made up of the page level number from CAC memory 14-40S and offset from register 14-432 is loaded into the address registers of BTA memory 14-414 and PGR memory 14-410. Also, the block and word (BN; WN) values are loaded into offset register 25 14-432. The valid VB bit for the specified block is checkecl by BTA memory 14-414. If it is valid (a binary ONE) and the CPU cache request is a read request, the cache control circuits 14-404 cause the requested 36-bit data double word to be read out from PGR memory 30 14-410 onto the input bu~ of CPU 14-2 and loaded into the CPU's execution (E) unit data registers. During the sam0 cache control cycle of operation, the contents o~ offset register 14-432 are incremented by one.

~7~ 510-02220 As shown, if the cache control circuits 14-404 detenmine that the read operation is complete (i.e~, only one double word requested), this completes the operation and the cache memory 14-40 is ready to 5 process another CPU request. If the read operation i~
not complete (i.e., more than a single double word requested), then cache control cirucits 14-404 test for the occurrence of an off~et overflcw condition. If an overflow i~ detected, the cache memory 14-40 will 10 initiate another new address sequence. In the absence of an over~low, the read operation i9 continued upon another double word from PGR memory 14-410.
As seen from block 604-4, if a CAC miss is detected, the sequence of operations of blocks ~05-2 15 through 605-22 (Figure 6b, Sheet 3) are performed.
- More specifically, the cache control circuits 14-404 cause LRU replacement circuits 14-422 to apply a page level number value to bus 14-420. This number concatenated with the of f set val ue is used as the cache 20 address by the siphon old page sequence of block 614.
Next, VMM:U 14- 400 generates a 20-bit physical address having the format of Figure 5b. The page frame number bits ~PAU) are applied to the PAC memory 14-408 and used to check for the presence of virtual address 25 synonyms. If PAC memory 14-408 detects an identical comparison between the page frame numbers, it generates a hit signal and page level number signals as output~.
The page level number and offset values are concatenated to form the cache address applied to bus 30 14-420. As seen from block 605~10, the cache control circuits 14-404 load the CAC location designated by the PAC page level number signals with the EPN value ~rom AR register 14-402. At the ~ame time, the valid bit V~

-2~-in the CAS location is set to a binary ONE. This prevents the mapping of more than one virtual address into the same physical address.
If a pa~e frame hit i5 not detected by PAC memory 5 14-408, then a siphon operation is performed as indicated by block 605-12. That is, the squence of operation~ of blocks 614-2 through 614-12 is per~ormed. This results in the transfer of written blocks of a page back to main memory so that the blocks 10 o~ a new page can be written into tht same page.
As seen from block 614-2, the page level number value generated by the LRU replacement circuits 14-422 is u~ed to obtain the block number value for any written block in that pageO A group of written bit (WB) locations are read out and the BTA priority encoder circuit generates a block number ~BN) value for the highest priority location containing a binary ONE.
The page level number from the LRU circuits 14-422 concatenated with the BTA block number value selected 20 via position two of swi~ch 14-430 is used as a cache address to read out the block of words from PGR memory 14-410, a double word at a time into FIFO memory 14-436.
Also~ the LRU page level number value is used to 25 read out the physical address page frame number from PAR memory 14-412. The PAR memory page frame number concatenated with the BTA memory written block number and VMMU word counter selected via position 1 o~ switch 14-440 is loaded into memory address register 14-442.
30 This address i5 incremented by VMMU 14-400 and is used to write the block of eight double words from PGR
memory 14-410 in~o main memory. A~ seen from block 614-10, when the entire block has been written, the L~U

page level number and BTA written block number values applied to bus 14-420 are used to reset the block written bit of the block written into main memory.
As seen from Figure 6b, the sequence of operations 5 of blocks 614-2 through 614-12 are repeated for each written block detected by the BTA priority encoder circuit. That is, the same group of block written bits are accessed and examined for binary ONES until none are detected. Tbis same operation i9 performed on a 10 next group o~ block written bits until all of the 64 block written bits have been examined and reset. At this time, the siphon operation is complete and the sequence is resumed.
As indicated by block 605-16, the LRU page level 15 number value applied to bus 14-420 is used to write the VMMU new page frame number valu~ ~PAU) into the appropriate locations of PAR and PAC memories 14-412 and 14-408. Also, the ~ffective page number (EPN) address bits from AR register 14-402 are written into 20 the CAC memory location specified by the same LRU page level number value with the valid bit position of the loca~ion being set to a binary ONE. As block 605-20 indicates, signals representative of the private and modified bits from segment and page descriptors by VMMU
25 14-400 are written into the PTA memory location specified by the LRU page level number value. This completes the page ~iss sequence.
As seen from block 604-6, the cache address made up of the page level number from the LR~ circui~s 30 14-422 and offset from register 14-432 i8 loaded into the BT~ and PGR address registers. Again, the valid VB
bit is scheduled as described above. From block 604-8, 51~-02220 it is ~een that when the block valid bit of the requested block is not valid, the sequence of operations defined by blocks 606-2 through 606 8 are performed. This results in the requested block being 5 fetched from main memory. As indicated by block 606-2, the page level number value of the cache address applied to bus 14-420 by CAC memory 14-~06 is used to read the page fr~ne number value from PAR memory 14-412 into memory address register 14-4~2.
The page level number value concatenated with the block number ~BN) value obtained in block previously stored in off set register 14-432 in block 604-6 are used as a base address selected via position 0 of switch 14-440, to transfer the missing block from main 15 memory into cache memory 14-40. The double words transferred from main memory into FIFO memory 14-436 are written into PGR memory 14-410 at the locations deined by the page level number and BTA block number and word counter values applied via position 1 of switch 14-430. At the completion of the eight double word transfer, the valid bit position in the BTA memory 14-414 of the block defined by the C~C/LRU page level number is set to a binary ONE. This completes the block miss sequence.
Assuming the requested block was valid, it is seen from block 604-10 that the cache control circuits 14-404, upon detecting that the reques~ waa a write, causes the sequence of operations of blocks 609-2 through 609-10 to be per~ormed. This results in a 30 double word being written in~o PG~ memory 14-410 from the output bus of CPU 1~ 2. More speciically, the CAC/~RU page level number value and effective block ~ 510-02220 number value from AR register 14-4n2 applied via position 3 of switch 14-430 are used as a cache address to access the appropriate location in PGR memory 14-410. The double word is written into the location 5 under the control of cache control circuits 14-404.
The same CAC/LRU page level number value is used to address PTA memory 14-416 ~or testing the state of the page modiied bit. If the modi~ied bit i8 on (i.e., a binary ONE), the page private bit is also ]0 accessed from PTA memory 14-416 using the same CAC/LRU
page level number value. If the page private bit is on ~a binary ONE), the page level number value concatenated with the effective block number value of AR register 14-~02 applied via position 1 of switch 15 14-444 is used to addres~ BTA memory 14-414. Cache control circuits 14-404 cause the written bit of the specified block to be set to a binary ONE. At this time, the write sequence is complete. It is assumed that each write request from the CPU is initiated 20 separately. Therefore, the cache control circuits 14-404 will now wait for new cache operation requests as shown by block 602-8.
As seen from Figure 6b, the absence of the modified bit and the private bit having been set, cause 25 a set modified and global sequences to be performed.
The se~ modi~ied sequence of opertion~ of blocks 610-2 through 610-8 cause the VMMU 14-400 to perform a validity test on the page descriptor fetched from main memory and update and restore the descriptor to main 30 memory if valid. ~he global sequence of operations of blocks 612-2 and 612-4 causes nonprivate or shared data written into PGR memory 14-410 by CPU 14-2 ~o al~o be written into main memory.

As seen from block 612-2, the CAC page level number is used to obtain the page frame number ~ddress from PAR memory 14-412. This value is concatenated with the contents of offset register 14-432 applied via 5 position 0 of switch 14-440 to form the physical address which is loaded into MA~ register 1~-442.
Using the same page level number and offset register value applied via position 0 of switch 1~-430 as a cache address, the data contents of location written 10 into by CPU 14-2 are read out to FIFO memory 14-43~.
~rom there, the data i8 written into main memory at the location specified by the physical address stored in MAR register 14-442D
Figure 6c provides an example of how the cache 15 orsanization of the present invention also facilitates -- . the execution of certain operating system functions (system commands) requiring alterations in information pertaining to a given page~ For example, after a given period of time of inactivity, it becomes desirabl2 to-20 eliminate data pertaining to an old process. This can be done by a system command initiated by any central ~ubsystem which is broadcasted to all central subsystems of Figure 1 via ~he command bus portion of system bu 12~ This causes the sequence of operations 25 o;E blscks 616-2 through 616-8 ~o be performed~ The operation designate~ the clearing of a page frame number value specified by the system command which has been stored in snoop register 14-450. As shown, this value is applied by the snoop register 14-450 to PAC
30 memory 14-4080 I a hit is detected, PAC memory 14-408 generates a hit signal and applies the page level number to bus 14-420. The page level number value is ~ ~7 ~

used to invalidate the page information in the specified level in both CAC memory 14-406 and PAC
memory 14-408 by causing cache control circuits 14-404 to reset the associated valid bit positions to ZE~OS. .
5 Thus, through the use of page level number value, the specified operation can be performed expeditiously.

~l9~_gE_S~ Q

From a comparison of Figures 6a through 6c and Figures 7a through 7c, i~ can be seen that both the 10 data and instruction cache memories of 14-40 and 14 50 of Figures 2 and 3, respectively, operate in a similar fashionO ~his is illustrated through the use of similar reference numbers in Figures 6a through 6c and Figures 7a through 7c. The differences reside in that lS since cache memory 14-40 fetches inqtruction~, certain sequence~ of operations can be eliminated (i e., siphon and write sequences). Hence, the address s~quence of Figure 6b is simplified.
It will be noted that the presence of CAC memory 20 hit and block valid condition result in the loading of the CPU instruction (I) unit with the requested in~truction double word obtained from ICR memory 14-510. At that time, the instruction address register of~set block number and double word contents of IAR
25 register in use are incremented by one. This arrangement of instruction addre~s and page level number registers permits rapld transfer o~ instructions to CPU 14-2 by cache memory 14-50. That is, since it is moee likely that CPU 14-2 will continue to request 30 instruc~ions from the same block, repetition of the ~278~ 510-02220 loop shown provides fast access and transfer of instructions from ICR memory 14-510. The trans~er occurs until an overflow is detected at which time another page will be required.
As seen from the above, the same cache organization of the present invention can be used in the construction of both data and instruction cache memories. It provides immediate access to all o~ the related information pertaining to a page through the use o~ a common cache address. Whenever, it becomes desirable to perform other operations on a page (e~g.
security operations), additional memories can be added to the page level number bus to access the associated information.
Since input CAM memory performs virtual or - physical address comparison on only a single tag value, operational speed for page level number generation is increased. Moreover, in the case of data cache memory 14-40, while only 32 levels are shown, the number of 20 pages can be incréased substantially with little a~fect on operational speedO It will be understood by those s~illed in the art that the operations set forth in the flow diagrams of Figures 6a through 6c and Figure~ 7a through 7c are for the purpose of illustration. For 25 example~ it may be possible to combine certain opera~ions or perfonm them at different times to reduce steps and conserve cache control cycles.
Also, it will be appreciated by those skilled in the art that many other changes may be made to the 30 preferred embodiment of the present invention.
While in accordance with the provisions and statu~es there has been ill ustrated and described the best form o~ the inventionO certain changes may be made without departing f rom the spirit of the inven~ion as set f orth in the appended claims and that in some cases, certain features of the invention may be used to advantage without a corresp~nding use of other .
5 f eatur es .
What is claimed is:

Claims

1. A cache memory for use in a multiprocessing system in which a number of processing units connect in common to share a main memory, said main memory being divided into a number of segments in which each segment includes a plurality of pages, each containing a plurality of blocks, each of which has a plurality of words, said cache memory being coupled to one of said processing units for providing fast access information fetched from said main memory in response to requests for information received from said one processing unit, each request including an input address for identifying the information words to be accessed from said cache memory, said cache memory comprising:
a plurality of content addressable memories, each containing a plurality of locations for storing address information pertaining to each of a predetermined number of said plurality of pages, a first one of said content addressable memories being coupled to receive said input address from said one processing unit;
a plurality of directly addressable random access memories, each containing a plurality of locations for storing address, control and data information pertaining to each of said plurality of pages;
a common internal bus connecting each of content addressable and directly addressable memories in common; and, cache control means coupled to receive said requests from said one processing unit, said cache control means being operative in response to each request for information to apply a first portion of said input address corresponding to an effective address to said first one of said content addressable memories, said first content addressable memory being operative upon detecting a hit condition indicating that the page containing the requested information resides in cache memory to generate a page level number value on said bus identifying where information is stored in said content addressable and directly addressable memories pertinent to said page, said cache control means applying said page level number value together with other portions of said input address as a cache address to other ones of said memories as required for reading out the requested information words to said one processing unit.

2. The cache memory of claim 1 wherein said input address is a virtual address and said first content addressable memory locations contain segment and page virtual addresses identifying which ones of said main memory segment pages have been allocated storage locations in said cache memory and said cache memory further including virtual memory address translation means coupled to receive said input address from said one processing unit enabling the translation of said virtual address to a physical address to overlap the interrogation of said input content addressable memory for determining the presence of said hit condition and the generation of said page level number value for accessing the requested information words.

3. A cache memory for use with a processing unit which connects to a main memory, said main memory being divided into a number of pages, each containing a plurality of blocks, each of which has a plurality of words, said cache memory providing fast access information fetched from said main memory in response to requests for information received from said processing unit, each request including an input address for identifying the information words to be accessed from said cache memory, said cache memory comprising:
a plurality of content addressable memories, each containing a plurality of locations for storing a first type of information pertaining to each of a number of said plurality of pages, a first one of said content addressable memories being coupled to receive said input address from said processing unit;
a plurality of directly addressable random access memories, each containing a plurality of locations for storing other types of information pertaining to each of said plurality of pages;
a common internal bus connecting each of content addressable and directly addressable memories in common, and cache control means coupled to receive said requests from said processing unit, said cache control means being operative in response to each request for information to apply a first portion of said input address to said first one of said content addressable memories, said first content addressable memory being operative upon detecting a hit condition indicating that the page containing the requested information resides in cache memory to generate a page level number value on said bus identifying where said other types of information is stored in said content addressable and directly addressable memories associated with said page, said cache control means applying said page level number value together with other portions of said input address as a cache address to other ones of said memories for accessing the requested information words.

4. The cache memory of claim 3 wherein said input address is a virtual address and said first content addressable memory locations contain page virtual addresses identifying which ones of said main memory pages have been allocated storage locations in said cache memory and cache memory further including virtual memory address translation means coupled to receive said input address from said processing unit enabling the translation of said virtual address to a physical address to overlap the interrogation of said first content addressable memory for determining the presence of said hit condition and the generation of said page level number value for accessing the requested informaiton words.

5. The cache memory of claim 3 wherein the locations of a first one of said directly addressable random access memories store valid bit indications for said plurality of blocks for said number of pages, said cache control means in response to a signal from said first content addressable memory indicative of said hit condition to enable said first directly addressable random access memory to read out a valid bit indication specified by said page level number value and a block number portion of said other portions of said input address for determining whether or not a valid block containing the requested information words is stored in said cache memory.

6. The cache memory of claim 5 wherein a second one of said content addressable memories has locations for storing the physical addresses of said pages allocated storage locations in said cache memory and indications of the validity status of said physical addresses, said another one of said content addressable memories being coupled to said virtual memory translation means for receiving each new physical address, said second content addressable memory being operative upon detecting a comparison between said new physical address and any stored valid physical address to generate said page level any stored valid physical address to generate said page level number value on said bus for storing said new virtual address in one of said locations of said input content addressable memory specified by said page level number value thereby eliminating reloading the same page and preventing the mapping of two virtual addresses into the same physical address.

7. The cache memory of claim 6 wherein said cache memory further includes snoop register and decode means couples in common with said main memory to receive write requests including the physical addresses in main memory where information is to be written, said snoop register means being coupled to said second content addressable memory and operative in response to each received write request to condition said second content addressable memory to generate a page level number value upon detecting a comparison between the write request physical address and any stored physical address for maintaining consistency between the contents of said main memory and said cache memory.

8. The cache memory of claim 7 wherein said first directly addressable random access memory couples to said snoop register means to said second content addressable memory, said second content addressable memory being operative to generate a hit signal signaling said comparison for conditioning said first directly address random access memory to invalidate the valid bit indication of the block specified by said physical address from said snoop register means located at the level specified by said page level number applied to said bus.

9. The cache memory of claim 3 wherein said cache memory further includes replacement means for generating page level number values, said replacement means being coupled to said input content addressable memory and to said common internal bus, said replacement means being operative in response to a signal conditioned by said first content addressable memory indicating the absence of a hit condition to apply a page level number value to said bus for specifying where the information pertaining to the new page is to be written into different ones of said content addressable and directly addressable random access memories.

10. The cache memory of claim 9 wherein a second one of said directly addressable random access memories stores data words of at least one of a plurality of data blocks of each of said plurality of pages allocated storage locations and wherein one of a third one of said directly addressable random access memories further include storage locations containing written bit indications for designating any blocks of said each page which have been written into said third one of said directly addressable random access memories and said cache control means being operative in said absence of said hit condition to perform an operation on said page causing each previously written block designated by said written bit indications to be read out from said second directly addressable random access memory for transfer to said main memory enabling a new page to be allocated the same storage locations within said second memory