CA1290414C - Multilayer capacitor - Google Patents
Multilayer capacitorInfo
- Publication number
- CA1290414C CA1290414C CA000595452A CA595452A CA1290414C CA 1290414 C CA1290414 C CA 1290414C CA 000595452 A CA000595452 A CA 000595452A CA 595452 A CA595452 A CA 595452A CA 1290414 C CA1290414 C CA 1290414C
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- Prior art keywords
- capacitor
- tabs
- islands
- laminae
- metallurgy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
Disclosed is a multilayer capacitor consisting of a plurality of laminae with each of the laminae includ-ing a conductive plate portion and a non-conductive sheet portion. The conductive plate portion has at least one tab projecting to at least one edge of the conductive plate portion with the maximum number of tabs per conductive plate portion being limited to avoid excessive lateral congestion. The laminae are divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs. The laminae are interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other.
The capacitor finally includes islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs.
Disclosed is a multilayer capacitor consisting of a plurality of laminae with each of the laminae includ-ing a conductive plate portion and a non-conductive sheet portion. The conductive plate portion has at least one tab projecting to at least one edge of the conductive plate portion with the maximum number of tabs per conductive plate portion being limited to avoid excessive lateral congestion. The laminae are divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs. The laminae are interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other.
The capacitor finally includes islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs.
Description
04~.~
IMPROVED MULTILAYER CAP~CITOR
BACKG~OUND OF THE INVENTION
The present invention concerns multilayer ceramic capacitors having multiple capacitor plates which are terminated at a common face and more particularly, relates to impro~ements to multilayer capacitors resulting in greater flexibility in use and ease in manufacturing.
The continuing objective of data processing equipment designers is to produce equipment having increased operating speed, reduced physical size and lower manufacturing cost.
Advances in integrated circuit technology have gone a long way to satisfy this objective. One particu-lar area of concentration is the capacitor. In aneffort to get ever greater switching speed, circuit designers have gone to a decoupling capacitor which provides a low impedance path across the power supply to power the semiconductor chips without coupling noise into the signal wiring. The noise, if coupled, could cause errors in the computer functions. Such decou-pling capacitors are discrete, i.e. separate from the chips. However, to retain the advantages of integrated form, the circuit designers have sought dlscrete capacitors of small size, maximum capacitance, high speed (rapid responding), low inductance, low resis-tance and reasonable cost.
The capacitor frequently suggested for use today in this particular application is the multilayer ceramic capacitor. This capacitor consists of a series of parallel plates which are laminated together. Each of these plates consists of a sheet of ceramic dielectric material and a metallic plate. For ~2~4~L4 convenience, the dielectric material may be simply metallize~ to form each parallel plate. Each of the metallic plates has one or more laterally spaced tabs which may or may not terminate at a common side so as to form longitudinal rows o~ tabs. Each row of tabs is connected one to the other by a shorting bar or elec-trode. Final connection of the capacitor to the chips may be conveniently accomplished by surface mounting techniques or, more preferably, by ~lip-chip mounting the capacitor on a multilayer ceramic substrate with the use of solder balls as disclosed, for example, in sajorek et al U.S. Patent 4,349,862. Instead of solder Il balls, an array of solder bars may be used as disclosed ¦ in Chance et al U.S. Patent 4,430,690.
Other types of multilayer ceramic capacitors are disclosed, for example, in Swart et al. U.S. Patent 3,398,326 and Sakamoto U.S. Patent 4,590,537. In each of these references, the shorting bar or electrode connects all the tabs in each row.
A common characteristic of these multilayer capacitors is that each plate type is assi~ned to only one voltage and each row of tabs is also assigned to only one voltage. For example, in the IBM Technical Disclosure Bulletin, Vol. 26, No. 12, May 198~ (pp.
6595-6597~, it is desired to decouple among four different voltages. Each plate type is assigned to only one voltage and each row of ta~s is assigned to only one voltage. More importantly, it is nëcessary to have eleven laterally spaced tabs to accomplish this result.
*Registered Trade Mark ~.29~
IBM Technical ~i5closure Bulletin, Vol. 26, No. 9, February ~1984(p.4489) and IBM Technical Disclosure Bulletin, Vol 26, No. lOB, Mareh 1984 (p.5325) also illustrate the lateral congestion eneountered in these types of eapacitors. These last two references also illustrate that the tabs may emerge at two common sides of the capacitor, one side being for conneetion to the substrate with the other side being used for testing or other purposes.
Recognizing the problems inherent in properly aligning the tabs and shorting bars which are only a few thousandths of an inch in width, Locke U.S. Patent 4,419,714 proposed a new method of manufacturing the eapacitor to eorreet for misalignment of the tabs and shorting bars. This method essentially consists of putting in grooves in the face of the capacitor to thereby align the tabs or at least eliminate that portion of each tab which is out of alignment.
While the Locke referenee provides a way to lessen the problem of lateral congestion, it te~ehes nothing about eliminating the problem itself. And further, the teaching of Locke is that one plate type may only be assigned to one voltage and each row of tabs may only be assigned to one voltage.
It would be desirable to eliminate the problem of lateral eongestion so that solutions sueh as that proposed in the Locke reference do not need to eome into play.
~290~4 Accordingly, it is an object of the invention to have a capacitor which does not suffar from lateral congestion of the tabs.
It is another object of the invention to have a S capacitor which allows for a plurality of assigned voltages so that each row of tabs may be assigned to more than one voltage.
It is still another object of the invention to have a capacitor which is high in speed, reasonable in ~o cost and small in size.
It is yet another object of the invention to have a capacitor which is low in inductance, low in resis-tance and maximized for capacitance.
These and other objects of the invention will become more apparent after referring to the following description considered in conjunction wlth the accompa-nying drawings.
BRIEF SUMMARY OF THE INVENTION
The objects of the invention have been achieved by providing, according to one aspect of the invention, a muitilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate ~ortion and a non-conductive sheet portion;
said conductive plate portion having at least one tab projecting to at least one edge of the conduc-tive plate portion;
. ~ .
said laminae divided into different groups with .
~299~4 the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the loca-tion of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a ; lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs.
Accordin~ to a second aspect of the invention, there is provided a multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having a plurality of tabs projecting to at least one edge of the conductive plate portion; ' . . .
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said laminae divided into only two different groups ~ith the laminae from each group having the same number and location of tabs and with the laminae from different groups differlng by at least the location of the tabs;
the laminae interleaved so that:
; (a) a lamina from one group alternates with a lamina from a different ~roup, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae from rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands -overs a portion of each row of tabs.
According to another aspect of the invention, there is provided an electronic component arrangement comprising:
.
a ceramic substrate having pads for solder bonding to ~ an electronic component; and a multilayer capacitor comprising:
. ~ .. .
.. . .
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a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having at least one tab projecting to at least one edge of the conduc-tive plate portion;
; said laminae divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the loca-tion of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not.
in registry with each other; and islands of metallurgy joining 5elected groups of tabs in each row such that each of the islands covers a portion of each row of tabs; and additional metallurgy on each of the islands for terminating the capacitor to a substrate wherein ~290~
the additional metallurgy comprises a solder pad covering substantially each of the islands;
wherein the capacitor is joined to the subs-trate by contacting the pads of the substrate with the solder pad of the capacitor.
There is provided, according to a final aspect of the invention, an electronic component arrangement comprising:
a ceramic substrate having pads for solder bonding to an electronic component; and a multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a r.on-conductive sheet portion;
said conductive plate portion having a plurality of tabs projecting to at least one edge of the conductive plate portion;
said laminae divided into only two different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs;
the laminae interleaved so that:
~a) a lamina from one group alternates with a lamina from a different group, (b~ the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, ~c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs; and additional metallurgy on each of the islands for terminating the capacitor to a substrate wherein the additional metallurgy comprises a solder pad covering substantially each of the islands;
wherein the capacitor is joined to the substrate by contacting the pads of the substrate with the solder pad of the capacitor.
RIEF DESCRIPTION OF THE D~AWINGS
Figure l is ! a perspective view of a multilayer capacitor according to the invention with the end non-conductive sheet portion removed.
Figure lA is a modification of the multilayer capacitor shown in Figure l.
Figure 2 is an exploded perspective view of the multilayer capacitor of Figure l, with the top metal-lurgy removed.
Figure 3 is a side view of the multilayer capaci-tor of Figure l.
FI9-8~-005 9 Figure 4 is a side view of an alternative embodi-ment of a multilayer capacitor according to the inven-tion.
Figure 4A is a modification of the multilayer capacitor shown in Figure 4.
Figure 5 is an enlarged top view of the multilayer capacitor shown in Figure 1.
Figure 6 is a side view of another embodiment of a multilayer capacitor according to the invention.
Figure 7 is an enlarged perspective view of one corner of a multilayer capacitor according to the invention showing further details of the top metallur-gY- .
Figure 8 is a side view in partial cross section showing a multilayer capacitor according to the inven-tion jointed to a substrate.
DETAILED DESCRIPTION OF THE INVENTION
Referring now to the Figures in more detail and particularly referring to Figures 1 to 3 there is shown a multilayer capacitor, generally indicated by 10, according to the invention. The multilayer capacitor 10 comprises a plurality of laminae 12 wherein each of the laminae comprises a conductive plate portion 14 and a non-conductive sheet portion 16. At each end oE the multilayer capaci.tor 10 there is at least one non-conductive sheet portion 18 which does not contain a conductive plate portion. There may, of course, be more than one non-conductive sheet portion 18, if desired. The conductive plate portion 14 has at least one tab 20 projecting to at least one surface edge 32 of the conductive plate portion 14 and lamina 12. An important feature of the invention is that the maximum number of tabs 20 per conductive plate portion 14 is FIg-88-005 10 ~;~9Va~
limited so as to avoid excessive lateral conyestion.
The importance of this limitation will become more apparent hereafter.
The laminae 12 are divided into different groups with all the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of tabs. That is, specifically referring to Figure 2, there is one group of laminae represented by lamina 22 wherein the conductive plate portion 14, for example, has a tab 24 to the far right of the conductive plate portion 14 and another tab 26 laterally spaced there-from. There is a second group of laminae represented by lamina 28 which, for example, has a tab 30 all the way to the far left of the conductive plate portion 14 and another tab 31 spaced laterally therefrom. By comparing the laminae from the group represented by lamina 22 and the laminae from the group represented by lamina 28, it can be seen that the conductive plate portions on each of the non-conductive sheet portions for each of the groups are distinctly different. While only two different groups are illustrated in Figure 2, there may be three or more different groups as re-quired. The ultimate limit on the number of different groups of laminae is the requirement to avoid excessive lateral congestion of the various tabs.
For purposes of illustration, and not of limita-tion, all the conductive plate portions in Figure 2 have two tabs projecting therefrom. There may, in fact, be a number of tabs other than two. It should be understood -that al] that is required according to the invention is that there be at least one tab projecting from each of the conductive plate portions.
~9~4 The laminae 12 are interleaved so that a lamina from one group, such as that represented by lamina 22, alternates with a lamina from a different group, such as that represented by lamina 28. The conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina.
Thus, for example, conductive plate portion 29 of lamina 28 is in contact with non-conductive sheet portion 27 of lamina 22. The tabs 20 of each of the laminae 12 are at a common edge 32 of each lamina so that the tabs of the interleaved laminae form rows of tabs as is most apparent from Figure 1. Finally, the tabs 20 from adjacent laminae are not in registry with each other, as is most apparent from Figure 3.
The multilayer capacitor 10 further comprises islands of metallurgy 34 joining selective groups of tabs 20 in each row such that each of the islands 34 covers a portion of each row of tabs. It is preferred that the islands 34 cover only a portion of each and every row of tabs. This is most apparent in Figure 1.
Each of the islands 34 is spaced apart from any adja-cent island 34. There may be circumstances, however, where it would be desirable to have say one entire row of tabs connected together where the remaining tabs are connected by islands 34. It is thus within the scope of the invention for the islands 34 to cover only a portion of substantially all the rows of the tabs.
Figure lA is a modification of the multilayer capacitor of Figure 1. The principal difference between E'igures l and lA is that in Figure l, equal or near equal groups of tabs have been joined by the islands of metallurgy while in Figure lA, partial combination of the groups of tabs has occurred which ~:9~4~
limits flexibility bu-t allows contact with more plates.
The embodiment of Figure lA merely illustrates the versatility of the present invention in that the size of the islands can be varied (and hence the number of tabs connected) to suit the design of the system. The embodiment of Figure l, is preferred because of its lower inductance. The lower inductance arises because the vertical flow of current into and out of each island alternates direction between any adjacent island. Other variations in the arrangement of the islands can be imagined and these other arrangements are to be considered within the scope of the present invention.
It should be understood that the tabs shown in Figures l and lA, while representative of the inven-tion, are schematically illustrated. The actual number of tabs may thus differ from that shown in the Figures.
The importance of having the islands of metallurgy cannot be overemphasi~ed. In the past each row of tabs was only capable of being assigned to one voltage. Now each of the islands 34 along with its selected groups of tabs is now capable of being independently assigned to any particular or predetermined power level.
For example, as shown in Figure l, there are sixteer different islands 34. Since each conductive plate portion 14 has two tabs 20 for the purpose of providing redundancy for the multilayer capacitor l0, the capacitor l0 shown in Figure l may be assigned to eight different power levels. Thiq is easily accom-plished without the tabs being so close as to causelateral congestion. If redundancy were not required, then the capacitor l0 could be assigned to sixteen ~.29~
different power levels - all without causing excessive lateral congestion.
Similarly, in Figure lA, there are twelve differ-ent islands 34. If redundancy were required, the capacitor as shown in Figure lA would be assigned to six different power levels. If redundancy were not required, twelve different power levels could be assigned, also without causing excessive lateral congestion.
A distinct advantage of the present invention is that one capacitor fits all potential applications whereas prior art capacitors are specialized for only one particular application.
Another advantage of the present invention, which bears repeating, is the low inductance of the capaci-tors. For the capacitors of the present invention, inductance is usually less than lO0 picohenries.
It is preferred that there be at least two tabs per lamina to provide redundancy. The maximum number of tabs per lamina is limited only by design considera tions, manufacturing technology and capacitor size.
Suffice it to say here that for the purposes of the present invention, two tabs per lamina is the optimum number of tabs to have. For other applications, more than two tabs per lamina might be required. Such other applications and corresponding changes to the design of the capacitor are considered to be within the scope of the present invention.
It is of course possible that there may be a number of different groups of laminae as alluded to earlier. The various groups of lamina may differ by the lateral spacing of the tabs and/or by the number of tabs per lamina. For example, one group of laminae may ~L29~4~.4 have one tab while another group of laminae may have two tabs and yet another group may have three tabs and so on. Each of these groups may be interspersed so as to satisfy the desired redundancy and voltage require ments. It is most preferred however, that there be only two such groups oE laminae and that each of these groups have two tabs as shown in Figures 1 to 3.
; The multilayer capacitor lO further comprises additional metallurgy generally indicated by 36 on each of the islands 34 for terminating the capacitor 10 to a substrate (not shown). In one embodiment as shown in Figure 3, the additional metallurgy 36 comprises ball limiting metallurgy 38 and solder or solder balls 40.
Referring to Figure 7 there is shown an alterna-tive embodiment of the additional metallurgy 36. In this case the additional metallurgy comprises a solder pad 42 which substantially covers each of the islands 34. As shown in Figure 7 there is only one island 34 but, of course, it is to be unde~stood that there will be a plurality of such islands.
The metallurgy comprising each of the i,lands of metallurgy 34 may be made from any number of materials which are well known to those skilled in the art. A
particularly preferred composition is for there to be layers of chromium (700A), copper (4300A~ and then chromium (2000A) again. Alternatively, there could be a single layer of chromium (1500A). In the embodiment of Figure 7, it is preferred that the composition for the islands of metallurgy be layers of chromium (700A), copper (4300A) and gold (lOOOA). For the ball limiting metallurgy 38 it is preferred that it be comprised of layers of chromium (1600A), copper (4300A) and gold (lOOOA), respectively. If necessary, there may be 9~4~
co-deposited a chromium/copper layer between the chromium and copper layers in the island metallurgy and ball limiting metallurgy. This co-deposited layer aids in the adhesion of the chromium and copper layers.
Another embodiment of the invention is shown in Figure 4. Capacitor 110 is substantially similar to capacitor 10 shown in Figures 1 to 3 in that capacitor 110 comprises a plurality of laminae having a conduc-tive plate portion and a non-conductive sheet portion, tabs 20 and islands of metallurgy 34. However, capaci-tor 110 further comprises at least one tab 43 project-ing to an opposite edge 45 of each of the conductive plate portions 114. The capacitor 110 further compris-es- islands of metallurgy 46 which join selected groups of opposed tabs 43.
Figure 4A is a modification of capacitor 110 shown in Figure 4. Capacitor 120 of Figure 4A also further comprises at least one tab 43 projecting to an opposite edge 45 of each of the conductive plate portions 122.
Capacitor 120, h~wever, is configured such that each edge 32, 45 of the conductive plate portion 122 has at least one tab which represents a mirror image of the opposed edge 45, 32 of the conductive plate portion 122. That is, tabs 43 represent a mirror image of tabs 20. ~ith respect to the islands of metallurgy, the islands of metallurgy 34, 46 on opposed sides of the capacitor 110 join mirror-image selected groups of tabs.
The choice of whether to use the embodiment of Figure 4 or 4A is dictated primarily by manufacturing and assembly concerns. Each of the embodiments offers a particular type of symmetry which those skilled in the art may find useful.
, The capacitor llO, 120 may also comprise addition-al metallurgy on each of the islands 34, 46. For example, the capacitor llO, 120 may comprise an adcdi~
tional metallurgy 36 of ball limiting metallurgy and solder as was discussed previously with respect to Figures 1 to 3. In this case by having the additional metallurgy 36 on either side of the capacitor 110, 120 the capacitor may be joined to a substrate without regard to its orientation. That is, the top or bottom of the capacitor llO, 120 may be joined to a substrate.
Alternatively, as shown in Figures 4 and 4A, only one side of the capacitor llO, 120 has the additional metallurgy 36 for terminating the capacitor to a substrate while additional metallurgy 48 on the opposed side of the capacitor 110, 120 is simply a pad for the placement of a probe for in place testing of the capacitor. Thus, the capacitor 110, 120 may be in-stalled on a substrate using additional metallurgy 36 and, once in place, additional metallurgy 48 may be used for testing of the capacitor 110, 120.
Additional metallurgy may comprise layers of ~hromium (1600A), copper ~4300A) and gold (lOOOA). A
co-deposited layer of chromium/copper between the chromium and copper layers may also be used if desired.
Additional metallurgy 48 is preferred if testing of the capacitor 110, 120 is to take place. It is, however, within the scope of the invention for additional metallurgy 48 to be dispensed with and testing may then take place directly upon islands of metallurgy 46.
To obtain the advantages of the invention it is preferred that the thickness of the- non-conductive sheet portions 16 between adjacent conductive plate portions 14 is uniform or generally of the same 34~L~
thickness, e~cept that between each of the islands 34 the non-conductive sheet portion 50 should be of an in-creased thic~ness. This may be accomplished by placing addltional non-conductive sheets between groupings of laminae. The purpose for this limitation is so that adjacent islands are properly insulated from one another. This aspect of the invention is shown in Figure 5.-; Also shown in Figure 5 is another interesting aspect of the present invention, to wit, the staggering of the edges of the islands. Progressing across the surface of the capacitor, in a direction generally perpendicular to the rows of tabs, the islands of metallurgy end after contacting the last tab. Conse-quently, the islands of metallurgy in adjacent rows end at different points, leading to a staggered configura-tion. In so doing, the maximum number of tabs are con-tacted by the islands with also the maximum amount of separation between islands in each row.
Another embodiment of the capacitor is shown in Figure 6. In this embodiment of the capacitor 210, each of the conductive plate portions is divided into separate and distinct segments 52, 5~, such that there are a plurality of conductive plate segments for each non-conductive sheet portion 16. Where this occurs, the conductive plate portion is divided into two or more, equal or unequal, segments with each of the segments having at least one tab projecting from a common edge thereof, for example, edge 56. As shown in Figure 6, each of the conductive plate portions 52, 54 has two tabs on each conductive plate portion at edge 56. It is preferred that there be at least two tabs so as to provide the necessary or desired redundancy.
. .
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There may of course be circumstances where such redun-dancy is not required in which case only one tab per conductive plate portion would be required. Each of the conductive plate portions may further comprise tabs at an opposed edge 58 of the conductive plate portion as discussed previously and as illustrated in Figure 6.
The advantage of breaking up each conductive plate portion into two or more segments provides an addition-al flexibility in providing the necessary power levels while avoiding excessive lateral congestion of the tabs. In the embodiment shown in Figure 6, each of the conductive plate portions which is divided into seg-ments is alternated with a conductive plate portion which is not divided into segments. The arrangement shown in Figure 6 is only one of many possible arrange-mentsO Each of the succeeding conductive plate por-tions could also have been split. There may also be an arrangement where segmented and non-segmented conduc-tive plate portions are arranged in some predetermined order which has not been shown but is nevertheless contemplated within the scope of the invention. The ultimate arrangement of the laminae depends on the perceived need for simplicity of manufacture and the number of voltages one would like to couple.
Referring now to Figure 8 there is shown a further embodiment of the invention in which a multilayer capacitor lO is joined to a ceramic substrate 60 to form an electronic component arrangement. While the multilayer capacitor lO is the one shown in Figures l to 3, it should be understood that any of the other capacitors which have been previously discussed may be utilized in the embodiment of Figure 8. The ceramic substrate 60 has pads 62 on its surface for solder FI9-88-005 l9 ~29~4~ .
bonding to an elec-tronic component which, ~or purposes of illustration, is the multilayer capacitor lO. The multilayer capacitor as discussed previously has islands of metallurgy 3~ which join selective groups of tabs. The multilayer capacitor lO further comprises additional metallurgy 36 on each of the islands 34 for terminating the capacitor lO to the substrate 60. The additional metallurgy 36 in this embodiment, however, comprises a solder pad 42 which covers substantially each of the islands 34. As can be appreciated this additional metallurgy 36, i.e. so der pad 42, is identical to that which was discussed with reference to the embodiment of Figure 7. The capacitor is joined to the substrate 60 by contacting the pads 62 of the substrate 60 with solder pad 42 of the capacitor lO and then heating so as to melt solder pad 42.
The particular advantage of the embodiment shown in Figure 8 is that previously where each of the pads 62 on substrate 60 would be connected to a single via in the substrate now, due to the greater contact surface area between the capacitor lO and the substrate 60 through solder pad 42, each of the pads 62 may now be connected to at least two vias 6~ 2nd 66. In conformance with the advantages of the invention discussed previously, the fact that multiple vias may be connected to each pad 62 provides additional redun-dancy in the substrate wiring thereby enhancing the overall operation of the electronic package.
Such full island terminals are also advantageous as the capacitor tabs feed through, and not along, islands and directly into matching substrate islands, thereby greatly reducing resistance within the inter-connection complex. To a somewhat lesser extent, . .. ~ . , , . .: , . .
resistance is also reduced where the terminatioll is through the solder balls.
It should be apparent by now that the multilayer capacitor according to the invention may be joined to multilayer ceramic substrates. Joining to the sub-strate may be by full island terminals, as just dis-cussed, or solder balls. Additionally, the capacitors may be surface mounted with connections made to the substrate by wire bonding. Finally, the capacitors alternatively may be joined to polymeric or organic substrates such as printed circuit boards~
lt will be apparent to those skilled in the art having regard to this disclosure that other modifica-tions of this invention beyond those embodiments specifically described here may be made without depart-ing from the spiri~ of the invention. Accordingly, such modifications are considered within the scope of the invention as limited~lsolely by the appended claims.
IMPROVED MULTILAYER CAP~CITOR
BACKG~OUND OF THE INVENTION
The present invention concerns multilayer ceramic capacitors having multiple capacitor plates which are terminated at a common face and more particularly, relates to impro~ements to multilayer capacitors resulting in greater flexibility in use and ease in manufacturing.
The continuing objective of data processing equipment designers is to produce equipment having increased operating speed, reduced physical size and lower manufacturing cost.
Advances in integrated circuit technology have gone a long way to satisfy this objective. One particu-lar area of concentration is the capacitor. In aneffort to get ever greater switching speed, circuit designers have gone to a decoupling capacitor which provides a low impedance path across the power supply to power the semiconductor chips without coupling noise into the signal wiring. The noise, if coupled, could cause errors in the computer functions. Such decou-pling capacitors are discrete, i.e. separate from the chips. However, to retain the advantages of integrated form, the circuit designers have sought dlscrete capacitors of small size, maximum capacitance, high speed (rapid responding), low inductance, low resis-tance and reasonable cost.
The capacitor frequently suggested for use today in this particular application is the multilayer ceramic capacitor. This capacitor consists of a series of parallel plates which are laminated together. Each of these plates consists of a sheet of ceramic dielectric material and a metallic plate. For ~2~4~L4 convenience, the dielectric material may be simply metallize~ to form each parallel plate. Each of the metallic plates has one or more laterally spaced tabs which may or may not terminate at a common side so as to form longitudinal rows o~ tabs. Each row of tabs is connected one to the other by a shorting bar or elec-trode. Final connection of the capacitor to the chips may be conveniently accomplished by surface mounting techniques or, more preferably, by ~lip-chip mounting the capacitor on a multilayer ceramic substrate with the use of solder balls as disclosed, for example, in sajorek et al U.S. Patent 4,349,862. Instead of solder Il balls, an array of solder bars may be used as disclosed ¦ in Chance et al U.S. Patent 4,430,690.
Other types of multilayer ceramic capacitors are disclosed, for example, in Swart et al. U.S. Patent 3,398,326 and Sakamoto U.S. Patent 4,590,537. In each of these references, the shorting bar or electrode connects all the tabs in each row.
A common characteristic of these multilayer capacitors is that each plate type is assi~ned to only one voltage and each row of tabs is also assigned to only one voltage. For example, in the IBM Technical Disclosure Bulletin, Vol. 26, No. 12, May 198~ (pp.
6595-6597~, it is desired to decouple among four different voltages. Each plate type is assigned to only one voltage and each row of ta~s is assigned to only one voltage. More importantly, it is nëcessary to have eleven laterally spaced tabs to accomplish this result.
*Registered Trade Mark ~.29~
IBM Technical ~i5closure Bulletin, Vol. 26, No. 9, February ~1984(p.4489) and IBM Technical Disclosure Bulletin, Vol 26, No. lOB, Mareh 1984 (p.5325) also illustrate the lateral congestion eneountered in these types of eapacitors. These last two references also illustrate that the tabs may emerge at two common sides of the capacitor, one side being for conneetion to the substrate with the other side being used for testing or other purposes.
Recognizing the problems inherent in properly aligning the tabs and shorting bars which are only a few thousandths of an inch in width, Locke U.S. Patent 4,419,714 proposed a new method of manufacturing the eapacitor to eorreet for misalignment of the tabs and shorting bars. This method essentially consists of putting in grooves in the face of the capacitor to thereby align the tabs or at least eliminate that portion of each tab which is out of alignment.
While the Locke referenee provides a way to lessen the problem of lateral congestion, it te~ehes nothing about eliminating the problem itself. And further, the teaching of Locke is that one plate type may only be assigned to one voltage and each row of tabs may only be assigned to one voltage.
It would be desirable to eliminate the problem of lateral eongestion so that solutions sueh as that proposed in the Locke reference do not need to eome into play.
~290~4 Accordingly, it is an object of the invention to have a capacitor which does not suffar from lateral congestion of the tabs.
It is another object of the invention to have a S capacitor which allows for a plurality of assigned voltages so that each row of tabs may be assigned to more than one voltage.
It is still another object of the invention to have a capacitor which is high in speed, reasonable in ~o cost and small in size.
It is yet another object of the invention to have a capacitor which is low in inductance, low in resis-tance and maximized for capacitance.
These and other objects of the invention will become more apparent after referring to the following description considered in conjunction wlth the accompa-nying drawings.
BRIEF SUMMARY OF THE INVENTION
The objects of the invention have been achieved by providing, according to one aspect of the invention, a muitilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate ~ortion and a non-conductive sheet portion;
said conductive plate portion having at least one tab projecting to at least one edge of the conduc-tive plate portion;
. ~ .
said laminae divided into different groups with .
~299~4 the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the loca-tion of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a ; lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs.
Accordin~ to a second aspect of the invention, there is provided a multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having a plurality of tabs projecting to at least one edge of the conductive plate portion; ' . . .
~29~)4~
said laminae divided into only two different groups ~ith the laminae from each group having the same number and location of tabs and with the laminae from different groups differlng by at least the location of the tabs;
the laminae interleaved so that:
; (a) a lamina from one group alternates with a lamina from a different ~roup, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae from rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands -overs a portion of each row of tabs.
According to another aspect of the invention, there is provided an electronic component arrangement comprising:
.
a ceramic substrate having pads for solder bonding to ~ an electronic component; and a multilayer capacitor comprising:
. ~ .. .
.. . .
904~
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having at least one tab projecting to at least one edge of the conduc-tive plate portion;
; said laminae divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the loca-tion of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not.
in registry with each other; and islands of metallurgy joining 5elected groups of tabs in each row such that each of the islands covers a portion of each row of tabs; and additional metallurgy on each of the islands for terminating the capacitor to a substrate wherein ~290~
the additional metallurgy comprises a solder pad covering substantially each of the islands;
wherein the capacitor is joined to the subs-trate by contacting the pads of the substrate with the solder pad of the capacitor.
There is provided, according to a final aspect of the invention, an electronic component arrangement comprising:
a ceramic substrate having pads for solder bonding to an electronic component; and a multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a r.on-conductive sheet portion;
said conductive plate portion having a plurality of tabs projecting to at least one edge of the conductive plate portion;
said laminae divided into only two different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs;
the laminae interleaved so that:
~a) a lamina from one group alternates with a lamina from a different group, (b~ the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, ~c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs; and additional metallurgy on each of the islands for terminating the capacitor to a substrate wherein the additional metallurgy comprises a solder pad covering substantially each of the islands;
wherein the capacitor is joined to the substrate by contacting the pads of the substrate with the solder pad of the capacitor.
RIEF DESCRIPTION OF THE D~AWINGS
Figure l is ! a perspective view of a multilayer capacitor according to the invention with the end non-conductive sheet portion removed.
Figure lA is a modification of the multilayer capacitor shown in Figure l.
Figure 2 is an exploded perspective view of the multilayer capacitor of Figure l, with the top metal-lurgy removed.
Figure 3 is a side view of the multilayer capaci-tor of Figure l.
FI9-8~-005 9 Figure 4 is a side view of an alternative embodi-ment of a multilayer capacitor according to the inven-tion.
Figure 4A is a modification of the multilayer capacitor shown in Figure 4.
Figure 5 is an enlarged top view of the multilayer capacitor shown in Figure 1.
Figure 6 is a side view of another embodiment of a multilayer capacitor according to the invention.
Figure 7 is an enlarged perspective view of one corner of a multilayer capacitor according to the invention showing further details of the top metallur-gY- .
Figure 8 is a side view in partial cross section showing a multilayer capacitor according to the inven-tion jointed to a substrate.
DETAILED DESCRIPTION OF THE INVENTION
Referring now to the Figures in more detail and particularly referring to Figures 1 to 3 there is shown a multilayer capacitor, generally indicated by 10, according to the invention. The multilayer capacitor 10 comprises a plurality of laminae 12 wherein each of the laminae comprises a conductive plate portion 14 and a non-conductive sheet portion 16. At each end oE the multilayer capaci.tor 10 there is at least one non-conductive sheet portion 18 which does not contain a conductive plate portion. There may, of course, be more than one non-conductive sheet portion 18, if desired. The conductive plate portion 14 has at least one tab 20 projecting to at least one surface edge 32 of the conductive plate portion 14 and lamina 12. An important feature of the invention is that the maximum number of tabs 20 per conductive plate portion 14 is FIg-88-005 10 ~;~9Va~
limited so as to avoid excessive lateral conyestion.
The importance of this limitation will become more apparent hereafter.
The laminae 12 are divided into different groups with all the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of tabs. That is, specifically referring to Figure 2, there is one group of laminae represented by lamina 22 wherein the conductive plate portion 14, for example, has a tab 24 to the far right of the conductive plate portion 14 and another tab 26 laterally spaced there-from. There is a second group of laminae represented by lamina 28 which, for example, has a tab 30 all the way to the far left of the conductive plate portion 14 and another tab 31 spaced laterally therefrom. By comparing the laminae from the group represented by lamina 22 and the laminae from the group represented by lamina 28, it can be seen that the conductive plate portions on each of the non-conductive sheet portions for each of the groups are distinctly different. While only two different groups are illustrated in Figure 2, there may be three or more different groups as re-quired. The ultimate limit on the number of different groups of laminae is the requirement to avoid excessive lateral congestion of the various tabs.
For purposes of illustration, and not of limita-tion, all the conductive plate portions in Figure 2 have two tabs projecting therefrom. There may, in fact, be a number of tabs other than two. It should be understood -that al] that is required according to the invention is that there be at least one tab projecting from each of the conductive plate portions.
~9~4 The laminae 12 are interleaved so that a lamina from one group, such as that represented by lamina 22, alternates with a lamina from a different group, such as that represented by lamina 28. The conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina.
Thus, for example, conductive plate portion 29 of lamina 28 is in contact with non-conductive sheet portion 27 of lamina 22. The tabs 20 of each of the laminae 12 are at a common edge 32 of each lamina so that the tabs of the interleaved laminae form rows of tabs as is most apparent from Figure 1. Finally, the tabs 20 from adjacent laminae are not in registry with each other, as is most apparent from Figure 3.
The multilayer capacitor 10 further comprises islands of metallurgy 34 joining selective groups of tabs 20 in each row such that each of the islands 34 covers a portion of each row of tabs. It is preferred that the islands 34 cover only a portion of each and every row of tabs. This is most apparent in Figure 1.
Each of the islands 34 is spaced apart from any adja-cent island 34. There may be circumstances, however, where it would be desirable to have say one entire row of tabs connected together where the remaining tabs are connected by islands 34. It is thus within the scope of the invention for the islands 34 to cover only a portion of substantially all the rows of the tabs.
Figure lA is a modification of the multilayer capacitor of Figure 1. The principal difference between E'igures l and lA is that in Figure l, equal or near equal groups of tabs have been joined by the islands of metallurgy while in Figure lA, partial combination of the groups of tabs has occurred which ~:9~4~
limits flexibility bu-t allows contact with more plates.
The embodiment of Figure lA merely illustrates the versatility of the present invention in that the size of the islands can be varied (and hence the number of tabs connected) to suit the design of the system. The embodiment of Figure l, is preferred because of its lower inductance. The lower inductance arises because the vertical flow of current into and out of each island alternates direction between any adjacent island. Other variations in the arrangement of the islands can be imagined and these other arrangements are to be considered within the scope of the present invention.
It should be understood that the tabs shown in Figures l and lA, while representative of the inven-tion, are schematically illustrated. The actual number of tabs may thus differ from that shown in the Figures.
The importance of having the islands of metallurgy cannot be overemphasi~ed. In the past each row of tabs was only capable of being assigned to one voltage. Now each of the islands 34 along with its selected groups of tabs is now capable of being independently assigned to any particular or predetermined power level.
For example, as shown in Figure l, there are sixteer different islands 34. Since each conductive plate portion 14 has two tabs 20 for the purpose of providing redundancy for the multilayer capacitor l0, the capacitor l0 shown in Figure l may be assigned to eight different power levels. Thiq is easily accom-plished without the tabs being so close as to causelateral congestion. If redundancy were not required, then the capacitor l0 could be assigned to sixteen ~.29~
different power levels - all without causing excessive lateral congestion.
Similarly, in Figure lA, there are twelve differ-ent islands 34. If redundancy were required, the capacitor as shown in Figure lA would be assigned to six different power levels. If redundancy were not required, twelve different power levels could be assigned, also without causing excessive lateral congestion.
A distinct advantage of the present invention is that one capacitor fits all potential applications whereas prior art capacitors are specialized for only one particular application.
Another advantage of the present invention, which bears repeating, is the low inductance of the capaci-tors. For the capacitors of the present invention, inductance is usually less than lO0 picohenries.
It is preferred that there be at least two tabs per lamina to provide redundancy. The maximum number of tabs per lamina is limited only by design considera tions, manufacturing technology and capacitor size.
Suffice it to say here that for the purposes of the present invention, two tabs per lamina is the optimum number of tabs to have. For other applications, more than two tabs per lamina might be required. Such other applications and corresponding changes to the design of the capacitor are considered to be within the scope of the present invention.
It is of course possible that there may be a number of different groups of laminae as alluded to earlier. The various groups of lamina may differ by the lateral spacing of the tabs and/or by the number of tabs per lamina. For example, one group of laminae may ~L29~4~.4 have one tab while another group of laminae may have two tabs and yet another group may have three tabs and so on. Each of these groups may be interspersed so as to satisfy the desired redundancy and voltage require ments. It is most preferred however, that there be only two such groups oE laminae and that each of these groups have two tabs as shown in Figures 1 to 3.
; The multilayer capacitor lO further comprises additional metallurgy generally indicated by 36 on each of the islands 34 for terminating the capacitor 10 to a substrate (not shown). In one embodiment as shown in Figure 3, the additional metallurgy 36 comprises ball limiting metallurgy 38 and solder or solder balls 40.
Referring to Figure 7 there is shown an alterna-tive embodiment of the additional metallurgy 36. In this case the additional metallurgy comprises a solder pad 42 which substantially covers each of the islands 34. As shown in Figure 7 there is only one island 34 but, of course, it is to be unde~stood that there will be a plurality of such islands.
The metallurgy comprising each of the i,lands of metallurgy 34 may be made from any number of materials which are well known to those skilled in the art. A
particularly preferred composition is for there to be layers of chromium (700A), copper (4300A~ and then chromium (2000A) again. Alternatively, there could be a single layer of chromium (1500A). In the embodiment of Figure 7, it is preferred that the composition for the islands of metallurgy be layers of chromium (700A), copper (4300A) and gold (lOOOA). For the ball limiting metallurgy 38 it is preferred that it be comprised of layers of chromium (1600A), copper (4300A) and gold (lOOOA), respectively. If necessary, there may be 9~4~
co-deposited a chromium/copper layer between the chromium and copper layers in the island metallurgy and ball limiting metallurgy. This co-deposited layer aids in the adhesion of the chromium and copper layers.
Another embodiment of the invention is shown in Figure 4. Capacitor 110 is substantially similar to capacitor 10 shown in Figures 1 to 3 in that capacitor 110 comprises a plurality of laminae having a conduc-tive plate portion and a non-conductive sheet portion, tabs 20 and islands of metallurgy 34. However, capaci-tor 110 further comprises at least one tab 43 project-ing to an opposite edge 45 of each of the conductive plate portions 114. The capacitor 110 further compris-es- islands of metallurgy 46 which join selected groups of opposed tabs 43.
Figure 4A is a modification of capacitor 110 shown in Figure 4. Capacitor 120 of Figure 4A also further comprises at least one tab 43 projecting to an opposite edge 45 of each of the conductive plate portions 122.
Capacitor 120, h~wever, is configured such that each edge 32, 45 of the conductive plate portion 122 has at least one tab which represents a mirror image of the opposed edge 45, 32 of the conductive plate portion 122. That is, tabs 43 represent a mirror image of tabs 20. ~ith respect to the islands of metallurgy, the islands of metallurgy 34, 46 on opposed sides of the capacitor 110 join mirror-image selected groups of tabs.
The choice of whether to use the embodiment of Figure 4 or 4A is dictated primarily by manufacturing and assembly concerns. Each of the embodiments offers a particular type of symmetry which those skilled in the art may find useful.
, The capacitor llO, 120 may also comprise addition-al metallurgy on each of the islands 34, 46. For example, the capacitor llO, 120 may comprise an adcdi~
tional metallurgy 36 of ball limiting metallurgy and solder as was discussed previously with respect to Figures 1 to 3. In this case by having the additional metallurgy 36 on either side of the capacitor 110, 120 the capacitor may be joined to a substrate without regard to its orientation. That is, the top or bottom of the capacitor llO, 120 may be joined to a substrate.
Alternatively, as shown in Figures 4 and 4A, only one side of the capacitor llO, 120 has the additional metallurgy 36 for terminating the capacitor to a substrate while additional metallurgy 48 on the opposed side of the capacitor 110, 120 is simply a pad for the placement of a probe for in place testing of the capacitor. Thus, the capacitor 110, 120 may be in-stalled on a substrate using additional metallurgy 36 and, once in place, additional metallurgy 48 may be used for testing of the capacitor 110, 120.
Additional metallurgy may comprise layers of ~hromium (1600A), copper ~4300A) and gold (lOOOA). A
co-deposited layer of chromium/copper between the chromium and copper layers may also be used if desired.
Additional metallurgy 48 is preferred if testing of the capacitor 110, 120 is to take place. It is, however, within the scope of the invention for additional metallurgy 48 to be dispensed with and testing may then take place directly upon islands of metallurgy 46.
To obtain the advantages of the invention it is preferred that the thickness of the- non-conductive sheet portions 16 between adjacent conductive plate portions 14 is uniform or generally of the same 34~L~
thickness, e~cept that between each of the islands 34 the non-conductive sheet portion 50 should be of an in-creased thic~ness. This may be accomplished by placing addltional non-conductive sheets between groupings of laminae. The purpose for this limitation is so that adjacent islands are properly insulated from one another. This aspect of the invention is shown in Figure 5.-; Also shown in Figure 5 is another interesting aspect of the present invention, to wit, the staggering of the edges of the islands. Progressing across the surface of the capacitor, in a direction generally perpendicular to the rows of tabs, the islands of metallurgy end after contacting the last tab. Conse-quently, the islands of metallurgy in adjacent rows end at different points, leading to a staggered configura-tion. In so doing, the maximum number of tabs are con-tacted by the islands with also the maximum amount of separation between islands in each row.
Another embodiment of the capacitor is shown in Figure 6. In this embodiment of the capacitor 210, each of the conductive plate portions is divided into separate and distinct segments 52, 5~, such that there are a plurality of conductive plate segments for each non-conductive sheet portion 16. Where this occurs, the conductive plate portion is divided into two or more, equal or unequal, segments with each of the segments having at least one tab projecting from a common edge thereof, for example, edge 56. As shown in Figure 6, each of the conductive plate portions 52, 54 has two tabs on each conductive plate portion at edge 56. It is preferred that there be at least two tabs so as to provide the necessary or desired redundancy.
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There may of course be circumstances where such redun-dancy is not required in which case only one tab per conductive plate portion would be required. Each of the conductive plate portions may further comprise tabs at an opposed edge 58 of the conductive plate portion as discussed previously and as illustrated in Figure 6.
The advantage of breaking up each conductive plate portion into two or more segments provides an addition-al flexibility in providing the necessary power levels while avoiding excessive lateral congestion of the tabs. In the embodiment shown in Figure 6, each of the conductive plate portions which is divided into seg-ments is alternated with a conductive plate portion which is not divided into segments. The arrangement shown in Figure 6 is only one of many possible arrange-mentsO Each of the succeeding conductive plate por-tions could also have been split. There may also be an arrangement where segmented and non-segmented conduc-tive plate portions are arranged in some predetermined order which has not been shown but is nevertheless contemplated within the scope of the invention. The ultimate arrangement of the laminae depends on the perceived need for simplicity of manufacture and the number of voltages one would like to couple.
Referring now to Figure 8 there is shown a further embodiment of the invention in which a multilayer capacitor lO is joined to a ceramic substrate 60 to form an electronic component arrangement. While the multilayer capacitor lO is the one shown in Figures l to 3, it should be understood that any of the other capacitors which have been previously discussed may be utilized in the embodiment of Figure 8. The ceramic substrate 60 has pads 62 on its surface for solder FI9-88-005 l9 ~29~4~ .
bonding to an elec-tronic component which, ~or purposes of illustration, is the multilayer capacitor lO. The multilayer capacitor as discussed previously has islands of metallurgy 3~ which join selective groups of tabs. The multilayer capacitor lO further comprises additional metallurgy 36 on each of the islands 34 for terminating the capacitor lO to the substrate 60. The additional metallurgy 36 in this embodiment, however, comprises a solder pad 42 which covers substantially each of the islands 34. As can be appreciated this additional metallurgy 36, i.e. so der pad 42, is identical to that which was discussed with reference to the embodiment of Figure 7. The capacitor is joined to the substrate 60 by contacting the pads 62 of the substrate 60 with solder pad 42 of the capacitor lO and then heating so as to melt solder pad 42.
The particular advantage of the embodiment shown in Figure 8 is that previously where each of the pads 62 on substrate 60 would be connected to a single via in the substrate now, due to the greater contact surface area between the capacitor lO and the substrate 60 through solder pad 42, each of the pads 62 may now be connected to at least two vias 6~ 2nd 66. In conformance with the advantages of the invention discussed previously, the fact that multiple vias may be connected to each pad 62 provides additional redun-dancy in the substrate wiring thereby enhancing the overall operation of the electronic package.
Such full island terminals are also advantageous as the capacitor tabs feed through, and not along, islands and directly into matching substrate islands, thereby greatly reducing resistance within the inter-connection complex. To a somewhat lesser extent, . .. ~ . , , . .: , . .
resistance is also reduced where the terminatioll is through the solder balls.
It should be apparent by now that the multilayer capacitor according to the invention may be joined to multilayer ceramic substrates. Joining to the sub-strate may be by full island terminals, as just dis-cussed, or solder balls. Additionally, the capacitors may be surface mounted with connections made to the substrate by wire bonding. Finally, the capacitors alternatively may be joined to polymeric or organic substrates such as printed circuit boards~
lt will be apparent to those skilled in the art having regard to this disclosure that other modifica-tions of this invention beyond those embodiments specifically described here may be made without depart-ing from the spiri~ of the invention. Accordingly, such modifications are considered within the scope of the invention as limited~lsolely by the appended claims.
Claims (50)
1. A multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having at least one tab projecting to at least one edge of the conductive plate portion;
said laminae divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs.
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having at least one tab projecting to at least one edge of the conductive plate portion;
said laminae divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs.
2. The capacitor of claim 1 wherein the maximum number of tabs per conductive plate portion is limited to avoid excessive lateral congestion.
3. The capacitor of claim 1 wherein each of the islands of metallurgy covers only a portion of each and every row of tabs.
4. The capacitor of claim 1 wherein the total number of tabs for each lamina shall be two and the total number of tabs for any two adjacent laminae shall be four.
5. The capacitor of claim 1 wherein each of the islands and selected groups of tabs is capable of being independently assigned to a predetermined power level.
6. The capacitor of claim 1 wherein the thickness of the non-conductive sheet portions between adjacent conductive plate portions is uniform except that between each of the islands, the non-conductive sheet portion is of increased thickness.
7. The capacitor of claim 1 wherein each of the conductive plate portions is divided into separate and distinct segments such that there are a plurality of conductive plate portion segments for each non-conductive sheet portion.
8. The capacitor of claim 7 wherein the conductive plate portion is divided into two equal segments with each of the segments having at least one tab projecting from a common edge thereof.
9. The capacitor of claim 1 further comprising addi-tional metallurgy on each of the islands for terminat-ing the capacitor to a substrate.
10. The capacitor of claim 9 wherein the additional metallurgy comprises ball limiting metallurgy and solder balls.
11. The capacitor of claim 9 wherein the additional metallurgy comprises a solder pad covering substantial-ly each of the islands.
12. The capacitor of claim 11 wherein the islands of metallurgy comprise layers of chromium/copper/gold, respectively.
13. The capacitor of claim 1 wherein the islands of metallurgy comprise layers of chromium/copper/chromium, respectively.
14. The capacitor of claim 1 wherein the islands of metallurgy comprise a layer of chromium.
15. The capacitor of claim 10 wherein the ball limiting metallurgy comprises layers of chromium/copper/gold, respectively.
16. The capacitor of claim 1 further comprising at least one tab projecting to an opposite edge of each of the conductive plate portions.
17. The capacitor of claim 16 further comprising islands of metallurgy joining selected groups of opposed tabs.
18. The capacitor of claim 1 further comprising at least one tab projecting to an opposite edge of each of the conductive plate portions such that each edge of the conductive plate portions having at least one tab represents a mirror image of the opposed edge of the conductive plate portions.
19. The capacitor of claim 18 further comprising islands of metallurgy joining selected groups of opposed tabs such that the islands of metallurgy on opposed sides of the capacitor join mirror-image selected groups of tabs.
20. The capacitor of claim 17 further comprising additional metallurgy on each of the islands wherein the additional metallurgy on one side of the capacitor is for terminating the capacitor to a substrate and the additional metallurgy on the opposed side of the capacitor is for in-place testing of the capacitor.
21. The capacitor of claim 1 wherein the islands of metallurgy in adjacent rows are staggered.
22. The capacitor of claim 1 wherein the capacitor is a decoupling capacitor.
23. A multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having a plurality of tabs projecting to at least one edge of the conductive plate portion;
said laminae divided into only two different groups with the laminae from each group having the same number and location of tabs and with the laminae from differ-ent groups differing by at least the location of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs.
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having a plurality of tabs projecting to at least one edge of the conductive plate portion;
said laminae divided into only two different groups with the laminae from each group having the same number and location of tabs and with the laminae from differ-ent groups differing by at least the location of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs.
24. The capacitor of claim 23 wherein the maximum number of tabs per conductive plate portion is limited to avoid excessive lateral congestion.
25. The capacitor of claim 23 wherein each of the islands of metallurgy covers only a portion of each and every row of tabs.
26. The capacitor of claim 23 wherein the total number of tabs for each lamina shall be two and the total number of tabs for any two adjacent laminae shall be four.
27. The capacitor of claim 23 wherein each of the islands and selected groups of tabs is capable of being independently assigned to a predetermined power level.
28. The capacitor of claim 23 wherein the thickness of the non-conductive sheet portions between adjacent conductive plate portions is uniform except that between each of the islands, the non-conductive sheet portion is of increased thickness.
29. The capacitor of claim 23 wherein each of the conductive plate portions is divided into separate and distinct segments such that there are a plurality of conductive plate portion segments for each non-conductive sheet portion.
30. The capacitor of claim 29 wherein the conductive plate portion is divided into two equal segments with each of the segments having at least one tab projecting from a common edge thereof.
31. The capacitor of claim 23 further comprising additional metallurgy on each of the islands for terminating the capacitor to a substrate.
32. The capacitor of claim 31 wherein the additional metallurgy comprises ball limiting metallurgy and solder balls.
33. The capacitor of claim 31 wherein the additional metallurgy comprises a solder pad covering substantial-ly each of the islands.
34. The capacitor of claim 33 wherein the islands of metallurgy comprise layers of chromium/copper/gold, respectively.
35. The capacitor of claim 23 wherein the islands of metallurgy comprise layers of chromium/copper/chromium, respectively.
36. The capacitor of claim 23 wherein the islands of metallurgy comprise a layer of chromium.
37. The capacitor of claim 32 wherein the ball limit-ing metallurgy comprises layers of chromi-um/copper/gold, respectively.
38. The capacitor of claim 23 further comprising at least one tab projecting to an opposite edge of each of the conductive plate portions.
39. The capacitor of claim 38 further comprising islands of metallurgy joining selected groups of opposed tabs.
40. The capacitor of claim 23 further comprising at least one tab projecting to an opposite edge of each of the conductive plate portions such that each edge of the conductive plate portions having at least one tab represents a mirror image of the opposed edge of the conductive plate portions.
41. The capacitor of claim 40 further comprising islands of metallurgy joining selected groups of opposed tabs such that the islands of metallurgy on opposed sides of the capacitor join mirror-image selected groups of tabs.
42. The capacitor of claim 39 further comprising additional metallurgy on each of the islands wherein the additional metallurgy on one side of the capacitor is for terminating the capacitor to a substrate and the additional metallurgy on the opposed side of the capacitor is for in-place testing of the capacitor.
43. The capacitor of claim 23 wherein the islands of metallurgy in adjacent rows are staggered.
44. The capacitor of claim 23 wherein the capacitor is a decoupling capacitor.
45. An electronic component arrangement comprising:
a ceramic substrate having pads for solder bonding to an electronic component; and a multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having at least one tab projecting to at least one edge of the conduc-tive plate portion;
said laminae divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the loca-tion of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs; and additional metallurgy on each of the islands for terminating the capacitor to a substrate wherein the additional metallurgy comprises a solder pad covering substantially each of the islands;
wherein the capacitor is joined to the substrate by contacting the pads of the substrate with the solder pad of the capacitor.
a ceramic substrate having pads for solder bonding to an electronic component; and a multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having at least one tab projecting to at least one edge of the conduc-tive plate portion;
said laminae divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the loca-tion of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs; and additional metallurgy on each of the islands for terminating the capacitor to a substrate wherein the additional metallurgy comprises a solder pad covering substantially each of the islands;
wherein the capacitor is joined to the substrate by contacting the pads of the substrate with the solder pad of the capacitor.
46. The electronic component arrangement of claim 45 wherein the maximum number of tabs per conductive plate portion is limited to avoid excessive lateral conges-tion.
47. The electronic component arrangement of claim 45 wherein each of the islands of metallurgy covers only a portion of each and every row of tabs.
48. An electronic component arrangement comprising:
a ceramic substrate having pads for solder bonding to an electronic component; and a multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having a plurality of tabs projecting to at least one edge of the conductive plate portion;
said laminae divided into only two different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs; and additional metallurgy on each of the islands for terminating the capacitor to a substrate wherein the additional metallurgy comprises a solder pad covering substantially each of the islands;
wherein the capacitor is joined to the substrate by contacting the pads of the substrate with the solder pad of the capacitor.
a ceramic substrate having pads for solder bonding to an electronic component; and a multilayer capacitor comprising:
a plurality of laminae, each of said laminae comprising a conductive plate portion and a non-conductive sheet portion;
said conductive plate portion having a plurality of tabs projecting to at least one edge of the conductive plate portion;
said laminae divided into only two different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs;
the laminae interleaved so that:
(a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other; and islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs; and additional metallurgy on each of the islands for terminating the capacitor to a substrate wherein the additional metallurgy comprises a solder pad covering substantially each of the islands;
wherein the capacitor is joined to the substrate by contacting the pads of the substrate with the solder pad of the capacitor.
49. The electronic component arrangement of claim 48 wherein the maximum number of tabs per conductive plate portion is limited to avoid excessive lateral conges-tion.
50. The electronic component arrangement of claim 48 wherein each of the islands of metallurgy covers only a portion of each and every row of tabs.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US212,361 | 1988-06-27 | ||
| US07/212,361 US4831494A (en) | 1988-06-27 | 1988-06-27 | Multilayer capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1290414C true CA1290414C (en) | 1991-10-08 |
Family
ID=22790683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000595452A Expired - Fee Related CA1290414C (en) | 1988-06-27 | 1989-03-31 | Multilayer capacitor |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4831494A (en) |
| EP (1) | EP0351343B1 (en) |
| JP (1) | JP2657953B2 (en) |
| BR (1) | BR8903107A (en) |
| CA (1) | CA1290414C (en) |
| DE (1) | DE68907658T2 (en) |
| ES (1) | ES2044199T3 (en) |
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- 1989-04-25 ES ES89480066T patent/ES2044199T3/en not_active Expired - Lifetime
- 1989-06-19 JP JP1154815A patent/JP2657953B2/en not_active Expired - Fee Related
- 1989-06-26 BR BR898903107A patent/BR8903107A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| DE68907658T2 (en) | 1994-02-17 |
| EP0351343A1 (en) | 1990-01-17 |
| DE68907658D1 (en) | 1993-08-26 |
| EP0351343B1 (en) | 1993-07-21 |
| US4831494A (en) | 1989-05-16 |
| JPH02256216A (en) | 1990-10-17 |
| BR8903107A (en) | 1990-02-06 |
| JP2657953B2 (en) | 1997-09-30 |
| ES2044199T3 (en) | 1994-01-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |