CA1301942C - Memory cartridge - Google Patents
Memory cartridgeInfo
- Publication number
- CA1301942C CA1301942C CA000536489A CA536489A CA1301942C CA 1301942 C CA1301942 C CA 1301942C CA 000536489 A CA000536489 A CA 000536489A CA 536489 A CA536489 A CA 536489A CA 1301942 C CA1301942 C CA 1301942C
- Authority
- CA
- Canada
- Prior art keywords
- data
- memory
- address
- bank
- holding means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Controls And Circuits For Display Device (AREA)
- Memory System (AREA)
- Pinball Game Machines (AREA)
- Storage Device Security (AREA)
- Processing Or Creating Images (AREA)
- Multi Processors (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Automatic Disk Changers (AREA)
- Microcomputers (AREA)
- Read Only Memory (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A memory cartridge is loaded in a main unit of a computer when used. The memory cartridge comprises a case, and a printed circuit board which is installed therein and on which a large-capacity, one-chip ROM is mounted. Storage area of the one-chip ROM is divided into a plurality of banks respectively having memory addresses of a number accessible by a central processing unit of the main unit, and one specific bank among them is allocated to an address space accessible all the time by the central processing unit. Bank selecting data for selecting other banks is stored in that specific bank. The bank selecting data is read out with progress of a program stored in the specific bank, being loaded in a counter. The content of the counter is inputted to the most significant three bits of address of the one-chip ROM. The most significant three bits of the address function as bank designating bits. An arbitrary bank of the one-chip ROM is changed over at an arbitrary timing by the bank selecting data outputted from the other hanks of the one-chin ROM.
A memory cartridge is loaded in a main unit of a computer when used. The memory cartridge comprises a case, and a printed circuit board which is installed therein and on which a large-capacity, one-chip ROM is mounted. Storage area of the one-chip ROM is divided into a plurality of banks respectively having memory addresses of a number accessible by a central processing unit of the main unit, and one specific bank among them is allocated to an address space accessible all the time by the central processing unit. Bank selecting data for selecting other banks is stored in that specific bank. The bank selecting data is read out with progress of a program stored in the specific bank, being loaded in a counter. The content of the counter is inputted to the most significant three bits of address of the one-chip ROM. The most significant three bits of the address function as bank designating bits. An arbitrary bank of the one-chip ROM is changed over at an arbitrary timing by the bank selecting data outputted from the other hanks of the one-chin ROM.
Description
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The present invention relates to a memory cartridge. More specifically, the present invention relates to a memory cartridge which is attachable to and detachable from a main unit of a personal computer or a home video gaming machine which includes a computer and a is loaded in the main unit when used.
Home personal computers or the gaming machine which includes a computer called the "Nintendo Entertainment System" (trade mark) manufactured and sold by the assignee of the present invention and the one called the "MSX" (commodity name) use an external memory cartridge in which a game or educational program or the like is written in advance is used, and the computer is enabled by loading such external memory cartridge in the main unit.
The memory cartridge includes a non-volatile memory (for example, ROM) for storing program data and/or character data for display.
When a central processing unit (CPU) located in the main unit of the computer accesses the ROM of the memory cartridye, the maximum number of accessible B
" 3~3~3~2 addresses, that i5, address space is limited by the performance (number of bits) of the central processing unit, and therefore the usable memory capacity of the ROM
comprised in the memory cartridge is also limited naturally. For example, in the above-described "Nintendo Entertainment System", only a 256K-bit ROM can be used for program and a 64K-bit ROM for characters at a maximum.
Thus, the maximum number of program steps is limited to the maximum address space accessible by the central processing unit, and therefore when such a computer is used as a gaming machine, for example, the length of story of the game, the extension of variation in the game, the number of ! display scenes and the number of characters capable of being displayed are limited.
15One prior art approach which was proposed to ` eliminate such an inconvenience disclosed in, for example, the Japanese Patent Laid-Open No. 112352/1984, laid open on June 28, 1984 which corresponds to the U.S. Patent Application Serial No. 261,301, now U.S. Patent No.
4,368,515.
In the above~identified prior art, an address from the central processing unit installed in the main unit of the gaming machine is given to a plurality of memory chips as a common address input, while that address is decoded by an address decoder. When a specific address is outputted by the central processing unitl the address decoder outputs a B
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signal, and in response to the signal, a flip-flop or a latching circuit is operated. From the flip-flop ox the latching circuit, a chip select (CS) signal for selecting a chip corresponding to that specific address is outputted, and 5 the chip select signal enables the corresponding memory chip. Accordingly, the memory area designated by the address of the selected memory chip can be accessed by the central processing unit.
The above described prior art has an advantage that the 10 memory capacity can be expanded without increasing the address ports from the central processing unit, but leaves the following problem to solve.
With the recent advance in the semiconductor technology, the degree of integration of integrated circuit chip is 15 being more and more increased, but the above-described prior art cannot accommodate or such a one-chip, large-capacity memory; Bècause, output of the 1ip~flop or the latching circuit is used as a chip select signal, and such a chip select signal can only select enabling or disabling on a 20 chip basis, and cannot perform enable/disable of the specific area in the one-chip memory. In other words, in the prior art, an arbitxary chip of the memory chips respectively having the nur~er of addresses accessible by the central processing unit can be enabled to designa~e an 25 address, but banks respectively having addresses acces-.
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sible by the central processing unit of a one-chip memory having addresses of a number larger than the address space accessible by the central processing unit cannot be selected or addressed. Accordingly, by the prior art, the benefit of the up-to-date semiconductor technology cannot : be given, and the ratio of the rise in cost to the increase in memory capacity is large, eventually resulting in a high price.
In addition, various other methods of changing over the memory banks have been proposed, but any of them does not relate to the memory cartridge intended by the present invention.
Therefore, a principal object of the present invention is to provide a memory cartridge which, even if the maximum address space accessible by a central processing unit comprised in a main unit of a computer or video game machine which includes a computer to which the same is loaded is limited, can store data more than the address space and is accessible by the central processing address unit.
Another object of the present invention is to provide a memory cartridge in which each address of a large-capacity, one-chip memory can be accessed by the central processing unit without increasing the number of address ports of the B
.
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central processing unit.
The memory cartridge in accordance with the present invention is attachable to and detachable from the main unit including the central processing 5 unit accessible to a xelatively small address space, and is loaded in the main unit when used, comprising: a case,.a circuit board housed in the case, a first memory which is . mounted on the board and has a relatively large memory capacity and whose memory area is divided into a plurality 10 of banks, an active device which is mounted on the board and is for selectively designating a bank of the first memory, and conductive patterns for leading address terminals and data terminals of the first memory to the edge of the board to enable them to connect to the central processing unit of 15 the main unit and connecting the first memory and the active device~
`~ When the central processing unit accesses a Dre-determined bank of the first memory, data stored in the bank is read out. If the data includes data showing a bank of 20 the first memory to be accessed next, the active device e.nables that bank of the first memory based on that data, for example. The central processing unit accesses to that bank using another address space.
. If the memory cartridge includes a second memory, data 25 read from the bank of the first memory is transferred to the ~`
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second memory as required. When memory cartridge is used for the gaming machine, character data is stored in the second memory.
In accordance with the present invention, even if the 5 address space accessible by the central processing unit is limited, by properly changing-over banks of the first memory, a memory having capacity larger than the ma~imum address space of the central processing unit can be utilized. This means that, in accordance with the present 10 invention, the memory capacity accessible by the cen-tral processing unit can be expanded apparently.
In an embodiment, a large-capacity, one-chip ROM is used as the first memory. ~ specific bank of the one-chip ROM is kep-t accessible all the time by the central processing unit.
15 When the specific bank is accessed and a bank selecting data for selecting another bank is read therefrom, the bank selec-ting data is given to a counter as an active device.
Output of the counter is given to the most significan-t three bits of the address of the one-chip ROM, and thereby another 20 bank in the one-chip ROM is enabled. The bank thus enabled can be addressed by the output from the address port of the central processing unit.
Selecting data for still another bank is stored in the previously enabled bank, and when the same is read out, the 25 counter outputs an address which is to enable that still .
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another bank to the most significant three bits of the address of the one-chip ROM in a similar manner.
Thus, in accordance with the embodiment of the present invention, change-over to an arbitrary bank can be made at 5 an arbitrary tlming with the progress of a program.
Accordingly, by utilizin~ the memory cartridge as described above for a cartridge for gaming machine, a more versa-tile game can be realized. In -this case, the character data stored in the bank of the one-chip ROM can be utilized in 10 common in each scene of displaying performed by each bank of the one-chip ROM, and therefore a series of games having long stories can also be produced easily.
Also, in accordance with the present invention, an unjust copying or dubbing of the memory cartridge can be 15 pr~vented by arbitrarily setting the bank selecting data at an arbitrary progxam step.
These objects and other objects, features, aspects and advantages of the present inven-tion will become more apparent from the following detailed descrip-tion of the 20 embodiments of the present invention when taken in con-junction with accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is an exploded perspective view showing one embodiment in accordance with the present invention.
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Fig. 2 is a schematic block diagram showing one example of a home TV gaming machine capable of utilizing a cartridge as shown in Fig. l.
Fig. 3 is a detailed circuit diagram showing a 5 relationship between a memory for program and a memory for characters as shown in Fig. l and Fig. 2.
Fig. 4 is an illustrative view showing a relationship between banks of the memory for program and a memory map of a microprocessor.
DESCRIPTION OF THE PREFERRED EMBODI~ENTS
Fig. l is an exploded perspective view showing one embodi-ment in accorclance with the present invention. A memory cartridge or gaming machine (hereinafter reerred to simply as cartridge) 10 comprises a case 12 formed by an upper case 15 12a and a lower case 12b. The case 12 is flat and nearly rectangular, and a protrudent portion 14 is formed at one side thereof. Then, an opening 16 is formed by this protrudent portion 14 and the other sides of the case 12 are sealed by side walls.
A printed circuit board 18 is housed in the case 12, and a protrudent portion 20 is formed at a portion of the printed circuit board 18 corresponding to the protrudent portion 14 of the above-described case 12. Accordingly, the protrudent portion~20 of the printed circuit board 18 is '.' '' ' ' ~3~
exposed through the cpening 16 of the case 12. Then, conductive patterns or contacts 22, 22, ... constituting .
means for connecting the cartridge 10 to a main unit of a y gaming machine are formed on the pro-trudent portion 20 in a 5 manner of distributing in the extending direction of the side of the protrudent portion 20.
A program memory 24 as a first memory, a character memory 26 as a second memory and a semiconductor device 28 ; as an active device are mounted on the printed circuit board 10 18. As detailed later, the semiconductor device 28 may bé a counter or a latching circuit. Then, these devices 24, 26 and 28 are connected to proper conductive patterns on the printed circuit board 18, being connected to predetermined contacts 22 farmed on the protrudent portion 20 as required.
Fig. 2 is a schematic block diagram showing one example o a home TV gaming machine capable of utilizing the cartridge as shown in Fig. 1. A configuration in this Fig.
The present invention relates to a memory cartridge. More specifically, the present invention relates to a memory cartridge which is attachable to and detachable from a main unit of a personal computer or a home video gaming machine which includes a computer and a is loaded in the main unit when used.
Home personal computers or the gaming machine which includes a computer called the "Nintendo Entertainment System" (trade mark) manufactured and sold by the assignee of the present invention and the one called the "MSX" (commodity name) use an external memory cartridge in which a game or educational program or the like is written in advance is used, and the computer is enabled by loading such external memory cartridge in the main unit.
The memory cartridge includes a non-volatile memory (for example, ROM) for storing program data and/or character data for display.
When a central processing unit (CPU) located in the main unit of the computer accesses the ROM of the memory cartridye, the maximum number of accessible B
" 3~3~3~2 addresses, that i5, address space is limited by the performance (number of bits) of the central processing unit, and therefore the usable memory capacity of the ROM
comprised in the memory cartridge is also limited naturally. For example, in the above-described "Nintendo Entertainment System", only a 256K-bit ROM can be used for program and a 64K-bit ROM for characters at a maximum.
Thus, the maximum number of program steps is limited to the maximum address space accessible by the central processing unit, and therefore when such a computer is used as a gaming machine, for example, the length of story of the game, the extension of variation in the game, the number of ! display scenes and the number of characters capable of being displayed are limited.
15One prior art approach which was proposed to ` eliminate such an inconvenience disclosed in, for example, the Japanese Patent Laid-Open No. 112352/1984, laid open on June 28, 1984 which corresponds to the U.S. Patent Application Serial No. 261,301, now U.S. Patent No.
4,368,515.
In the above~identified prior art, an address from the central processing unit installed in the main unit of the gaming machine is given to a plurality of memory chips as a common address input, while that address is decoded by an address decoder. When a specific address is outputted by the central processing unitl the address decoder outputs a B
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signal, and in response to the signal, a flip-flop or a latching circuit is operated. From the flip-flop ox the latching circuit, a chip select (CS) signal for selecting a chip corresponding to that specific address is outputted, and 5 the chip select signal enables the corresponding memory chip. Accordingly, the memory area designated by the address of the selected memory chip can be accessed by the central processing unit.
The above described prior art has an advantage that the 10 memory capacity can be expanded without increasing the address ports from the central processing unit, but leaves the following problem to solve.
With the recent advance in the semiconductor technology, the degree of integration of integrated circuit chip is 15 being more and more increased, but the above-described prior art cannot accommodate or such a one-chip, large-capacity memory; Bècause, output of the 1ip~flop or the latching circuit is used as a chip select signal, and such a chip select signal can only select enabling or disabling on a 20 chip basis, and cannot perform enable/disable of the specific area in the one-chip memory. In other words, in the prior art, an arbitxary chip of the memory chips respectively having the nur~er of addresses accessible by the central processing unit can be enabled to designa~e an 25 address, but banks respectively having addresses acces-.
., 13~ 4~
sible by the central processing unit of a one-chip memory having addresses of a number larger than the address space accessible by the central processing unit cannot be selected or addressed. Accordingly, by the prior art, the benefit of the up-to-date semiconductor technology cannot : be given, and the ratio of the rise in cost to the increase in memory capacity is large, eventually resulting in a high price.
In addition, various other methods of changing over the memory banks have been proposed, but any of them does not relate to the memory cartridge intended by the present invention.
Therefore, a principal object of the present invention is to provide a memory cartridge which, even if the maximum address space accessible by a central processing unit comprised in a main unit of a computer or video game machine which includes a computer to which the same is loaded is limited, can store data more than the address space and is accessible by the central processing address unit.
Another object of the present invention is to provide a memory cartridge in which each address of a large-capacity, one-chip memory can be accessed by the central processing unit without increasing the number of address ports of the B
.
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central processing unit.
The memory cartridge in accordance with the present invention is attachable to and detachable from the main unit including the central processing 5 unit accessible to a xelatively small address space, and is loaded in the main unit when used, comprising: a case,.a circuit board housed in the case, a first memory which is . mounted on the board and has a relatively large memory capacity and whose memory area is divided into a plurality 10 of banks, an active device which is mounted on the board and is for selectively designating a bank of the first memory, and conductive patterns for leading address terminals and data terminals of the first memory to the edge of the board to enable them to connect to the central processing unit of 15 the main unit and connecting the first memory and the active device~
`~ When the central processing unit accesses a Dre-determined bank of the first memory, data stored in the bank is read out. If the data includes data showing a bank of 20 the first memory to be accessed next, the active device e.nables that bank of the first memory based on that data, for example. The central processing unit accesses to that bank using another address space.
. If the memory cartridge includes a second memory, data 25 read from the bank of the first memory is transferred to the ~`
` B
~3~
second memory as required. When memory cartridge is used for the gaming machine, character data is stored in the second memory.
In accordance with the present invention, even if the 5 address space accessible by the central processing unit is limited, by properly changing-over banks of the first memory, a memory having capacity larger than the ma~imum address space of the central processing unit can be utilized. This means that, in accordance with the present 10 invention, the memory capacity accessible by the cen-tral processing unit can be expanded apparently.
In an embodiment, a large-capacity, one-chip ROM is used as the first memory. ~ specific bank of the one-chip ROM is kep-t accessible all the time by the central processing unit.
15 When the specific bank is accessed and a bank selecting data for selecting another bank is read therefrom, the bank selec-ting data is given to a counter as an active device.
Output of the counter is given to the most significan-t three bits of the address of the one-chip ROM, and thereby another 20 bank in the one-chip ROM is enabled. The bank thus enabled can be addressed by the output from the address port of the central processing unit.
Selecting data for still another bank is stored in the previously enabled bank, and when the same is read out, the 25 counter outputs an address which is to enable that still .
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another bank to the most significant three bits of the address of the one-chip ROM in a similar manner.
Thus, in accordance with the embodiment of the present invention, change-over to an arbitrary bank can be made at 5 an arbitrary tlming with the progress of a program.
Accordingly, by utilizin~ the memory cartridge as described above for a cartridge for gaming machine, a more versa-tile game can be realized. In -this case, the character data stored in the bank of the one-chip ROM can be utilized in 10 common in each scene of displaying performed by each bank of the one-chip ROM, and therefore a series of games having long stories can also be produced easily.
Also, in accordance with the present invention, an unjust copying or dubbing of the memory cartridge can be 15 pr~vented by arbitrarily setting the bank selecting data at an arbitrary progxam step.
These objects and other objects, features, aspects and advantages of the present inven-tion will become more apparent from the following detailed descrip-tion of the 20 embodiments of the present invention when taken in con-junction with accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is an exploded perspective view showing one embodiment in accordance with the present invention.
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Fig. 2 is a schematic block diagram showing one example of a home TV gaming machine capable of utilizing a cartridge as shown in Fig. l.
Fig. 3 is a detailed circuit diagram showing a 5 relationship between a memory for program and a memory for characters as shown in Fig. l and Fig. 2.
Fig. 4 is an illustrative view showing a relationship between banks of the memory for program and a memory map of a microprocessor.
DESCRIPTION OF THE PREFERRED EMBODI~ENTS
Fig. l is an exploded perspective view showing one embodi-ment in accorclance with the present invention. A memory cartridge or gaming machine (hereinafter reerred to simply as cartridge) 10 comprises a case 12 formed by an upper case 15 12a and a lower case 12b. The case 12 is flat and nearly rectangular, and a protrudent portion 14 is formed at one side thereof. Then, an opening 16 is formed by this protrudent portion 14 and the other sides of the case 12 are sealed by side walls.
A printed circuit board 18 is housed in the case 12, and a protrudent portion 20 is formed at a portion of the printed circuit board 18 corresponding to the protrudent portion 14 of the above-described case 12. Accordingly, the protrudent portion~20 of the printed circuit board 18 is '.' '' ' ' ~3~
exposed through the cpening 16 of the case 12. Then, conductive patterns or contacts 22, 22, ... constituting .
means for connecting the cartridge 10 to a main unit of a y gaming machine are formed on the pro-trudent portion 20 in a 5 manner of distributing in the extending direction of the side of the protrudent portion 20.
A program memory 24 as a first memory, a character memory 26 as a second memory and a semiconductor device 28 ; as an active device are mounted on the printed circuit board 10 18. As detailed later, the semiconductor device 28 may bé a counter or a latching circuit. Then, these devices 24, 26 and 28 are connected to proper conductive patterns on the printed circuit board 18, being connected to predetermined contacts 22 farmed on the protrudent portion 20 as required.
Fig. 2 is a schematic block diagram showing one example o a home TV gaming machine capable of utilizing the cartridge as shown in Fig. 1. A configuration in this Fig.
2 shows the above-described "Nintendo Entertainment System"
`' manufactured and sold by the applicant of the present 20 invention. However, note that t~le present Invention can e.uti-lïze~ for every apparatus s~ucn -as ~-n-e gaming-a-ppa-ra-~as or a microcomputer ~hat uses an e~ternal memory c-a-rtrr~g-e.
As described above, the cartridge' 10 comprises the 25 program memory 24, the character memory 26 and the _ 9 _ i' ~B .
` " ~,3,~
semiconductor device 28 which are mounted on the printed circuit board 18, and the protrudent portion 20 of the printed circuit board 18 is attached to an edge connector 32 of a gaming machine main unit 30, and thereby the cartridge 5 10 and the gaming machine main unit 30 are connected electrically so as to constitute one gaming system.
The gaming machine main unit 30 comprises a micro-processor 34 which may be, for example, the integrated circuit "2A03" manufactured by Nintendo, and controllers 10 38a and 38b are connected to the microprocessor 34 through an I/O interface 36. The gaming machine main unit 30 is fur-ther provided with a PPU tpicture processing unit) 40, a video R~M 42 and an RF modulator 44. For the PPU 40, for example, the integrated circuit "2C02" manufactured by 15 Nintendo ls used, and the PPU 40 reads video data under the control oE the microprocessor 34, and gives the same to the RF modulator 44 as a video signal. The RF modula-tor 44 outputs a video signal being given as a television signal for a TV receiver, for example, of the NTSC system.
Here, detailed description is made on correlation among the program memory 24, the character memory 26 and the semiconductor device 28 in reference to Fig. 3. For example, the program memory 24 is composed of a lM-bit masked ROM, and the character memory 26 is composed of a 25 64K-bit static RAM. Ground terminals G of the program , .: , : .
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memory 24 and the character memory 26 are connected to the ground, and-a predetermined powex supply voltage Vcc is applied to these memories 24 and 26 through power supply terminals.
A chip enable terminal CE of the program memory 24 is connected to the gaming machine main unit 30 (Fig. 2) through a predetermined terminal (for example, No. 44 terminal) of the edge connector 32. A memory select signal ROMSEL from the gaming machine main unit 30 is given to the 10 chip enable terminal CE. Furthermore, the program memory 24 has address terminals A0-A16 of 17 bits, and has data terminals D0-D7 of 8 bits. These address terminals and data terminals are connected to the gaminy machine main unit 30 through the edge connector 32, and data from predetermined 15 terminals, that is, data from the terminals D0-D2 of the least significant three bits in this embodlment, is given as bank selecting data and as three~bit input of the semi-conductor device, that is, the counter 28.
A chip select terminal CS, the chip enable terminal CE
20 and a write enable terminal WE of the character memory 26 are all connected to the gaming machine main unit 30 through the terminals of the edge connector 32 ~for example, No. 56 termina], No. 17 terminal and No. 47 terminal). A
read signal XD from the gaming machine main unit 30 i~ given 25 to the chip enable terminal CE through the edge connector .
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32, and the write signal WE is given to the write enable terminal WE. Also, the character memory 26 comprises address terminals A0-A12 of 13 bits and data terminals D0-D7 of 8 bits. The address terminals A0-A12 are connected to 5 the gaming machine main unit 30 through the edge connector 32. The data terminals D0-D7 are connected likewise to the gaming machine main unit 30.
Note that one digit of address is indicated by the hexadecimal notation.
In this embodiment, as shown in Fig. 4, the program memory 24 is constituted, for example, as a set of memory banks on a 128K-bit basis. This means that the firs-t memory or the program memory 24 comprises eight 128K-bit banks BK0-BK7. These banks BK0-BK7 are defined by addresses 15 "00000~lFFFF".
Also, the second memory or -the character memory 26 is constituted as a 64K-bit static RAM.
Furthermore, in this embodiment, for the semiconductor device 28, for example, the integrated circuit "74LS161"
20 manufactured by Texas Instruments is used, and accordingly the semiconductor device 28 is constituted as a three-bit counter. A read/write signal R/W from the gaming machine main unit 30 is given to a load terminal LOAD of the counter 28, and as described above, the data terminals D0-D2 of the 25 least significant three bits of the program memory 2~ are connec-ted to the load terminal LOAD as a preset input.
Furthermore, -the memory select slgnal ROMSEL from the gaming machine main unit 30 to the program memory 24 is given to a clock terminal CK through the edge connector 32.
5 Accordingly, count input is given to the counter 28 every time when the program memory 24 is selected by the gaming machine main unit 30, and the counter 28 is incremented ~or decremented) by that count input.
Output terminals of the counter 28 is of three bits, and 10 the three-bit output is given to the address terminals of the most significant three bits A16, A15 and A14 of the program memory 24 -through respective OR gates 46a, 46b and 46c. More specifically, the address terminal (No. 35 terminal) of the yaming machine main unit 30 is connec-ted to 15 one input oE each oE these OR gates 46a, 46b and 46c, and each output of the corresponding bit of the counter 28 is given to the other input of each OR gate. Accordingly, for the program memory 24, the bank thereof is selected accordlng to the bank selecting data (Eig. 4) in the output 20 of the counter 28. For example, as shown in Fiy. 4, if the output of the counter 28 is "000", the bank BK0 is selected, if "001" the bank BKl is selected, if "010" the bank BK2 is ; selected, if "011" the bank BK3 is selected, if "100" the bank BK4 is selected, if "101" the bank sK5 is selected, if 25 "110" the bank BK6 ls selected, and if '1111" the bank BK7 is 9~
selected, respectively.
The microprocessor 34 of the gaming machine main unit 30 is accessible only to two-bank area of the program memory 24 as the first memory. This means that the microprocessor 5 34 has address spaces for two banks, "8000-FFFF". Among them, a first address space "C000-FF~F" is allocatQd so as to access in a fixed fashion always to the ~ank BK7 of the program memory 24. Then, when an arbitrary bank of the banks BK0-BK7 of the program memory 24 is selected, a second 10 address space of 64K bits defined by addresses "8000-C000"
is allocated to the address space corresponding to the selected bank.
; Accordingly, in the banks BK0-BK7 of the first memory 24, the bank selecting data for the bank to be selected next 15 is required to be stored in the last of or halfway that data. .To be detailed, in the bank ~X7 as a standing area, the data of the bank to be accessed next by the central processing unit or the microprocessor 34 is stored, and in the bank to be read next in such a manner, the selecting 20 data for the still next bank is stored. Then, all the banks of the program memory 24 can be utilized at an arbitrary timing by the second address space of the microprocessor 34.
In the operation, the power supply is first turned on in the state tha~ the cartridge 10 is loaded in the gaming 25 machine main unit 30, and immediately after that or after a B
~3-~J~
reset switch has been depressed, a read command is outputted from the microprocessor 34 of the gaming machine main unit 30 through the address terminal A14 thereof (No. 35 terminal of the edge connector 32). When the address terminal A14 5 goes high, all outputs of the OR gates 46a-46c become high, and "1" is inputted to all of the address terminals A16-A14 of the most significant three bits of the program memory 24, and accordingly, at this point the microprocessor 34 is accessible to the standing area, that is, the bank BK7 of 10 the program memory 24.
Then, the program data of the bank BK7 of the program memory 24 is read and the microprocessor 34 is operated based on that program data. This means that, at this time, the microprocessor 34 can address the bank BK7 using the 15 first address space of the addresses "C000-FFFF".
The mi.croprocessor 34 executes a program according to a program data of the bank BK7 of the program memory 24, and the bank selecting data for designating a bank of the proyram memory 24 is set in the first of (or in the last of 20 or halfway) that program data. As described previously, the bank selecting data selects any one of the banks BKO-BK7 of the program memory 24 by three bits of "000"-"111".
Then, the bank selecting data from the data terminals D0-D2 of the lleast significant three bits of the program 25 memory 24 is given as a preset input of the counter 28. On - \
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the other hand, -the read/write signal R/W is given to the counter 28 as a load command of the counter 28 from the microprocessor 34, and at this time, the signal R/W is given as the high level, and accordingly in the coun-ter 28, the 5 preset inpu-t thereof is not loaded.
When the read/write signal R/W yoes low level during execution of -the program, that is, when the load command is given, the bank selecting data outputted from the data terminals D0-D2 of theleast significant three bits of the 10 program memory 24 is written to the counter 28. Thereafter, the microprocessor 34 gives a read signalr that is, changes the signal R/W to the high level, and accesses to the bank (Eor example, BK6) selected by the counter 28 using the second address space as described above.
When the memory select signal ROMSEL from the micro-processor 34 of the gaming machine main unit 30 is low levelr the counter 28 and the program memory 24 are enabled.
Then, if the data of the selected bank (for example, BK6) is character data, a command of transferring the character da-ta 20 to the second memory, that is, the character memory 26 is outputted.
Then~ according to that transfer command, the write enable signal WE from the microprocessor 34 is changed to the low level, and write of the character memory 26 is made 25 possible. Then, thle data of the selected bank (for example, , . .. ..
- ` -~3~
BK6) of the program memory 24 are all read in the address sequenee, and the read eharaeter data are given to the mieroproeessor 34. The rnieroproeessor 34 gives the eharaeter data to the PPU 40, and the PPU 40 writes the 5 charaeter data to the eharaeter memory 26 in synchronism with address designating of the character memory 26.
Thereafter, similarly, according to the bank selecting data contained in the program data from the program memory 24, any of the banks BK0-BK7 of this program memory 24 is lO addressed as "8000-C000" of the second address spaee of the microprocessor 34, and the game progresses based on the program data of the bank selected at that time and the eharaeter data of the eharaeter memory 26. Aceordingly, the eharacter data has only to be written in advance to an 15 arbitrary bank of the proqram memory 24 to be required.
This means that the bank seleeting data is set in advance in a program data eontained in any of the banks of the program memory 24, and the data of the bank seleeted by the bank selecting data is written into the character memory for 20 eharacters 26, and thereby the bank of that character data has only to be accessed only when required. In order words, proeessing has only to jump to the required bank during execution of the program to read the character data at that time. Then, sueh a bank selecting data can be set 25 arbitrarily by the program, and therefore copying or dubbing - ~3~ Z
of the cartridge 10 can be prevented effectively.
As in the case with this embodiment, even if the maximum address space of the microprocessor 34 is relatively small, all of the banks of the program memory 24 can be selected 5 arbitrarily, and therefore the memory capacity which can be utilized by the microprocessor 34 can be expanded apparently. In addition, the present invention can be utilized -not only for the gaming system but also for the educational system, being able to have universality.
In addition, in the above-described embodiment, the case is described where among a plurality of banks BK0-BK7 comprised in the program memory 24, in the bank B~7, data for transfer-controlling the character data (that is, bank selecting data, latch command of bank selecting data, write 15 command to the character memory 26 and the like) are program-set in advance, and a return command is set in advance in the last address o the bank storing the character data, and with the progress of the game, based on the program of the bank BK7, a character data of another 20 bank is controlled to be transferred to the character memory 26. However, the transfer-controlling data may be stored in several bytes close to the last address of each bank storing the character data.
Also, in the above-described embodiment, a masked ROM is 25 used for the program memory 24. However, for the program B
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memory 24, for example, an EPROM or the like can be utilized, and further any type of memory can be utilized if it not volatile.
Furthermore, in the embodiment, the character data is 5 written into the character memory 26, but for such data, besides, video data and the like can be written, and in this case, the character memory 26 can be utilized also as a so-called video RAM
~lthough the present invention has been described and 10 illustrated in detail, it is clearly understood that the same is by way of illustration and example onl~ and is not to be taken by way of limitation, the spring and scope of the present invention bein~ lim.ited only by the -terms of the appended claims.
, .~ - -
`' manufactured and sold by the applicant of the present 20 invention. However, note that t~le present Invention can e.uti-lïze~ for every apparatus s~ucn -as ~-n-e gaming-a-ppa-ra-~as or a microcomputer ~hat uses an e~ternal memory c-a-rtrr~g-e.
As described above, the cartridge' 10 comprises the 25 program memory 24, the character memory 26 and the _ 9 _ i' ~B .
` " ~,3,~
semiconductor device 28 which are mounted on the printed circuit board 18, and the protrudent portion 20 of the printed circuit board 18 is attached to an edge connector 32 of a gaming machine main unit 30, and thereby the cartridge 5 10 and the gaming machine main unit 30 are connected electrically so as to constitute one gaming system.
The gaming machine main unit 30 comprises a micro-processor 34 which may be, for example, the integrated circuit "2A03" manufactured by Nintendo, and controllers 10 38a and 38b are connected to the microprocessor 34 through an I/O interface 36. The gaming machine main unit 30 is fur-ther provided with a PPU tpicture processing unit) 40, a video R~M 42 and an RF modulator 44. For the PPU 40, for example, the integrated circuit "2C02" manufactured by 15 Nintendo ls used, and the PPU 40 reads video data under the control oE the microprocessor 34, and gives the same to the RF modulator 44 as a video signal. The RF modula-tor 44 outputs a video signal being given as a television signal for a TV receiver, for example, of the NTSC system.
Here, detailed description is made on correlation among the program memory 24, the character memory 26 and the semiconductor device 28 in reference to Fig. 3. For example, the program memory 24 is composed of a lM-bit masked ROM, and the character memory 26 is composed of a 25 64K-bit static RAM. Ground terminals G of the program , .: , : .
~3~
memory 24 and the character memory 26 are connected to the ground, and-a predetermined powex supply voltage Vcc is applied to these memories 24 and 26 through power supply terminals.
A chip enable terminal CE of the program memory 24 is connected to the gaming machine main unit 30 (Fig. 2) through a predetermined terminal (for example, No. 44 terminal) of the edge connector 32. A memory select signal ROMSEL from the gaming machine main unit 30 is given to the 10 chip enable terminal CE. Furthermore, the program memory 24 has address terminals A0-A16 of 17 bits, and has data terminals D0-D7 of 8 bits. These address terminals and data terminals are connected to the gaminy machine main unit 30 through the edge connector 32, and data from predetermined 15 terminals, that is, data from the terminals D0-D2 of the least significant three bits in this embodlment, is given as bank selecting data and as three~bit input of the semi-conductor device, that is, the counter 28.
A chip select terminal CS, the chip enable terminal CE
20 and a write enable terminal WE of the character memory 26 are all connected to the gaming machine main unit 30 through the terminals of the edge connector 32 ~for example, No. 56 termina], No. 17 terminal and No. 47 terminal). A
read signal XD from the gaming machine main unit 30 i~ given 25 to the chip enable terminal CE through the edge connector .
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32, and the write signal WE is given to the write enable terminal WE. Also, the character memory 26 comprises address terminals A0-A12 of 13 bits and data terminals D0-D7 of 8 bits. The address terminals A0-A12 are connected to 5 the gaming machine main unit 30 through the edge connector 32. The data terminals D0-D7 are connected likewise to the gaming machine main unit 30.
Note that one digit of address is indicated by the hexadecimal notation.
In this embodiment, as shown in Fig. 4, the program memory 24 is constituted, for example, as a set of memory banks on a 128K-bit basis. This means that the firs-t memory or the program memory 24 comprises eight 128K-bit banks BK0-BK7. These banks BK0-BK7 are defined by addresses 15 "00000~lFFFF".
Also, the second memory or -the character memory 26 is constituted as a 64K-bit static RAM.
Furthermore, in this embodiment, for the semiconductor device 28, for example, the integrated circuit "74LS161"
20 manufactured by Texas Instruments is used, and accordingly the semiconductor device 28 is constituted as a three-bit counter. A read/write signal R/W from the gaming machine main unit 30 is given to a load terminal LOAD of the counter 28, and as described above, the data terminals D0-D2 of the 25 least significant three bits of the program memory 2~ are connec-ted to the load terminal LOAD as a preset input.
Furthermore, -the memory select slgnal ROMSEL from the gaming machine main unit 30 to the program memory 24 is given to a clock terminal CK through the edge connector 32.
5 Accordingly, count input is given to the counter 28 every time when the program memory 24 is selected by the gaming machine main unit 30, and the counter 28 is incremented ~or decremented) by that count input.
Output terminals of the counter 28 is of three bits, and 10 the three-bit output is given to the address terminals of the most significant three bits A16, A15 and A14 of the program memory 24 -through respective OR gates 46a, 46b and 46c. More specifically, the address terminal (No. 35 terminal) of the yaming machine main unit 30 is connec-ted to 15 one input oE each oE these OR gates 46a, 46b and 46c, and each output of the corresponding bit of the counter 28 is given to the other input of each OR gate. Accordingly, for the program memory 24, the bank thereof is selected accordlng to the bank selecting data (Eig. 4) in the output 20 of the counter 28. For example, as shown in Fiy. 4, if the output of the counter 28 is "000", the bank BK0 is selected, if "001" the bank BKl is selected, if "010" the bank BK2 is ; selected, if "011" the bank BK3 is selected, if "100" the bank BK4 is selected, if "101" the bank sK5 is selected, if 25 "110" the bank BK6 ls selected, and if '1111" the bank BK7 is 9~
selected, respectively.
The microprocessor 34 of the gaming machine main unit 30 is accessible only to two-bank area of the program memory 24 as the first memory. This means that the microprocessor 5 34 has address spaces for two banks, "8000-FFFF". Among them, a first address space "C000-FF~F" is allocatQd so as to access in a fixed fashion always to the ~ank BK7 of the program memory 24. Then, when an arbitrary bank of the banks BK0-BK7 of the program memory 24 is selected, a second 10 address space of 64K bits defined by addresses "8000-C000"
is allocated to the address space corresponding to the selected bank.
; Accordingly, in the banks BK0-BK7 of the first memory 24, the bank selecting data for the bank to be selected next 15 is required to be stored in the last of or halfway that data. .To be detailed, in the bank ~X7 as a standing area, the data of the bank to be accessed next by the central processing unit or the microprocessor 34 is stored, and in the bank to be read next in such a manner, the selecting 20 data for the still next bank is stored. Then, all the banks of the program memory 24 can be utilized at an arbitrary timing by the second address space of the microprocessor 34.
In the operation, the power supply is first turned on in the state tha~ the cartridge 10 is loaded in the gaming 25 machine main unit 30, and immediately after that or after a B
~3-~J~
reset switch has been depressed, a read command is outputted from the microprocessor 34 of the gaming machine main unit 30 through the address terminal A14 thereof (No. 35 terminal of the edge connector 32). When the address terminal A14 5 goes high, all outputs of the OR gates 46a-46c become high, and "1" is inputted to all of the address terminals A16-A14 of the most significant three bits of the program memory 24, and accordingly, at this point the microprocessor 34 is accessible to the standing area, that is, the bank BK7 of 10 the program memory 24.
Then, the program data of the bank BK7 of the program memory 24 is read and the microprocessor 34 is operated based on that program data. This means that, at this time, the microprocessor 34 can address the bank BK7 using the 15 first address space of the addresses "C000-FFFF".
The mi.croprocessor 34 executes a program according to a program data of the bank BK7 of the program memory 24, and the bank selecting data for designating a bank of the proyram memory 24 is set in the first of (or in the last of 20 or halfway) that program data. As described previously, the bank selecting data selects any one of the banks BKO-BK7 of the program memory 24 by three bits of "000"-"111".
Then, the bank selecting data from the data terminals D0-D2 of the lleast significant three bits of the program 25 memory 24 is given as a preset input of the counter 28. On - \
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the other hand, -the read/write signal R/W is given to the counter 28 as a load command of the counter 28 from the microprocessor 34, and at this time, the signal R/W is given as the high level, and accordingly in the coun-ter 28, the 5 preset inpu-t thereof is not loaded.
When the read/write signal R/W yoes low level during execution of -the program, that is, when the load command is given, the bank selecting data outputted from the data terminals D0-D2 of theleast significant three bits of the 10 program memory 24 is written to the counter 28. Thereafter, the microprocessor 34 gives a read signalr that is, changes the signal R/W to the high level, and accesses to the bank (Eor example, BK6) selected by the counter 28 using the second address space as described above.
When the memory select signal ROMSEL from the micro-processor 34 of the gaming machine main unit 30 is low levelr the counter 28 and the program memory 24 are enabled.
Then, if the data of the selected bank (for example, BK6) is character data, a command of transferring the character da-ta 20 to the second memory, that is, the character memory 26 is outputted.
Then~ according to that transfer command, the write enable signal WE from the microprocessor 34 is changed to the low level, and write of the character memory 26 is made 25 possible. Then, thle data of the selected bank (for example, , . .. ..
- ` -~3~
BK6) of the program memory 24 are all read in the address sequenee, and the read eharaeter data are given to the mieroproeessor 34. The rnieroproeessor 34 gives the eharaeter data to the PPU 40, and the PPU 40 writes the 5 charaeter data to the eharaeter memory 26 in synchronism with address designating of the character memory 26.
Thereafter, similarly, according to the bank selecting data contained in the program data from the program memory 24, any of the banks BK0-BK7 of this program memory 24 is lO addressed as "8000-C000" of the second address spaee of the microprocessor 34, and the game progresses based on the program data of the bank selected at that time and the eharaeter data of the eharaeter memory 26. Aceordingly, the eharacter data has only to be written in advance to an 15 arbitrary bank of the proqram memory 24 to be required.
This means that the bank seleeting data is set in advance in a program data eontained in any of the banks of the program memory 24, and the data of the bank seleeted by the bank selecting data is written into the character memory for 20 eharacters 26, and thereby the bank of that character data has only to be accessed only when required. In order words, proeessing has only to jump to the required bank during execution of the program to read the character data at that time. Then, sueh a bank selecting data can be set 25 arbitrarily by the program, and therefore copying or dubbing - ~3~ Z
of the cartridge 10 can be prevented effectively.
As in the case with this embodiment, even if the maximum address space of the microprocessor 34 is relatively small, all of the banks of the program memory 24 can be selected 5 arbitrarily, and therefore the memory capacity which can be utilized by the microprocessor 34 can be expanded apparently. In addition, the present invention can be utilized -not only for the gaming system but also for the educational system, being able to have universality.
In addition, in the above-described embodiment, the case is described where among a plurality of banks BK0-BK7 comprised in the program memory 24, in the bank B~7, data for transfer-controlling the character data (that is, bank selecting data, latch command of bank selecting data, write 15 command to the character memory 26 and the like) are program-set in advance, and a return command is set in advance in the last address o the bank storing the character data, and with the progress of the game, based on the program of the bank BK7, a character data of another 20 bank is controlled to be transferred to the character memory 26. However, the transfer-controlling data may be stored in several bytes close to the last address of each bank storing the character data.
Also, in the above-described embodiment, a masked ROM is 25 used for the program memory 24. However, for the program B
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memory 24, for example, an EPROM or the like can be utilized, and further any type of memory can be utilized if it not volatile.
Furthermore, in the embodiment, the character data is 5 written into the character memory 26, but for such data, besides, video data and the like can be written, and in this case, the character memory 26 can be utilized also as a so-called video RAM
~lthough the present invention has been described and 10 illustrated in detail, it is clearly understood that the same is by way of illustration and example onl~ and is not to be taken by way of limitation, the spring and scope of the present invention bein~ lim.ited only by the -terms of the appended claims.
, .~ - -
Claims (22)
1. A memory cartridge attachable and detachable from a main unit including a computer, said main unit having a data bus, address bus, and a central processing unit, said memory cartridge comprising:
a circuit board having address lines and data lines attachable to said address bus and said data bus, respectively, when said cartridge is attached to said main unit;
a first memory mounted on said circuit board and connected to said address lines and said data lines, said first memory being non-volatile and having a bank selecting input terminal, said first memory having a predetermined storage capacity and being divided into a plurality of banks, each of said banks having a plurality of address locations, at least one of said banks storing bank selecting data for selecting other of said banks; and data holding means for holding said bank selecting data, said data holding means being mounted on said circuit board and connected to at least certain of said data lines and to said bank selecting input terminal to said first memory, said data holding means being loaded with bank selecting data read from said first memory in response to an enable signal for selecting or enabling said first memory and a write signal for writing data to said data holding means, such that said first memory is conditioned for reading data in an address being addressed by said central processing unit in a bank which is selected by said bank selecting data previously loaded into and held by said data holding means, wherein said first memory includes address terminals and said data holding means includes a semiconductor device which receives said hank selecting data from said first memory and sends a bank-switching signal to said address terminals, and wherein said semiconductor device is a counter.
a circuit board having address lines and data lines attachable to said address bus and said data bus, respectively, when said cartridge is attached to said main unit;
a first memory mounted on said circuit board and connected to said address lines and said data lines, said first memory being non-volatile and having a bank selecting input terminal, said first memory having a predetermined storage capacity and being divided into a plurality of banks, each of said banks having a plurality of address locations, at least one of said banks storing bank selecting data for selecting other of said banks; and data holding means for holding said bank selecting data, said data holding means being mounted on said circuit board and connected to at least certain of said data lines and to said bank selecting input terminal to said first memory, said data holding means being loaded with bank selecting data read from said first memory in response to an enable signal for selecting or enabling said first memory and a write signal for writing data to said data holding means, such that said first memory is conditioned for reading data in an address being addressed by said central processing unit in a bank which is selected by said bank selecting data previously loaded into and held by said data holding means, wherein said first memory includes address terminals and said data holding means includes a semiconductor device which receives said hank selecting data from said first memory and sends a bank-switching signal to said address terminals, and wherein said semiconductor device is a counter.
2. A memory cartridge in accordance with claim 1, wherein said counter includes a gating means which, when provided with a signal produced by said central processing unit, directs this signal to the most significant of said address terminals of said first memory, and when not provided with this signal, directs an output of said holding means to the most significant of said address terminals of said first memory.
3. A memory cartridge attachable to and detachable from a data processing apparatus, said data processing apparatus having first and second data buses, first and second address buses, a central processing unit having limited addressing capability and being connected to said first data bus and said first address bus, and a video processing unit connected to said second data bus and said second address bus, said memory cartridge comprising:
a circuit board having first and second data lines attachable to said first and second data buses, respectively and having first and second address lines attachable to said first and second address buses, respectively;
a first memory mounted on said circuit board and connected to said first data lines and said first address lines, said first memory being non-volatile and having a bank selecting input terminal, said first memory having a predetermined addressable storage capacity exceeding that of the limited addressing capability of the central processing unit, said first memory being divided into a plurality of banks, each of said banks having a memory capacity less than the address space accessible by said first address bus, at least one of said banks adapted to store program data, at least one of said address locations of one of said banks adapted to store bank selecting data for selecting another of said banks;
a second memory connected to said second data lines and said second address lines, said second memory storing character data for video processing;
data holding means mounted on said circuit board for holding said bank selecting data, said data holding means having a data input terminal connected to at least certain of said first data lines, and having an output terminal; and conductive pattern means formed on said circuit board and connecting said output terminal of said data holding means to said bank selecting input terminal to said first memory; wherein said data holding means is loaded with bank selecting data that is read from said first memory in response to an enable signal for enabling said first memory and a write signal for writing of said data holding means, and said first memory reads out data stored in an address that is addressed by said central processing unit in a bank that is selected by said bank selecting data that has been previously loaded into said data holding means, wherein said first memory includes address terminals, and said data holding means includes a semiconductor device which receives said bank selecting data from said first memory and sends a bank-switching signal to said address terminals, said semiconductor device comprises a counter means for holding said bank selecting data.
a circuit board having first and second data lines attachable to said first and second data buses, respectively and having first and second address lines attachable to said first and second address buses, respectively;
a first memory mounted on said circuit board and connected to said first data lines and said first address lines, said first memory being non-volatile and having a bank selecting input terminal, said first memory having a predetermined addressable storage capacity exceeding that of the limited addressing capability of the central processing unit, said first memory being divided into a plurality of banks, each of said banks having a memory capacity less than the address space accessible by said first address bus, at least one of said banks adapted to store program data, at least one of said address locations of one of said banks adapted to store bank selecting data for selecting another of said banks;
a second memory connected to said second data lines and said second address lines, said second memory storing character data for video processing;
data holding means mounted on said circuit board for holding said bank selecting data, said data holding means having a data input terminal connected to at least certain of said first data lines, and having an output terminal; and conductive pattern means formed on said circuit board and connecting said output terminal of said data holding means to said bank selecting input terminal to said first memory; wherein said data holding means is loaded with bank selecting data that is read from said first memory in response to an enable signal for enabling said first memory and a write signal for writing of said data holding means, and said first memory reads out data stored in an address that is addressed by said central processing unit in a bank that is selected by said bank selecting data that has been previously loaded into said data holding means, wherein said first memory includes address terminals, and said data holding means includes a semiconductor device which receives said bank selecting data from said first memory and sends a bank-switching signal to said address terminals, said semiconductor device comprises a counter means for holding said bank selecting data.
4. A memory cartridge in accordance with claim 3, wherein said counter includes a gating means which, when provided with a signal by said central processing unit, sends this signal to the most significant of said address terminals of said first memory, and when not provided with this signal, sends the output of said holding means to the most significant of said address terminals of said first memory.
5. A memory cartridge attachable to and detachable from a main unit including a computer, said main unit having a data bus, an address bus and a central processing unit, said memory cartridge comprising:
a circuit board having address lines and data lines attachable to said address bus and said data bus, respectively, when said cartridge is attached to said main unit;
a first memory mounted on said circuit board, said first memory being non-volatile and having address terminals connected to said address lines and data terminals connected to said data lines, said first memory having predetermined storage capacity and being divided into a plurality of banks, each of said banks having a plurality of address locations, at least one of said banks storing bank selecting data for selecting other of said banks;
data holding means mounted on said circuit board for holding bank selecting data, said data holding means having at least one data input terminal connected to at least one of said data lines, and having at least one output terminal; and conductive pattern means formed on said circuit board and connecting said at least one output terminal of said data holding means to a predetermined portion of said address terminals of said first memory; wherein said data holding means is loaded with bank selecting data that is read from said first memory in response to an enable signal for enabling said first memory and a read/write signal for accessing said first memory means both of which are received from said central processing unit, and said first memory includes means for reading out data stored in an address location that is addressed by said central processing unit in a bank that is selected by said bank selecting data that has been previously loaded into said data holding means.
a circuit board having address lines and data lines attachable to said address bus and said data bus, respectively, when said cartridge is attached to said main unit;
a first memory mounted on said circuit board, said first memory being non-volatile and having address terminals connected to said address lines and data terminals connected to said data lines, said first memory having predetermined storage capacity and being divided into a plurality of banks, each of said banks having a plurality of address locations, at least one of said banks storing bank selecting data for selecting other of said banks;
data holding means mounted on said circuit board for holding bank selecting data, said data holding means having at least one data input terminal connected to at least one of said data lines, and having at least one output terminal; and conductive pattern means formed on said circuit board and connecting said at least one output terminal of said data holding means to a predetermined portion of said address terminals of said first memory; wherein said data holding means is loaded with bank selecting data that is read from said first memory in response to an enable signal for enabling said first memory and a read/write signal for accessing said first memory means both of which are received from said central processing unit, and said first memory includes means for reading out data stored in an address location that is addressed by said central processing unit in a bank that is selected by said bank selecting data that has been previously loaded into said data holding means.
6. A memory cartridge in accordance with claim 5 wherein character data is stored as display data in at least portions of the banks of said first memory that are not adapted to store bank selecting data, said main unit is a video game machine, and said character data is data corresponding to game characters.
7. A memory cartridge in accordance with claim 5, wherein a specific memory bank among said plurality of banks of said first memory is allocated to a first address space of said central processing unit and is accessible at all times by said central processing unit, said specific memory bank stores bank selecting data for the selection of a bank corresponding to a second address space accessible by said central processing unit, and said data holding means selects a bank of said first memory for said second address space based on said bank selecting data sent from said first memory.
8. A memory cartridge in accordance with claim 5, wherein said data holding means includes a semiconductor device which receives said bank selecting data from said first memory and sends a bank selection signal to said predetermined portion of said address terminals.
9. A memory cartridge in accordance with claim 5, wherein said data holding means includes gating means which, when provided with an alternate bank select signal by said central processing unit designating a specific bank in said first memory sends said alternate bank select signal to the most significant of said address terminals of said first memory and when not provided with said alternative bank select signal, sends the output of said holding means to the most significant of said address terminals of said first memory.
10. A memory cartridge attachable to and detachable from a main unit including a computer, said main unit having a data bus, address bus, and a central processing unit, said memory cartridge comprising:
a circuit board having address lines and data lines attachable to said address bus and said data bus, respectively, when said cartridge is attached to said main unit;
a first memory mounted on said circuit board, said first memory being non-volatile and having address terminals connected to said address lines and data terminals connected to said data lines, said first memory having a predetermined storage capacity and being divided into a plurality of banks, each of said banks having a plurality of address locations, at least one of said banks storing bank selecting data for selecting other of said banks; and data holding means for holding bank selecting data said data holding means being mounted on said circuit board, said data holding means having a plurality of input terminals and a plurality of output terminals, said plurality of input terminals being connected to at least certain of said data lines and said plurality of output terminals being connected to a predetermined portion of said address terminals which are used to select any one of said plurality of banks of said first memory;
said data holding means being loaded with bank selecting data read from said first memory in response to an enable signal for enabling said first memory and a read/write signal for accessing said first memory means, both of which are received from said central processing unit, such that said first memory is conditioned for reading data in an address being addressed by said central processing unit in a bank which is selected by said bank selecting data previously loaded into and held by said data holding means.
a circuit board having address lines and data lines attachable to said address bus and said data bus, respectively, when said cartridge is attached to said main unit;
a first memory mounted on said circuit board, said first memory being non-volatile and having address terminals connected to said address lines and data terminals connected to said data lines, said first memory having a predetermined storage capacity and being divided into a plurality of banks, each of said banks having a plurality of address locations, at least one of said banks storing bank selecting data for selecting other of said banks; and data holding means for holding bank selecting data said data holding means being mounted on said circuit board, said data holding means having a plurality of input terminals and a plurality of output terminals, said plurality of input terminals being connected to at least certain of said data lines and said plurality of output terminals being connected to a predetermined portion of said address terminals which are used to select any one of said plurality of banks of said first memory;
said data holding means being loaded with bank selecting data read from said first memory in response to an enable signal for enabling said first memory and a read/write signal for accessing said first memory means, both of which are received from said central processing unit, such that said first memory is conditioned for reading data in an address being addressed by said central processing unit in a bank which is selected by said bank selecting data previously loaded into and held by said data holding means.
11. A memory cartridge in accordance with claim 10, wherein a specific bank among said plurality of banks of said first memory is allocated to a first address space of said central processing unit and is accessible at all times by said central processing unit, said specific bank stores bank selecting data for the selection of a bank corresponding to a second address space accessible by said central processing unit, and said data holding means selects a bank of said first memory for said second address space based on said bank selecting data sent from said first memory.
12. A memory cartridge in accordance with claim 10, wherein character data is stored as display data in at least portions of the banks of said first memory that are not adapted to store bank selecting data, said computer main unit is a video game machine, and said character data is data corresponding to game characters.
13. A memory cartridge attachable to and detachable from a data processing apparatus, said data processing apparatus having first and second data buses, first and second address buses, a central processing unit having limited addressing capability and being connected to said first data bus and said first address bus, and a video processing unit connected to said second data bus and said second address bus, said memory cartridge comprising:
a circuit board having first and second data lines attachable to said first and second data buses, respectively, and having first and second address lines attachable to said first and second address buses, respectively;
a first memory mounted on said circuit board, said first memory being non-volatile and having address terminals connected to said first address lines and data terminals connected to said first data lines, said first memory having a predetermined addressable storage capacity exceeding that of the limited addressing capability of the central processing unit, said first memory being divided into a plurality of banks, each of said banks having a memory capacity less than the address space accessible by said first address bus, at least one of said banks storing program data, at least one of said address locations of one of said banks storing bank selecting data for selecting another of said banks;
a second memory connected to said second data lines and said second address lines, said second memory storing-character data for video processing;
data holding means mounted on said circuit board for holding bank selecting data, said data holding means having data input terminals connected to at least certain of said first data lines, and having data output terminals;
and conductive pattern means formed on said circuit board and connecting said output terminals of said data holding means to a predetermined portion of said address terminals which are used to select any one of said plurality of banks, wherein said data holding means is loaded with bank selecting data that is read from said first memory in response to an enable signal for enabling said first memory and a read/write signal for accessing said first memory means, both of which are received from said central processing unit, and said first memory reads out data stored in an address that is addressed by said central processing unit in a bank that is selected by said bank selecting data that has been previously loaded into said data holding means.
a circuit board having first and second data lines attachable to said first and second data buses, respectively, and having first and second address lines attachable to said first and second address buses, respectively;
a first memory mounted on said circuit board, said first memory being non-volatile and having address terminals connected to said first address lines and data terminals connected to said first data lines, said first memory having a predetermined addressable storage capacity exceeding that of the limited addressing capability of the central processing unit, said first memory being divided into a plurality of banks, each of said banks having a memory capacity less than the address space accessible by said first address bus, at least one of said banks storing program data, at least one of said address locations of one of said banks storing bank selecting data for selecting another of said banks;
a second memory connected to said second data lines and said second address lines, said second memory storing-character data for video processing;
data holding means mounted on said circuit board for holding bank selecting data, said data holding means having data input terminals connected to at least certain of said first data lines, and having data output terminals;
and conductive pattern means formed on said circuit board and connecting said output terminals of said data holding means to a predetermined portion of said address terminals which are used to select any one of said plurality of banks, wherein said data holding means is loaded with bank selecting data that is read from said first memory in response to an enable signal for enabling said first memory and a read/write signal for accessing said first memory means, both of which are received from said central processing unit, and said first memory reads out data stored in an address that is addressed by said central processing unit in a bank that is selected by said bank selecting data that has been previously loaded into said data holding means.
14. A memory cartridge in accordance with claim 13, wherein display data for forming a display screen, program data for executing a program, and command data for transferring said display data to said second memory are stored in at least one of said banks of said first memory.
15. A memory cartridge in accordance with claim 13, wherein said first memory includes a ROM, and said second memory includes a RAM.
16. A memory cartridge in accordance with claim 13, wherein a specific bank among said plurality of banks of said first memory is allocated to a first address space of said central processing unit and is accessible at all times by said central processing unit, said specific bank stores bank selecting data for the selection of a bank corresponding to a second address space accessible by said central processing unit, and said data holding means selects a bank of said first memory for said second address space according to said bank selecting data sent from said first memory.
17. A memory cartridge attachable to and detachable from a data processing apparatus, said data processing apparatus having first and second data buses, first and second address buses, a central processing unit of limited addressing capacity connected to said first data bus and said first address bus, and a video processing unit connected to said second data bus and said second address bus, said memory cartridge comprising:
a circuit board having first and second data lines attachable to said first and second data buses, respectively, and having first and second address lines attachable to said first and second address buses, respectively;
a first memory mounted on said circuit board, said first memory being non-volatile and having address terminals connected to said first address lines and data terminals connected to said first data line, said first memory having address space that is divided into a plurality of banks, said banks each having a plurality of address locations, each of said banks having a memory capacity less than the address space accessible by said first address bus, at least one of said banks storing program data, at least one of said address locations of at least one of said banks storing bank selecting data for selecting another of said banks;
a second memory connected to said second data lines and said second address lines, said second memory storing video character data which is used for video processing; and data holding means for holding bank selecting data, said data holding means mounted on said circuit board, said data holding means including a plurality of input terminals connected to at least certain of said first data lines, said data holding means including a plurality of output terminals connected to a predetermined portion of said address terminals of said first memory which are used to select any one of said plurality of banks, said data holding means holding the bank selecting data that is read from said first memory at a time when an enable signal received from said central processing unit enables said first memory and when a read/write signal received from said central processing unit for accessing said first memory means instructs said data holding means to load, such that said first memory is conditioned to read data in an address being addressed by said central processing unit in a bank which is selected by said bank selecting data held in said data holding means.
a circuit board having first and second data lines attachable to said first and second data buses, respectively, and having first and second address lines attachable to said first and second address buses, respectively;
a first memory mounted on said circuit board, said first memory being non-volatile and having address terminals connected to said first address lines and data terminals connected to said first data line, said first memory having address space that is divided into a plurality of banks, said banks each having a plurality of address locations, each of said banks having a memory capacity less than the address space accessible by said first address bus, at least one of said banks storing program data, at least one of said address locations of at least one of said banks storing bank selecting data for selecting another of said banks;
a second memory connected to said second data lines and said second address lines, said second memory storing video character data which is used for video processing; and data holding means for holding bank selecting data, said data holding means mounted on said circuit board, said data holding means including a plurality of input terminals connected to at least certain of said first data lines, said data holding means including a plurality of output terminals connected to a predetermined portion of said address terminals of said first memory which are used to select any one of said plurality of banks, said data holding means holding the bank selecting data that is read from said first memory at a time when an enable signal received from said central processing unit enables said first memory and when a read/write signal received from said central processing unit for accessing said first memory means instructs said data holding means to load, such that said first memory is conditioned to read data in an address being addressed by said central processing unit in a bank which is selected by said bank selecting data held in said data holding means.
18. A memory cartridge in accordance with claim 17, wherein a specific bank among said plurality of banks of said first memory is allocated to a first address space of said central processing unit and is accessible at all times by said central processing unit, said specific bank stores bank selecting data for the selection of a bank corresponding to a second address space accessible by said central processing unit, and said data holding means selects a bank of said first memory for said second address space based on said bank selecting data sent from said first memory.
19. A memory cartridge in accordance with claim 17, wherein said first memory includes a ROM, and said second memory includes a RAM.
20. A memory cartridge in accordance with claim 17, wherein said data holding means includes a semiconductor device that receives said bank selecting data from said first memory and sends a bank-switching signal to said predetermined portion of said address terminals.
21. A memory cartridge in accordance with claim 20, wherein said data holding means includes a gating means which, when provided with a signal by said central processing unit, sends this signal to the most significant of said address terminals of said first memory, and when not provided with this signal, sends the output of said holding means to the most significant of said address terminals of said first memory.
22. A memory cartridge in accordance with claim 17, wherein display data for forming a display screen, program data for executing a program, and command data for transferring said display data to said second memory are stored in at least one of said banks of said first memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP104175/1986 | 1986-05-06 | ||
| JP61104175A JPS62260244A (en) | 1986-05-06 | 1986-05-06 | Memory cartridge |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1301942C true CA1301942C (en) | 1992-05-26 |
Family
ID=14373685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000536489A Expired - Fee Related CA1301942C (en) | 1986-05-06 | 1987-05-06 | Memory cartridge |
Country Status (12)
| Country | Link |
|---|---|
| US (2) | US4926372A (en) |
| EP (1) | EP0246025B1 (en) |
| JP (1) | JPS62260244A (en) |
| KR (1) | KR930011784B1 (en) |
| CN (1) | CN1009970B (en) |
| AR (1) | AR241833A1 (en) |
| AU (2) | AU602141B2 (en) |
| BR (1) | BR8702303A (en) |
| CA (1) | CA1301942C (en) |
| DE (1) | DE3751852T2 (en) |
| MY (1) | MY104380A (en) |
| NO (1) | NO172914C (en) |
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-
1986
- 1986-05-06 JP JP61104175A patent/JPS62260244A/en active Granted
-
1987
- 1987-05-04 NO NO871847A patent/NO172914C/en unknown
- 1987-05-05 US US07/047,039 patent/US4926372A/en not_active Expired - Lifetime
- 1987-05-06 CN CN87103401A patent/CN1009970B/en not_active Expired
- 1987-05-06 AR AR87307485A patent/AR241833A1/en active
- 1987-05-06 AU AU72528/87A patent/AU602141B2/en not_active Ceased
- 1987-05-06 CA CA000536489A patent/CA1301942C/en not_active Expired - Fee Related
- 1987-05-06 DE DE3751852T patent/DE3751852T2/en not_active Expired - Fee Related
- 1987-05-06 BR BR8702303A patent/BR8702303A/en not_active IP Right Cessation
- 1987-05-06 EP EP87304050A patent/EP0246025B1/en not_active Expired - Lifetime
- 1987-05-06 KR KR1019870004420A patent/KR930011784B1/en not_active IP Right Cessation
-
1988
- 1988-12-30 MY MYPI88001603A patent/MY104380A/en unknown
-
1989
- 1989-12-29 US US07/459,323 patent/US4984193A/en not_active Expired - Lifetime
-
1990
- 1990-12-21 AU AU68352/90A patent/AU644394B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| BR8702303A (en) | 1988-02-17 |
| AU644394B2 (en) | 1993-12-09 |
| NO871847L (en) | 1987-11-09 |
| JPH0420492B2 (en) | 1992-04-03 |
| KR870011614A (en) | 1987-12-24 |
| US4926372A (en) | 1990-05-15 |
| CN87103401A (en) | 1987-11-25 |
| CN1009970B (en) | 1990-10-10 |
| NO172914B (en) | 1993-06-14 |
| EP0246025A3 (en) | 1989-07-26 |
| AU7252887A (en) | 1987-11-12 |
| AU602141B2 (en) | 1990-10-04 |
| KR930011784B1 (en) | 1993-12-21 |
| DE3751852D1 (en) | 1996-08-08 |
| AU6835290A (en) | 1991-03-14 |
| NO871847D0 (en) | 1987-05-04 |
| DE3751852T2 (en) | 1997-01-02 |
| MY104380A (en) | 1994-03-31 |
| NO172914C (en) | 1993-09-22 |
| AR241833A1 (en) | 1992-12-30 |
| US4984193A (en) | 1991-01-08 |
| JPS62260244A (en) | 1987-11-12 |
| EP0246025B1 (en) | 1996-07-03 |
| EP0246025A2 (en) | 1987-11-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |