CA1309495C - Method and system for correcting long bursts of consecutive errors - Google Patents
Method and system for correcting long bursts of consecutive errorsInfo
- Publication number
- CA1309495C CA1309495C CA000603836A CA603836A CA1309495C CA 1309495 C CA1309495 C CA 1309495C CA 000603836 A CA000603836 A CA 000603836A CA 603836 A CA603836 A CA 603836A CA 1309495 C CA1309495 C CA 1309495C
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- Canada
- Prior art keywords
- bytes
- errors
- parity
- syndromes
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1866—Error detection or correction; Testing, e.g. of drop-outs by interleaving
Abstract
ABSTRACT
A method is disclosed for correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise subblocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading.
A sequence of N sequential parity check bytes is written at the end of each block. After ECC syndromes are generated during reading, parity syndromes are generated by comparing parity check bytes computed from data bytes and check bytes as read with the parity check bytes as written. When a long-burst error occurs, a pointer points to the first of the N consecutive bytes in a block that could have been influenced by the error burst. After correcting correctable errors in all subblocks not affected by the N bytes identified by the pointer, and adjusting the parity syndromes for errors thus corrected, the adjusted parity syndromes are used to correct the errors in the N bytes indicated by the pointer. Unused ECC syndromes are then adjusted for errors corrected by the adjusted parity syndromes and used to correct all correctable errors then remaining.
A method is disclosed for correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise subblocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading.
A sequence of N sequential parity check bytes is written at the end of each block. After ECC syndromes are generated during reading, parity syndromes are generated by comparing parity check bytes computed from data bytes and check bytes as read with the parity check bytes as written. When a long-burst error occurs, a pointer points to the first of the N consecutive bytes in a block that could have been influenced by the error burst. After correcting correctable errors in all subblocks not affected by the N bytes identified by the pointer, and adjusting the parity syndromes for errors thus corrected, the adjusted parity syndromes are used to correct the errors in the N bytes indicated by the pointer. Unused ECC syndromes are then adjusted for errors corrected by the adjusted parity syndromes and used to correct all correctable errors then remaining.
Description
13~9~9~
NETE~OD ANl:~ SYSTE:M FOR CORRECTING
LONG BURSTS OF CONSECUTIVE ERRORS
This invention relates to a method and system for correcting multiple byte errors in data read from a magnetic medium in a count-key-data (CKD) or fi~ed block (FB) environment with inter-record gaps, and more particularly to a method and system capable of correcting conventional errors using two-level error correction code (ECC) syndromes and also correcting occasional long bursts of consecutive errors due to a major signal perturbation.
Background of the Invention It is known to correct conventional errors in data read from a magnetic medium by use of a pointer, and check bytes, and one or more parity checks. These error correction code (ECC) error detection and correction functions are carried out on both write and read operations. These methods for accomplishing the error correction vary, depending on where the error is, the correction capability available in the hardware, system error recovery procedures, and the like.
The IBM 3380 Models J and K disk files use a two-level ECC to correct errors and are capable of correcting any single burst error involving two successive bytes (16 bits) in each subblock read from the disk and any error involving four successive bytes (32 bits) in one of the subblock in a block. However, there are instances where the duration of a SA9-88-041 l ~
. .
.
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perturbation and resultant error burst may be 16 bytes or more. This is longer than that o~ a "conventional" error burst and typically so long that it will exceed the correction capability of the two-level ECC heretofore available without creating a very wasteful design.
While the IBM 3850 Mass Storage Device is capable of correcting long-burst errors in data read from a magnetic tape, the method and apparatus used are not capable of correcting both conventional and long-burst errors in a disk file using a two-level ECC.
There is a need for a method and system capable of correcting both conventional errors and long-burst errors of 16 or more consecutive bytes due to a major perturbation of the signal during reading of data from a magnetic medium, such as a magnetic disk.
Summary of the Invention Toward this end, and according to the invention, a method and system is disclosed capable of correcting not only conventional errors covered by the two-level ECC but also a long burst of up to N consecutive byte errors in a magnetic disk medium on which data is recorded in form of subblocks within a block of variable or fixed length. These blocks comprise data bytes and check bytes and include ECC
for which ECC syndromes are generated during reading. At the end of each block a sequence of N sequential parity check bytes is written. Then, during reading, after the 13~949~
generation of the ECC syndromes, parity syndromes are generated by comparing parity check bytes computed from the data bytes and check bytes as read with the parity check bytes as written. In response to a long-burst error, a s pointer is generated to the first of N consecutive bytes in a block that could have been in~luenced by the error. Then those ECC syndromes not dependent on the N bytes identified by the pointer are used to correct any correctable errors.
Following this, the parity syndromes are adjusted according lo to the errors thus corrected. The adjusted parity syndromes are then used to correct correctable errors in the N bytes indicated by the pointer. Any unused ECC syndromes are adjusted according to the errors thus corrected by the adjusted parity syndromes; whereupon the adjusted ECC
syndromes are used to correct all correctable errors then remaining.
Brief Description of the Drawings Fig. 1 illustrates a two-level ECC format to which the invention has been applied;
Fig. 2 illustrates how each parity byte is computed from the consecutive ordered sets of N (assume as 16) interleaved data bytes and check bytes in a subblock to form N parity groups; and Fig. 3 illustrates an embodiment of the logic for generating the parity bytes in writing and the parity byte syndromes in reading; and ~3~949~
Figs. 4A, 4B, 4C and 4D lllustrat~ various error conditions under which imaged errors are correctable.
Des~ription of Preferred Embodiment The method implementing the invention is shown applied to a two-level ECC system of the type disclosed in U.S.
Patents 4,525,838, 4,703,485 and 4,706,250 constituting improvements thereto. These patents disclose a two-level multibyte error correcting system operable to correct up to t1 errors in each subblock of a block of data and t2 errors in said block, where t2>t1.
In the two-level ECC system as described in U.S. Patent 4,706,250 and illustrated in Fig. 1, data is recorded in blocks of variable (or fixed) length each comprising a plurality of subblocks, preferably of the same length except possibly the last. Each subblock comprises a variable (or fixed) number of data bytes and six subblock check bytes S
for first level error correction. At the end of the last subblock in the block are four C~C bytes C for data integrity checking, followed by two block check bytes B for second level error correction.
According to the invention, a sequence of N parity check bytes P is written at the end of each block in the gap between it and the succeeding block; i.e. in the inter-block gap. The parity byte P0 immediately follows the last byte of the area; i.e., B1, the last block check byte. As ; illustrated in Fig. 2, these parity check bytes P make an ~3~9~9~
interleaved parity check across N consecutive ordered groups of data bytes, check bytes and CRC bytes; i.e., all bytes in each ordered group are N bytes apart, and all bytes in the block are counted in determining the displacement in the count/key/data (CKD) area to which the parity bytes are appended. The number N is preselected to equal the longest anticipated burst of consecutive errors so that no single long~burst error can affect more than one byte in any one of the N parity groups. As customary in parity checks, all bytes are exclusively OR'd ~XOR'd). As used in this specification and in the claims, the term "byte" is defined as comprising one or more bits.
A pointer is generated in response to an error burst of up to N consecutive bytes to indicate the first of N
consecutive bytes in a block that could have been affected by the long-burst. The pointer may be an after-the-fact indication. For example, if it could be sensed that a long-burst error had started no more than ten byte times earlier, then the appropriate earliest byte indication would be ten bytes previous to the byte being read at the time the error was sensed.
In Fig. 2, it is assumed for sake of illustration that N is 16, and that parity bytes P0 through Pl5 are therefore written in order immediately following the last byte (block check byte ~l) of the block. Thus, the parity group including P0 is the result of XOR'ing bytes D2, Dl8, SO of subblock X and Dlo and D26 of subblock Y; and the parity 1309~9~
group including P11 is the result of XOR'ing bytes D13, D29 of subblock X and D5, D21 of subblock Y and C1.
Fig. 3 depicts an exclusive OR gate (XOR) 20, a parity shift register 21 and multiplexers 22 and 23 each of which is one byte wide. Register 21 has a length of N stages (assumed, as already stated, as 16).
Assume initially that shift register 21 has been reset to zero in conventional manner. To write on a magnetic medium, multiplexers 22 and 23 are conditioned to connect Write Data line W to XOR 20 and gate all bytes BL of each block via Data In line DI and multiplexer 23 to the Output for writing on a selected track of a direct access storage device (not shown). Thus Data In includes all data bytes followed by appropriate check bytes through B1 as illustrated in Fig. 1. At the end of Data In, multiplexers 22 and 23 are conditioned to connect line ~ to XOR 20 and gate the N parity bytes P0 through P15 from the parity shift register 21 to the Output via line SR.
To read data from the magnetic medium and calculate the parity byte syndromes, multiplexers 22 and 23 are conditioned to connect Read Data line R to Data In line DI
and gate all bytes BL of each block to the Output via line DI. Thereupon, multiplexers 22 and 23 are conditioned to gate the N parity bytes P0 through P15 from line R to XOR 20 and gate the output of XOR 20 to the Output via line X.
The resultant output is the BL bytes of the block with the 16 parity byte syndromes appended.
In operation, assume that during reading, there are errors detected, but none are long-burst errors. Under this condition, error correction and veri~ication will be effected conventionally, as explained in the cited prior art using the subblock check, block check and CRC syndromes. At the subblock level up to t1 errors can be corrected and t1 +
c errors detected. Thereafter, at the block level, up to t2 errors are correctable in any one of the subblocks of the block.
If there are more errors than can be corrected, ~orrection is abandoned and the error is treated as uncorrectable. ~uch structure and mode of operation form no part of the present invention.
Note that in the absence of a long-burst error, the parity bytes need not be read. Hence, under normal conditions, with no long-burst error, preparations for processing the next block can be started without reading the parity bytes. Conventionally this processing is done as the read head passes over the inter-block gap - the area that is left unrecorded for this purpose. According to a feature of this invention the parity bytes will be recorded in this inter-block gap and will be read only if long-burst error recovery is required. Thus long-burst error protection is obtained without increasing the length of the medium required for the check bytes and the inter-block gap.
.
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Assume now that, during r~dlng, there are errors detected and that the pointer indieates a long-burst error.
Subbloek eheek, bloek check and CRC syndromes are calculated as in the absence of a long-burst error. Also, the parity bytes are read and the parity byte syndromes are calculated as deseribed above.
According to the invention, if the earliest byte at which the error could have started (and hence the earliest byte which could have been affected by the error) was at displacement Z (See Fig. 4A), then the following steps are performed:
(1) First level correetlon is applied, as neeessary, to all subhlocks which could not have been affected by the long-burst error; that is, subblocks which have no data or check bytes in the displacement range Z to Z+N.
This correction is done as described in the cited prior art.
NETE~OD ANl:~ SYSTE:M FOR CORRECTING
LONG BURSTS OF CONSECUTIVE ERRORS
This invention relates to a method and system for correcting multiple byte errors in data read from a magnetic medium in a count-key-data (CKD) or fi~ed block (FB) environment with inter-record gaps, and more particularly to a method and system capable of correcting conventional errors using two-level error correction code (ECC) syndromes and also correcting occasional long bursts of consecutive errors due to a major signal perturbation.
Background of the Invention It is known to correct conventional errors in data read from a magnetic medium by use of a pointer, and check bytes, and one or more parity checks. These error correction code (ECC) error detection and correction functions are carried out on both write and read operations. These methods for accomplishing the error correction vary, depending on where the error is, the correction capability available in the hardware, system error recovery procedures, and the like.
The IBM 3380 Models J and K disk files use a two-level ECC to correct errors and are capable of correcting any single burst error involving two successive bytes (16 bits) in each subblock read from the disk and any error involving four successive bytes (32 bits) in one of the subblock in a block. However, there are instances where the duration of a SA9-88-041 l ~
. .
.
1309~9~
perturbation and resultant error burst may be 16 bytes or more. This is longer than that o~ a "conventional" error burst and typically so long that it will exceed the correction capability of the two-level ECC heretofore available without creating a very wasteful design.
While the IBM 3850 Mass Storage Device is capable of correcting long-burst errors in data read from a magnetic tape, the method and apparatus used are not capable of correcting both conventional and long-burst errors in a disk file using a two-level ECC.
There is a need for a method and system capable of correcting both conventional errors and long-burst errors of 16 or more consecutive bytes due to a major perturbation of the signal during reading of data from a magnetic medium, such as a magnetic disk.
Summary of the Invention Toward this end, and according to the invention, a method and system is disclosed capable of correcting not only conventional errors covered by the two-level ECC but also a long burst of up to N consecutive byte errors in a magnetic disk medium on which data is recorded in form of subblocks within a block of variable or fixed length. These blocks comprise data bytes and check bytes and include ECC
for which ECC syndromes are generated during reading. At the end of each block a sequence of N sequential parity check bytes is written. Then, during reading, after the 13~949~
generation of the ECC syndromes, parity syndromes are generated by comparing parity check bytes computed from the data bytes and check bytes as read with the parity check bytes as written. In response to a long-burst error, a s pointer is generated to the first of N consecutive bytes in a block that could have been in~luenced by the error. Then those ECC syndromes not dependent on the N bytes identified by the pointer are used to correct any correctable errors.
Following this, the parity syndromes are adjusted according lo to the errors thus corrected. The adjusted parity syndromes are then used to correct correctable errors in the N bytes indicated by the pointer. Any unused ECC syndromes are adjusted according to the errors thus corrected by the adjusted parity syndromes; whereupon the adjusted ECC
syndromes are used to correct all correctable errors then remaining.
Brief Description of the Drawings Fig. 1 illustrates a two-level ECC format to which the invention has been applied;
Fig. 2 illustrates how each parity byte is computed from the consecutive ordered sets of N (assume as 16) interleaved data bytes and check bytes in a subblock to form N parity groups; and Fig. 3 illustrates an embodiment of the logic for generating the parity bytes in writing and the parity byte syndromes in reading; and ~3~949~
Figs. 4A, 4B, 4C and 4D lllustrat~ various error conditions under which imaged errors are correctable.
Des~ription of Preferred Embodiment The method implementing the invention is shown applied to a two-level ECC system of the type disclosed in U.S.
Patents 4,525,838, 4,703,485 and 4,706,250 constituting improvements thereto. These patents disclose a two-level multibyte error correcting system operable to correct up to t1 errors in each subblock of a block of data and t2 errors in said block, where t2>t1.
In the two-level ECC system as described in U.S. Patent 4,706,250 and illustrated in Fig. 1, data is recorded in blocks of variable (or fixed) length each comprising a plurality of subblocks, preferably of the same length except possibly the last. Each subblock comprises a variable (or fixed) number of data bytes and six subblock check bytes S
for first level error correction. At the end of the last subblock in the block are four C~C bytes C for data integrity checking, followed by two block check bytes B for second level error correction.
According to the invention, a sequence of N parity check bytes P is written at the end of each block in the gap between it and the succeeding block; i.e. in the inter-block gap. The parity byte P0 immediately follows the last byte of the area; i.e., B1, the last block check byte. As ; illustrated in Fig. 2, these parity check bytes P make an ~3~9~9~
interleaved parity check across N consecutive ordered groups of data bytes, check bytes and CRC bytes; i.e., all bytes in each ordered group are N bytes apart, and all bytes in the block are counted in determining the displacement in the count/key/data (CKD) area to which the parity bytes are appended. The number N is preselected to equal the longest anticipated burst of consecutive errors so that no single long~burst error can affect more than one byte in any one of the N parity groups. As customary in parity checks, all bytes are exclusively OR'd ~XOR'd). As used in this specification and in the claims, the term "byte" is defined as comprising one or more bits.
A pointer is generated in response to an error burst of up to N consecutive bytes to indicate the first of N
consecutive bytes in a block that could have been affected by the long-burst. The pointer may be an after-the-fact indication. For example, if it could be sensed that a long-burst error had started no more than ten byte times earlier, then the appropriate earliest byte indication would be ten bytes previous to the byte being read at the time the error was sensed.
In Fig. 2, it is assumed for sake of illustration that N is 16, and that parity bytes P0 through Pl5 are therefore written in order immediately following the last byte (block check byte ~l) of the block. Thus, the parity group including P0 is the result of XOR'ing bytes D2, Dl8, SO of subblock X and Dlo and D26 of subblock Y; and the parity 1309~9~
group including P11 is the result of XOR'ing bytes D13, D29 of subblock X and D5, D21 of subblock Y and C1.
Fig. 3 depicts an exclusive OR gate (XOR) 20, a parity shift register 21 and multiplexers 22 and 23 each of which is one byte wide. Register 21 has a length of N stages (assumed, as already stated, as 16).
Assume initially that shift register 21 has been reset to zero in conventional manner. To write on a magnetic medium, multiplexers 22 and 23 are conditioned to connect Write Data line W to XOR 20 and gate all bytes BL of each block via Data In line DI and multiplexer 23 to the Output for writing on a selected track of a direct access storage device (not shown). Thus Data In includes all data bytes followed by appropriate check bytes through B1 as illustrated in Fig. 1. At the end of Data In, multiplexers 22 and 23 are conditioned to connect line ~ to XOR 20 and gate the N parity bytes P0 through P15 from the parity shift register 21 to the Output via line SR.
To read data from the magnetic medium and calculate the parity byte syndromes, multiplexers 22 and 23 are conditioned to connect Read Data line R to Data In line DI
and gate all bytes BL of each block to the Output via line DI. Thereupon, multiplexers 22 and 23 are conditioned to gate the N parity bytes P0 through P15 from line R to XOR 20 and gate the output of XOR 20 to the Output via line X.
The resultant output is the BL bytes of the block with the 16 parity byte syndromes appended.
In operation, assume that during reading, there are errors detected, but none are long-burst errors. Under this condition, error correction and veri~ication will be effected conventionally, as explained in the cited prior art using the subblock check, block check and CRC syndromes. At the subblock level up to t1 errors can be corrected and t1 +
c errors detected. Thereafter, at the block level, up to t2 errors are correctable in any one of the subblocks of the block.
If there are more errors than can be corrected, ~orrection is abandoned and the error is treated as uncorrectable. ~uch structure and mode of operation form no part of the present invention.
Note that in the absence of a long-burst error, the parity bytes need not be read. Hence, under normal conditions, with no long-burst error, preparations for processing the next block can be started without reading the parity bytes. Conventionally this processing is done as the read head passes over the inter-block gap - the area that is left unrecorded for this purpose. According to a feature of this invention the parity bytes will be recorded in this inter-block gap and will be read only if long-burst error recovery is required. Thus long-burst error protection is obtained without increasing the length of the medium required for the check bytes and the inter-block gap.
.
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Assume now that, during r~dlng, there are errors detected and that the pointer indieates a long-burst error.
Subbloek eheek, bloek check and CRC syndromes are calculated as in the absence of a long-burst error. Also, the parity bytes are read and the parity byte syndromes are calculated as deseribed above.
According to the invention, if the earliest byte at which the error could have started (and hence the earliest byte which could have been affected by the error) was at displacement Z (See Fig. 4A), then the following steps are performed:
(1) First level correetlon is applied, as neeessary, to all subhlocks which could not have been affected by the long-burst error; that is, subblocks which have no data or check bytes in the displacement range Z to Z+N.
This correction is done as described in the cited prior art.
(2) Since the CRC and block check byte syndromes have been calculated from erroneous data, they need to be adjusted for each first level correction thus made.
This adjustment is described in the cited prior art.
Since the parity byte syndromes have also been calculated from erroneous data, they need to be adjusted for each first level correction thus made.
This adjustment is done by XOR'ing the error pattern for each byte corrected into the parity byte syndrome . . ... ~ ~ ., ~ . .
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for the parity group to which the corrected hyte belongs.
This adjustment is described in the cited prior art.
Since the parity byte syndromes have also been calculated from erroneous data, they need to be adjusted for each first level correction thus made.
This adjustment is done by XOR'ing the error pattern for each byte corrected into the parity byte syndrome . . ... ~ ~ ., ~ . .
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for the parity group to which the corrected hyte belongs.
(3) Next, long-burst errors are corrected as follows:
The parity byte syndromes are overlaid on the data bytes and check bytes covering the N bytes ~ollowing the byte at displacement Z. This range of displacements is referred to as the parity overlay range OR (Fig. 4A), and is N bytes in length. Each byte in this range is corrected by XORing the lQ corresponding overlaid parity byte syndrome.
Appropriate subblock check byte, block check byte and CRC syndromes are adjusted for these changes in the same way that they were adjusted for changes resulting from first level error correction.
(4~ Next, the long-burst-affected subblocks are processed through the two-level ECC algorithm. Note that any conventional errors in these subblocks outside the parity overlay range have contributed to the parity byte syndromes. When the parity byte syndromes were overlaid in step 3, these errors in the parity byte syndromes created errors in the parity overlay r~nge OR
as images of the conventional errors. Figs. 4A-4D
illustrate various error conditions under which imaged errors are correctable:
Fig. 4A shows a conventional error e in the affected subblock which b~comes a parity error in the corresponding parity group and becomes an ......
130949~
image error e' in the long burst area in the overlay range OR. This error pair, the conventional error e and its image error e' in the same subblock, is correctable by second level decoding in the two-level ECC.
Fig. 4B shows the case where the conventional error e and its image error e' appear in adjacent subblocks. In this case the error pair is corrected by the first-level processing of the two adjacent subblocks.
Fig. 4C shows the case where conventional errors el and e'2 in the parity bytes appear as image errors e'l and e'2 in the same subblock. These errors are corrected by decoding the affected subblock through second level correction.
Fig. 4D shows the case where conventional errors el and e2 in the parity bytes appear as image errors e'l and e'2 in adjacent subblocks. These errors are corrected by decoding the affected subblocks through first level correction.
In operation, first-level correction as described above is applied iteratively to the long-burst-affected subblocks until each has been corrected or found SA9-88-041 l0 non-eorreetable at ~irst level. If one sub~loek remains uncorrected a~ter this processing, the block check bytes ean be used and seeond level correetion applied as deseribed in the cited prior art.
(51 After all eorrections are applied, the correction is verified from the eondition of the adjusted CRC
syndromes as described in the eited prior art.
The error-correcting capability of the algorithm in this invention ean be generally summarized as follows:
A. When lons-burst error eorrection is not required, the correetion capability of the two-level code is unaffected.
B. When long-burst error eorreetion is required, the errors ean be corrected provided that all of the following eonditions are satisfied:
(i) The long-burst is not longer than the parity byte overlay range.
(ii) The eonventional errors in each subbloek are within the first level capability of the two-level ECC.
(iii) If the long-burst error affects more than one subbloek, only one of these long-burst-affected subbloeks has conventional errors.
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(iv) If the parlty bytes are affected by conventional errors, the long-burst-affected subblocks do not have any conventional errors.
Note that N may exceed the length of one subblock without impairing correction capability.
It should also be noted that the two-level ECC
structure disclosed in the cited patents could be restructured to provide N-way (instead of two-way~
interleaving of codewords; but, using this approach, the cost to enable correction of up to N consecutive bytes in error in a long-burst error would be prohibitive. With applicants' method and system, however, which involves appending the N parity bytes, up to N consecutive bytes in error can be corrected more cheaply and expeditiously; and the selected value of N can be increased without significant increase in complexity and cost.
While the invention has been described in connection with a preferred embodiment thereof, it will be understood that the foregoing and other changes may be made in the method and system herein disclosed. The embodiment illustrated is therefore to be considered merely illustrative and the invention is not to be considered limited except as specified in the claims.
The parity byte syndromes are overlaid on the data bytes and check bytes covering the N bytes ~ollowing the byte at displacement Z. This range of displacements is referred to as the parity overlay range OR (Fig. 4A), and is N bytes in length. Each byte in this range is corrected by XORing the lQ corresponding overlaid parity byte syndrome.
Appropriate subblock check byte, block check byte and CRC syndromes are adjusted for these changes in the same way that they were adjusted for changes resulting from first level error correction.
(4~ Next, the long-burst-affected subblocks are processed through the two-level ECC algorithm. Note that any conventional errors in these subblocks outside the parity overlay range have contributed to the parity byte syndromes. When the parity byte syndromes were overlaid in step 3, these errors in the parity byte syndromes created errors in the parity overlay r~nge OR
as images of the conventional errors. Figs. 4A-4D
illustrate various error conditions under which imaged errors are correctable:
Fig. 4A shows a conventional error e in the affected subblock which b~comes a parity error in the corresponding parity group and becomes an ......
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image error e' in the long burst area in the overlay range OR. This error pair, the conventional error e and its image error e' in the same subblock, is correctable by second level decoding in the two-level ECC.
Fig. 4B shows the case where the conventional error e and its image error e' appear in adjacent subblocks. In this case the error pair is corrected by the first-level processing of the two adjacent subblocks.
Fig. 4C shows the case where conventional errors el and e'2 in the parity bytes appear as image errors e'l and e'2 in the same subblock. These errors are corrected by decoding the affected subblock through second level correction.
Fig. 4D shows the case where conventional errors el and e2 in the parity bytes appear as image errors e'l and e'2 in adjacent subblocks. These errors are corrected by decoding the affected subblocks through first level correction.
In operation, first-level correction as described above is applied iteratively to the long-burst-affected subblocks until each has been corrected or found SA9-88-041 l0 non-eorreetable at ~irst level. If one sub~loek remains uncorrected a~ter this processing, the block check bytes ean be used and seeond level correetion applied as deseribed in the cited prior art.
(51 After all eorrections are applied, the correction is verified from the eondition of the adjusted CRC
syndromes as described in the eited prior art.
The error-correcting capability of the algorithm in this invention ean be generally summarized as follows:
A. When lons-burst error eorrection is not required, the correetion capability of the two-level code is unaffected.
B. When long-burst error eorreetion is required, the errors ean be corrected provided that all of the following eonditions are satisfied:
(i) The long-burst is not longer than the parity byte overlay range.
(ii) The eonventional errors in each subbloek are within the first level capability of the two-level ECC.
(iii) If the long-burst error affects more than one subbloek, only one of these long-burst-affected subbloeks has conventional errors.
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(iv) If the parlty bytes are affected by conventional errors, the long-burst-affected subblocks do not have any conventional errors.
Note that N may exceed the length of one subblock without impairing correction capability.
It should also be noted that the two-level ECC
structure disclosed in the cited patents could be restructured to provide N-way (instead of two-way~
interleaving of codewords; but, using this approach, the cost to enable correction of up to N consecutive bytes in error in a long-burst error would be prohibitive. With applicants' method and system, however, which involves appending the N parity bytes, up to N consecutive bytes in error can be corrected more cheaply and expeditiously; and the selected value of N can be increased without significant increase in complexity and cost.
While the invention has been described in connection with a preferred embodiment thereof, it will be understood that the foregoing and other changes may be made in the method and system herein disclosed. The embodiment illustrated is therefore to be considered merely illustrative and the invention is not to be considered limited except as specified in the claims.
Claims (11)
1. A method of correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise subblocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading, said method comprising the steps of:
writing at the end of each block a sequence of N
sequential parity check bytes;
during reading, after the generation of the ECC
syndromes, generating parity syndromes by comparing the parity check bytes computed from the data bytes and check bytes as read with the parity check bytes as written;
in response to a long-burst error condition, generating a pointer to the first of the N consecutive bytes in a block that could have been influenced by the error burst;
using any ECC syndromes which are not affected by the N
bytes identified by the pointer, correcting correctable errors in all subblocks not affected by these identified bytes;
adjusting the parity syndromes according to the errors thus corrected;
using the adjusted parity syndromes, correcting the errors in the N bytes indicated by the pointer;
adjusting any unused ECC syndromes according to the errors corrected by the adjusted parity syndromes; and using the adjusted ECC syndromes, correcting all correctable errors then remaining.
writing at the end of each block a sequence of N
sequential parity check bytes;
during reading, after the generation of the ECC
syndromes, generating parity syndromes by comparing the parity check bytes computed from the data bytes and check bytes as read with the parity check bytes as written;
in response to a long-burst error condition, generating a pointer to the first of the N consecutive bytes in a block that could have been influenced by the error burst;
using any ECC syndromes which are not affected by the N
bytes identified by the pointer, correcting correctable errors in all subblocks not affected by these identified bytes;
adjusting the parity syndromes according to the errors thus corrected;
using the adjusted parity syndromes, correcting the errors in the N bytes indicated by the pointer;
adjusting any unused ECC syndromes according to the errors corrected by the adjusted parity syndromes; and using the adjusted ECC syndromes, correcting all correctable errors then remaining.
2. The method of claim 1, wherein the parity bytes make an interleaved parity check across consecutive ordered groups of N data bytes and check bytes.
3. The method of claim 1, wherein said condition is a long-burst error not exceeding N bytes.
4. The method of claim 1, wherein the blocks are of variable length and comprise a variable number of data bytes and a preselected number of check bytes.
5. The method of claim 1, wherein the parity bytes are written in the gap between adjacent blocks.
6. The method of claim 1, wherein N may exceed the total number of bytes in a subblock.
7. A method of correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise subblocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading, said method being operable to correct up to a preselected number of errors in each subblock during processing at a first level of error correction and additional errors in each block during processing at a second level of error correction, said method comprising the steps of:
writing at the end of each block a sequence of N
sequential parity check bytes to create N parity groups from interleaved data bytes and check bytes;
during reading, after the generation of the ECC
syndromes, generating during first level correction parity syndromes by comparing the parity check bytes computed from the data bytes and check bytes as read with the parity check bytes as written;
in response to a long-burst error condition, generating a pointer to the first of the N consecutive bytes in a block that could have been influenced by the error burst;
using any ECC syndromes which are not dependent on the N bytes identified by the pointer, correcting any correctable errors during first level correction;
adjusting the parity syndromes according to the errors thus corrected;
using the adjusted parity syndromes, correcting the long-burst errors in the N bytes indicated by the pointer;
adjusting any unused first level ECC syndromes according to the errors corrected by the adjusted parity syndromes; and using the adjusted first level ECC syndromes, correcting all first level correctable errors;
adjusting second level ECC syndromes for all errors thus far corrected; and using the adjusted second level ECC syndromes, correcting all correctable errors then remaining.
writing at the end of each block a sequence of N
sequential parity check bytes to create N parity groups from interleaved data bytes and check bytes;
during reading, after the generation of the ECC
syndromes, generating during first level correction parity syndromes by comparing the parity check bytes computed from the data bytes and check bytes as read with the parity check bytes as written;
in response to a long-burst error condition, generating a pointer to the first of the N consecutive bytes in a block that could have been influenced by the error burst;
using any ECC syndromes which are not dependent on the N bytes identified by the pointer, correcting any correctable errors during first level correction;
adjusting the parity syndromes according to the errors thus corrected;
using the adjusted parity syndromes, correcting the long-burst errors in the N bytes indicated by the pointer;
adjusting any unused first level ECC syndromes according to the errors corrected by the adjusted parity syndromes; and using the adjusted first level ECC syndromes, correcting all first level correctable errors;
adjusting second level ECC syndromes for all errors thus far corrected; and using the adjusted second level ECC syndromes, correcting all correctable errors then remaining.
8. The method of claim 7, including the step of:
responsive to a conventional error in one of the subblocks that results in a parity error in the corresponding parity group that in turn results in an image error in that parity overlay range N bytes in length as measured from the earliest byte which could have been affected by the conventional error, correcting said conventional error and its image error by decoding during second-level correction.
responsive to a conventional error in one of the subblocks that results in a parity error in the corresponding parity group that in turn results in an image error in that parity overlay range N bytes in length as measured from the earliest byte which could have been affected by the conventional error, correcting said conventional error and its image error by decoding during second-level correction.
9. The method of claim 7, including the step of:
responsive to a conventional error and its image error in adjacent subblocks, correcting both errors by first-level correction of said adjacent subblocks.
responsive to a conventional error and its image error in adjacent subblocks, correcting both errors by first-level correction of said adjacent subblocks.
10. The method of claim 7, including the step of:
responsive to two conventional errors in the parity bytes that create corresponding image errors in adjacent subblocks, correcting the errors by first level correction of said adjacent subblocks.
responsive to two conventional errors in the parity bytes that create corresponding image errors in adjacent subblocks, correcting the errors by first level correction of said adjacent subblocks.
11. The method of claim 7, including the steps of:
responsive to two conventional errors in the parity bytes that create corresponding image errors in the same subblock, correcting the errors by decoding during second-level correction.
responsive to two conventional errors in the parity bytes that create corresponding image errors in the same subblock, correcting the errors by decoding during second-level correction.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/247,461 | 1988-09-21 | ||
| US07/247,461 US4916701A (en) | 1988-09-21 | 1988-09-21 | Method and system for correcting long bursts of consecutive errors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1309495C true CA1309495C (en) | 1992-10-27 |
Family
ID=22935027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000603836A Expired - Fee Related CA1309495C (en) | 1988-09-21 | 1989-06-23 | Method and system for correcting long bursts of consecutive errors |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4916701A (en) |
| EP (1) | EP0360424B1 (en) |
| JP (1) | JPH0831805B2 (en) |
| KR (1) | KR920006998B1 (en) |
| CN (1) | CN1011268B (en) |
| AU (1) | AU616788B2 (en) |
| BR (1) | BR8904735A (en) |
| CA (1) | CA1309495C (en) |
| DE (1) | DE68920523T2 (en) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03198544A (en) * | 1989-12-27 | 1991-08-29 | Nec Corp | Parity count circuit |
| JP2770611B2 (en) * | 1991-07-17 | 1998-07-02 | 日本電気株式会社 | Data error retry circuit |
| US5623507A (en) * | 1991-09-13 | 1997-04-22 | Storage Technology Corporation | Error pointers for enhanced error correction |
| JP2721099B2 (en) * | 1991-12-18 | 1998-03-04 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Trial and error method for error burst correction and multibyte error correction method |
| JP3259323B2 (en) * | 1992-04-13 | 2002-02-25 | ソニー株式会社 | De-interleave circuit |
| US5329535A (en) * | 1992-04-30 | 1994-07-12 | International Business Machines Corporation | Variable block lengths on-the-fly error correcting decoder |
| JP3520576B2 (en) * | 1994-10-24 | 2004-04-19 | ソニー株式会社 | Error correction method |
| US5497111A (en) * | 1994-12-22 | 1996-03-05 | International Business Machines Corporation | Peak detection circuit for suppressing magnetoresistive thermal asperity transients in a data channel |
| CN1105421C (en) * | 1995-04-03 | 2003-04-09 | 松下电器产业株式会社 | Data transmission system, data recording and reproducing apparatus and recording medium each having data structure of error correcting code |
| DE19614701A1 (en) * | 1996-04-15 | 1997-10-16 | Bosch Gmbh Robert | Method for the transmission of coded data |
| US6219814B1 (en) | 1996-12-23 | 2001-04-17 | International Business Machines Corporation | Method and apparatus for selectively varying error correcting code (ECC) power in a direct access storage device (DASD) |
| JP3104646B2 (en) * | 1997-06-04 | 2000-10-30 | ソニー株式会社 | External storage device |
| US6003144A (en) * | 1997-06-30 | 1999-12-14 | Compaq Computer Corporation | Error detection and correction |
| US6275965B1 (en) * | 1997-11-17 | 2001-08-14 | International Business Machines Corporation | Method and apparatus for efficient error detection and correction in long byte strings using generalized, integrated, interleaved reed-solomon codewords |
| JP2000148408A (en) * | 1998-11-17 | 2000-05-30 | Nec Corp | Circuit, system, and method for checking data of magnetic disk drive |
| JP2002027782A (en) | 2000-07-10 | 2002-01-25 | Sony Corp | Sensorless motor drive system |
| JP4174967B2 (en) * | 2000-12-18 | 2008-11-05 | 船井電機株式会社 | Recording method of write once optical disc |
| US7013422B2 (en) * | 2001-06-15 | 2006-03-14 | International Business Machines Corporation | Noise removal in multibyte text encodings using statistical models |
| US6891690B2 (en) * | 2002-11-20 | 2005-05-10 | International Business Machines Corporation | On-drive integrated sector format raid error correction code system and method |
| KR101300810B1 (en) * | 2006-04-03 | 2013-08-26 | 삼성전자주식회사 | Method and apparatus for encoding and decoding data, storage medium and storage medium driving system thereof |
| DE112006003922T5 (en) * | 2006-06-28 | 2009-04-30 | Intel Corporation, Santa Clara | Modification in a meggit decoder for error correction methods in bursts |
| US7721140B2 (en) * | 2007-01-02 | 2010-05-18 | International Business Machines Corporation | Systems and methods for improving serviceability of a memory system |
| EP2009828B1 (en) * | 2007-06-28 | 2016-01-27 | Alcatel Lucent | Method for providing unequal error protection to data packets in a burst transmission system |
| US8289640B2 (en) | 2008-08-11 | 2012-10-16 | International Business Machines Corporation | Error burst detection and amelioration |
| US8717698B2 (en) | 2011-10-12 | 2014-05-06 | International Business Machines Corporation | Hierarchical control of tiered error recovery for storage devices |
| CN103809147A (en) * | 2012-11-12 | 2014-05-21 | 苏州工业园区新宏博通讯科技有限公司 | AC ammeter fault self diagnosis method |
| US9148176B2 (en) | 2013-06-24 | 2015-09-29 | Micron Technology, Inc. | Circuits, apparatuses, and methods for correcting data errors |
| CN107203436B (en) * | 2017-05-25 | 2021-04-06 | 郑州云海信息技术有限公司 | Method and device for data verification of Nand Flash |
| US11886295B2 (en) | 2022-01-31 | 2024-01-30 | Pure Storage, Inc. | Intra-block error correction |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2485237B1 (en) * | 1980-06-19 | 1987-08-07 | Thomson Csf | DEVICE FOR CORRECTING, IN REAL TIME, ERRORS ON DATA RECORDED ON A MAGNETIC MEDIUM, AND DATA PROCESSING SYSTEM COMPRISING SUCH A DEVICE |
| JPS5735444A (en) * | 1980-08-12 | 1982-02-26 | Sony Corp | Pcm signal transmission method |
| US4525838A (en) * | 1983-02-28 | 1985-06-25 | International Business Machines Corporation | Multibyte error correcting system involving a two-level code structure |
| US4706250A (en) * | 1985-09-27 | 1987-11-10 | International Business Machines Corporation | Method and apparatus for correcting multibyte errors having improved two-level code structure |
| JPS62120670A (en) * | 1985-11-20 | 1987-06-01 | Sony Corp | Method for correcting error of data |
| US4703485A (en) * | 1986-02-10 | 1987-10-27 | International Business Machines Corporation | Method and apparatus for computing and implementing error detection check bytes |
| JPS62234426A (en) * | 1986-04-04 | 1987-10-14 | Sony Corp | Error correction method |
| NL8601446A (en) * | 1986-06-05 | 1988-01-04 | Philips Nv | METHOD AND DEVICE FOR DECODING A BLOCK OF CODE SYMBOLS DIVIDED IN TWO WAYS OF CODEWORDS EACH PROTECTED BY A MINIMUM REMOTE SAVABLE CODE. |
| JP2605271B2 (en) * | 1987-02-10 | 1997-04-30 | ソニー株式会社 | Error correction and checking device |
-
1988
- 1988-09-21 US US07/247,461 patent/US4916701A/en not_active Expired - Lifetime
-
1989
- 1989-06-23 CA CA000603836A patent/CA1309495C/en not_active Expired - Fee Related
- 1989-08-03 AU AU39282/89A patent/AU616788B2/en not_active Ceased
- 1989-08-18 JP JP1211542A patent/JPH0831805B2/en not_active Expired - Fee Related
- 1989-08-24 EP EP89308569A patent/EP0360424B1/en not_active Expired - Lifetime
- 1989-08-24 DE DE68920523T patent/DE68920523T2/en not_active Expired - Fee Related
- 1989-09-08 KR KR1019890012988A patent/KR920006998B1/en not_active IP Right Cessation
- 1989-09-08 CN CN89106994A patent/CN1011268B/en not_active Expired
- 1989-09-20 BR BR898904735A patent/BR8904735A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CN1011268B (en) | 1991-01-16 |
| DE68920523D1 (en) | 1995-02-23 |
| US4916701A (en) | 1990-04-10 |
| JPH0295029A (en) | 1990-04-05 |
| EP0360424B1 (en) | 1995-01-11 |
| AU616788B2 (en) | 1991-11-07 |
| AU3928289A (en) | 1990-03-29 |
| EP0360424A2 (en) | 1990-03-28 |
| CN1041463A (en) | 1990-04-18 |
| BR8904735A (en) | 1990-05-01 |
| DE68920523T2 (en) | 1995-07-20 |
| JPH0831805B2 (en) | 1996-03-27 |
| EP0360424A3 (en) | 1991-10-16 |
| KR900005292A (en) | 1990-04-13 |
| KR920006998B1 (en) | 1992-08-24 |
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