CA1323928C - 5-transistor memory cell with known state on power-up - Google Patents
5-transistor memory cell with known state on power-upInfo
- Publication number
- CA1323928C CA1323928C CA000595793A CA595793A CA1323928C CA 1323928 C CA1323928 C CA 1323928C CA 000595793 A CA000595793 A CA 000595793A CA 595793 A CA595793 A CA 595793A CA 1323928 C CA1323928 C CA 1323928C
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- Prior art keywords
- transistor
- channel
- memory circuit
- source
- drain
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Abstract
WITH KNOWN STATE ON POWER-UP
Hung-Cheng Hsieh ABSTRACT
A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation.
Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.
Hung-Cheng Hsieh ABSTRACT
A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation.
Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.
Description
~23928 A 5-TRANSISTOR HEMO~Y C~LL
~` WITH KNOWN STATE 0~ POWER-UP
- Hung-Cheng Hsieh - This application relates to U.S. Patent ~,750,155 issued June 7, 1988.
FIELD OF THE INVE~TION
.
~ This invention relates ko a static memory cell and in ., particular to a five-transistor memory cell which can be reliably read and written.
. 10 BACKGROUND
;, Figure 4 shows a prior art 6 transistor CMOS memory cell similar to the Intel 5101 cell. Transistors T'l, T'2, T'3 and T'4 .~
'~ constitute a cross-coupled latch that typically draws a steady ;~ state currenk of approximately one nanoampere. Transistors T'5 and T' are gating devices (pass transistors) that couple the bit ~' 6 lines (data lines) to the latch when the voltage on the row select line (address line) is high (5 volts). The output signal Q is a .
logical 1 when N channel enhancement mode transistor T'3 is off and P channel enhancement mode transistor T'4 is on, and it is a logical zero when these s~ates are reversed. Reading and writing .
~ are accomplished through the left and right blt llnes. For t~-; example to read the data out of the memory cell in Figure 4, a .....
high signal ls applied to the row select, turning on transistors T'5 and T'6. If a logical O (O volts) is on node A and a loyical 1 (5 volts) is on node B, the left bit line is charged to a lower level than the right bit line. These two bit lines are typically connected to a differential amplifier (not shown) that amplifies ,.'.1 .,,j ~
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` ~323928 ~he difference ln voltage levels on the bit line~. The amplified di~ference is then interpreted as a logical O or a logical 1, according to some design convention.
To write a bit into the memory cell, the row select line . is brought hlgh (to 5 volts) and the left and right bit .
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13~3~28 lines are charged to opposi~e sta~es by t~.e write drlver ~not shown in Fig. 4), which drlves node A to the sa~e logic level as the le~t bit line and node ~ to the same logic level as the right bit line.
The ~ix transistor memory cell requires two ga~ing devices ~pass transi~tors1 and two bit lines to be reliably read and written. Note that the six transistor memory cell can als~ be implemented in NMOS. See ~olt, Electronic Circuits, John Wiley and S0~5, Inc., pp. 293-294 ~1978)o .
:
SUMM~RY 0~ T~E INVENTION
.
- In contrast to the prior art, the present invention describes a five transi~tor memory cell which can be reliably read and written from a single data line. The memory cell includes a first and a second inverter with the ` output of ~he ~irst inverter connected to the input o~ the ,. second inverter and the output of the second inverter .5 connected to the input of the ~irst inverter and only a i................. single gating ~passl transistor which 1s connected between '~1 the lnput lead of the first inverter and the single bit ^~ line.
.. ~. In one embodiment of the invention the memory cell also :^
,~ includes a Eirst and a second output node llead) which :~ eontinuously provides the 6tate of the memory cell to ~ circuitry external to the memory/ for example to control the .~, gates of external p~ss transistors or to provide an input ignal to a logic gate.
.i Typically a plurality of fiYe tran~istor memory cells are connected to the same data line. As one feature of the invention, means are provided for increasing the rise time on the gate of the pass transistor in order to reduce the ; possibility of disturbing the content of the memory cell ,lj during the read operation. A5 another feature of the invPntion, the trigger point of the first inverter is ... . .
selected to be more than one thre~hold voltage wi~h body ~ effect below the voltage applied to the gate of the pas~
; transistor and channel dimensions of the pass tran~istor .,;~
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relative to channel dimensions of the N channel and P channel i- transistors in the second inverter are selected to insure that the me~nory cell can be successfully written.
In another embodiment, cir~uitry is provided for precharging the data line to a first selected voltage level prior to reading a stored bit in order to reduce read disturbance.
In another embodiment circuitry is provided for charginy the gate of the pass transistor to a first level during the read operation and to a second level during the write operation and for precharging the data line to a third selected voltage level prior to the read operation. The voltage levels are selected to minimize read disturbance.
~, According to a broad aspect of the invention there is .~
`~i- provided a memory circuit comprising:
~, a first inverter having an input lead and an output lead;
a second inverter having an input lead connected to said output lead of said first inverter and havlng an output lead; and one and only one pass transistor, said pass transistor having a first source~drain, a second source/drain, and a control gate, said second sourcetdrain being connected to said input lead of said first inverter and to said output lead of said second inverter;
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said first inverter comprising a first P channel enhancement mode transistor having a source and a drain, and a first N channel enhancement mode transistor having a source and a drain, said source of said first P channel transistor for connscting to a first voltage supply, said drain of said first P channel -~ transistor being connected to said drain of said first N channel ~, 3 ~, :., ,, ~ , ~, : -. . :
... ~ . ., .. : .
transistor, said source of said first N channel transistor for .~ being connected to a second voltage supply having a voltage lower than said first voltacJe supply; and :
said second inverter comprising a second P channe . enhancement mode transistor having a source and a drain, and a second N channel enhancement mode transistor having a source and a drain, said source of said second P channel enhancement mode transistor for being connected to said first voltage supply, said drain of said second P channel enhancament mode transistor being connected to said drain of said second N channel enhancement mode ; transistor, said source of said second N channel enhancement mode transistor for being connected to said second voltage supply; and :~ wherein a threshold voltage of said first P channel ..
enhancement mode transistor is sufficiently higher than a threshold voltage of said second P channel transistor khat upon ~, power-up of said memory circuit said first P channel transistor remains in an off-state and said second P channel transistor ,;~ assumes an on-state, thereby causing said memory circuit to ::s provide a logical 1 at said output lead of said second inverter at . 20 completion of power-up.
; According to another broad aspect of the invention there ~`1 ., is provided a memory circuit comprising:
~ a first inverter having an input lead and an output lead;
a second inverter having an input lead connected to said output lead of said first inverter and having an output lead; and one and only one pass transistor, said pass transiskor having a first source/drain, a second source~drain, and a control gate, said second source/drain being connected to said input lead of . ~ .
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. said first inverter and to said output lead of said second . .
. inverter;
~ said first inverter comprising a first P channel enhancement ~. mode transistor having a source and a dra.in, and a first N channel .:. enhancement mode kransistor having a source and a drain, said source of said first P channel transistor for connecting to a . first voltage supply, said drain of said first P channel transistor being connected to said drain of said first N channel ` transistor, said source of said first N channel transistor for ; 10 being connected to a second voltage supply having a voltage lower ,.
than said first voltage supply;
.~ said second inverter comprising a second P channel . enhancement mode transistor having a source and a drain, and a ~ second N channel enhancement mode transistor having a source and a -~ drain, said source of said second P channel enhancement mode -., transistor for being connected to said first voltage supply, said -j drain of said second P channel enhancement mode transistor being connected to said drain of said second N channel enhancement mode ~ '1 ;~3 ~:. transistor, said source of said second N channel enhancement mode ,.j transistor for being connected to said second voltage supply; and .~ wherein a threshold voltage of said first P channel .. ~j; transistor is sufficiently lower than a threshold voltaye of said `''`i!
second P channel transistor that upon power-up of said memory ~:~ circuit said first P channel transistor assumes an on-state and ,:, ~ said second P channel transistor remains in an off-state, thereby .'~ Jj causing said memory circuit to provide a loyical 0 at said output 1 lead of said second inverter at completion of power-up.
.~i il According to another broad aspect of the invention there ~ 3b , .~ . .
: ~ .. : -i ~ , . . : ~ . , :, . , . , ,, ~ .
, ,, ~ ~ . , : , :: . : .
1323~2~
is provided a memory ~ir~uit comprising:
a first memory transistor and a second memory transistor;
a first load transistor and a second load transistor;
each of said memory and load transistors having a gate, a sour~e, and a drain, means for connecting said drain of said first memory ! transistor~ said drain of sald first load transistor, and said gate of said second memory transistor together;
means for connecting said drain of said second memory transistor, said drain of said second load transistor, and said gate of said first memory transistor together;
means for connecting said gates of said first and second load ~: transistors to a first voltage supply;
means for connecting said sources of said first and second load transistors to a second voltage supply;
-~ means for connecting said sources of said first and second memory transistors to a third voltage supply;
:~ wherein said first load transistor has a threshold voltage sufficiently lower than a threshold voltage of said second load transistor that upon power-up said drain of said first memory `j transistor provides a logical one and said drain of said second `~i memory transistor provides a logical zero.
The invention will be more readily understood by ~i! reference to the drawings and the detailed description.
8RIEF D~SCRIPTION OF TH~ DRAWINGS
Figure 1 shows a fiYe transistor memory cell according to ~he present invention.
, Figure 2 shows a circui~ for precharging the data line i 3c : I
,, . ~ -. . . .
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~ ~.323~28 for the memory cell shown in Figure 1.
Figure 3 shows an address supply voltage sour~e an~ an .
address driver for supplying a first selected voltage level to the address line for the memory cell of Figure 1 during the read ., ; operation and a second selected voltage level duriny the write ~ . ~
operation; Figure 3 also shows a precharge circuit for precharging ~'~ the data line to a third selected voltage level prior to the read -;
operation.
Figure 4 shows a prior art six transistor memory cell.
, ., Figure 5 shows a five transistor memory cell of the present invention using NMOS technology.
DETAILED DESCRIPTION
Figure 1 shows one embodiment of memory cell 10 of the :- .,.
~i present invention. Memory cell 10 includes N channel enhancement ~, mode pass transistor N3 and inverters INV1 and INV2.
Inverter INV1 includes P channel enhancement mode .. .
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,',`. ' ' ' ' ', ~, ' .`', ~ ` ' ' ~ ~'~; . : ' ` .' ' 'r :'~:'': ' ` ` `, ~L3~3928 1 transistor Pl and N channel enhaneeme~t mode t~ansistor '`': Nl. Source 1 of transistor Pl is connected to the positive voltage supply having magnitude Vcc, which is typically 5 ~ 4 volts plus or minus 10~ although other voltages may be '.' 5 employed for Vcc. Drain 2 of transistor Pl is connected to 6 drain 4 of transistor Nl whose source is connected to , ground. Gates 3 and 6 of transistors Pl and Nl, ,~. respectively are connected to sense node A. The common ~, ' 9 drains 2 and 4 are connected to output node B.
Inverter INV2 includes P channel enhancement mode ~- 11 transistor P2 and M channel enhancement mode transistor .. ;~ 12 N2. Source 7 of transistor P2 is connected to the positive ... ,~
~, ~ voltage supply having magnitude Vcc. Drain 8 of transistor r' 14 P2 is connected to drain 10 of transistor N~ whose source is connected to ground. Gates 9 and 12 of transistors P2 and , 16 N2,respectively, are connected to output node B. Drains 8 '',' 7 and 10 are connected to sense node A. In operation theA~ 18 output signal on node B is continuously available to other 19 circuits (not shown in Fig. 1), for example, as a gate ' 20 control signal for other transistors.
Data line DM is connected to sense node A via pass ~, transistor N3. Gate 15 of transistor N3 is controlled by :- ~, the voltage signal on address line AN. Source/drain 13 of ~4 transistor N3 i5 conneeted to data line DM and source/drain ~5 14 of transistor M3 is connected to sense node A.
26 One advantage of memory cell 10 is that while the ,'~. 27 signal on output node B is used, typically continuouslyt to ~"il 28 control other circuits (not shown in Fig. 1), the content of ::-' 29 memory cell 10 (i.e. the signal stored on node A) can be repeatedly checked by a read operation to verify the : 31 integrity of the memory cell's data content without ` 32 degrading the output signal on node B. Furthermore, if :~, 33 desi,red, for example if the complement of the signal on node '.~ 34 B is required.to control other circuits, sense node A can ~''. 35 also be used as an output node. This is indicated by the ., 36 dotted arrow in Fig. 1. The voltage level at sense node A
i'~' 37 may be somewhat degraded during the read operation.
,~ 38 When sense node A stores a logical 0 and it is desired :.' ....
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~:-., ~, 132~928 to write a logical 1 to cell 10, the sig~al provided at source/drain 14 of transistor N3 must be sufficient to 3 increase the voltage on sense node A above the trigger point 4 of inverter INVl despite the pulldown effect of current flowing through transistor N2 of inverter INV2 (the trigger 6 point of an inverter is the voltage at which the gate 7 (input) voltage of the inverter equals the output voltage of 8 the inverter). Conversely, when sense node A stores a 9 logical 1 and it is desired to write a logical 0 to sense ~ node A, the signal provided at source/drain 14 of transistor 11 N3 must be sufficient to decrease the voltage on ~ense node 12 A below the trigger point of inverter INVl despite the 13 pullup effect of transistor P2 of inverter INV2.
14 The operation of writing data into cell 10 and the selection of the parameters for transistors Nl, N2, N3 t 16 and P2 may be understood by considering the following 17 examples.
19 ExamPle 1 Suppose that memory cell 10 stores a logical 0, i.e.
21 the voltage on node A is 0 volts (logical o) and that the 22 output signal of inverter INVl is Vcc (logical 1). Suppose 23 that a logical 1 having a voltage level of Vcc on data line 24 DM is to be written to node A and that transistor N3 is turned on by applying the signal Vcc to gate 15. A voltage 26 level of Vcc on source/drain 13 and a voltage level of Vcc 27 on gate 15 results in a voltage on source/drain 14 not higher than VCC VTH(N3)- VTH(N3) is the threshold voltage 29 of transistor N3 with body effect. Thus the trigger point of inverter INVl, denoted by VTRIG(INVl), is selected to be 31 less than Vcc ~ VTH(N3). This is accomplished by selecting 32 the ratio of the ratio of the channel width to channel 33 length of pullup transistor Pl to the ratio of channel width 34 to channel length of pulldown transistor Nl of inverter INV
to be sufficiently small. For example, if Vcc equals 36 5 volts and the channel width and channel length of 37 transistors Nl and Pl are as given in the following table:
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` 1323928 , 1 - Tr~ns~stor Channel width C~.3nnel Length 2 Pl 5~m 2.5~m Nl 9.75~m 2.5~m . 3 ' ~i;
4 then the trigger point of inverter INVl will be less than 2 . 5 volts. Having selected the channel width and channel length .~. b of transistors Pl and Nl so that the trigger po.int of 7 erter INVl is les5 than Vcc - VTH(N3~ the channel -~ 8 dimensions of N2 relative to the channel dimensions of N3 . g are selected so that the voltage at node A rises above the trigger point TP of inverter INVl. When transistors N3 and 11 N2 are both on, they act as a voltage divider, and the 1~ volta~e at ~ense node A is given by Vcc x 13 lR~N2)/(R(N2)+R(N3))) where R(~2) is the channel resistance 14 provided by transistor N2, and R(N3) is the channel resistance provided by transistor N3. R(N2) is directly 16 proportional to L(N2)/W(N2) and R(N3) is directly 17 proportional to L~N3)/W~N3) where L(N2~ is the channel ~` lB length of transistor N2, W(N2j is the channel width of 19 transistor N~, L(N3) is the channel length of transistor N3 and W(N3) is the channel width of transistor N3. By 21 appropriately choosiny the channel length and channel -- 22 widths, we may ensure that Vc~ x (R(N2)/(R(N2)+R(N3))) is ~' , 23 greater than the trigger point TP of inverter INV1. In one 24 embodiment, the channel length of pass transistor N3 is 2.5 . 25 microns and the channel width is 7.5 microns. Transistor N2 - - .
26 has a channel length of 4 microns and a channel width of 4 `~ 27 microns. In this case R(N2)/(R(N2)+R(N3)) equals 0.~.
~i 28 Hence the voltage on node A will rise above the trigger ;! 29 point of inverter INV~. Once the voltage on sense node A
~s 30 rises above the trigger point, VTRIG(INVl), t p .~ 31 signal on node B goes low and the output signal of inverter 32 INV2 goes high driving sense node A to the Vcc level.
:............. 33 ~` 34 Exam~le 2 ' 3~ In writin~ a logical 0 to memory cell ~0, assume the 36 voltage on data line DM is 0 volts, address line AN is ~; 37 charged to Vcc, and a voltage signal Vcc ~logical 1) is 38 stored on node A. When both transistors P2 and N3 are on, i - 6 -,::
- . , - -, -, .
~323928 1 pullup transisto~ P2 i~ ir.~ert~r IWV2 and transistor N3 act as a voltage divider and the voltage at sense node A is 3 given by VCC (R(N3)/~R(N3~+R(P2))) ~here R~P2) is the :~ 4 channel resistance provided by transistor P~ and R(N3) is the channel resistance provided by transistor N3. The channel resistance of P2 is directly proportional to ~ .~, 7 L(P2)/~(P2) where L~P2) is the channel length of transistor : 8 P2 and W(P2) is the channel width of transistor P2, The 9 channel resistance of N channel transistor N3 is directly proportional to L~N3)/W(N3) where L(N3) is the channel , 1 length of transistor N3 and W(N3) is the channel width of .~ transistor N3. These channel lengths and widths are chosen 13 so that the voltage on sense node A falls below the trigger . 14 point of inverter INVl. In one embodiment, transistor P2 in inverter INV2 has a channel length of 4 microns and a 16 channel w.idth of 6 microns. The fraction RIN3)/(R(N3)+R(P2)) -~ equals 0.1. In this case, the voltage on sense node A will ,A' 18 fall below the trigger point of inverter INVl where the :: 19 channel dimensions of inverter INVl are specified in the above table. Once the voltage on sense node ~ falls below the trigger point, the output signal on node 8 goes high and the output signal of inverter INV2 goes low driving sense " 23 node A to 0 ~olts. The above analysis assumes that the 24 channel resistance of the pullup and pulldown transistors of . 25 the write driver (not shown) are significantly smaller (less 26 than 10~) than the channel resistanee of transistors P2, N2 7 and N3.
28 It is also desirable to be able to read the data signal 29 stored on sense node A by transmitting this signal via pass transistor N3 to data line DM without disturbing the content .~. 31 of the memory. The value read is the value that appears on 32 source/drain 13 of transistor N3. ~ypically data line DM, , 33 which may be connected to many cells similar to cell 10 of :', 34 Fig. 1, has a large capacitanee compared to the capacitance .`~ 35 of sense node A. When address line AN ~oes high to turn ~' 36 pass transistor N3 in order to read the value stored on .;., 37 node A, the content of the memory (the value stored on node ~;~ ~O
A) may be disturbed due to charge shaxing. The following.
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;.-1 techniques can be employed to reduce the danger of 2 disturbing the memory cell during the read operation.
3 First, one may increase the rise time of the address line AN
~` WITH KNOWN STATE 0~ POWER-UP
- Hung-Cheng Hsieh - This application relates to U.S. Patent ~,750,155 issued June 7, 1988.
FIELD OF THE INVE~TION
.
~ This invention relates ko a static memory cell and in ., particular to a five-transistor memory cell which can be reliably read and written.
. 10 BACKGROUND
;, Figure 4 shows a prior art 6 transistor CMOS memory cell similar to the Intel 5101 cell. Transistors T'l, T'2, T'3 and T'4 .~
'~ constitute a cross-coupled latch that typically draws a steady ;~ state currenk of approximately one nanoampere. Transistors T'5 and T' are gating devices (pass transistors) that couple the bit ~' 6 lines (data lines) to the latch when the voltage on the row select line (address line) is high (5 volts). The output signal Q is a .
logical 1 when N channel enhancement mode transistor T'3 is off and P channel enhancement mode transistor T'4 is on, and it is a logical zero when these s~ates are reversed. Reading and writing .
~ are accomplished through the left and right blt llnes. For t~-; example to read the data out of the memory cell in Figure 4, a .....
high signal ls applied to the row select, turning on transistors T'5 and T'6. If a logical O (O volts) is on node A and a loyical 1 (5 volts) is on node B, the left bit line is charged to a lower level than the right bit line. These two bit lines are typically connected to a differential amplifier (not shown) that amplifies ,.'.1 .,,j ~
"~'.`.'` ' ' ~ ~ . ' J
` ~323928 ~he difference ln voltage levels on the bit line~. The amplified di~ference is then interpreted as a logical O or a logical 1, according to some design convention.
To write a bit into the memory cell, the row select line . is brought hlgh (to 5 volts) and the left and right bit .
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13~3~28 lines are charged to opposi~e sta~es by t~.e write drlver ~not shown in Fig. 4), which drlves node A to the sa~e logic level as the le~t bit line and node ~ to the same logic level as the right bit line.
The ~ix transistor memory cell requires two ga~ing devices ~pass transi~tors1 and two bit lines to be reliably read and written. Note that the six transistor memory cell can als~ be implemented in NMOS. See ~olt, Electronic Circuits, John Wiley and S0~5, Inc., pp. 293-294 ~1978)o .
:
SUMM~RY 0~ T~E INVENTION
.
- In contrast to the prior art, the present invention describes a five transi~tor memory cell which can be reliably read and written from a single data line. The memory cell includes a first and a second inverter with the ` output of ~he ~irst inverter connected to the input o~ the ,. second inverter and the output of the second inverter .5 connected to the input of the ~irst inverter and only a i................. single gating ~passl transistor which 1s connected between '~1 the lnput lead of the first inverter and the single bit ^~ line.
.. ~. In one embodiment of the invention the memory cell also :^
,~ includes a Eirst and a second output node llead) which :~ eontinuously provides the 6tate of the memory cell to ~ circuitry external to the memory/ for example to control the .~, gates of external p~ss transistors or to provide an input ignal to a logic gate.
.i Typically a plurality of fiYe tran~istor memory cells are connected to the same data line. As one feature of the invention, means are provided for increasing the rise time on the gate of the pass transistor in order to reduce the ; possibility of disturbing the content of the memory cell ,lj during the read operation. A5 another feature of the invPntion, the trigger point of the first inverter is ... . .
selected to be more than one thre~hold voltage wi~h body ~ effect below the voltage applied to the gate of the pas~
; transistor and channel dimensions of the pass tran~istor .,;~
., -, :
" , . .
,. :................................................ , -,, .
, . ..
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; . ~ . .
i32392~
relative to channel dimensions of the N channel and P channel i- transistors in the second inverter are selected to insure that the me~nory cell can be successfully written.
In another embodiment, cir~uitry is provided for precharging the data line to a first selected voltage level prior to reading a stored bit in order to reduce read disturbance.
In another embodiment circuitry is provided for charginy the gate of the pass transistor to a first level during the read operation and to a second level during the write operation and for precharging the data line to a third selected voltage level prior to the read operation. The voltage levels are selected to minimize read disturbance.
~, According to a broad aspect of the invention there is .~
`~i- provided a memory circuit comprising:
~, a first inverter having an input lead and an output lead;
a second inverter having an input lead connected to said output lead of said first inverter and havlng an output lead; and one and only one pass transistor, said pass transistor having a first source~drain, a second source/drain, and a control gate, said second sourcetdrain being connected to said input lead of said first inverter and to said output lead of said second inverter;
,,i!
said first inverter comprising a first P channel enhancement mode transistor having a source and a drain, and a first N channel enhancement mode transistor having a source and a drain, said source of said first P channel transistor for connscting to a first voltage supply, said drain of said first P channel -~ transistor being connected to said drain of said first N channel ~, 3 ~, :., ,, ~ , ~, : -. . :
... ~ . ., .. : .
transistor, said source of said first N channel transistor for .~ being connected to a second voltage supply having a voltage lower than said first voltacJe supply; and :
said second inverter comprising a second P channe . enhancement mode transistor having a source and a drain, and a second N channel enhancement mode transistor having a source and a drain, said source of said second P channel enhancement mode transistor for being connected to said first voltage supply, said drain of said second P channel enhancament mode transistor being connected to said drain of said second N channel enhancement mode ; transistor, said source of said second N channel enhancement mode transistor for being connected to said second voltage supply; and :~ wherein a threshold voltage of said first P channel ..
enhancement mode transistor is sufficiently higher than a threshold voltage of said second P channel transistor khat upon ~, power-up of said memory circuit said first P channel transistor remains in an off-state and said second P channel transistor ,;~ assumes an on-state, thereby causing said memory circuit to ::s provide a logical 1 at said output lead of said second inverter at . 20 completion of power-up.
; According to another broad aspect of the invention there ~`1 ., is provided a memory circuit comprising:
~ a first inverter having an input lead and an output lead;
a second inverter having an input lead connected to said output lead of said first inverter and having an output lead; and one and only one pass transistor, said pass transiskor having a first source/drain, a second source~drain, and a control gate, said second source/drain being connected to said input lead of . ~ .
::. 3a .. ,1 ~ ., . !:
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~323~2~
. said first inverter and to said output lead of said second . .
. inverter;
~ said first inverter comprising a first P channel enhancement ~. mode transistor having a source and a dra.in, and a first N channel .:. enhancement mode kransistor having a source and a drain, said source of said first P channel transistor for connecting to a . first voltage supply, said drain of said first P channel transistor being connected to said drain of said first N channel ` transistor, said source of said first N channel transistor for ; 10 being connected to a second voltage supply having a voltage lower ,.
than said first voltage supply;
.~ said second inverter comprising a second P channel . enhancement mode transistor having a source and a drain, and a ~ second N channel enhancement mode transistor having a source and a -~ drain, said source of said second P channel enhancement mode -., transistor for being connected to said first voltage supply, said -j drain of said second P channel enhancement mode transistor being connected to said drain of said second N channel enhancement mode ~ '1 ;~3 ~:. transistor, said source of said second N channel enhancement mode ,.j transistor for being connected to said second voltage supply; and .~ wherein a threshold voltage of said first P channel .. ~j; transistor is sufficiently lower than a threshold voltaye of said `''`i!
second P channel transistor that upon power-up of said memory ~:~ circuit said first P channel transistor assumes an on-state and ,:, ~ said second P channel transistor remains in an off-state, thereby .'~ Jj causing said memory circuit to provide a loyical 0 at said output 1 lead of said second inverter at completion of power-up.
.~i il According to another broad aspect of the invention there ~ 3b , .~ . .
: ~ .. : -i ~ , . . : ~ . , :, . , . , ,, ~ .
, ,, ~ ~ . , : , :: . : .
1323~2~
is provided a memory ~ir~uit comprising:
a first memory transistor and a second memory transistor;
a first load transistor and a second load transistor;
each of said memory and load transistors having a gate, a sour~e, and a drain, means for connecting said drain of said first memory ! transistor~ said drain of sald first load transistor, and said gate of said second memory transistor together;
means for connecting said drain of said second memory transistor, said drain of said second load transistor, and said gate of said first memory transistor together;
means for connecting said gates of said first and second load ~: transistors to a first voltage supply;
means for connecting said sources of said first and second load transistors to a second voltage supply;
-~ means for connecting said sources of said first and second memory transistors to a third voltage supply;
:~ wherein said first load transistor has a threshold voltage sufficiently lower than a threshold voltage of said second load transistor that upon power-up said drain of said first memory `j transistor provides a logical one and said drain of said second `~i memory transistor provides a logical zero.
The invention will be more readily understood by ~i! reference to the drawings and the detailed description.
8RIEF D~SCRIPTION OF TH~ DRAWINGS
Figure 1 shows a fiYe transistor memory cell according to ~he present invention.
, Figure 2 shows a circui~ for precharging the data line i 3c : I
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~ ~.323~28 for the memory cell shown in Figure 1.
Figure 3 shows an address supply voltage sour~e an~ an .
address driver for supplying a first selected voltage level to the address line for the memory cell of Figure 1 during the read ., ; operation and a second selected voltage level duriny the write ~ . ~
operation; Figure 3 also shows a precharge circuit for precharging ~'~ the data line to a third selected voltage level prior to the read -;
operation.
Figure 4 shows a prior art six transistor memory cell.
, ., Figure 5 shows a five transistor memory cell of the present invention using NMOS technology.
DETAILED DESCRIPTION
Figure 1 shows one embodiment of memory cell 10 of the :- .,.
~i present invention. Memory cell 10 includes N channel enhancement ~, mode pass transistor N3 and inverters INV1 and INV2.
Inverter INV1 includes P channel enhancement mode .. .
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,',`. ' ' ' ' ', ~, ' .`', ~ ` ' ' ~ ~'~; . : ' ` .' ' 'r :'~:'': ' ` ` `, ~L3~3928 1 transistor Pl and N channel enhaneeme~t mode t~ansistor '`': Nl. Source 1 of transistor Pl is connected to the positive voltage supply having magnitude Vcc, which is typically 5 ~ 4 volts plus or minus 10~ although other voltages may be '.' 5 employed for Vcc. Drain 2 of transistor Pl is connected to 6 drain 4 of transistor Nl whose source is connected to , ground. Gates 3 and 6 of transistors Pl and Nl, ,~. respectively are connected to sense node A. The common ~, ' 9 drains 2 and 4 are connected to output node B.
Inverter INV2 includes P channel enhancement mode ~- 11 transistor P2 and M channel enhancement mode transistor .. ;~ 12 N2. Source 7 of transistor P2 is connected to the positive ... ,~
~, ~ voltage supply having magnitude Vcc. Drain 8 of transistor r' 14 P2 is connected to drain 10 of transistor N~ whose source is connected to ground. Gates 9 and 12 of transistors P2 and , 16 N2,respectively, are connected to output node B. Drains 8 '',' 7 and 10 are connected to sense node A. In operation theA~ 18 output signal on node B is continuously available to other 19 circuits (not shown in Fig. 1), for example, as a gate ' 20 control signal for other transistors.
Data line DM is connected to sense node A via pass ~, transistor N3. Gate 15 of transistor N3 is controlled by :- ~, the voltage signal on address line AN. Source/drain 13 of ~4 transistor N3 i5 conneeted to data line DM and source/drain ~5 14 of transistor M3 is connected to sense node A.
26 One advantage of memory cell 10 is that while the ,'~. 27 signal on output node B is used, typically continuouslyt to ~"il 28 control other circuits (not shown in Fig. 1), the content of ::-' 29 memory cell 10 (i.e. the signal stored on node A) can be repeatedly checked by a read operation to verify the : 31 integrity of the memory cell's data content without ` 32 degrading the output signal on node B. Furthermore, if :~, 33 desi,red, for example if the complement of the signal on node '.~ 34 B is required.to control other circuits, sense node A can ~''. 35 also be used as an output node. This is indicated by the ., 36 dotted arrow in Fig. 1. The voltage level at sense node A
i'~' 37 may be somewhat degraded during the read operation.
,~ 38 When sense node A stores a logical 0 and it is desired :.' ....
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~:-., ~, 132~928 to write a logical 1 to cell 10, the sig~al provided at source/drain 14 of transistor N3 must be sufficient to 3 increase the voltage on sense node A above the trigger point 4 of inverter INVl despite the pulldown effect of current flowing through transistor N2 of inverter INV2 (the trigger 6 point of an inverter is the voltage at which the gate 7 (input) voltage of the inverter equals the output voltage of 8 the inverter). Conversely, when sense node A stores a 9 logical 1 and it is desired to write a logical 0 to sense ~ node A, the signal provided at source/drain 14 of transistor 11 N3 must be sufficient to decrease the voltage on ~ense node 12 A below the trigger point of inverter INVl despite the 13 pullup effect of transistor P2 of inverter INV2.
14 The operation of writing data into cell 10 and the selection of the parameters for transistors Nl, N2, N3 t 16 and P2 may be understood by considering the following 17 examples.
19 ExamPle 1 Suppose that memory cell 10 stores a logical 0, i.e.
21 the voltage on node A is 0 volts (logical o) and that the 22 output signal of inverter INVl is Vcc (logical 1). Suppose 23 that a logical 1 having a voltage level of Vcc on data line 24 DM is to be written to node A and that transistor N3 is turned on by applying the signal Vcc to gate 15. A voltage 26 level of Vcc on source/drain 13 and a voltage level of Vcc 27 on gate 15 results in a voltage on source/drain 14 not higher than VCC VTH(N3)- VTH(N3) is the threshold voltage 29 of transistor N3 with body effect. Thus the trigger point of inverter INVl, denoted by VTRIG(INVl), is selected to be 31 less than Vcc ~ VTH(N3). This is accomplished by selecting 32 the ratio of the ratio of the channel width to channel 33 length of pullup transistor Pl to the ratio of channel width 34 to channel length of pulldown transistor Nl of inverter INV
to be sufficiently small. For example, if Vcc equals 36 5 volts and the channel width and channel length of 37 transistors Nl and Pl are as given in the following table:
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, `:
` 1323928 , 1 - Tr~ns~stor Channel width C~.3nnel Length 2 Pl 5~m 2.5~m Nl 9.75~m 2.5~m . 3 ' ~i;
4 then the trigger point of inverter INVl will be less than 2 . 5 volts. Having selected the channel width and channel length .~. b of transistors Pl and Nl so that the trigger po.int of 7 erter INVl is les5 than Vcc - VTH(N3~ the channel -~ 8 dimensions of N2 relative to the channel dimensions of N3 . g are selected so that the voltage at node A rises above the trigger point TP of inverter INVl. When transistors N3 and 11 N2 are both on, they act as a voltage divider, and the 1~ volta~e at ~ense node A is given by Vcc x 13 lR~N2)/(R(N2)+R(N3))) where R(~2) is the channel resistance 14 provided by transistor N2, and R(N3) is the channel resistance provided by transistor N3. R(N2) is directly 16 proportional to L(N2)/W(N2) and R(N3) is directly 17 proportional to L~N3)/W~N3) where L(N2~ is the channel ~` lB length of transistor N2, W(N2j is the channel width of 19 transistor N~, L(N3) is the channel length of transistor N3 and W(N3) is the channel width of transistor N3. By 21 appropriately choosiny the channel length and channel -- 22 widths, we may ensure that Vc~ x (R(N2)/(R(N2)+R(N3))) is ~' , 23 greater than the trigger point TP of inverter INV1. In one 24 embodiment, the channel length of pass transistor N3 is 2.5 . 25 microns and the channel width is 7.5 microns. Transistor N2 - - .
26 has a channel length of 4 microns and a channel width of 4 `~ 27 microns. In this case R(N2)/(R(N2)+R(N3)) equals 0.~.
~i 28 Hence the voltage on node A will rise above the trigger ;! 29 point of inverter INV~. Once the voltage on sense node A
~s 30 rises above the trigger point, VTRIG(INVl), t p .~ 31 signal on node B goes low and the output signal of inverter 32 INV2 goes high driving sense node A to the Vcc level.
:............. 33 ~` 34 Exam~le 2 ' 3~ In writin~ a logical 0 to memory cell ~0, assume the 36 voltage on data line DM is 0 volts, address line AN is ~; 37 charged to Vcc, and a voltage signal Vcc ~logical 1) is 38 stored on node A. When both transistors P2 and N3 are on, i - 6 -,::
- . , - -, -, .
~323928 1 pullup transisto~ P2 i~ ir.~ert~r IWV2 and transistor N3 act as a voltage divider and the voltage at sense node A is 3 given by VCC (R(N3)/~R(N3~+R(P2))) ~here R~P2) is the :~ 4 channel resistance provided by transistor P~ and R(N3) is the channel resistance provided by transistor N3. The channel resistance of P2 is directly proportional to ~ .~, 7 L(P2)/~(P2) where L~P2) is the channel length of transistor : 8 P2 and W(P2) is the channel width of transistor P2, The 9 channel resistance of N channel transistor N3 is directly proportional to L~N3)/W(N3) where L(N3) is the channel , 1 length of transistor N3 and W(N3) is the channel width of .~ transistor N3. These channel lengths and widths are chosen 13 so that the voltage on sense node A falls below the trigger . 14 point of inverter INVl. In one embodiment, transistor P2 in inverter INV2 has a channel length of 4 microns and a 16 channel w.idth of 6 microns. The fraction RIN3)/(R(N3)+R(P2)) -~ equals 0.1. In this case, the voltage on sense node A will ,A' 18 fall below the trigger point of inverter INVl where the :: 19 channel dimensions of inverter INVl are specified in the above table. Once the voltage on sense node ~ falls below the trigger point, the output signal on node 8 goes high and the output signal of inverter INV2 goes low driving sense " 23 node A to 0 ~olts. The above analysis assumes that the 24 channel resistance of the pullup and pulldown transistors of . 25 the write driver (not shown) are significantly smaller (less 26 than 10~) than the channel resistanee of transistors P2, N2 7 and N3.
28 It is also desirable to be able to read the data signal 29 stored on sense node A by transmitting this signal via pass transistor N3 to data line DM without disturbing the content .~. 31 of the memory. The value read is the value that appears on 32 source/drain 13 of transistor N3. ~ypically data line DM, , 33 which may be connected to many cells similar to cell 10 of :', 34 Fig. 1, has a large capacitanee compared to the capacitance .`~ 35 of sense node A. When address line AN ~oes high to turn ~' 36 pass transistor N3 in order to read the value stored on .;., 37 node A, the content of the memory (the value stored on node ~;~ ~O
A) may be disturbed due to charge shaxing. The following.
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132~92~
;.-1 techniques can be employed to reduce the danger of 2 disturbing the memory cell during the read operation.
3 First, one may increase the rise time of the address line AN
4 by slowing the rate of increase of the voltage of address S line AN. Then transistor N3 turns on more 510wly, allowins 6 memory cell 10 to react to the disturbance caused by charge 7 sharing without changing the content of the data stored on node A. For example, if YCc is stored on node A, the rise 9 time must be sufficiently long that the voltage on node A
does not fall to VTRIG(INVl) when transistor N3 turns on.
11 If 0 volts is stored on node A, the rise time of the signal on address AN must be sufficiently long that the voltage on 13 node A does not rise to VTRIG(INVl) when transistor N3 turns 14 on. A typical address rise time should be 200ns or mo~e.
The rise time of address line ~N is increased by usin~ a 16 ."weak" !small channel width to channel length ratio) pullup 17 transistor (not shown) in the address driver.18 A second techni~ue for avoiding disturbing the content 19 of cell 10 duriny the read operation is to precharge the data line DM to the value VTRIG(INVl)-21 Assume data line DM is precharged to the value 22 VTRIG(INVl). Assume also that a read signal of magnitude 23 Vcc is applied to address line AN. If Vcc (logical 1) is 24 stored on sense node A; then pullup transistor R2 f ~5 inverter INV2 and pass transistor N3 form a voltage divider 26 network and sense node A does not fall below VTRIG(I~Vl).
27 Similarly, if 0 volts ~logical 0) i5 stored on sense node A, 28 then sense node A does not rise above VTRIG(INVl), since in ~9 this event transistors N2 and N3 form a resistor divider network and data line DM is precharged to VTRIG(INV13. In 31 one embodiment, the circuit shown in FigO 2 is used to 32 precharge data line DM to VTRIG(INVl)-33 The VTRIG(INYl) precharge circuit shown in Figure 2 34 includes P,,channel enhancement mode,transistor Tl, N channel enhancement mode transistor T2, and N channel enhancement 36 mode pass transistor T3. As shown in Fig. 2, source 20 of 37 ~ransistor Tl is connected to the positive voltage supply 38 vc~. Drain 21 of transistor ~1 is connected to drain 23 of ~j .
,~ - 8 ~ .
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~323928 1 transistor T~ whose source ~ is connected to ground. Gates 2 22 and 25 of transistors Tl and T2, respectively, are connected to the common dra n connection of tra~sistors T
4 and T2 which also connects to drain 26 of pass transistor T3. Source 27 of transistor T3 is connected to data line DM
6 and gate 28 of transistor T3 is connected to precharge 7 signal, ~prechar~e. The "ir.verter" comprising transistors 8 Tl and T2 is designed to have the same trigger point as 9 inverter INVl, shown in Fig. 1~ In the precharge cycle, the g g al, ~precharge~ is set t~ Vcc, which turns on N channel pass transistor T3, and data line DM is precharged to a voltage level of VT~IG(INVl) (assuming VTRIG(INVl) is 13 lower than the voltage l~ve7 of ~precharge minus TH,T3) 14 The precharge signal ~prechar~e is then brought low by control circuitry lnot shown), turning off pass transistor 16 T3 just before the address line AN connected to gate 15 of 17 pass transistor N3 is ~rought high.
18 The third technique for avoiding disturbing the content 19 of memory cell 10 during the read operation is to precharge data line DM to Vcc and set the high level of address line 21 AN to~the va~ue VTRIG~INVl). These conditions are 22 implemented using the circuitry shown in Fig. 3. Under 23 these conditions, when the value stored in cell 10 is Vcc 24 (logical 1), pass transistor N3 remains off and the value sensed at source/drain 13 is Vcc tlogical 1), and sense node 26 A is undisturbed. On the other hand, when the value stored 27 in cell 10 is O volts (logical 0), the highest voltage that 28 sense node A can be charged to is VTRIG(INVl) - V~H(N33 29 since N3 is cut off when the voltage on source/drain 14 reaches this value. Hence the read "O" operation has a 31 noise margin of VTH(N3). This is the preferred technique 32 because the memory cell 10 is guaranteed not to be disturbed 33 by the read operation regardless of the rise time of address 34 line AN, the imbalance between the capacitance on the data line DM and the capacitance on the sense node A, or the 36 ratio of channel resistance between transistor N3 and 37 transistor P2 or N2. This third technique requires that the 38 address line AN be charged to Vcc for a write operation and ., .
.b ~ 132~28 1 to VTRIG(INVl) during a read operation. Symbolically, 2 VADDRESS SUPPLY = Vcc during write 3 VTRIG(INVl) during read 4 The address supply voltage source can be implemented as shown in Fig. 3O Address supply circuit 90 shown in Fig. 3 6 includes P channel enhancement mode transistor TAl, N
7 channel enhancement mode transistor TA2, N channel 8 enhancement mode transistor TA4, and P channel enhancement 9 mode transistor TA3. As shown in Fig. 3, source 30 of transistor TAl i5 connected to the positive voltage supply 11 Vcc. Drain 31 of transistor TAl is connected to drain 33 of 12 transistor TA2 whose source 34 is connected to drain 36 of 13 transistor TA~ whose source 37 is connected to ground.
14 Source 39-of P channel transistor TA3 is connected to Vcc and drain 40 of transistor TA3 is connected to gates 32 and 16 35 of transistors TAl and TA2 and to the common drain 17 connection of transistors T~l and TA2 Gates 41 and 38 of 18 transistors TA3 and T~g are controlled by the signal on line 19 R/W. In the write mode, a signal of 0 volts is applied to line R/W, which turns off N channel transistor TA4. P
21 channel transistor TA3 then charges VADDRESS SUPPLY to 22 Vcc. Note that transistor TA3 should be designed to be 23 sufficiently large to provide the current to address driver 24 70 to charge up address line AN in the write mode. In the read mode, Vcc (logical 1) is applied to line R/W. This ~6 turns P channel transistor TA3 off and turns on N channel 27 transistor TA4. By appropriately choosing channel lengths 28 and channel widths, the circuit comprising transistor TAl, 29 transistor TA2 and transistor T~q is designed such that the voltage a~ the output node 45~ VADDRESS SUPPLY is the same 31 as the trigger point of in~erter INVl shown in Fig. 1.
Thus~ VADDRESS SUPPLY is equal to VTRIG~INVl)~ Note that 33 transistor TAl should be designed to be sufficiently large 34 to provide the current to address driver 70 to charge up address line AN in the read mode. In one embodiment, 36 transistors ~Al and TA3 have a channel length of 2.5 microns 37 and a channel width of 30 microns and transistors TA2 and 38 TA4 have a channel length of 2.5 microns and a channel width .. `. -- 10 --`' ' .. .. .
. . -- .
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~23928 of 108 microns.
2Address driver 70 is loglcally a NOR gate having input 3 lead 54 for receiving the signal address clock and input 4 lead 55 for receiving the signal address select Lead 54 provides the signal address clock to gate 58 of 6 p channel enhancement mode transistor 52 and to inverter 56 ... 7 whose output signal controls gate 61 of N channel 8 enhancement mode transistor 50. Lead 54 is also connected 9 to gate 65 of N channel enhancement mode transistor 66.
~"~ 10 Lead 55 provides the address select signal to gate 59 - 11 of p channel enhancement mode transistor 53 and to inverter 12 57 whose output signal controls gate 62 of N channel 13 enhancement mode transistor 51. Lead 55 is also connected i 14 to gat~ 63 of N channel enhancement mode transistor 64.
; 15 Transistors 50, 51, S2, and 53 comprise four 16 transmission gates forming two parallel pairs of gates with 17 the gates of each pair connected in series. Note that when 18 signals address clock and address select are both low (0 19 volts) all four transistors 50, 51, 52 and 53 are on and N
channel transistors 64 and 6b are off and thus the voltage ;1 - ~ 22 VADDREsg SUPPLY is transmitted to address line ~N.
:. P channel enhancement mode transistor 80 is connected "~ 23 between the voltage supply Vcc and data line DM. Data line ~ DM is precharged to Vcc by applying a low (0 volts) '`?,, 26 ~precharge signal to gate 81 on lead 82.
,: The third technique described above in conjunction with 27 Fig. 3 can be modified by replacing P channel transistor 80 ~ 2~ by an N channel enhancement mode transistor (not shown~
',.;! 29 whose gate is controlled by the signal ~precha~ge~ the complement of ~precharge In this embodiment, the data line 31 is precharged to Vcc-VT where VT is the threshold volta~e of 32 the N channel transistorO
. 33 ~ypically a plurality of memory cells identical to cell ~`'J 34 10 are connected to data line DM. Fig. 3 shows two such ', 5 memory cells having address lines AN connected to address `~ 36 driver 70 and AN+l which is connected to a corresponding 37 address driver (not shown). In another embodiment (not 38 shown), a rectangular memory array is formed which comprises , . .j ,..................................... .
'''',;' '' ~' '' ' ' .'.' . -.~., - :
. .~.
~3239~8 1 a plurality of data lines, a plurality of address lines, and 2 a plurality of memory cells, the rnemory cells attached to a 3 given one of said data lines forming a column in the array 4 and the memory cells attached to a given one of the address lines forming a row in the rectangular array.
; 6 The above embodiments are intended to be exemplary and 7 not limiting. For example, while the circuits described 8 above are implemented using CMOS technology, they may also ; 9 be implemented using NMOS technology.
10 There can be a problem in some logic arrays if a random ~`~ 11 initial memory state on power-up causes devices controlled > 12 by the memory cells in the array to become shorted 13 together. The shorting may cause the devices controlled by the memory cells to become unprogrammable or even damaged.
This is a noticeable problem for large arrays, It is 16 therefore desirable to control the initial memory state of 17 the memory cells on power-up.
18 According to a preferred embodiment of this invention, -~ 19 in which the two inverters INVl and INV2 of Fig. 1 are both i~ 20 CMOS, each having a p-channel pull-up transistor, Pl and P2 21 respectively, the two p-channel transistors Pl and P2 are -22 differentially doped to exhibit different threshold 23 voltages. Before power-up~ all nodes in the memory cell, in 24 particular nodes A and B, will have a voltage level of 0 volts. At power-up, as the Vcc voltage level ia rising from 26 o volts to the supply voltage level, the p-channel 27 transistor requiring the lo~est voltage difference between 28 the gate and source will turn on first. In the circuit of 29 Fig. 1, according to one preferred e~lbodiment, transistor P2 is manufactured to have a threshold voltage of -0.7 volts 31 while transistor Pl is manufactured to have a threshold 32 voltage of -1.6 volts. During power-up, a low voltage 33 applied at terminal AN to gate 15 of transistor N3 causes 34 pass transistor N3 to be off. As the Vcc voltage level passes 0.7 volts, the gate voltages on gates 3, 6, 9, and 12 36 remain approximately 0 volts. Therefore, transistor P2 will 37 begin to turn on. The increasing Ycc voltage level will 3g then be placed by p-channel transistor P2 onto node A, ~hich , 1 .: , .
.. ~ . .
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~323928 1 will in turn apply this increasing level to gate 3 of 2 p-channel transistor Pl, thus preventing the gate to source 3 voltage of transistor Pl from reaching the threshold voltage 4 of -1.6 volts during power-up. Thus at the completion of ;~5 power-up the memory cell is in the known state in which node 6 A is at a logical 1 and node B is at a logical 0.
7 In order to achieve the opposite initial state, the 8 threshold voltage of transistor Pl can be manufactured to be 9 lower than that of transistor P2. It is preferred, however, ` 10 that all memory cells in a given array be manufactured so 11 that they adopt the same initial state on power-up, in order 12 that the ratios of channel length and channel width of the 13 pass transistor and second inverter of each cell throughout 14 the array, and the trigger points of inverters throughout the array can be consistent throughout the array. If it is 16 desired that some devices controlled by memory cells be 17 initialized at a logical one and others at a logical zero, 18 then some devices can be controlled from node A of their 19 respec~ive memory cells and others can be controlled from node B of their respective memory cells.
`~1 The threshold voltages can be adjusted somewhat by 422 adjusting the channel length of the transistors rather than ~!" 23 by varying doping level. Transistors with shorter channel 24 lenyth have a somewhat lower threshold voltage than transistors with a longer channel length~ Ho~ever, a more sensitive method, and the preferred method of controlling 27 threshold voltage is to dope the two p-channel transistors 28 Pl and P2 differentlyO According to a preferred method of ~9 forming the structure, the doping level in the channel of transistor P2 is not changed from that of the n-well in 31 which it is formed whereas the doping level oP transistor Pl 32 is increased durin~ a separate masking process, during which 33 the channel of transistor P2 is masked so as not to be 34 af~ected-The same principle described above with rPspect to a 36 CMOS memory cell can also be applied to the NMOS memory cell 37 shown in Fig. 5. In Fig. 5, transistors N5 and N6 are 38 equivalent to transistors Nl and N2 respectively of Fig. 1.
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~323928 1 N-channel transistors N7 and N8 ~orm resistlve loads for the 2 memory cell, being controlled by a vol~age Vgg applied to 3 their gates. Transistor N7 in one embodiment is 4 manufactured to have a threshold voltage VtN7 of 0.7 volts ~ 5 while transistor N8 is rnanufactured to have a threshold -~ 6 voltage VtN8 of 1.6 volts. Thus, on power-up, as voltages 7 Vcc and Vgg rise above 0.7 volts, transistor N7 will begin 8 to turn on while transistor N8 remains ofP. Thus the 9 voltage at node B will rise to Vgg - VtN7 and this voltage will in turn be applied to the gate of transistor N6. As 11 the voltage Vgg - VtN7 rises above the threshold voltage of 12 transistor N6, transistor N6 begins to turn on, pulling node ~ 13 A to ground, and holding transistor N5 off. As the voltage - 14 Vgg rises above 1.6 volts, transistor N8 will begin to turn on. By selecting the ratio of channel width to channel ~` 16 length of transistor N8 to be significantly less than the 17 ratio of channel width to channel length of transistor N6, - 18 when both transistors N6 and N8 turn on the voltage level at :~ 19 node A is a logical "0". Thus on the completion of power-up, the cell of Fig. 5 is in a known state in which node B
~i 21 provides a logical "1" and node A provides a logical "0".
2 In the embodiment of Fig. 5, it is possible for Vgg to 23 be equal to Vcc. However, because this NMOS embodiment 24 consumes a steady state current ~in the above example, when node A is at logical "0" there is steady state current from . 26 Vcc through transistors N8 and N6 to ground~, it is i 27 preferred that Vgg be separately controlled so that the Vgg 28 voltage can be lowered to increase resistance of transistors 29 N7 and N8, and thereby save power, or so that the cell can be turned off altogether when not in use.
31 Many other modifications will become obvious to one of ;~ 3~ average skill in the art in light of ~he above dîsclosure i 33 and are included within the scope of the invention.
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does not fall to VTRIG(INVl) when transistor N3 turns on.
11 If 0 volts is stored on node A, the rise time of the signal on address AN must be sufficiently long that the voltage on 13 node A does not rise to VTRIG(INVl) when transistor N3 turns 14 on. A typical address rise time should be 200ns or mo~e.
The rise time of address line ~N is increased by usin~ a 16 ."weak" !small channel width to channel length ratio) pullup 17 transistor (not shown) in the address driver.18 A second techni~ue for avoiding disturbing the content 19 of cell 10 duriny the read operation is to precharge the data line DM to the value VTRIG(INVl)-21 Assume data line DM is precharged to the value 22 VTRIG(INVl). Assume also that a read signal of magnitude 23 Vcc is applied to address line AN. If Vcc (logical 1) is 24 stored on sense node A; then pullup transistor R2 f ~5 inverter INV2 and pass transistor N3 form a voltage divider 26 network and sense node A does not fall below VTRIG(I~Vl).
27 Similarly, if 0 volts ~logical 0) i5 stored on sense node A, 28 then sense node A does not rise above VTRIG(INVl), since in ~9 this event transistors N2 and N3 form a resistor divider network and data line DM is precharged to VTRIG(INV13. In 31 one embodiment, the circuit shown in FigO 2 is used to 32 precharge data line DM to VTRIG(INVl)-33 The VTRIG(INYl) precharge circuit shown in Figure 2 34 includes P,,channel enhancement mode,transistor Tl, N channel enhancement mode transistor T2, and N channel enhancement 36 mode pass transistor T3. As shown in Fig. 2, source 20 of 37 ~ransistor Tl is connected to the positive voltage supply 38 vc~. Drain 21 of transistor ~1 is connected to drain 23 of ~j .
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~323928 1 transistor T~ whose source ~ is connected to ground. Gates 2 22 and 25 of transistors Tl and T2, respectively, are connected to the common dra n connection of tra~sistors T
4 and T2 which also connects to drain 26 of pass transistor T3. Source 27 of transistor T3 is connected to data line DM
6 and gate 28 of transistor T3 is connected to precharge 7 signal, ~prechar~e. The "ir.verter" comprising transistors 8 Tl and T2 is designed to have the same trigger point as 9 inverter INVl, shown in Fig. 1~ In the precharge cycle, the g g al, ~precharge~ is set t~ Vcc, which turns on N channel pass transistor T3, and data line DM is precharged to a voltage level of VT~IG(INVl) (assuming VTRIG(INVl) is 13 lower than the voltage l~ve7 of ~precharge minus TH,T3) 14 The precharge signal ~prechar~e is then brought low by control circuitry lnot shown), turning off pass transistor 16 T3 just before the address line AN connected to gate 15 of 17 pass transistor N3 is ~rought high.
18 The third technique for avoiding disturbing the content 19 of memory cell 10 during the read operation is to precharge data line DM to Vcc and set the high level of address line 21 AN to~the va~ue VTRIG~INVl). These conditions are 22 implemented using the circuitry shown in Fig. 3. Under 23 these conditions, when the value stored in cell 10 is Vcc 24 (logical 1), pass transistor N3 remains off and the value sensed at source/drain 13 is Vcc tlogical 1), and sense node 26 A is undisturbed. On the other hand, when the value stored 27 in cell 10 is O volts (logical 0), the highest voltage that 28 sense node A can be charged to is VTRIG(INVl) - V~H(N33 29 since N3 is cut off when the voltage on source/drain 14 reaches this value. Hence the read "O" operation has a 31 noise margin of VTH(N3). This is the preferred technique 32 because the memory cell 10 is guaranteed not to be disturbed 33 by the read operation regardless of the rise time of address 34 line AN, the imbalance between the capacitance on the data line DM and the capacitance on the sense node A, or the 36 ratio of channel resistance between transistor N3 and 37 transistor P2 or N2. This third technique requires that the 38 address line AN be charged to Vcc for a write operation and ., .
.b ~ 132~28 1 to VTRIG(INVl) during a read operation. Symbolically, 2 VADDRESS SUPPLY = Vcc during write 3 VTRIG(INVl) during read 4 The address supply voltage source can be implemented as shown in Fig. 3O Address supply circuit 90 shown in Fig. 3 6 includes P channel enhancement mode transistor TAl, N
7 channel enhancement mode transistor TA2, N channel 8 enhancement mode transistor TA4, and P channel enhancement 9 mode transistor TA3. As shown in Fig. 3, source 30 of transistor TAl i5 connected to the positive voltage supply 11 Vcc. Drain 31 of transistor TAl is connected to drain 33 of 12 transistor TA2 whose source 34 is connected to drain 36 of 13 transistor TA~ whose source 37 is connected to ground.
14 Source 39-of P channel transistor TA3 is connected to Vcc and drain 40 of transistor TA3 is connected to gates 32 and 16 35 of transistors TAl and TA2 and to the common drain 17 connection of transistors T~l and TA2 Gates 41 and 38 of 18 transistors TA3 and T~g are controlled by the signal on line 19 R/W. In the write mode, a signal of 0 volts is applied to line R/W, which turns off N channel transistor TA4. P
21 channel transistor TA3 then charges VADDRESS SUPPLY to 22 Vcc. Note that transistor TA3 should be designed to be 23 sufficiently large to provide the current to address driver 24 70 to charge up address line AN in the write mode. In the read mode, Vcc (logical 1) is applied to line R/W. This ~6 turns P channel transistor TA3 off and turns on N channel 27 transistor TA4. By appropriately choosing channel lengths 28 and channel widths, the circuit comprising transistor TAl, 29 transistor TA2 and transistor T~q is designed such that the voltage a~ the output node 45~ VADDRESS SUPPLY is the same 31 as the trigger point of in~erter INVl shown in Fig. 1.
Thus~ VADDRESS SUPPLY is equal to VTRIG~INVl)~ Note that 33 transistor TAl should be designed to be sufficiently large 34 to provide the current to address driver 70 to charge up address line AN in the read mode. In one embodiment, 36 transistors ~Al and TA3 have a channel length of 2.5 microns 37 and a channel width of 30 microns and transistors TA2 and 38 TA4 have a channel length of 2.5 microns and a channel width .. `. -- 10 --`' ' .. .. .
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2Address driver 70 is loglcally a NOR gate having input 3 lead 54 for receiving the signal address clock and input 4 lead 55 for receiving the signal address select Lead 54 provides the signal address clock to gate 58 of 6 p channel enhancement mode transistor 52 and to inverter 56 ... 7 whose output signal controls gate 61 of N channel 8 enhancement mode transistor 50. Lead 54 is also connected 9 to gate 65 of N channel enhancement mode transistor 66.
~"~ 10 Lead 55 provides the address select signal to gate 59 - 11 of p channel enhancement mode transistor 53 and to inverter 12 57 whose output signal controls gate 62 of N channel 13 enhancement mode transistor 51. Lead 55 is also connected i 14 to gat~ 63 of N channel enhancement mode transistor 64.
; 15 Transistors 50, 51, S2, and 53 comprise four 16 transmission gates forming two parallel pairs of gates with 17 the gates of each pair connected in series. Note that when 18 signals address clock and address select are both low (0 19 volts) all four transistors 50, 51, 52 and 53 are on and N
channel transistors 64 and 6b are off and thus the voltage ;1 - ~ 22 VADDREsg SUPPLY is transmitted to address line ~N.
:. P channel enhancement mode transistor 80 is connected "~ 23 between the voltage supply Vcc and data line DM. Data line ~ DM is precharged to Vcc by applying a low (0 volts) '`?,, 26 ~precharge signal to gate 81 on lead 82.
,: The third technique described above in conjunction with 27 Fig. 3 can be modified by replacing P channel transistor 80 ~ 2~ by an N channel enhancement mode transistor (not shown~
',.;! 29 whose gate is controlled by the signal ~precha~ge~ the complement of ~precharge In this embodiment, the data line 31 is precharged to Vcc-VT where VT is the threshold volta~e of 32 the N channel transistorO
. 33 ~ypically a plurality of memory cells identical to cell ~`'J 34 10 are connected to data line DM. Fig. 3 shows two such ', 5 memory cells having address lines AN connected to address `~ 36 driver 70 and AN+l which is connected to a corresponding 37 address driver (not shown). In another embodiment (not 38 shown), a rectangular memory array is formed which comprises , . .j ,..................................... .
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~3239~8 1 a plurality of data lines, a plurality of address lines, and 2 a plurality of memory cells, the rnemory cells attached to a 3 given one of said data lines forming a column in the array 4 and the memory cells attached to a given one of the address lines forming a row in the rectangular array.
; 6 The above embodiments are intended to be exemplary and 7 not limiting. For example, while the circuits described 8 above are implemented using CMOS technology, they may also ; 9 be implemented using NMOS technology.
10 There can be a problem in some logic arrays if a random ~`~ 11 initial memory state on power-up causes devices controlled > 12 by the memory cells in the array to become shorted 13 together. The shorting may cause the devices controlled by the memory cells to become unprogrammable or even damaged.
This is a noticeable problem for large arrays, It is 16 therefore desirable to control the initial memory state of 17 the memory cells on power-up.
18 According to a preferred embodiment of this invention, -~ 19 in which the two inverters INVl and INV2 of Fig. 1 are both i~ 20 CMOS, each having a p-channel pull-up transistor, Pl and P2 21 respectively, the two p-channel transistors Pl and P2 are -22 differentially doped to exhibit different threshold 23 voltages. Before power-up~ all nodes in the memory cell, in 24 particular nodes A and B, will have a voltage level of 0 volts. At power-up, as the Vcc voltage level ia rising from 26 o volts to the supply voltage level, the p-channel 27 transistor requiring the lo~est voltage difference between 28 the gate and source will turn on first. In the circuit of 29 Fig. 1, according to one preferred e~lbodiment, transistor P2 is manufactured to have a threshold voltage of -0.7 volts 31 while transistor Pl is manufactured to have a threshold 32 voltage of -1.6 volts. During power-up, a low voltage 33 applied at terminal AN to gate 15 of transistor N3 causes 34 pass transistor N3 to be off. As the Vcc voltage level passes 0.7 volts, the gate voltages on gates 3, 6, 9, and 12 36 remain approximately 0 volts. Therefore, transistor P2 will 37 begin to turn on. The increasing Ycc voltage level will 3g then be placed by p-channel transistor P2 onto node A, ~hich , 1 .: , .
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~323928 1 will in turn apply this increasing level to gate 3 of 2 p-channel transistor Pl, thus preventing the gate to source 3 voltage of transistor Pl from reaching the threshold voltage 4 of -1.6 volts during power-up. Thus at the completion of ;~5 power-up the memory cell is in the known state in which node 6 A is at a logical 1 and node B is at a logical 0.
7 In order to achieve the opposite initial state, the 8 threshold voltage of transistor Pl can be manufactured to be 9 lower than that of transistor P2. It is preferred, however, ` 10 that all memory cells in a given array be manufactured so 11 that they adopt the same initial state on power-up, in order 12 that the ratios of channel length and channel width of the 13 pass transistor and second inverter of each cell throughout 14 the array, and the trigger points of inverters throughout the array can be consistent throughout the array. If it is 16 desired that some devices controlled by memory cells be 17 initialized at a logical one and others at a logical zero, 18 then some devices can be controlled from node A of their 19 respec~ive memory cells and others can be controlled from node B of their respective memory cells.
`~1 The threshold voltages can be adjusted somewhat by 422 adjusting the channel length of the transistors rather than ~!" 23 by varying doping level. Transistors with shorter channel 24 lenyth have a somewhat lower threshold voltage than transistors with a longer channel length~ Ho~ever, a more sensitive method, and the preferred method of controlling 27 threshold voltage is to dope the two p-channel transistors 28 Pl and P2 differentlyO According to a preferred method of ~9 forming the structure, the doping level in the channel of transistor P2 is not changed from that of the n-well in 31 which it is formed whereas the doping level oP transistor Pl 32 is increased durin~ a separate masking process, during which 33 the channel of transistor P2 is masked so as not to be 34 af~ected-The same principle described above with rPspect to a 36 CMOS memory cell can also be applied to the NMOS memory cell 37 shown in Fig. 5. In Fig. 5, transistors N5 and N6 are 38 equivalent to transistors Nl and N2 respectively of Fig. 1.
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~323928 1 N-channel transistors N7 and N8 ~orm resistlve loads for the 2 memory cell, being controlled by a vol~age Vgg applied to 3 their gates. Transistor N7 in one embodiment is 4 manufactured to have a threshold voltage VtN7 of 0.7 volts ~ 5 while transistor N8 is rnanufactured to have a threshold -~ 6 voltage VtN8 of 1.6 volts. Thus, on power-up, as voltages 7 Vcc and Vgg rise above 0.7 volts, transistor N7 will begin 8 to turn on while transistor N8 remains ofP. Thus the 9 voltage at node B will rise to Vgg - VtN7 and this voltage will in turn be applied to the gate of transistor N6. As 11 the voltage Vgg - VtN7 rises above the threshold voltage of 12 transistor N6, transistor N6 begins to turn on, pulling node ~ 13 A to ground, and holding transistor N5 off. As the voltage - 14 Vgg rises above 1.6 volts, transistor N8 will begin to turn on. By selecting the ratio of channel width to channel ~` 16 length of transistor N8 to be significantly less than the 17 ratio of channel width to channel length of transistor N6, - 18 when both transistors N6 and N8 turn on the voltage level at :~ 19 node A is a logical "0". Thus on the completion of power-up, the cell of Fig. 5 is in a known state in which node B
~i 21 provides a logical "1" and node A provides a logical "0".
2 In the embodiment of Fig. 5, it is possible for Vgg to 23 be equal to Vcc. However, because this NMOS embodiment 24 consumes a steady state current ~in the above example, when node A is at logical "0" there is steady state current from . 26 Vcc through transistors N8 and N6 to ground~, it is i 27 preferred that Vgg be separately controlled so that the Vgg 28 voltage can be lowered to increase resistance of transistors 29 N7 and N8, and thereby save power, or so that the cell can be turned off altogether when not in use.
31 Many other modifications will become obvious to one of ;~ 3~ average skill in the art in light of ~he above dîsclosure i 33 and are included within the scope of the invention.
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Claims (38)
1. A memory circuit comprising:
a first inverter having an input lead and an output lead;
a second inverter having an input lead connected to said output lead of said first inverter and having an output lead; and one and only one pass transistor, said pass transistor having a first source/drain, a second source/drain, and a control gate, said second source/drain being connected to said input lead of said first inverter and to said output lead of said second inverter;
said first inverter comprising a first P channel enhancement mode transistor having a source and a drain, and a first N channel enhancement mode transistor having a source and a drain, said source of said first P channel transistor for connecting to a first voltage supply, said drain of said first P
channel transistor being connected to said drain of said first N channel transistor, said source of said first N channel transistor for being connected to a second voltage supply having a voltage lower than said first voltage supply; and said second inverter comprising a second P channel enhancement mode transistor having a source and a drain, and a second N channel enhancement mode transistor having a source and a drain, said source of said second P channel enhancement mode transistor for being connected to said first voltage supply, said drain of said second P channel enhancement mode transistor being connected to said drain of said second N channel enhancement mode transistor, said source of said second N channel enhancement mode transistor for being connected to said second voltage supply; and wherein a threshold voltage of said first P
channel enhancement mode transistor is sufficiently higher than a threshold voltage of said second P
channel transistor that upon power-up of said memory circuit said first P channel transistor remains in an off-state and said second P channel transistor assumes an on-state, thereby causing said memory circuit to provide a logical 1 at said output lead of said second inverter at completion of power-up.
a first inverter having an input lead and an output lead;
a second inverter having an input lead connected to said output lead of said first inverter and having an output lead; and one and only one pass transistor, said pass transistor having a first source/drain, a second source/drain, and a control gate, said second source/drain being connected to said input lead of said first inverter and to said output lead of said second inverter;
said first inverter comprising a first P channel enhancement mode transistor having a source and a drain, and a first N channel enhancement mode transistor having a source and a drain, said source of said first P channel transistor for connecting to a first voltage supply, said drain of said first P
channel transistor being connected to said drain of said first N channel transistor, said source of said first N channel transistor for being connected to a second voltage supply having a voltage lower than said first voltage supply; and said second inverter comprising a second P channel enhancement mode transistor having a source and a drain, and a second N channel enhancement mode transistor having a source and a drain, said source of said second P channel enhancement mode transistor for being connected to said first voltage supply, said drain of said second P channel enhancement mode transistor being connected to said drain of said second N channel enhancement mode transistor, said source of said second N channel enhancement mode transistor for being connected to said second voltage supply; and wherein a threshold voltage of said first P
channel enhancement mode transistor is sufficiently higher than a threshold voltage of said second P
channel transistor that upon power-up of said memory circuit said first P channel transistor remains in an off-state and said second P channel transistor assumes an on-state, thereby causing said memory circuit to provide a logical 1 at said output lead of said second inverter at completion of power-up.
2. A memory circuit as in claim 1 in which said threshold voltage of said first P channel transistor is at least 0.5 volts higher than said threshold voltage of said second P channel transistor.
3. A memory circuit as in Claim 1 in which a doping level of said second P channel transistor is the same as a doping level of a well in which said second P channel transistor is located and a doping level of said first P
channel transistor is higher than said doping level of said second P channel transistor.
channel transistor is higher than said doping level of said second P channel transistor.
4. A memory circuit as in Claim 1 in which a doping level of said first P channel transistor is the same as a doping level of said second P channel transistor, and said first P channel transistor has a longer channel length than said second P channel transistor.
5. A memory circuit as in Claim 1 further comprising an output node connected to said output lead of said first inverter for supplying the output signal of said first inverter to a circuit external to said memory circuit.
6. A memory circuit as in Claim 5 further comprising an output node connected to said output lead of said second inverter for supplying the output signal of said second inverter to a circuit external to said memory circuit.
7. A memory circuit as in Claim 1 wherein the ratio of the ratio of the channel width to channel length of said first P channel transistor to the ratio of said channel width to said channel length of said first N channel transistor is less than 1.
8. A memory circuit as in Claim 7 wherein the ratio of the channel length to channel width of said pass transistor is less than the ratio of the channel length to channel width of said N channel transistor of said second inverter.
9. A memory circuit as in Claim 8 wherein the ratio of the channel length to channel width of said second P
channel transistor is greater than the ratio of the channel length to channel width of said pass transistor.
channel transistor is greater than the ratio of the channel length to channel width of said pass transistor.
10. A memory circuit as in Claim 1, further comprising:
means for precharging said first source/drain region of said pass transistor to a first selected voltage level prior to reading a signal stored on said second source/drain region via said pass transistor.
means for precharging said first source/drain region of said pass transistor to a first selected voltage level prior to reading a signal stored on said second source/drain region via said pass transistor.
11. A memory circuit as in Claim 10 wherein said means for precharging said first source/drain region of said pass transistor includes means for establishing said first selected voltage level as the trigger voltage of said first inverter.
12. A memory circuit as in Claim 1 including means for providing to said gate of said pass transistor a first selected voltage level during reading a data signal out of said memory circuit and a second selected level higher than said first voltage level during writing a data signal into said memory circuit.
13. A memory circuit as in Claim 12 wherein during reading a data signal out of said memory circuit said first selected voltage level is approximately equal to the trigger voltage of said first inverter.
14. A memory circuit as in Claim 12 wherein during writing data into said memory circuit said second selected voltage level is greater than said trigger voltage of said first inverter plus the threshold voltage with body effect of said pass transistor.
15. A memory circuit as in Claim 1 further including means for precharging said first source/drain of said pass transistor to a third selected voltage level prior to reading data from said memory circuit via said pass transistor.
16. A memory circuit as in Claim 15 wherein said means for precharging includes a P channel transistor having a source for connecting to a supply voltage, a drain connected to said first source/drain, and a gate for receiving a precharge signal for establishing said third selected voltage level as the level of said supply voltage.
17. A memory circuit as in Claim 15 wherein said means for precharging includes an N channel transistor having a gate for receiving a control signal, a source, and a drain for establishing said third selected voltage level as the voltage level of said control signal minus the threshold voltage of said N channel transistor.
18. A memory array comprising:
a plurality of memory circuits as in Claim 1; and a data line connected to said first source/drain of said pass transistor of each of said plurality of memory circuits.
a plurality of memory circuits as in Claim 1; and a data line connected to said first source/drain of said pass transistor of each of said plurality of memory circuits.
19. A memory array comprising:
a plurality of data lines;
a plurality of address lines;
a plurality of memory circuits as in Claim 1, arranged in a rectangular array, wherein each memory circuit in said plurality is attached to only one of said data lines and to only one of said address lines.
a plurality of data lines;
a plurality of address lines;
a plurality of memory circuits as in Claim 1, arranged in a rectangular array, wherein each memory circuit in said plurality is attached to only one of said data lines and to only one of said address lines.
20. A memory circuit comprising:
a first inverter having an input lead and an output lead;
a second inverter having an input lead connected to said output lead of said first inverter and having an output lead; and one and only one pass transistor, said pass transistor having a first source/drain, a second source/drain, and a control gate, said second source/drain being connected to said input lead of said first inverter and to said output lead of said second inverter;
said first inverter comprising a first P channel enhancement mode transistor having a source and a drain, and a first N channel enhancement mode transistor having a source and a drain, said source of said first P channel transistor for connecting to a first voltage supply, said drain of said first P
channel transistor being connected to said drain of said first N channel transistor, said source of said first N channel transistor for being connected to a second voltage supply having a voltage lower than said first voltage supply;
said second inverter comprising a second P channel enhancement mode transistor having a source and a drain, and a second N channel enhancement mode transistor having a source and a drain, said source of said second P channel enhancement mode transistor for being connected to said first voltage supply, said drain of said second P channel enhancement mode transistor being connected to said drain of said second N channel enhancement mode transistor, said source of said second N channel enhancement mode transistor for being connected to said second voltage supply and wherein a threshold voltage of said first P
channel transistor is sufficiently lower than a threshold voltage of said second P channel transistor that upon power-up of said memory circuit said first P
channel transistor assumes an on-state and said second P channel transistor remains in an off-state, thereby causing said memory circuit to provide a logical 0 at said output lead of said second inverter at completion of power-up.
a first inverter having an input lead and an output lead;
a second inverter having an input lead connected to said output lead of said first inverter and having an output lead; and one and only one pass transistor, said pass transistor having a first source/drain, a second source/drain, and a control gate, said second source/drain being connected to said input lead of said first inverter and to said output lead of said second inverter;
said first inverter comprising a first P channel enhancement mode transistor having a source and a drain, and a first N channel enhancement mode transistor having a source and a drain, said source of said first P channel transistor for connecting to a first voltage supply, said drain of said first P
channel transistor being connected to said drain of said first N channel transistor, said source of said first N channel transistor for being connected to a second voltage supply having a voltage lower than said first voltage supply;
said second inverter comprising a second P channel enhancement mode transistor having a source and a drain, and a second N channel enhancement mode transistor having a source and a drain, said source of said second P channel enhancement mode transistor for being connected to said first voltage supply, said drain of said second P channel enhancement mode transistor being connected to said drain of said second N channel enhancement mode transistor, said source of said second N channel enhancement mode transistor for being connected to said second voltage supply and wherein a threshold voltage of said first P
channel transistor is sufficiently lower than a threshold voltage of said second P channel transistor that upon power-up of said memory circuit said first P
channel transistor assumes an on-state and said second P channel transistor remains in an off-state, thereby causing said memory circuit to provide a logical 0 at said output lead of said second inverter at completion of power-up.
21. A memory circuit as in claim 20 in which said threshold voltage of aid first P channel transistor is at least 0.5 volts lower than said threshold voltage of said second P channel transistor.
22. A memory circuit as in Claim 20 in which a doping level of said first P channel transistor is the same as a doping level of a well in which said first P channel transistor is located and a doping level of said second P
channel transistor is higher than said doping level of said first P channel transistor.
channel transistor is higher than said doping level of said first P channel transistor.
23. A memory circuit as in Claim 20 in which a doping level of said second P channel transistor is the same as a doping level of said first P channel transistor, and said second P channel transistor has a longer channel length than said first P channel transistor.
24. A memory circuit as in Claim 20 further comprising an output node connected to said output lead of said first inverter for supplying the output signal of said first inverter to a circuit external to said memory circuit.
25. A memory circuit as in Claim 24 further comprising an output node connected to said output lead of said second inverter for supplying the output signal of said second inverter to a circuit external to said memory circuit.
26. A memory circuit as in Claim 20 wherein the ratio of the ratio of the channel width to channel length of said first P channel transistor to the ratio of said channel width to said channel length of said first N channel transistor is less than 1.
27. A memory circuit as in Claim 26 wherein the ratio of the channel length to channel width of said pass transistor is less than the ratio of the channel length to channel width of said N channel transistor of said second inverter.
28. A memory circuit as in Claim 27 wherein the ratio of the channel length to channel width of said second P
channel transistor is greater than the ratio of the channel length to channel width of said pass transistor.
channel transistor is greater than the ratio of the channel length to channel width of said pass transistor.
29. A memory circuit as in Claim 20, further comprising:
means for precharging said first source/drain region of said pass transistor to a first selected voltage level prior to reading a signal stored on said second source/drain region via said pass transistor.
means for precharging said first source/drain region of said pass transistor to a first selected voltage level prior to reading a signal stored on said second source/drain region via said pass transistor.
30. A memory circuit as in Claim 29 wherein said means for precharging said first source/drain region of said pass transistor includes means for establishing said first selected voltage level as the trigger voltage of said first inverter.
31. A memory circuit as in Claim 20 including means for providing to said gate of said pass transistor a first selected voltage level during reading a data signal out of said memory circuit and a second selected level higher than said first voltage level during writing a data signal into said memory circuit.
32. A memory circuit as in Claim 31 wherein during reading a data signal out of said memory circuit said first selected voltage level is approximately equal to the trigger voltage of said first inverter.
33. A memory circuit as in Claim 31 wherein during writing data into said memory circuit said second selected voltage level is greater than said trigger voltage of said first inverter plus the threshold voltage with body effect of said pass transistor.
34. A memory circuit as in Claim 20 further including means for precharging said first source/drain of said pass transistor to a third selected voltage level prior to reading data from said memory circuit via said pass transistor.
35. A memory circuit as in Claim 34 wherein said means for precharging includes a P channel transistor having a source for connecting to a supply voltage, a drain connected to said first source/drain, and a gate for receiving a precharge signal for establishing said third selected voltage level as the level of said supply voltage.
36. A memory circuit as in Claim 34 wherein said means for precharging includes an N channel transistor having a gate for receiving a control signal, a source, and a drain for establishing said third selected voltage level as the voltage level of said control signal minus the threshold voltage of said N channel transistor.
37. A memory array comprising:
a plurality of memory circuits as in Claim 20; and a data line connected to said first source/drain of said pass transistor of each of said plurality of memory circuits.
a plurality of memory circuits as in Claim 20; and a data line connected to said first source/drain of said pass transistor of each of said plurality of memory circuits.
38. A memory array comprising:
a plurality of data lines;
a plurality of address lines;
a plurality of memory circuits as in Claim 20, arranged in a rectangular array, wherein each memory circuit in said plurality is attached to only one of said data lines and to only one of said address lines.
a plurality of data lines;
a plurality of address lines;
a plurality of memory circuits as in Claim 20, arranged in a rectangular array, wherein each memory circuit in said plurality is attached to only one of said data lines and to only one of said address lines.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/777,670 | 1985-09-19 | ||
| US07/201,509 US4821233A (en) | 1985-09-19 | 1988-06-02 | 5-transistor memory cell with known state on power-up |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1323928C true CA1323928C (en) | 1993-11-02 |
Family
ID=22746110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000595793A Expired - Fee Related CA1323928C (en) | 1988-06-02 | 1989-04-05 | 5-transistor memory cell with known state on power-up |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4821233A (en) |
| EP (1) | EP0344894A3 (en) |
| JP (1) | JPH0224897A (en) |
| CA (1) | CA1323928C (en) |
| DE (1) | DE344894T1 (en) |
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| FR2877143A1 (en) * | 2004-10-25 | 2006-04-28 | St Microelectronics Sa | VOLATILE MEMORY CELL PRE-RECORDED |
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| US3644907A (en) * | 1969-12-31 | 1972-02-22 | Westinghouse Electric Corp | Complementary mosfet memory cell |
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| US4189782A (en) * | 1978-08-07 | 1980-02-19 | Rca Corporation | Memory organization |
| DE3032333A1 (en) * | 1980-08-27 | 1982-04-22 | Siemens AG, 1000 Berlin und 8000 München | MONOLITHIC STATIC STORAGE CELL AND METHOD FOR THEIR OPERATION |
| JPS58108095A (en) * | 1981-12-22 | 1983-06-28 | Nec Corp | Memory |
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| US4750155A (en) * | 1985-09-19 | 1988-06-07 | Xilinx, Incorporated | 5-Transistor memory cell which can be reliably read and written |
| EP0224887B1 (en) * | 1985-12-06 | 1992-03-11 | Siemens Aktiengesellschaft | Gate array arrangement using the cmos technique |
-
1988
- 1988-06-02 US US07/201,509 patent/US4821233A/en not_active Expired - Lifetime
-
1989
- 1989-04-05 CA CA000595793A patent/CA1323928C/en not_active Expired - Fee Related
- 1989-04-06 EP EP19890303408 patent/EP0344894A3/en not_active Withdrawn
- 1989-04-06 DE DE198989303408T patent/DE344894T1/en active Pending
- 1989-04-11 JP JP1091703A patent/JPH0224897A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0224897A (en) | 1990-01-26 |
| US4821233A (en) | 1989-04-11 |
| EP0344894A3 (en) | 1992-04-08 |
| EP0344894A2 (en) | 1989-12-06 |
| DE344894T1 (en) | 1991-07-04 |
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