CA1327081C - Reconfigurable counter apparatus and method of operation thereof - Google Patents

Abstract

RECONFIGURABLE COUNTER APPARATUS AND
METHOD OF OPERATION THEREOF
ABSTRACT OF THE DISCLOSURE
A reconfigurable counter is provided which includes first and second memories coupled via a common bus to a microprocessor which controls the process of configuring and reconfiguring the counter. A
programmable hardware array, coupled to the microprocessor, is capable of being programmed to emulate a plurality of different counter types. The first memory stores a plurality of different counter configuration profiles, each of which corresponds to a different type counter configuration. In one or more of the selected counter types, different counter modes such as an up-down counter mode, pulse direction counter mode and A quad B counter modes are available.
When the user indicates a selected counter profile to the microprocessor, the microprocessor writes the corresponding counter configuration profile from the first memory into the programmable hardware array using the parameters or modes of operation stored in the second memory until such time as the user indicates the choice of another counter profile to the microprocessor.

Description

~327~

-1- 30GF-lO08 RECONFIGUR~LE COUNTER APP~R~TUS
AND METHOD OF OPERATION THEREOF

BACKGROUND OF THE INVENTION

This inv~ntion relat~s in g~n~ral to hi~h spoed counters workin8 in conjunction with programmable logio controller~, el~ctronic procassors, or othsr host or operator interfac~ d~ice~. More ; particularly, tho inv~ntion r~lates to an apparatus and m~thod for providing a hiBh sp~od ~ountor which is r~configurable to ono of s~veral counter configurations.

'` 10 :;:
In the fi~ld of industrial and process control. a programmabl~ logic controll~r (PLC3 or industrial comput~r i~ frequ~ntly us~d to monStor input si~nals .: from a varioty of ~npu~ sensors which rspor~ ~ents ~ 15 and condition~ occurring in ~ controlled proc~3s. A
: PLC, for exampl~, can monitor suoh input conditions as ~; t~mperaturo, pr~sur~, volum~tric flow and th~ like.
A control pro~ram is stored in a m~mory to in~truct tho PLC as to what action~ to ta~o upon encount~ring particular input signal~ or conditions. In r~spons~
.
~"~

2~Q~

30GF-lO08 to th~so input signals, th0 PLC deriYe3 and ~noratos output signal~ whlch aro transmitt~d to various output d~vic08 to control the implemsntation of tho procoss.
For e~ample, th~ PLC issues output signals to op~n or closs a rslay, raise or lower t~mperatur~ and pre~ur~, or control the spood o~ a conv~y~r. a~ well a~ many other control functions.
Vary o~ten, how~v~r, proc~s data input repres~nt~d by puls~ trains ~ust b~ count~d at rats~
which exc~d th~ normal capabiliti~s of th~ PLC or th~
comput~r a~ the case may b~. Mor~over. differontial or quadratura inputs may bo requir~d which are ofton difficult or impossible to handle in conv~tional PLC
ladder logic. For thes~ rea ons. hi~h speed countors (HSC's) of varyinæ de~ign and compl~xity hav~ bo~n used in conjunction with PLC's.
Typically, th~ PLC is pro~ramm~d to acquir~ count information from a d~dicat~d counter at selected tim~s d~termined by tho application. For som~ applications.
simple up~down counters ar~ r~guired. For other applicatlons more complex counters such as A quad 8 oounters or bidir~ctionAl counters ars required. It is appar~nt that a do~ignor of PLC's whioh ~mploy hi8h speQd counters is confrontod with ~ wid~ ran~o of ~iff~r~nt hardwar~ ooun~r typ0s. Thes0 count~r typ~s ar~ couplod in divarse ways to a PLC, ~ach countor typo havin~ its own typ~ of interfac~ with th~ PLC.
In PLC applications 6cvsral counters ar~ often employod. The total number of count2r~ us~d in a PLC
applic~tion t~nds to b~ inversely r~lat~d to th~
count~r comple~ity. That is. th~ greatsr th~ numb~r of count~r~ us~d in a particular application, ~enerally the lesser is th~ complexity of each .

~3~7~ i 30~10 ~ 3 --counter. Convers~ly, when fewer counters ar~ ~mployod in a PLC application, such counters genorally t3nd to be mor~ complex. Tho quantity and diversity of count~rs which an ~l~ctronic~ di~tributor or user must stock in invantory to fulfill ~uch varying r~quir~monts i~ thu~ s~on to b~ r~lativoly large.
One obj~ct of the pr~80nt in~ention i8 to provid~
a hi~h sp~d countor (HSC) which may b0 p~ogramm~bly roconfi~ured to one of s~reral diff~r~nt hardwar~
count~r configurations.
Another .object of ths pr~sent inv~ntion is. to obYiate th~ n~od for stockin~ sovvral differ~nt typo~
of hiBh sp~d counter~ for U3~ in conjunction with : PLC's or oth~r host d~vicos.
15In accordancG with ona ~mbodimont of th~ pr~sent invention, a r~oonfi~urabl~ count~r i prvvid~d including a memory ror storing a plurality of usor solectable count0r profilc~ ch counter profi 19 rorrespondlng to a diffvr~nt typ~ of counter configur~tion. Th0 csunt~r include~ a s~l~ctor.
op~ratively coupled to th~ m~mory, for in~icating a s~lectcd countor profile desirod for th~ counter. Th~
count~r furthsr inclu~o3 a programm2bl~ hardwar~ logic array, respGn~iv~ to the sol~ctor, and which is confi~urabl~ to e~hibit th~ counter confi~uration corro-~pondlng to th~ sel~ct~d profil~.
;In accordanc~ with ano~hor embodim~nt of the r~ccnfigura~lo countor of th~ ln~ontion, i r~configurabl~ count~r i~ providod which includ0s a microproc~ssor for controllin~ tho confi~uration and reconfiguration of th~ count~r. Tho count~r includes a fir~t m~mory, couplod to ths microproce~or. for stor~nB a plurality of usor s~l0ctable counter profiles, aach count0r profile corr~sponding to a differont typ~ of counter configuration. Th~ count~r further includes a selector, couplod to tho microprocossor, for permittin~ a usor to sol~ct one o~
th~ count~r profilos storod in th~ flrst momory. Th~
prof i le which is select~d by the user i8 dosi~natgd th~ olected profile. Th~ count~r also includ~ a s~cond m~mory, coupled to th~ microproce sor, for storin~ variou~ usor sslectable paramotors (or modas of op~ration) for each confizuration. A pro~rammable hard~arG 103ic array is coupled to tho micrcproc~sor.
Th~ programmabls hardware lo~ic array is configurod to ~hibit a count~r configuration corr~ponding to tho s~lect~d proflle storod in tho fir~t momory and having u~r paramat~rs from th~ secont m0mory. To confi4ura or reconfigure the prosrammable hardwar~ logi¢ array of th~ counter, the microproc~ssor causes tho solected profile of th~ first m~mory to ba imposod on (or written to~ th~ pro~rammablo hardwars logic array so that it ~hibits a counter confi~uration corresponding . to tho sel~cted counter profil~ and ha~inB th~ usor -: param~tcrs of th~ second memory.
In yot anoth~r embodiment of the invention, a r~confi~ura~le countor apparatu~ is provid~d which includes a momory for storin~ at le~st first and ~ocond u~or sol~ctable count~r profi 1~8, ~ha f i rst profile corr~spondin~ to a plurality of count~rs sxhibitin~ a first counter typ~, th~ s~con~ profilo correspondin8 to first and s~cond count~rs aach of ; 30 which aro capa~l~ of assuming first and s~cond usor soloctabl~ mod~s. Tho count~r appAratus furth~r includ~s a first sel~ctin~ d~ice. oporative1y coupled to th~ momory, for sel~cting a d~irod counter prof i 1~

~ ~ 2 ~

30CF-lO08 _ ~ _ for tho r~configurable counter apparatus thu~
dosignatlng on~ of the fir~t and s~cond count~r profi le8 as boing a solect~d counter profil~. Th0 counter apparatu~ includes a sRcond sal~ctin~ d~vic~, oporativ0ly coupled to the memory. for selo6tin~ a d~sirod mod~ for each of th0 first and socond count~r~
wh~n the s~lected counter profilo i~ the socond counter profile. For convenienca, tho s~cond s~lecting d~vice may be combin~d with the flrst s~locti.n~ dovicc. Th~ countor apparatu~ furthor includ~ a programmable hardwaro logic array, re~ponsiv~ to ~ho first and s~cond salectin~ devic~s.
for ~hibiti n~ a count~r configuration corr~spondin8 to tha s~l~cted counter profile an~ any s~l~cted mode~.
Although for purposes of 0~amplo, the reconfigurabl~ countQr discus~ad and shown h~rsin is b~ing us~d in conjunctio~ with a PLC. tho counter n~d not necessarily ba us~d with a PLC. It may ind~d b~
us~d with various host devic~ (such as a p~rsonal comput~r) or bo usod stand-alone~ with variou~
opsrator int~rfac~ devic~ such a~ the typical k~yboard or k~ypad. O~her applications will b~
appar~nt to thos0 s~ d sn th~ art.

~

Tho f~atur~ of th~ invvn~ion beli~vod to b~ nov~l ar~ sp~cifically set forth in tho appond~d claim~.
How~v~r, th~ inv~ntion its~lf, both as to its structuro and m~thod of op~ration, may be~t bo und~rstood by roferrin~ t4 tho followin~ d~scription ~ 3 ~

3~ lOO~

tak~n in conjunction with tho accompanying trawin~s in which:
FIG. 1 i~ a g~naraliz0d block dia~ram of a roconfigurable high spood counter in accortanco with the teachinss of tho pr~nt in~ention;
FIG. 2 is a mor~ tetail~d ~ys.~m bloc~ dia~ram of the rQconfigurabl~ hi~h speod ~ounter o~ FIG. 1;
FIG. 3 is a ~ymbolic dia8ram of a programmable hardwar~ array configur~d to a Typ~ A r~lativoly low 1~ complaxity counter configur~tion;
FIG. 4A is a sin~ ended input ~ignal conditioning circuit which is coupl~d to s~locted counter input~;
FIG. 4~ is a diff~r~ntial input sign~l lS conditio~in8 circuit which .i~ coupl~d to oth~r s~l~cted counter inputs;
FIG. 5 is a symbolic dia8ram o~ a programmabl~
hardwar0 array configured to a m~dium complaxity Typ~
B counter confi~uration:
FIG. 6 is a symbolic diagram of a programmablo hardware array confi~ured to a r~lati~ely high compl~xity Typa C counter conf iguration:
FIe. 7A r~pres~nts a count input ~ignal and count occurrenco in tho up-counter modo for tho Typ~ A
count~r o~ FIG, 3:
FIG. 7B r~pr~nts a count input si~nal and count occurr~ in the do~n-count~r mode for tho Typo A
countsr o~ FIG. 3;
FI~. 8A repre~ents a count input signal and count occurrenc0 in the up-count~r mod~ fcr the Typo B and : Type C counters:

~2~3~

30GF-lO08 FIG. 8B repre~nt~ a count input signal and count.
occurrenc~ in th~ down-count~r mod~ f or th~ Type B and Type C counters;
FIG. 9A repres~nt~ th~ count and diraction input signal~ and the count occurr~nco for the puls~
diraction countcr in tho Typo C countor;
FIG. 98 repr~s~nts th~ count and dir*ction input signals and th~ count occurr~nco for tho puls~
direction oount~r in tho Typo-C counter;
1~ FIG lOA show~ input sign ls and count occurronc~s for up-countin~ with an A quad B counter in tho Typa B
~ and ryp~ C countsrs;
FIG. lOB shows input si~nals ~nd count occurrenc~
for down-counting with an A quad B countor in th~ Typo B and Typ~ C count~rs; and : FIG. ll is a goneralized flo~chart o~ th~
operation of a reoonfigurabl0 count~r in accordance with the teachin~s Or tho pr~sent invantion.

In accordanca with one embodi~nt of tho pre~snt inv~ntion, FIGo ~ show~ a hiBh spo~d count~r (HSC) lO
includin~ a plurality of counter inpu~s 15 and a plur~lity of ounter outputs 20. In one applacation of th~ invontion, count~r input~ 15 ar~ supplied with . .
2S data ~ignals from a controlled proce3s (not shown).
althou~h cl~arly th~ inv~ntion may b~ us~d to monitor oth~r data signals a~ well. HSC lO furthor includ~s a roconfi~urabl~ counter portion 2~ which is configurabl~ in a plurality of diff~r~nt count~r topolcgie~ to provido diffarent usor~sele~table r~

30GF~ 08 count~r characteristios. Counter input~ 15 and countar outputs 20 extond from counter portion 25. A
microproces~or 30 i~ couplod to reconfi~urable counter portion 25 to ~nable microproc~ssor 30 to in~truct counter portion 25 whi~.h countor co~fi~uration to e~hibit.
An input d~vice 35 such a~ the G~niu~ Input/Output hand-h~lt monitor manufactured by GE Fanuc Automation N.A., Inc. (~E Fanuc~ is eoupled via a bus 33 to microproc~ssor 30 to. enabl~ tha user to instruct microproc~ssor 30 as to which ona of a plurality of counter configuration3 is d~sired. Tho Genius I/O bu~
d~signed by GE Fanuc is an exampl~ of one bus which may b~ employe~ a~ bus 33. Mcr~ informatio~ with r~spect to thes~ d~vice~ is disclose~ in publish~d product bullstin~ on theso products ~nd aro availa~le from GE Fanuc Automation N.A., Inc., Ch~rlott~svill~.
Vir~inia.
A plurality of differ~nt counter configuration param~ter fil~s are stor~d in a non-volatile msmory 40 which is coupled to microproc~ssor 30. A programmable read only m~mory (PROM) such a~ an erasabIo programmabl~ road only memory (EP~O~, for ~xample. i5 con~nisntly u~d a~ m~mory 40 althou~h othsr type~ of momori~ may be employod a~ well. In on~ embodim~nt of th~ inY~n~ion, the us~r s~locts one of thr~
count~r confi~uration paramoter file~ which are stor~d in m~mory 40 by indicating such choi~ on input do~ira 35. On co~mand from input dovic~ 35, or ~ power up microproc~ssor 30 s~lect8 one of the thre~ count~r configuration paramot~r fil~ in m~mory 40 and caus~
: microproc~ssor 30 to pro~ram tho s~l~cted counter configuration into the reconfi~urablo counter porti on ~,~2rJ~g~, _ g _ 25. A socond m~mory 45, which may b~ ~lectrically ~rasabl* ~ 8-. an EEPROM). but which i~ pr~fera~ly nonvolatile in any ca~e, stor~s various us~r ~ s,. param~ters which aro sel~ctabls for furthor ~ -S c~nfi~uration of th~ ~olected count~r pro~lle. M~mory also s~rves as a pointer or s~lector d~vico since microprocessor 30 looks to that momory for instructions a~ to which confi~uration from m~mory 40 i8 to b~ s~loctod. Tho user paramot~rs of m~mory 45 ar~ im~osed on th~ select~d configuration programm~d into tho reconfigurabl~ counter portion 25.
Also conn~cted to bus 33 is a pro~rammable lo~ic controller (PLC) 37 which deriv~ information ~rom hiBh sp~d count~r 10 in tho u~ual modo of op~ration of pro~rammabl~ logic oontrollers used in conjunction with hiBh speod count~rs. That i~, from timo to timo PLC 37 acquir~s count information from count~r lO as th~ r~quirements of tha particular application dictate. It will be apparent, howev~r, that PLC 37 and input d~vice 35 may bo combined into a single host devic~, such as a personal compu~er. . Alt~rnatively.
if no control functionality is d~sir~d, the configurable counter of tho pr~ ~nt inven~ion m~y bo a "3tand-alon~" confi~urabla counter in which ca~ PLC
37 and input d~vico 35 mi~ht tak~ th~ form of various op~rator inter~ace dovice~ (e.g., a keyboart) for simply inputtin~ us~r paramet~r~ and count~r configuration s~l~ction.
On~ embodim0nt of hi8h sp~d counter (HSC) lO i5 shown in mor~ d~tail in th~ block diagram of FIG. 2.
In this particular ~mbodim~nt. roconfigurabl~ counter portion 25 includes an input signal conditionin~
circuit 26 for conditioning and buffering data signals ~27~

- -- 10 -- , which aro provid~d to conditionin~ circuit 26 from a controlled procosa or other sourco. Conditionin~
c~rçuit 26 includ~s twslve lnputs 15A-15L as s~en in FIG. 2. Thos0 counter inputs 15A-15L provido count~r control functions such as count signals, count dir~ction, count disable, proload, markor and stro~o.
Count3r inputs 15A-15L may b~ confi~urod as n~c~ssary for each count~r configuration typo a~ will b~
explain~d lat~r. Aft~r conditioning and buff~ring tho data si~nals, conditioning circuit 26 provid~s the rosultant condition~d data signals to a programmable .~ hardwar~ array 46 which is coupled to conditionina circuit 26. Ono programmabl~ hardwar~ array which may be employ~d a~ array 46 is a X~LINX devic~ currontly manuf~ctur~d by XILINX, Inc. 3nd Ad~ancod Micro Devices (AMD). Programmablv hardware array 46 is configur~d or programmod to exhibit on~ of thro~
count~r confi~urations which is solected by th~ usor V i a i npUt daY i C~ 35. Th~ mannor in which array 45 is confi~ured will b~ discuss~d in mora dotail lat~r.
Programmabl~ hardware array 46 then performs counting op~rations on tho condition~ data signals pro~id~d ther~to accor~ing to ~he par~icular countor configuration which ha~ b~on soloc~ed for array 46 by tho usor and having cortain usor param2t~r~ s~lect~d by th~ u~sr. An output driv~r cirGuit 47 is eoupled to miCroproC98~0r 30 via bus 32 a3 shown in FIG.
such that ona or moro coun~ signals are providod to output driver circuit 47. In this particular ~mbodiment of th~ inv~ntion, array 46 may b~
configured to b~ on~. two or ~our countors of varyin~
compl~xity. Thus, output drivor circuit 47 i~
provid~d with four outputs 20A. 20B, 20C and 20D

7~

30C~-1008 whoroin for th~ least compl~x counter configuration (four simplo counters) on~ output i5 provited for 0ach of tho four simplest counters; ~or the modium comple~ity count~r confi~uration (two counters~ two output~ por counter ar~ provided; and for th~ most compl~x counter configurution ~1 countor) all four output~ aro provided to th~ single complex counter.
Counter outputs 20A, 20B, 20C and 20D ar~ a~ailable to th~ us~r for drivin~ ~t~r~ally conn~cted d~vices ~uch as ind.icating lights. sGl~noids or relays a~ may be d~sirod in r~sponss to a particular condition (count value) of tho accumulators (discu~d lat~r) in hi8h sp~od counter 10.
Counter portion 2S includo~ a logic intorface 48 whioh couples programmabl~ hardwar~ array 46 to microproc~ sor 30 as shown in FIG~ 2. ~ common bus 32 coupl~s microproc~ssor 30 to P~OM 40. EPROM 45.
programmablo hardware array 46 and logic interfaeo 48.
Microprooessor 30 is al~o conn~c ~d by lo~ic bus 32 to 20 . a random acc~s~ memory (~AM) 50 which provide temporary stora~ m~mory which i8 usod by microproc~ssor 30 as ik operat~s. A clock o cillator is couplod to mi~roproco~or 30 to provid~ a timo ba~o si~nal or system olock si~n~l for microproce~or 30; In this particular e~bodim~nt of th~ inv~ntion, o~cillator 65 opora~e~ at a fre~u~ncy of 1O.B8 MH2.
al~hough those s~illed in tho art will apprcoiate that othor cloc~ oscillator fr~qu~ncio~ may b~ ~mploy~d a~
w~ll ln othor embodimonts of th~ inv~ntion.
Microprocos~or 30 include~ a ~ariable frequ~ncy oscillator which is couplod to dr~v~r circuit 55 via bus 32. Oscill~tor circuit 55 includ~s an output 60.
The frequ~ncy of th~ os illator output signal ~7~

30~F~l008 ^ - 12 - ~

g~norat0d at oscillator output 60 is programmably controlled by microprocessor 30 as will b~ s~en lat~r.
Counter lO includss a DC pow~r supply 75 which supplios all of th~ DC operati~g voltage~ r~quired by th~ circuits and dovic~s of hi~h spo~d counter lO a~
symbcliz~ by tho connoction botw~r supply 75 and microproc~ssor 30. For sak~ of br~vity, tho conn~ctions of pow~r supply 75 to th~ r~mainin~
circuits and deviees of coun~r lO ar~ not shown. A
suitable de~i~n for DC pow~r supply 75 is ~ll known t~ those skilled in the art.
A bus int2rface 70 is coupled betwe~n pro~rammabl~
lo~ic controll~r 37 and microprocessor 30 a~ shown in FIC. 2 to int~rfac~ controllor 37 with microproca~or 30.
It will b~ r~c ll~d that microprocos30r '30 iS
coupled to EEPROM 45 which contain~ th~ user parameters which may b~ imposed on th~ s~lect~d count~r confi~uration. Th~ content~ of momcry 45 ars used by microproc~s~or 30 followin~ tho power up soqu0nco to configure th~ pro~rammable hardwaro array 46. Thus, m~mory 45 s~rve~ also a~ a pointar or seleotor to indicate to microproo~gSor 30 which of the confi~uration~ from m~mory 40 is to be programm~d into th~ hardwar~ lo~ic array 4~. In this particular em~odim~nt of th~ in~ention, thr~ diff er~nt coUntar oonfiguration fil*s ar~ stor~d in PROM 40. Thoso count~r confi~uration file~ ar~ alternativ~ly r0f~rred to as configuration profilo~ h~rein. The user can 501ect any on~ of the thr~o counter oonfiguration file3 (profiles). Thos~ skill~d in tho art will appr~ciato that a ~r~ater or le~s~r numb~r of countor configuration files may be store~ in PROM 40 for ~ 3 ~

30CF-lOOB

. ~
s~lsction by th~ us0r. In the present embotim~nt, th~
thro~ count~r configuration paramoter file~ corr~spond to threo different counter configuration~ d~signated Typo A, Typo B and Typo C which may bo pro~rammed into pro~r~mmablo hardwaro array 46. Tho nature of Typo A.
Type B and Typo C count~r configuration~ will be d~scribet in mor~ d~tail sub~gu~ntly. Tho user sel~cts th~ d~sired onc of counter confi~uration Typos A, B and C and indicatoY that choic~ to miCroprocQ~sor 30 via input deviee 35 or other suitabl~ host device.
Microproc~ssor 30 th~n writes tho count~r confi~uration paramot~r file corr~sponding to tho sol~cted countor typ~ to array 46. The usor paramotor fil~ continue~ to resid~ in EPROM 45 even after power to counter 10 is turn~d of r. Thu~, on subsequ~nt pow~r up s~quences EEPROM 45 is look~d to as a point~r or selector so that th~ samo couater confi3uration file which w~s stored earlier in EPROM 45 is used to determine how to configuro array 46 from the oonfiguratio~ file~ in PROM 40 and the us~r parameters in EEPROM 45 until such timo a3 tho user loads a different user param~t~r file into EEPROM 45.

rh~ r~confi~uration of high spood count~r 10 und~r u~er control to ono of sev~ral counter type~ ( Typ~5 A .
B or C) consoqu~ntly redofines the input~ 15A-l~L and th~ outputs 20A-20D of hi8h sp~od count~r 10.
Mor~over, th~ int~rnal structur~ of pro~rammable hardwar~ array 46, is reconfigur~d according to th~
particular count~r type s~lected. For example, when ~ 3 ~

30GF~ 1 OOES

th~ u~or s010cts a Typo A countor confisuration, array 46 i9 configured into four ~ndepend~nt substantially 8imi lar counter~ lO0, 101. 102 and 103 a~ shown in tho symbolic diaBram of FIG. 3. Although count~rs 101, 102 and 103 ar~ e~sentially th~ ~amo a~ count~r 100, the intornal structur~ of countor~ 101, 102 and 103 is n~verthel~ss shown in FIG. 3 along with the int~rnal structur~ 100 for sak~ of co~plat~n~3.
Wh~r~a~ thn oporation of Typ~ A countor 100 will bo doscrib~d in d~tail subs~quently, th~ op~ration ~f ths indepond3ntly operating roplicato Typ~ A countors lO1, 102 a~d 103 is undorstood to b~ substantially similar to th~ operation of Typ~ A countor 100. Typo A count~r 100 input t~rminal 15A i8 analo30u~ in operation to th~ Typ~ A count~r 101 input torminal lSD~ Typo A countor 102 input tGrminal 15G and Typs A
countQr 103 input terminal 15J. In a like mann~r the rospoctiv~ Typ~ A count~r input terminals 15~, 15H and 15K ar~ analoRous in th~ir op~ration to Typ~ A Counter 100 input t~rminal 15B. Si~ilarly, t~r~inals 15F. 15I
and 15L ar~ analogou~ in thsir oporatlon to Typo A
count~r lOQ input t~rminal 15C. Furthermor~. Typo A
coun~r outputs 20B. 20G and 20D ~ach hav~ analogous op~rational characteristics to tho oporational charact~ri~tics of Typo A count~r lO0 outpuk 20A.
Typ~ A counter 100 inolu~s a counter pr~load input 15A which is coupled via conditioning circuit 26 to pr~load r~gister 115. Pr~load r~ister 115 may b~
s~t to any valuo within th~ csunt~r rangs as will be shown lat~r. Preload register 115 is conn~ct~d to a preload input of accumulator 120 a~ shown in FIG.
3. Count~r input 15B i5 also coupled to an input of accumulator 120. Preload r~Rist~r 115 i3 normally rd~

30GF- ~ 008 -- 15 ~

u~od to porform a ro~t function and can load its r~gister cont~nts into accumulator 120 upon r~ceivin~
tho prop~r input -~ignal from proload input 15~. Tho cont~nts of pr~load rs8i~tor 115 are alæo load0d into tho accumulator 120 durin8 th~ pow~r up s~qu~nce of hiBh spe~d counter 10.
Accumulator 120 of counter 100 is coupl~t to a tim~ ~as~ r~8i~t~r 130 and to a ~trobo rs~istor 135 to which is coupled a strobe input 15C. Aft~r the application of th~ prop~r signal to strobe input 15C, tho contents of accumulator 120 are load~d into strob~
regist~r 135. In th~ pr~ferr~d embodim~nt of tho invention, strobo input 15C i~ sensativ~ to sign.l ed~es an~ can be programm~d to rospond to eith~r a positive ~ignal edg2 or a ne~atiY~ si~nal o~e. ~h~n th~ appropriate signal e~8~ occurs at input 15C, th~
contonts of accumulator 120 are copied into strobe register 135, thus ov~rwriting th~ pr~ious conterts of strobe register 135. Thi~ permits a count val~e to be captur~d in responso to an e~tornal event (strobo) without affecting th~ counting proco~s itsolf.
It is notod that in th~ dirf~rent pos~ibl~ count~r configuration~, counter input~ u~d a~ strob~ inputs ar~ edg~ æ~nsitiv~. Th~ activ0 strob~ nal edge.
wh~ther it 1~ a leading edg~ or a trailing edg~, i8 d~fin~d by tho counter confi~ura~ion to ~p~cify eithor ths positiv~ leading ed8~ or n~ativ~ trailing strobo signal 0~8~ to b~ ~ctivo.
; At pr~d~t~rmined timo bas~ interv~ls th~ content~
of acoumulator 120 are loadet into tim~ bas~ r~gister 130. In thi~ embodim~nt of th0 invontion, timo b~s~
regist3r 130 is a 16 bit re8ist~r which contains the number of counts that have occurred in a s~l~ot~d tim~

30GF-lQ08 p~riod exhibitin~ a duration betweon 1 millisecond and 65535 milllsoconds. Tho tim~ poriod i8 solected by pro~rammabl~ lo~ic controller 37 via bu~ 33 and interfaca 70.
Accumulator 120 in cou~tor 100 i~ coupled to output comparator 27~. Counter 100 includ~ a pr~s~t regist~r 150 with pr~set valu~, an ON point and an OF~ point b~in~ a~sociatod th~rowith. Tho pres~t register 150 is also conn~cted to output driv~r 27A
which include~ an output 20A. Outp~t 20A of output driver 27A indicates wh~n the cont~nt~ of accumulator 120 ar~ botween tho two pros~t valuos contained in pr~set r~ist~r 150. The polarity of th~ output 20A
can b~ configured by pro~rammabl~ logic controll~r 37 to b0 ON betwe~n the two preso~ valu~s. Tho s~t point condition can bo configured by pro~ra~mabl~ lo~ic controll~r 37 to eith~r inclute or exclude th~ pr~s~t points.
The contents of strob~ register 135. tim~ base r~ister 130, preload register 115 and ON/OFF prcs~t registers 150 ar~ mad~ a~ailable to pro~rammablo logi controller 37 each time that th~ hi~h sp~ed counter 10 i5 int~rrogat0d by controller 37 via bu~ 33 a~d bus interfaco 70. In addition, contr3110r 37 c~n writ~ to pr~load r~gist~r 115 and to pr~set re~istor 150 a~
r~quirad for th~ normal op~ration of hi~h speet count~r 10. Th0 time base valu~ controlling th~ tim0 bas~ r~gister 130 is programmed by programm~bl~ logic controller 37.
In a manner similar to count~r 100 So which output driver 27A i~ coupled, output dr~v~rs 27B. Z7C and 27D
aro coupled to count~rs 101. 102 and 103 a~ s30n in ~21~8~

. 30GF-1008 FI~. 3. The outputs of driv~rs 278. 27C and 27D form outputs 20B. 20C and 20D, rospectiv~ly.
It will b~ r~callet that in tho present ~xample, hi~h spe~d count~r 10 ha3 beon rsconfi~ured into th~
Type A counter configuration, namely, four substantially similar and ind~p~ndont Typ~ A count~rs are confi~ured in the pro~rammable array 46. Type A
counter 100 is replicated four tim~ in array 46 a3 r~presented by countors 100, 101, 102 and 10 Statsd altern~tively, programmable hardware array 46 ha~ boon configured to represont four ind~p~ndontly op~ratin~
ossentially identical count~rs of th0 Typ~ A counter configuration. It is not~d that all twolv~ input~
15A-15L and all four outputs 20A-20D have bo0n 15 ut i 1 i z?~d .
It will also bo rooallod that data si~nals supplied to the countsr inputs 15A-15L are conditioned and buffer~d in r~p~ctiv~ input signal condition~rs collectiv~ly shown a~ conditionor 26 in FIC. 2 and 2~ FIG. 3. A~ s~n in FIC. 3, each of input~ 15A-15L is provaded with a r~sp~ctiv~ input signal condition~r 26A-~6L. Input signal condi~ion~rs may be of two different typo~, namsly sin~le endod input or differontial i nput . A mixtur~ of sin~ ndod input si~nal conditlon~r~ and di~for~n~ial input signal conditionors ar~ u~od a~ condition~rs 26~-Z6L in conditioner 26. It is not~d that input ~i~nal conditionors 26 aro fix~d, that i 5, conditionors 26 ar~ not a part of th~ pro~rammable hardware array 46.
FI~. 4A shows ~ typical singl~-ended contitioning circuit 226 which ma~ bo employ~d a~ on~ or mor~ of the conditioning circuits 26A-26L in ~i~nal conditioner 25. In conditioning cirouit 226 a single-3~3 ~

~ end2d signal input 215 is coupled via a r~sistor 220 to th0 n~ativo input 225 of diff~rontial amplifi~r 230. Nagative input 225 is coupl~d via a r~3istor 235 to a tcrminal 240 on which a z~ro voltag~ is impr~od. Tho positivo input 245 o~ differ~ntial amplifier 230 is connectad via a resistor 250 to a t~rminal 25~ on which a s01~ct~d ref~r~nce voltag~
pot~ntial is impressod. In th~ pr~ferr~d ~mbodimont of the inv~ntion, r~istor~ 220, 235 and 250 each hav0 r~sistance ~aluos of appro~imat~ly 2000 ohm~. ~ach of th~ inputs 15A, 15C, lSD, 15F, 15G~ 15I, l~J and 15L
is coupled throu~h re~p~¢tiv0 sin~le ended conditionin~ circuits typifiod by conditionin~ circuit 226 to count~r~ 100, 101, 102 and 103 in tha mann~r ~hown in FIC. 3. That i~, single ~nd~d conditioning sircuits such as conditionin~ cireuit 226 ar~ employ~d for conditionin~ circuits 26A. 26C. 26D~ 26F, 26C.
26I, 26J and 26L. Th~ romaining con~itioning circuits 26B, 26E, 26H and 26K employ differsntial input conditioning circuits such a~ dif~er~ntial input conditioning circuit 3 6 shown in d~tail in FI~. 4B
and discu~s~d below.
More ~p~cifically, FIG. 4B shows a typical diff~r~ntial input cenditionin~ circuit 326 includin~
a si~nal input 315 which is coupled via a resistor 320 to the nogativ~ input 325 Or a diff~r~ntial amplifler 30. N~ativ~ input 3~5 i8 couplet via a re~istor 335 t~ a t~rminal 340 on whioh a zoro volta~o is impres~ed. A si~nal input 316 i~ coupled via a resistor 3~1 to the positive input 345 of differ0ntial amplifier 330. Positive input 34$ is cuupled via a rosistor 350 to a t~rminal 3S~ cn which a selected reference voltag~ potential i5 impr~s~d. Input 315 ~7~

3ûGF- 1 0û8 and input 316 form a diff0rential input pair. In tha pr~f errad embodiment of this invention resistors 320.
321, 335 and 350 each have resistance valueæ of approximatoly 2000 ohm~.
Each of inputs 15B, 15E, 15H and 15K of th~ Typ~ A
count3r of FIG. 3 ar~ coupled to differ~ntial input signal conditioning circuits such as cirouit 3~6.
That isi differenti~l input signal conditioning circuit 326 i 5 employ~d as signal conditionin8 circuits 26B, 26E. 26H and 26K in ~IG. 3. It is noted that althou~h, inputs 15~, 15E, lSH and 15K ar~
differ~ntial inputs, they can bo ussd as single endod inputs by leaving th~ reæp~ctive terminal~
corr~pondin~ to ~h~ n~ativ~ diffar~ntial input 316 unconnQcted.
Each of tho tw~lve inputs 15A-15L is provid~d with a high frequency nois~ filt~r (not shown) of th~ typ~
which passo~ count~r si~nals at frequencies pr~ferably up to 200 Kiloh~rtz but att~nuates hi8her fr~qu~ncy noise componsnts. It i~ noted that input signal conditioning circuit 26 can b~ confi~ur~d by prosrammabl~ logic controllor 37 to provit0 control : inputs 15A, 15C, l5D, 15F, l~G, 1~I, 15J ant 15L with r~poctiv~ low fr~guency filt~rs (not shown) on an individual counter basis. Such low fr~quency signal ~lt~rs aro used to ~liminats erronoous signal fluctuations .which may b~ present tuo to contact bouncin~ in a~ociat~d procass equipmont. Tho d~ n ard construction of the such noise filter~ aro w~ll known to thos~ skillad practitionars of the art and is not detailed h~r~in.
Th~ status or state of e~ch of outputs 20A-20D is always mada av~ilabl~ by programmable hardwar~ array 30GF-1 oas 46 to programmabl~ logic controller 37 via microprocossor 30, bus 32. bus 33 and bus interface 70. Similarly, pro~rammable lo~ic controll~r 37 can access the stat~ of tho various regist~rs withi~ ~ach counter.

TYPE B COUNTER CONFIGURATION
.

FI~. 5 shows a symbolic diagr~m of programm~bl~
hardwar~ array 46 reconfigured into a Typ~ B count~r configuration which includ~s two ind~pend~ntly op~rating m~dium compl~xity counters 104 and 105.
Althou~h countor 105 is substantially similar to counter 104, the structur0s of both count~rs 104 and 105 are illustrated in d~tail in FIG. 5 for sak~ of completenes~. Althou~h programmable hardware array 46 of FIC. 5 i~ confi~ur0d with Typ~ B count~rs, it is not~d that thos0 inputs 15A, 15C, 15D, 15F. 15G, 15I.
15J and 15L which wor~ singlo-ended inputs in the Typ~
A count~r confi~uration of FIG. 3 aro lik~wis~ single-end~d in tho Typo B count~r configuration of FIG. 5.
Similarly tho ~ inputs 15B. 15E. 15H and 15K which wer~ diffsrontial input~ in tho Typ~ A counter confi~ur~tion of ~IG. 3 ar~ likewi~o diff~r~ntial in tho Type 8 counter configuration o~ FIG. 5. In comparin~ the configurations of FIG. 3 and FIG. 5, liko numerals ar~ us~d to d~si~nat~ liko elemcnts. It is not~d that many elem~nts are common bet~d~en th~
Typ~ A configuration of FI~. 3 and th~ Typ~ B
configuration of FIG. 5, although th~ connoction~
betw~en such elom~nt~ may vary a~ sub~equently d~scribed.

P8~

Type B counter configuration 104 includes an input15A which is coupl~d to the input of preload r~gist~r 115. The output of prsload r~ister 115 is coupled to an input of.an accumulator 120A. Countor input 15B, countor input 15E and di~abl~ input 15G ar~ coupled to r~spoctiv~ inputs of accumulator 120A. Accumulator 120A is coupled to ono anput of output triver ~7A and to one input of output drivQr 27B as shown in FIG. 5.
A f irst ONIOFF pr~sot re~ist~r 150A is coupled to tho rem~inin~ input of output driver 27A. Output driver 27A is coupl~d to output 20A. A second ON/OFF pre~t re~ister 150B is coupled to th~ remaanin~ input of output driver 27B~ Output triver 27B is coupled to output 20B.
Each of th~ two above montioned preset ro~ist0rs 150A ant 150B have two pr~set values a$sooiatod therewith, namely an ON point and an OFF point. The state of output 20A of output dr;v~r 27A indicates when th~ cont~nts o~ accumulator 120A are betw~n th~
preset valu~s contained in presot regist~r 150A. Th~
st.te o~ output 20B of output driY~r 278 i~dicak~s wh~n the cont~nts of accumulator 1208 ar~ botwson th~
preset valu~ contain~d in th~ pres~t reg;st~r 150B.
Th~ polarity of outputs 20A and 20~ can be configured by-pro~rsmmabl~ logic controllor 37 to be ON (~5 volts or gr~at~r~ botwe~n tho two pre ~ valu~s or OFF (O
volts~ b~two~n th~ ~wo preset value~. Th~ s~t point condition c~n conv~niently b~ confi~ured by tho programmablo logic controller 37 ei~hsr to includ0 or exclud~ th~ pr~s~t points.
Accumulator l~OA is coupl~d to tim~-baso r~ tor 130 into which the accumulator 120A contents ar~
load~d at re~ular tim~d intorvals dep~nding on the ~1 ~ 2 ~ 8 ~

3UGF~1008 s~1ected time base interval. In th~ proferrod embodimont of th~ inv~ntion, tim~-baso register 130 is a 16 bit re~ister which contains the number of counts that hav~ occurr~d in a s~lectod time pariod of betweon 1 millis~cond and 65535 miiliseconds. Tha time period i3 s01ect~d by th~ pro~ramma~lo lo~ic controller usin~ intorface 33. Th~ abo~e tim~ period is ~iv~r for purpose~ of example. It should b~
und~rstood that tho inv~ntion is not limit~d to such a timo p~riod and that oth~r shorter or longer tim~
periods may also b~ attained.
Accumulator 120A is also coupled tc a first strob~
r~gister 135A and a s~cond strob~ regist~r 135~ such that tho accumulator contents aro provid~d th~roto.
Strob~ r~gisters 135A and 135B includ~ inputs 15C a~d 15F, r~spectavely. Wh~n an appropriate si~nal is introducet to input 15C which is coupled to an input of first strobe r0~ister 135A, the contents of accumulator 120A ar~ down-loaded into flrst strob~
re~ist~r 135A. Similarly, wh~n an appropriate signal îs introduc~d to input 15F of second strobe register 1358, tho contents of accumula~or 120A are down-loaded into second strobe rQ~iSter 135B.
In the pr~ferred embodiment of th~ inv~ntion.
strob~ inpu ~ 15C and 15F are sonsitive to signal ed~es ant can b~ pro~ramm~d to r~gpon~ to either a posita~e edg~ or ~ n~atiYe ed3e of a data si~nal.
~h~n tho appropria~o signa1 ed~e occurs on input 15C.
th~ contents of the accumulator 120A ar3 copiod into 3~ strobo rogister 135A thus ov~rwritang th~ pr~vious contants of strob~ regist~r 135A. When the appropriata si~nal edg~ occurs on input 15F, tho contents of th~ accumulator 120A aro copi~d into 36~ g - ~3 -strobe re~ister 135B thus ov~rwri~ t-h~ provious contents o~ strob~ r~gister 135B.
Tho cont~nts of stroba r~gistors 135A, 135B, tim~-bas~ re~ister 130, pr~load r~gist~r 115, and ON/OFF
pr~s~t r~ist~rs 150A and 150B ar~ mad~ a~ailabl3 to th~ programmabl~ logic controll~r 37 each tim~ that th~ hi~h spe~d counter 10 is intarro~at~d by controllor 37 via bus 33 and bu~ int~rface 33.
Moreov0r, programmablo logac co~troll~r 37 can writ0 to pr~load register 115 and to pr~set r~isters 150A
; and 150~ as r~quired for th~ normal oper~tion of th~
high sp~d counter 10. The tim~-bas~ valuG
controllin~ tim~-baso r~gister 130 is programmed by the pro~rammable logic controller 37.
: 15 Type B counter 105 is substantially similar in configuration to Typo B counter 104. Input l~D of count~r 105 corrasponds in function to input 15A of counter 104. Input 15H of count~r 105 corresponds in function to inpu~ 15B of counter 104. Input 15J of ~; 2~ counter 105 corresponds in runction to input 15~ of counter 104. Input 15~ of coun~r 105 corresponds in function to input 15E of count~r 104. Input 15I of countor 105 corr~sponds in function ~o input 15C of cou~t~r 104. Input 15L of counter 105 corr3sponds in function to input 15F of counter 104.
It will b~ appreciated that in th~ Typ~ B counter configuration, pro~rammable hardware array 46 ha~ be~n configur~d to r~pr~s~nt ~wo ind~p~nd~ntly op~rating substantially similar medium complexi~y counters. All tw~lve inpUts 15A-15L and all four outputs 20A-20D
hav~ be~n uti1iz~d in th~ Type b confi~uration.

.

~ ~7~

TYPE ~ COUNTER CONFIGURATION

FIG. 6 shows a symbolic block diaBram of programmable hardwar~ array 46 reconfigured into a single relativ~ly high compl2xity Type C countor configuration. AlthouSh programmablo hardware array 46 shown in FIG. 6 is configured to Type C count~r 106, it is not~d that those inputs 15~, 15C. 15D, 15F, 15G, 15I, 15J and 15L. which wer~ sin~l~ entod input~
in.coun~er configuration Typ~ A of FIG. 3 and count~r configuration Typ~ B of FIC. 5, ar~ lik~wise sin~le-endsd inputs in counter configuration Type C of FIG.
6. Similarly thoso inputs 15B, 15E, 15H and 15K which w~r~ differ~ntial inputs in th~ Type A and B
confi~uration3 lik~wise exhibit diff~r~ntial inputs in the Typ3 C configuration. In comparin~ tho confi~urations of FI~. 3 ~Typ~ A) and FIG. 5 ~Typ~ B) with tho confi~uration of FIG. 6 (Type C~, lika num~rals ar~ used to d~signate lik~ elem~nts. It i~
noted that many el~m~nts are in common betw~en the configurations of FIG. 3, FIG. 5 and FIG. 6, althou~h th~ connections between such elem~nts may vary.
R~ferrin8 now to FIG. 6, input 15L is designated mark~r input 15L and input i5J i~ d~sign~ted limit-switoh input 15J. Marker input 15L and limit switch input 153 ar~ coupled to homo position r~ist~r 115A
a~ seon in FI~. 6. Hom0 position r~gis~er 115A is coupled to accumulat~r 120B. Homo po~ition rogist~r 115A down-loads its contant~ into accumulator 120B on th~ occurrenc~ of tho first low to hi~h si~nal transition on input 15L while input 15J is 2ctive.
Count~r confi~ura~ion 106 includ~ a rirst preload register 115a. tho input of which is coupled to input r~

~ 25 --15A via signal conditionin~ circuit 26 which ha~
alr~dy be~n d~scribcd in detail. The output of first preload register 115B i5 coupiod to an input of accumulator 120B. The contents of .first preload ro~ister 115B ar~ down-load~d to accumulAtor 120B whan an appropriate tata signal is appli~t to input 15A.
S~cond preload r~ister 115C includos an lnput which is coupled to input 15D. Ths output of second proload rsgist~r 115C is couplod to an input of accumulator 120B. Th~ contents of second preload r~gister 115C
ar~ down-load~d to accumulator l~OB wh~n an appropriat~ data signal is applied to input 15D.
Accumulator 120~ includes respactiv~ inputs which are coupled to count input 15~, count input 15E, count input 15H, count input 15~ and disable input 15~.
Accumulator 120B is coupl~d to timo-bas~ registar 130 into which the accumulator 120B contents ar~ loaded at - r~ul~r timed int~rvals d~p~nding on the s~lectet timo bas~ int~rval. In the praferr~d embodimont of the inventior, tlm~-base r~ ter 130 is a 16 bit r~gistsr which contain~ th~ numb~r of count~ tha~ haYe occurr~d in a s~lect~d tims p0riod of betw~un 10 millis~conts and 6553~ millis~conds. Altornative 0mbodimonts ~mploying other tim~ p~riods ar~ contompla~d and ar~
wi~hin ~ho scop~ of the inv~ntion. Th* time period is ssloct~d by pro~rammabl~ logic controll~r 37 using bus 33 and int~rfaco 70.
Accumulator 120B is also coupl~d ~o first strob~
r~gister 135A. to s~cond strobo re~ister 1358 and t9 third strobe r~gist~r 135C. First strob~ r~ist¢r 135A includ~s an input which is coupl~d to input 15C.
Socond strob~ re~ist~r 135B includ~s a~ input wh~ch is coupl~d to input 15F. Finally, third s~robo regist~r ~ J~

30C~-1008 - 2~ -1~5C includes an input which is couplod to an input15I. Wh~n an appropriataly conditioned data signal is introduc~d to input 15C of first strobo regist~r 135A, th~ contonts of accumulator 120B ar~ down-loa~d into first stroba r~ister 135A. Similarly, when an appropriate data signal is introduced to input 15F of ~econd strob~ rogistor 135B, tho cont~nts of accumulator 120B are down-load0d into s0cond strobo r~gist~r 135B. Likowis~, when an appropriate data 1~ si~nal is provided to input 15I of third strob~
r2gister 135C. the cont~nts of accu~ulator 120B ar~
down-loadsd into third strob~ re~ist~r 135C.
In the prsf~rred em~odim~nt of th~ invontion.
strob~ inputs l~C, 15~ and 15I ar~ s~nsitivs to signal ed~os and can b~ pro~rafflm~d to r~pond to eith~r a positiv~ ed~e or a n~at~v~ ~d~. Wh~n the appropriate si~nal edge occurs on input 15C, th~
contents of tho accumulator 120B ar~ copiod irto str~be re~ist~r 135~ so as to ov~r~rite th~ prsvious contents o~ the strob~ r~gister 135A. Similarly. wh~n th~ appropri~te signal 8d~e occurs on input 15F, the contents of accumul tor 120B ar~ copied into strobe rogistor 135~, thus overwritin~ th~ previous c ont ~nt 5 of th~ strob~ r~gist~r 135~. Likswise, wh~n an appropriat~ signal ed8e occurs on input 15I. th~
cont~nt~ of th~ accumula~or 120B ar~ copiod into strob~ rzgistor 135C so as to o~rwrit~ th0 prior contents of ths ~trobo ro~ister 135C.
Accumulator 120B i~ coupled ~o a firs~ input of output drivor 27A, to a first input of output driver 27B. to a first input of output drivor 27C and to a first input of output dri~r 27D. Tho socond input of output driv~r 27A is coupl~d to first ON/~FF pr~s~t ~ ~7~

register 150A. Output driv~r 27A includ~s an outputdo3ignated 20A as se~n in FIG. 6. Tho secont input of output driver 27B is coupled to second ON/OFF pr~et regist0r 150B. Output dri~r 27B includ~ an output 20B. Tho s~cond input of output driv~r 27C iQ coupl~d to thlrd ON/OFF prosot r~ister 150C. Output driv~r 27C include~ an output d~siBnated 20C. Th~ s~cond inp~t of output driver 27D i~ coupled to fourth ON/OFF
pre~t register 150D. Output driver 27D inclu~ss an output designated output ~OD.
Each of ths four pr~set re~isters 150A, lSOB, 150C
and 150D as~ociat~d with Type C counter confi~uration 106 exhibit pros~t valu~ including an ON pcint and a~
OFF point. Th~ ~tate of output 20A of output dri~or 27A indicate~ when the cont~nt~ of accum~lator 120 ara b~tween th~ two pres~t valu~ contained in th~ pros~t rQ~ister 150A. Th~ outpu~ 20B of ou~put dr~ Y~r 2tB
indicates wh~n th~ content~ of accumulator 120B ar~
b~twe~n th~ two pr~set valu~ contain~d in th~ preset r~is~or 150~. Furth0r, th~ output 20C of output driver 27C indicat~s when the cont~nts oi accumulator 120B a~e b~tween the two preset valu~s contain~d in the preset rogist~r l~OC. Similarly, th~ output 2~D
of output driv~r 27D indicat~s wh0n th~ ~ontont~ of accumuiator 120B ar~ b~tw~on the two pre~t value~
contain~d in th~ pr~s2t r~Bi~t~r 150D.
Th~ polarity of the outputs 20A, 20B, 20C and 20D
can b~ configured by pro~rammable logic controller 37 to be ON botwe~n the pr~t valu~s or OF~ betw~n th~
pres~t values. The s~t point condition can b~
confiB~r~d by pro~rammable logic controller 37 to either includ~ or exclud~ th~ pre~e~ points. In thi~
mann~r, ext~rnal user circuitry connoct~d to outputs ~3~u~
30~F-1008 - 2~.-20 i8 made responsiv~ to the count in accumulator 1208 ba~od on tho us~r pr~s~t value~ in pr~set r~gistors 150A, l50B, 150C and 150D.
From th0 above, it will b~ appr~ciat~d that th0 pro~rammablc hardwar~ array 46 ha~ be~n configur~d to r~pr~s~nt one r~lativ~ly hi8h compl~xity counter 106 of th~ Type C countar configuration and that all twelv~ inputs 15 and all four outputs ~Q h~ve b~n utilized.

., ~_ RELATED COUNTER_OPERATION

After the pro~rammabl~ hardware array lo~ic 46 confi~ur~d into ~ith~r Type A oount~rs or Typ~ B
counters or a Typ~ C count~r, th~ counter inputs 15B.
: . 15 15~. 15E. 15H, 15J and 15K are employ~d as inputs for various modes of th~ configured count0r op~ration a~
d~scrib~d ~ubs~qu~ntly.
Each of type A counters lOO, 101, 102 ~nd 103 car be indivldually pro~ramm~d by command~ on bus 33 from the programm~bl~ logic controll~r 37 to op~rate a~
oîth~r an up-count~r or a d~wn~count~r. That is.
80~0 of Typo A coun~ers lOO, 101, 102 and 103 may bs . progrsmm~d as up-counters while tho r~mainin8 on~s of '~ countor~ 100, lOI, 102 and 103 may b~ programmed a5 down-countors. In ~ho axample of FIG. 7A it i~
. a~sumod that a Typ~ A coun~r 100 has b~n pro~ramm~d j by commands from PLC 37 ovsr bu~ 33 to act as a up-countsr. 5hown in FIG. 7A is a typical input d~ta signal 415 drawn on a horizontal tim~ axi and pr~sent ~t input 15~. A1so drawn iD F1C. 7A i~ an up-count 30G~1008 - 29 - ~

3~ent 417 showing the timo relationship b~tweon tho leading ~dge of signal 415 and the ~ubs~qu~nt up-count event 417. Accumulator 120A i~ incrom~nted by one count durin~ such an up-count e~nt 417.
In tho exampl~ of FIG.. 7B it i5 assumed that typ~
A counter 100 has be~n programmad by command~ from PL~
37 over bu~ 33 to act a~ a down-count~r. FIG. 7B
shows th~ timo rolationship b~tweon an input signal 415 on input 15B of counter 100 and a down-count evont 419. In th~ down-counter modo thc down-count ev~nt 419 occurs aftor the nogative signal edgo of countor input signal 415 and. accordingly, accumulator 120A is decr~m~nted by one count during down-count event 419.
Typa B count~rs 104 an~ 105 ca~ b~ progra~m~d by commands on bu~ 33 from programmabl~ logic controller 37 to operat~ in on~ of thre0 mod~s. Th~ first mode is an up~down mode where, as shown in ths signal vs.
time diagram of FIG. 8, si~nal 415 is shown versus : time a~ appli~d to input 15B. That is, count~r input 23 15B is d~ignated to r~ceiv~ signal 415. When an up-count ev~nt 417 follows the l~ading edgo of signal 415 a~ shown in FIC. 8. counter 104 incram~nts accumulator 120A by on~ count. Simultaneously, count~r input 15E
is dosignat~d to receiv~ a signal 421. Down-count ~nt 419 follow~ th~ trailing ed~ o~ signal 421 as ; ~hown in tho low~r portion of FIG. 8 and count~r 104 d~cr~monts acGumulator 120A by ono count. Accumulator 120B thus accumulat~s th~ diff~ronce count b~tw~en th~
number ot leading edg~s of signal 415 on input 15B and tha number of trailing ed8e~ of signal 417 on input l5E. That is. accumulator 120B accumulat~s th~
d i f fer~nc~ count b~tw~on the number of up-count 2vents 417 and down-count evsnts 419. It is not~d that wh~n 8 ~

Typo B counter 104 is operating in tho abova describedfirst mod~ ~up/down countor mod~). an appropriata si~nal l~vel on disable input 15G will inhibit th~
operation of the counter 104 for th~ duration of the disable signal. In a lik~ manner, the r~plicat~ Typ~
B counter 105 can also b~ programm~t to op~rate in th~
upldown rounter mote an~ can be similarly disabled.
The second mod~ o~ op~ration of Type B counters 104 or 105 i5 the puls~-dir~ction modo which is bast ;llustrat~d by ref~rence to th~ si~nal vorsus time diagrams of FIG. 9A and FIG. 9~. Th~ input sisnal on count~r input 15E is defined to be input signal 423 as shown in FIG. 9A. ~h~n input signal 423 is high, tho occurronc~ of a leading ed8e transition of input signal 415 on input 15~ results in an up-count ev~nt 417. Ths occurrenca of such ar. up-count ev~nt results in an incremont of th~ counter contents of accumulator 120A by on~ count. ~ low ~i~nal 423', a~ shown in FIG. 9B, on counter input 15E caus~s a down-count eYont 41~_ which results in tho counter contents of accumulator 120A bRing decrem~nted by on~ count.
Thus, the polarity o~ si~nal (423 or 423') on counter input 15E controls wh~ther th~ count~r incr~monts or d~erom~nts th~ contonts of accumulator 120A. This darection signal may chang~ polari~y at any instance during th~ counting proco~S without affectin~ tho integrity of th~ expoct0d rssult~ in accumulator 12Q.
When th~ counter i~ inoromenting, po~itive leadin~
~ignal edg~s aro count~d wherea wh~n ~h~ counter is d~cr2menting, negative trailing edges aro count~d. It is noted th3t when Type B counter 104 i5 op~ratin~ in the abovo d~scussed second moda ~ pU 1 5~ direct~on mode3, an appropriate si~nal level on disable input :, 15C wi11 a~ain inhibit the oporation of the count0r 104 for the duration of tho disabl~ signal. In a llke manner, tho replicate Typo B counter 105 can also b~
pro~rammed to oparats in th0 puls~ dir~etion mode and : 5 can be similarly disabled.
Th~ third mod~ of op~ration of Type B counters 104 or 105 is th~ A quad B mode which is b~st illustrated by r~fer~nce to the sigral vorsu~ timo diagrams o~
FIG. lOA and FIG. 108. Tho phas~ r~lation~hip b~tw~n si~nal 415 on input 15~ and signal 425 on input 15E
d~tarmin~s the direction of the count. In FIG. 10 ~: th~ positIve going leading ~dge of signal 4as on input 15B oecurs whilo signal 425 on input 15E i5 low. In that phase r~lationship, up-eount e~ents 417 occur following each signal transition of both signalc 415 and 425. Th~ accumulator 120A count i5 inerement~d wh~n this input si~nal phase r~lationship oceurs. In FIG. lOB th3 positiv~ ~oin~ leadin~ ~d~ of si3nal 415 on input 15B oecur~ whil~ signal pu13~ 425 on input 15E i~ low. in that phas~ r~lationship, the counter events 419 ocour followin~ each signal transition of both siænals 415 and 425~. Th~ aceumula~or 120A count is doerem~ntod when this input signal phas~
rolat~on~hip oecurs. In the A quat B mod~ of opor ion for tho Typ0 ~ coun~r, four counter ~v~nts - are shown in FIG. lOA and FIG. lOB for each compl~te eyel~ of eith~r si~nal 41~ or si~nal 425. In this p~rtieular embodiment of the invent~on, up-eount ev~nts 417 and down-count e~an~s 419 are r~cord~d in "tim~ four~ mod~ to provids enh~need count r~solution.
It is noted that whon Typo B eount~r 104 is in th~
abov* discuss*d third mods (A quad d), an appropriat .

.~ 3' ~ ~

~ignal level on disable input 15G will once a~aininhibit th~ oporation of tho countor 1 M for the duration of th~ disabls signal. In a liko manner, th~
roplicato Typo B counter 105 ca~ also be programmod to operate in the A quad B mod~ and can be similarly disabled. It is also noted that Type B count~rs 104 and 105 n~d not nscessarily b~ programmed to th~ s~mo mcd~. That i~, counter 104 may ba pro~rammed in an up/down counter mod~ whil~ cGunter 105 i~
simultaneously programm~d in a pul~ diroction modo, for example.
Th~ Typo C count~r canfiguration 106 i~ a sin~le r~latlvely hi8h compl~xity differontial counter with two sats of counker inputs. Tho first set of counter inputs consists of inputs 15B and l5E which may bo consid~r~d a th~ inputs of tho po~itiYs loop of tho counter. Th~ modes of op~ra~ion of th~ss inputs ar~
id~ntical to tho modz~ of operation of inputs 158 and 15E of Typa B counter 104 as d~scrib~ earli~r by r~ferenco to FIGS. 8 - 10. Th~ s~cond set of count~r inputs consists of inputs 15H and 15K which may b~
considcred as tho inputs of th~ negativ~ loop of tho oount~r. Tho mod~ of op~ration of th~ input~ aro id~ntical to tha modes of operation on inputs 15H and 1~ of Typ~ B count~r lOS as d~scrib~d ~arli~r by r~feronce to PIGS. 8 - 10. Each s~ of count~r inputs for th~ Typo C cou~t~r is r~forr~d to a~ a count~r cha~n~l. Th~ two Typ~ C counter chann~ls can b~
indep~ndently programmed to oporat~ in any ona of tho mod~s toscribet for ~h~ Typo B count~r. Th0s~ mod3s are th~ up-down count~r mode. th~ pulse-direction mod~
and th~ A quad ~ counter mod~. Accumulator 120B
increments or decremonts depending on input signal ~3~7~

condition~ on each of th~ two countor channols. As an o~ample, if the flrst channol is recaivin~ data signals which caus~ up-count e~nts and the ~econd chann~l is receivin~ tata signals which caus~ down-count ev~nts, tho accumulator 120B r~ist~r5 th~ su~of the events on th~ first and s~cond channols. In the Tyye C~counter 106 a proper pr~d~terminsd si~nal levol on disable input 15G will inhibit th~ opor tion of counter 106 for th~ duration of tho disable si~al.
Tho contents of strob~ regist~rs 135A. 135B, 135C, time-baso reBister 130, home posi t i on r~g i ster 11 5A, preload r~ist~rs 115B and 115C, and ONIOFF pr~sot r~istsrs 150A, 150B, 150C and lSOD aro mad~ availablo to tho programmable lo~ic controllor 37 ~ach tim~ that th~ high sp~ed counter 10 is interrogat~d by controll~r 37 on the bus 33 via bus int~rfacu 70. In addition, controll~r 3~ can write to home position r~gister 115A, preload registers 1158 and 115C. and to pr~sot re~ister~ 150A. 150B, 150C ant 150D as roquired for tho normal op~ration of high spoed counter 10.
Th~ tim~ baso value controllin~ ~ho tim~-bas~ r0~ister 130 is pro~ramm~d by pro~rammable logic controller 37.
The ho~s position r~ister 115A down loads its cont~nts to the accu~ulator 120B within ons count :25 p~riod whon th~ limit switch input 153 is active and a ~:mark~r pul~ input occurs on the markor input 15L. In tho pref~rr~d ~mbodi~en~ of tho inv~ntion, the homo positien r~8ister 115A i~ a 24 bit rogister.
`FIG. 11 is a genoraliz~d ~lowchart sh~win~ th~
:~30 op~ration of r~configurabl~ counter 10. At power on, microproo~ssor 30 is initialized a~ por block 500 of tho flowchart of FIG. 11. A test i~ th~n p~rform~d at decision block 505 to de~ermin~ wh~thor or not a now ~ ~ 2 ~
30~F-1008 ~ 3~ -count~r con~iguration has be~n selocted by the usor atinput dovic~ 35. If at d~cision block 505 it i8 determined that a n~w counter configuration file ha~
bo~n s~lectod or that this i5 tho first tim~ that a counter confi~uration filo has e~er boon s~lected for counter 10, thon flow continue~ to.bloc~ 510 at which th~ particular configuration file sol~cted by the user is programm~d from PRO~ 40 to array 46. Block 515 indicate~ that tho configuration file us~d by 10 microproc~ssor 30 to confi~ure array 46 is doterminsd by the pointer of m~mory 45 and that the s~lectod usar param~ter~ of m~ory 45 are imposed on tho selected configuration. Once array 46 is so ~onfi3ur~d flow continue~ to block 520 at which th~ confi~ured count~r or counters monitor th~ input data from the controlled proc~s or other source.
How~ver, i f it was determined at decision block 505 that no nsw counter configuration has been s~loc.ted by tho user at input d~vic~ 35, thon the 2~ previou~ counter confi~uration as sal~cted by EEPROM

4~ is us~d by microprocog or 30 to confi~uro array 46 as per block 522. Flow th3 continue~ from block 522 to block 520 at which th~ configur~d count~r i5 usod to monitor input data.
-Tho count~r confi~ured in array 46 th~n ~nerate~
count information fro~ the input data a~ per bloc~ 525 in th~ manner pr~viou~ly dl~cus~d in d~tail. PLC 37 ~or oth~r host d~vic~) th~n acquir~ th~ count information fro~ th~ ~ounter or countor~ confi~urod in array 46 from timo to tim~ a~ dicta~od by tho : particular application a3 per block S30. Flow th~n continu~s bark to deci~ion block 50~ to determino if a new countsr profile has been selectod by th~ usQr.

~2~8~

Th~ process then continues as bofore. It is noted that PLC 37 nood not nec2ssarily acquire count information ~ch tim~ around the loop formvd by block~
505-530. That is, e~ecution of th~ functional block~
within loop 505-530 will continue ev~ if PLC 37 decido~ not to acquir* count information at block 530 ;n a p~rticular execution of loop 505-~30.
Thos~ skill~ in the art will appreciate that in actual practice block 522 at which array 46 i~
configur~d n~od not be ~x~cuted each ~im~ through loop 505-530. Rather, e~ecuting block 522 juæt once aft~r initial pow~r up of counter 10 will b~ sufficient to confi~ur~ count~r 10. Any subsequ~nt roconfiguration r~qu~sts are handled by blocks 505, 515 and 520.
While a reconflgurable count~r app r~tus ha boon dsscribed abov~ in detail, it will be appreciated that a method for configuring and r~confi~urin~ a count~r has also b0~n disclosod, such m~thod includin~ the steps of storin~ a plurality of us~r s~lectable count~r profile~ in a m~mory and th~ step of selectin~
ono of th~ us~r s~leotabl~ counter profiles thus designatins a selected counter profile. Th~ method furth~r includ~ th~ step of confi~uring a pro~rammablo hardwar~ array to exhibit a countar confi~ur~tion ~orr~sponding to th~ selected profil~.
In ono embodi~nt of th~ invention. tho method inclu~ th~ st~p of coupling tho count~r to a programmabl~ lo~ic controller or oth~r host d~ic~ to proYido th~ controller with count information.
In anoth~r embodim~nt of th~ method of inY~ntion.
th~ m~thod includ~ ~h~ steps of storing a plurality of user sel~ctabl~ count~r profil~ in ~ first memory and the ~tep of selecting ono of tho usor soloctablo ~2~

30GF-l208 count~r profiles thus d~si~nating a ~ei~cted counterprofil~. Th~ m~thod furthor includas th0 tep o~
writlng th~ select~d counter profile from th~ first momory to a programmable hardwaro array, and h~in~
imposod th~roon certain usor select~d parameter~
providod by a ~ocond memory.
In yot another embodiment of th~ mothod of the inv~ntion, a mothod is provid~d for confi~uring a counter includin~ the stcp of storing at l~ast first : 10 and second us3r s~lectable counter profil~ in a momory, the firs profile corrasponding to a plur~lity of counters exhibiting a first count~r typ~, tho s~cond profile corresponding to ~irst and second counter~ e~hibiting a socond count~r typo. Th~a first and socond counters are capable of a~suming first and second us~r s~lectable mode~. Th~ mothod furth~r includ~ the step of selectin~ one of the us~r s~lectable cou~ter profil~s thu~ d~signatin~ on~ of th~ first and second counter profil~ a b~in~ tho sel~cted countor profil~. Tho m~thod also include~ th~
step of selectin~ fir~t and second mod~s for th~ first and s0cond count~rs of the second counter typ~ wh~n th~ s~l~cted counter profile is tho second count~r profi1~, thu~ de~ignatin8 s~lect~d motss. Tho m~thod furth3r i~olud~s th0 step of confi~urin~ a program~bl~ h~rdwar~ array to exhibit a counter confi~uration correspontin~ to th~ s~lect~d counter profile ~nd ~ny soloct~d modo~.
~:~ Th~ foregoing ha~ d~cribod both a reconfigurabla counter apparatus and a mothot for roconfi~uring a count~r. Thst i 5, a hi8h sp~d count~r (HSG) i~
provided which may b~ pro~rammably rcconfigured t9 on~
of several different hardwar~ counter configurations.
:

2 r~

~ 37 --The counter advanta~eously pro~ido~ tho us~r a s~loctable functionality and cost tradooff to m~et a wido ransa of applications. Mor~over, th~ countor obviata tha neod for stockin~ sev~ral differant types Or high speed counters for us~ in conju~ction with PLC's, host computers, or, inde~d, a~ a stand-alon~
counter using any one of a numb~r of available op~rator interfaco devices such a~ a simple k~ypa~ or keyboard, and other applications.
While only certain pr~ferred featur~s of th~
invention have b~en sho~n by way o~ illustratio~, many modifications and changes will occur to those skilled in the art. For exampl~, althou~h first and s~cond memorie~ ar~ illustrated and discussod, it will b~
apparant that a sin~l~ memory s~rving the functio~ of th~ fir~t and second m~morie~ may, for ~omo applications, b~ substituted. It i5, th~refore, to b~
und~rstood that th~ pr~sant claims ar~ int~nded to covor all such modification~ and changos which fall 2~ within th~ tru~ spirit of tho inv~ntion.

Claims (21)

1. A reconfigurable counter comprising:
a microprocessor;
a bus coupled to said microprocessor;
first memory means, coupled to said microprocessor by said bus, for simultaneously storing a plurality of counter configuration files which respectively define a plurality of predetermined different counters, each counter configuration file completely defining a predetermined counter having a different structural complexity;
input means, coupled to said microprocessor, for inputting selection information to said microprocessor to indicate the selection of a particular one of said counter configuration files desired by a user of said counter;
second memory means, coupled to said microprocessor by said bus, for storing said selection information;
programmable logic means, coupled to said microprocessor by said bus, for emulating the particular predetermined counter defined by the particular counter configuration file indicated by said selection information; and said microprocessor writing to said programmable logic means the particular predetermined counter configuration file indicated by said selection information, such that said programmable logic means emulates the particular predetermined counter defined by the particular counter configuration file indicated by said selection information.

2. The counter of claim 1 wherein said first memory means comprises a non-volatile memory.

3. The counter of claim 1 wherein said second memory means comprises a programmable non-volatile memory.

4. The counter of claim 1 wherein said input means further includes means for inputting counter parameter information to said microprocessor for storage in said second memory means.

5. The counter of claim 1 wherein at least one of the counter configuration files stored in said first memory means defines a multi-mode counter including first and second modes.

6. The counter of claim 1 wherein at least one of the counter configuration files stored in said first memory means defines a multi-mode counter including a selectable UP/DOWN counter mode, a selectable pulse direction mode and a selectable A quad B counter mode.

7. The counter of claim 1 wherein said second memory means includes a pointer to indicate the selection of a particular one of said counter configuration files stored in said first memory means.

8. A reconfigurable counter comprising:
first memory means for simultaneously storing a plurality of counter configuration files which respectively define a plurality of predetermined different counters, each counter configuration file completely defining a predetermined counter having a different structural complexity;
selecting means, operatively coupled to said first memory means, for selecting one of said counter configuration files for said counter; .
programmable logic means, responsive to said selecting means, for emulating the particular predetermined counter defined by the particular counter configuration file selected by said selecting means; and writing means, coupled to said first memory means and said programmable logic means, for writing to said programmable logic means the particular predetermined counter configuration file selected by said selecting means, such that said programmable logic means emulates the particular predetermined counter defined by the particular counter configuration file selected by said selecting means.

9. The counter of claim 8 wherein said first memory means comprises a programmable non-volatile memory.

10. The counter of claim 8 wherein said selecting means comprises a second memory means for storing selection information which indicates which counter configuration file is to be written into said programmable logic means.

11. The counter of claim 10 wherein said second memory means comprises a non-volatile memory.

12. The counter of claim 8 wherein at least one of the counter configuration files stored in said first memory means defines multi-mode counter including selectable first and second modes.

13. The counter of claim 8 wherein at least one of the counter configuration files stored in said first memory means defines a multi-mode counter including a selectable UP/DOWN counter mode, a selectable pulse direction mode and a selectable A quad B counter mode.

14. The method of configuring a counter comprising the steps of:
storing simultaneously in a first memory a plurality of counter configuration files which respectively define a plurality of predetermined different counters, each counter configuration file completely defining a predetermined counter having a different structural complexity;
inputting selection information to said counter to indicate the selection of a particular one of said counter configuration files desired by a user of said counter; and storing said selection information in a second memory, and writing the counter configuration file indicated by said selection information to a programmable logic device such that said programmable logic device emulates the particular predetermined counter defined by the counter configuration file indicated by said selection information.

15. The method of claim 14 further comprising the step of inputting said selection information to a second memory in said counter to indicate the selection of a particular one of said counter configuration files by a user of said counter.

16. The method of claim 15 further comprising the steps of inputting counter parameter information to said second memory means and writing said counter parameter information to said programmable logic device to aid in configuration of said programmable logic device.

17. The method of claim 14 further comprising a substep wherein at least one of said counter configuration files stored in said first memory means defines a multi-mode counter including selectable first and second modes.

18. The counter of claim 14 further comprising a substep wherein at least one of the counter configuration files stored in said first memory means defines a multi-mode counter including a selectable UP/DOWN counter mode, a selectable pulse direction mode and a selectable A quad B counter mode.

19. A method of configuring a counter comprising the steps of:
storing simultaneously in a first memory a plurality of counter configuration files which respectively define a plurality of predetermined different counters, each counter configuration file completely defining a predetermined counter having a different structural complexity;
selecting one of said counter configuration files for said counter, the counter configuration file thus selected being designated the selected counter configuration file; and writing the selected counter configuration file to a programmable logic device such that said programmable logic device emulates the particular predetermined counter defined by said selected counter configuration file.

20. The method of claim 19 further comprising a substep wherein at least one of said counter configuration files stored in said first memory means defines a multi-mode counter including selectable first and second modes.

21. The counter of claim 19 further comprising a substep wherein at least one of the counter configuration files stored in said first memory means defines a multi-mode counter including a selectable UP/DOWN counter mode, a selectable pulse direction mode and a selectable A quad B counter mode.