CA1333418C - Digital key system architecture - Google Patents
Digital key system architectureInfo
- Publication number
- CA1333418C CA1333418C CA000573618A CA573618A CA1333418C CA 1333418 C CA1333418 C CA 1333418C CA 000573618 A CA000573618 A CA 000573618A CA 573618 A CA573618 A CA 573618A CA 1333418 C CA1333418 C CA 1333418C
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- CA
- Canada
- Prior art keywords
- digital
- signals
- interface circuits
- bus
- communication system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
Abstract
A digital communication system comprised of a universal backplane bus and a plurality of interface circuits connected to remote peripherals, for effecting bidirectional communication of information signals between the remote peripherals via the bus, as well as the exchange of message signals between local control circuitry resident on individual ones of the interface circuits. Each interface circuit is further comprised of a digital time and space switch for transmitting the information signals in PCM format between the remote peripherals and the universal bus, under control of the control circuitry resident on respective ones of the interface circuits.
An HDLC controller is provided on each of the interface circuits for controlling the exchange of message signals between the local control circuitry resident on the respective ones of the interface circuits.
An HDLC controller is provided on each of the interface circuits for controlling the exchange of message signals between the local control circuitry resident on the respective ones of the interface circuits.
Description
ol - l 1333418 02 This invention relates in general to 03 communication systems, and more particularly to a 04 digital telephone system utilizing distributed 05 processing and switching.
06 An important objective in modern day 07 telecommunications is to solve the problem of linking 08 together a number of telephone users and data 09 communication devices. The solution to this problem involves implementing circuitry for providing a 11 transmission and switching function, as well as 12 circuitry for providing a signaling and control 13 function.
14 Prior art digital (PCM) telephone systems have implemented the transmission and switching 16 function by means of a central time division 17 multiplexed matrix, for interconnecting a plurality of 18 remote telephone users and data communication devices 19 via individual codecs over dedicated unidirectional PCM highways connected to the central switch.
21 The individual codecs were usually 22 arranged in groups of 4, 8 or 12 on a printed circuit 23 board normally referred to as a port card, and each 24 card is plugged into a backplane printed circuit board that provides the electrical connection to the central 26 switch.
27 In prior art digital telephone systems, 28 the signaling and control function was generally 29 provided by a central processing unit that communicated with the port cards over either a 31 parallel microprocessor bus, or via a number of serial 32 buses in a circuit switched mode.
33 A fundamental disadvantage of prior art 34 systems which utilize a central switching matrix for transmitting signals over unidirectional PCM highways, 36 is that the unidirectional highways are characterized 37 by limited bandwidth. Furthermore, the backplane 133341~
02 access of individual port cards has been found to be 03 complex since each port card must be connected to 04 pre-allocated ones of the PCM highways. The complex 05 pattern of connections between the PCM highways to 06 individual boards in such prior art systems has resulted 07 in expensive and complicated backplane printed circuit 08 board layout. The principal disadvantage of implementing 09 the signaling and control function via a prior art central processing unit is that the main processor must perform a 11 routine port scanning function which requires a 12 substantial amount of processor time to implement.
13 Furthermore, prior art central controllers are typically 14 operated under control of a predetermined main call processing software package which is required to be 16 rewritten in the event new types and formats of port cards 17 are introduced to the system. Also, the communication 18 between the central controller and various ones of the 19 port cards typically requires multiple signaling and control lines for linking individual ones of the cards to 21 the central controller, thereby contributing to the 22 complex backplane layout discussed above.
23 According to the present invention, a 24 digital communication system is provided which utilizes distributed switching whereby a switching matrix is 26 provided on each interface circuit for accessing a 27 plurarity of bidirectional PCM highways disposed on a 28 universal backplane bus. The bidirectional PCM highways 29 of the present invention provide a more efficient digital transmission system than prior art unidirectional highways 31 since voice and data signals are transmitted directly 32 between interface circuits instead of via a central 33 switching matrix. The backplane access according to the 34 present invention is simplified over prior art systems utilizing a central switch, since all port cards or 36 interface circuits connect to the backplane in an 1333~18 01 _ 3 _ 02 identical manner. This results in improved 03 flexibility over prior art systems for future 04 applications since each card can access the full 05 system bandwidth. Furthermore, the backplane layout 06 of bidirectional PCM highways in accordance with the 07 present invention is much simplified as compared to 08 prior art unidirectional PCM highways connected to a 09 central switch since the PCM highways of the present invention can be laid out as a parallel bus rather 11 than routing the highway to individual boards in a 12 complex pattern.
13 According to the present invention, each 14 interface circuit is provided with local intelligence in form of a microprocessor or micro-controller 16 linking all port cards or interface circuits together 17 via a high-speed packet switched local area network, 18 utilizing the backplane bus as a transmission medium.
19 Accordingly, a system of distributed processing is provided which is characterized by the following 21 advantages over prior art central controller based 22 telephone system. Firstly, it relieves the main 23 processor from the prior art requirement for routine 24 port scanning. Secondly, it allows for the use of a high level message passing protocol, in order that new 26 types of port cards or interface circuits can be 27 introduced without having to rewrite the main call 28 processing software, as in prior art systems.
29 Furthermore, only one signaling and control line is required to link all of the port cards or interface 31 circuits in the system, which again simplifies the 32 backplane layout as compared to prior art systems.
33 In general, according to the present 34 invention, there is provided a digital telephone system comprised of a universal backplane bus, one or 36 more interface circuits each including control 37 circuitry for generating and receiving message signals 38 to and from the bus, and one or more remote 01 ~ 4 ~
02 peripherals connected to predetermined ones of the 03 interface circuits, for generating and receiving 04 information signals. Switching circuitry is provided 05 in each of the interface circuits for effecting 06 distributed bidirectional switching of the information 07 signals between the remote peripherals via the bus, 08 and communications controller circuitry is included in 09 each of the interface circuits for exchanging the message signals between the control circuitry via the 11 bus in accordance with a bit oriented data link 12 protocol, in response to which the control circuitry 13 supervises the bidirectional switching of the 14 information signals.
A better understanding of the present 16 invention will be obtained with reference to the 17 detailed description below in conjunction with the 18 following drawings in which:
19 Figure 1 is a block diagram illustrating a representative configuration of the telephone system 21 in accordance with the present invention, 22 Figures 2A-2C are block diagrams 23 illustrating the differences between prior art 24 unidirectional information signaling and bidirectional information signaling in accordance with 26 the present invention, 27 Figure 3 is a block schematic diagram 28 illustrating the backplane layout in accordance with a 29 preferred embodiment of the present invention, and Figure 4 is a schematic block diagram 31 showing a detail of the HDLC controller, digital 32 crosspoint switch and local control unit of an 33 interface circuit in accordance with the preferred 34 embodiment.
Turning to Figure 1, a general 36 architectural overview is provided by means of a block 37 diagram illustrating a universal backplane bus 1 in 1333~18 02 the form of a bidirectional PCM highway connected to a 03 plurality of interface circuits, such as main control 04 unit 3 and various peripheral port cards (eg. analog 05 station/trunk card 5, ISDN port card 7 and LAN gateway 06 card 9). Each of the interface circuits 3-9 is 07 connected to a further message signal line lA, which 08 forms part of the backplane bus 1.
09 In operation, a plurality of remote peripherals such as subscriber sets, personal 11 computers, attendant consoles, etc., are connected to 12 the peripheral port card interface circuits such as 13 analog station/trunk card 5, ISDN port card 7 and LAN
14 gateway card 9. Each of the interface circuits 3-9 are connected in an identical manner to the universal 16 backplane bus 1 which carries 12 megabit per second 17 information signals between respective ones of the 18 interface circuits 3-9. As discussed in greater 19 detail below with reference to Figure 3, each of the interface circuits 3-9 is further comprised of a 21 switching matrix for effecting digital time and space 22 switching of the information signals under the 23 supervision of resident control circuitry. The 24 exchange of message signals between the resident control circuitry of respective ones of the interface 26 circuits is effected by means of the D-channel link lA
27 of the backplane bus 1.
28 As seen from Figure 1, the interface 29 circuits 3-9 each contain a standard backplane connection that plugs into the backplane 1, which is 31 laid out in a parallel fashion, with all lines going 32 to the same pin numbers on each of the interface 33 circuits 3-9, with the exception of pins provided for 34 carrying 5-bit identification code signals for identifying to the individual circuits 3-9 which slot 36 of the backplane 1 the circuit has been plugged into, 37 as discussed below.
38 According to a successful prototype of the 1333~18 02 present invention, only 32 pins were required for each 03 slot to provide backplane access for each of the 04 interface circuits 3-9. The 32 pins were laid out on 05 a 0.2 inch x 0.2 inch matrix for reducing the 06 possibility of accidental short circuits, as follow:
07 Pin Assignments 08 PIN NUMBER ROW "A" ROW "C"
13 10 C4 SPRl 14 D0 Dl 16 16 D0 Bl 18 20 B4 B5(T) 19 22 ID0 IDl 22 28 +5V +5V
23 30 +5V E -5V E
25 Note: E indicates extended pre-charge pin 26 As discussed above, and in greater detail 27 below with reference to Figure 3, the telephone system 28 of the present invention utilizes bidirectional 29 information signaling along the parallel backplane bus 1. According to the successful prototype, 31 five bidirectional PCM data buses and a single 32 unidirectional PCM tone bus are provided on the 33 backplane for effecting bidirectional signal 34 translation.
Bidirectional signal translation allows 36 for greater bandwidth signal transmission over prior 37 art unidirectional systems, as seen with reference to 38 Figures 2A-2C.
01 _ 7_ 1333418 02 Turning to Figure 2A, a typical prior art 03 unidirectional PCM transmission scheme is illustrated 04 utilizing a central time/space switch 11 connected to 05 a plurality of PCM links such as PCM highways 13A and 06 13B. PCM highway 13A carries signals received from a 07 plurality of codecs such as codec 14 and codec 15 on 08 pre-designated time slot channels (eg. channel O from 09 codec 14 and channel 1 from codec 15) . A typical PCM
communication system will utilize 32 channel PCM
11 frames of data applied to each of the PCM highways in 12 a cyclic recurring manner. Thus, each of the transmit 13 and received PCM highways 13A and 13B carry 32 time 14 slots for accomodating 16 simultaneous conversations over 32 ports (ie. codecs). PCM information signals 16 are generated by codec 14 during time slot O for 17 reception by time/space switch 11 via transmit PCM
18 highway 13A. Likewise, codec 14 receives from 19 time/space switch 11 PCM information signals during time slot 0, via receive PCM highway 13B. Similarly, 21 codec 15 received and transmits PCM signals during 22 time slot channel 1. In like fashion, additional 23 codecs may be provided, in number up to 32.
24 Thus, a telephone system configured as in Figure 2A, running at 2MHZ, would be characterized by 26 a signal bandwidth of 4 megabits per second.
27 Turning to Figure 2B, a bidirectional 28 single wire system is illustrated in which time/space 29 switch 11 has been replaced by a predetermined time slot connection of codecs 14 and 15 to bidirectional 31 PCM highway 16. PCM information signals transmitted 32 during time slot O from codec 14 are carried by PCM
33 highway 16 and received by codec 15 during the same 34 time slot. Likewise, codec 15 generates and applies PCM signals to the highway 16 during time slot channel 36 1 for reception by codec 14. In this way, a 37 conversation is established between codecs 14 and 15 38 utilizing the single wire highway 16, without 02 requiring a dedicated central switching matrix. In 03 this manner, up to 16 conversations between 32 ports 04 (ie. codecs) may be accomodated utilizing a single 05 wire PCM highway 16. The system of Figure 2B is 06 characterized by a bandwidth capability of 2 megabits 07 per second yet utilizes only one wire as opposed to 08 the 2-wire system of Figure 2A, and eliminates the 09 neccessity for time/space switch 11. Furthermore, the number of ports which can be accomodated by the system 11 of Figure 2B, is doubled over the prior art system of 12 Figure 2A.
13 Figure 2C illustrates a 2-wire 14 bidirectional system in which codecs 14 and 15 are connected to a pair of bidirectional PCM highways 17A
16 and 17B. According to the system of Figure 2C, each 17 of the codecs 14 and 15 generates and receives PCM
18 signals on the shared time slot 0, for carrying on a 19 conversation. Thus, according to the 2-wire bidirectional system of Figure 2C, up to 32 21 conversations may be carried on between 64 ports over 22 32 time slots, with a bandwidth of 4 megabits per 23 second. Accordingly, the port handling capability of 24 the 2-wire bidirectional system of Figure 2C is exactly twice that of the prior art unidirectional 26 system shown in Figure 2A.
27 In order to implement the bidirectional 28 PCM signal transmission systems of either Figure 2B or 29 2C, each of the codecs 14 and 15 must be provided with circuitry for selectively enabling transmission and 31 reception of PCM signals via the individual codecs 32 during the predetermined time slot channels.
33 According to the present invention, such 34 time slot allocation circuitry is provided by means of a digital crosspoint switch, as shown in detail with 36 reference to Figures 3 and 4. In particular, a 37 preferred embodiment of the present invention is shown 38 with reference to Figure 3 in which PCM bus 1 is 02 comprised of a plurality of bidirectional PCM highways 03 B0-B4, a unidirectional tone bus B5(T), a 04 bidirectional data lead D0 and a plurality of timing 05 leads C4, F0 and NS. Each of the interface circuits 3 06 and 5 is shown comprised of a digital crosspoint 07 switching matrix (ie. DX chip 21A and 21B), control 08 circuitry (ie. central processor unit 23A and local 09 control unit 23B), a communication controller (ie.
HDLC controllers 25A and 25B) and timing generators 11 26A and 26B. Four unidirectional ST buses (eg. CST
12 and DST) are connected between the digital crosspoint 13 switching circuits 21A and 21B and respective ports, 14 such as tone generator and conference circuit 28 in main control unit 3 and the codecs and interface 16 circuitry 30 within station/trunk interface 5.
17 All of the PCM buses are run at a data 18 rate of preferably 2.048 megabits per second resulting 19 in a total backplane PCM bandwidth of 10.24 megabits per second, which provides a total non-blocking system 21 capacity of 160 voice-only ports, or 80 voice/data 22 (ISDN) ports.
23 The on-board control circuitry (eg. local 24 control unit 23B and central processor unit 23A) provide microprocessor controlled local intelligence.
26 Individual control circuitry of the respective 27 interface circuits communicate with each other over 28 the 2.048 megabit per second packet switched local 29 area network provided by data lead D0 and HDLC
controllers 25A and 25B.
31 In order to better understand the present 32 invention, a typical scenario will be described with 33 reference to Figures 1 and 3, for illustrating a 34 normal call sequence in accordance with the present invention.
36 For example, a remote user of a digital 37 subscriber set (not shown) connected to ISDN port card 38 7 may go off-hook. The off-hook condition is detected 1333~18 02 by the local control unit of ISDN port card 7, which 03 in response formulates a message signal for 04 transmission via the associated HDLC controller for 05 reception by main control unit 3, in order to indicate 06 to the main control unit 3 which one of the remote 07 peripherals has gone off-hook.
08 Meanwhile, tone generator 28 of main 09 control unit 3 is constantly generating and applying dial tone and other supervisory tones during 11 respective time slot channels on unidirectional tone 12 bus B5(T). The ISDN port card 7 extracts the dial 13 tone signal from bus B5(T) via the associated digital 14 switching circuit disposed thereon. The dial tone signal is then transmitted to the remote digital 16 subscriber set (not shown) in a well known manner.
17 In response to dialing predetermined 18 digits at the remote digital subscriber set, ISDN port 19 card 7 transmits dialling digit information via backplane bus 1 for reception by main control unit 3.
21 In the event that the central processor unit 23A of 22 main control unit 3 detects a valid telephone number 23 as identified by the dialling digits, the central 24 processor unit 23A formulates and generates a message signal to station/trunk interface circuit 5 for 26 establishing a connection in accordance with call 27 processing software and transmits dial digit 28 information via HDLC controller 25A and data lead 29 DO to a predetermined idle trunk circuit connected to one of the codecs and interfaces 30. The call 31 processing software may also implement such features 32 as least cost routine, long distance inhibit, etc.
33 The central processor unit 23A of main control unit 3 34 contains a memory map of available time slots within respective ones of the digital switches associated 36 with interface circuits 3-9. The available time slots 37 may be pre-selected for individual ones of the codecs 38 30, tone generator and conference circuit 28, or other - ol - ll - 1333418 02 peripheral interfaces since dynamic time slot 03 assignment is not required in accordance with the 04 present invention due to its non-blocking 05 configuration.
06 Thus, central processor unit 23A generates 07 message signals to station/trunk interface circuit 5 08 as well as ISDN port card 7 for allocating 09 predetermined time slots within the associated digital switching circuits in order to establish a 11 communication channel via a predetermined one of the 12 bidirectional signals buses B0-B4, between the remote 13 digital subscriber set connected to ISDN port card 7 14 and the remote trunk circuit connected to analog station/trunk card 5. Each of the digital switching 16 circuits 21A, 21B, etc., includes 256 memory locations 17 which are split between the backplane buses B0-B4 and 18 B5(T) and the CST and DST buses connected to the 19 remote peripherals.
Thus, a conversation path is established 21 by means of the circuitry shown in Figures 1 and 3 22 between a first remote peripheral such as a digital 23 subscriber set connected to ISDN port card 7 and a 24 second remote peripheral, which in this case is a remote trunk circuit connected to analog 26 station/trunk card 5. Additional connections between 27 a remote party and the trunk circuit are effected in a 28 well known manner.
29 Turning to Figure 4, a schematic block diagram is shown illustrating the HDLC controller 25A
31 and digital crosspoint switching circuit 21A of the 32 main controller connected to the central processor 33 unit 23A. Of course, the configuration of HDLC
34 controller, digital crosspoint switching circuit and control circuitry of Figure 4 is implemented on each 36 of the interface circuits 3-9, resulting in generic 37 access to the universal backplane, as discussed above.
38 According to the successful prototype ~ 01 - 12 - 1333~18 02 shown in Figure 4, the HDLC controller 25A was 03 implemented utilizing a MT8952B HDLC protocol 04 controller and the digital crosspoint switching 05 circuit 21A was implemented utilizing a model MT8980D
06 crosspoint switching circuit, both manufactured by 07 Mitel Corporation.
08 In summary, the system architecture in 09 accordance with the present invention is based on a flexible, wide bandwidth backplane with universal 11 slots. Any card (ie. interface circuits 3-9) may be 12 plugged into any slot on the backplane, and each card 13 has access to the full system bandwidth. The 14 backplane is preferably configured as one or more modules that can be expanded to a maximum of 32 16 slots. The system in accordance with the present 17 invention utilizes distributed processing as well as 18 distributed switching, for facilitating use of the 19 universal backplane. The disadvantages associated with prior art central processing and central 21 switching systems are overcome by the system of the 22 present invention, as discussed in detail above.
23 A person understanding the present 24 invention may conceive of other embodiments or variations therein.
26 For example, the data rate of PCM
27 signals carried by the backplane bus 1 may be 28 increased from 2.048 megabits per second in the 29 preferred embodiment to 4.096 megabits per second or greater. This would increase the system non blocking 31 capacity to upwards of 320 analog voice only ports or 32 160 voice/data (ISDN) ports. This modification would 33 be easy to achieve since the only significant change 34 would be to double the bit rate capacity of the digital crosspoint switch utilized in each of the 36 interface circuits.
37 Other applications of the present invention 38 are possible in connection with high capacity data 13334 ~ 8 02 only PABXs, or Tl digital trunk multiplexers, etc.
03 Also, whereas the block diagram of Figure 04 1 illustrates a representative configuration of 05 interface circuits, many other combinations of 06 interface circuits are possible. For example, Tl 07 digital trunk cards, miscellaneous alarms cards, etc.
08 may be advantageously incorporated into the system of 09 the present invention.
These and other embodiments or 11 modifications are believed to be within the sphere and 12 scope of the present invention as defined by the 13 claims appended hereto.
06 An important objective in modern day 07 telecommunications is to solve the problem of linking 08 together a number of telephone users and data 09 communication devices. The solution to this problem involves implementing circuitry for providing a 11 transmission and switching function, as well as 12 circuitry for providing a signaling and control 13 function.
14 Prior art digital (PCM) telephone systems have implemented the transmission and switching 16 function by means of a central time division 17 multiplexed matrix, for interconnecting a plurality of 18 remote telephone users and data communication devices 19 via individual codecs over dedicated unidirectional PCM highways connected to the central switch.
21 The individual codecs were usually 22 arranged in groups of 4, 8 or 12 on a printed circuit 23 board normally referred to as a port card, and each 24 card is plugged into a backplane printed circuit board that provides the electrical connection to the central 26 switch.
27 In prior art digital telephone systems, 28 the signaling and control function was generally 29 provided by a central processing unit that communicated with the port cards over either a 31 parallel microprocessor bus, or via a number of serial 32 buses in a circuit switched mode.
33 A fundamental disadvantage of prior art 34 systems which utilize a central switching matrix for transmitting signals over unidirectional PCM highways, 36 is that the unidirectional highways are characterized 37 by limited bandwidth. Furthermore, the backplane 133341~
02 access of individual port cards has been found to be 03 complex since each port card must be connected to 04 pre-allocated ones of the PCM highways. The complex 05 pattern of connections between the PCM highways to 06 individual boards in such prior art systems has resulted 07 in expensive and complicated backplane printed circuit 08 board layout. The principal disadvantage of implementing 09 the signaling and control function via a prior art central processing unit is that the main processor must perform a 11 routine port scanning function which requires a 12 substantial amount of processor time to implement.
13 Furthermore, prior art central controllers are typically 14 operated under control of a predetermined main call processing software package which is required to be 16 rewritten in the event new types and formats of port cards 17 are introduced to the system. Also, the communication 18 between the central controller and various ones of the 19 port cards typically requires multiple signaling and control lines for linking individual ones of the cards to 21 the central controller, thereby contributing to the 22 complex backplane layout discussed above.
23 According to the present invention, a 24 digital communication system is provided which utilizes distributed switching whereby a switching matrix is 26 provided on each interface circuit for accessing a 27 plurarity of bidirectional PCM highways disposed on a 28 universal backplane bus. The bidirectional PCM highways 29 of the present invention provide a more efficient digital transmission system than prior art unidirectional highways 31 since voice and data signals are transmitted directly 32 between interface circuits instead of via a central 33 switching matrix. The backplane access according to the 34 present invention is simplified over prior art systems utilizing a central switch, since all port cards or 36 interface circuits connect to the backplane in an 1333~18 01 _ 3 _ 02 identical manner. This results in improved 03 flexibility over prior art systems for future 04 applications since each card can access the full 05 system bandwidth. Furthermore, the backplane layout 06 of bidirectional PCM highways in accordance with the 07 present invention is much simplified as compared to 08 prior art unidirectional PCM highways connected to a 09 central switch since the PCM highways of the present invention can be laid out as a parallel bus rather 11 than routing the highway to individual boards in a 12 complex pattern.
13 According to the present invention, each 14 interface circuit is provided with local intelligence in form of a microprocessor or micro-controller 16 linking all port cards or interface circuits together 17 via a high-speed packet switched local area network, 18 utilizing the backplane bus as a transmission medium.
19 Accordingly, a system of distributed processing is provided which is characterized by the following 21 advantages over prior art central controller based 22 telephone system. Firstly, it relieves the main 23 processor from the prior art requirement for routine 24 port scanning. Secondly, it allows for the use of a high level message passing protocol, in order that new 26 types of port cards or interface circuits can be 27 introduced without having to rewrite the main call 28 processing software, as in prior art systems.
29 Furthermore, only one signaling and control line is required to link all of the port cards or interface 31 circuits in the system, which again simplifies the 32 backplane layout as compared to prior art systems.
33 In general, according to the present 34 invention, there is provided a digital telephone system comprised of a universal backplane bus, one or 36 more interface circuits each including control 37 circuitry for generating and receiving message signals 38 to and from the bus, and one or more remote 01 ~ 4 ~
02 peripherals connected to predetermined ones of the 03 interface circuits, for generating and receiving 04 information signals. Switching circuitry is provided 05 in each of the interface circuits for effecting 06 distributed bidirectional switching of the information 07 signals between the remote peripherals via the bus, 08 and communications controller circuitry is included in 09 each of the interface circuits for exchanging the message signals between the control circuitry via the 11 bus in accordance with a bit oriented data link 12 protocol, in response to which the control circuitry 13 supervises the bidirectional switching of the 14 information signals.
A better understanding of the present 16 invention will be obtained with reference to the 17 detailed description below in conjunction with the 18 following drawings in which:
19 Figure 1 is a block diagram illustrating a representative configuration of the telephone system 21 in accordance with the present invention, 22 Figures 2A-2C are block diagrams 23 illustrating the differences between prior art 24 unidirectional information signaling and bidirectional information signaling in accordance with 26 the present invention, 27 Figure 3 is a block schematic diagram 28 illustrating the backplane layout in accordance with a 29 preferred embodiment of the present invention, and Figure 4 is a schematic block diagram 31 showing a detail of the HDLC controller, digital 32 crosspoint switch and local control unit of an 33 interface circuit in accordance with the preferred 34 embodiment.
Turning to Figure 1, a general 36 architectural overview is provided by means of a block 37 diagram illustrating a universal backplane bus 1 in 1333~18 02 the form of a bidirectional PCM highway connected to a 03 plurality of interface circuits, such as main control 04 unit 3 and various peripheral port cards (eg. analog 05 station/trunk card 5, ISDN port card 7 and LAN gateway 06 card 9). Each of the interface circuits 3-9 is 07 connected to a further message signal line lA, which 08 forms part of the backplane bus 1.
09 In operation, a plurality of remote peripherals such as subscriber sets, personal 11 computers, attendant consoles, etc., are connected to 12 the peripheral port card interface circuits such as 13 analog station/trunk card 5, ISDN port card 7 and LAN
14 gateway card 9. Each of the interface circuits 3-9 are connected in an identical manner to the universal 16 backplane bus 1 which carries 12 megabit per second 17 information signals between respective ones of the 18 interface circuits 3-9. As discussed in greater 19 detail below with reference to Figure 3, each of the interface circuits 3-9 is further comprised of a 21 switching matrix for effecting digital time and space 22 switching of the information signals under the 23 supervision of resident control circuitry. The 24 exchange of message signals between the resident control circuitry of respective ones of the interface 26 circuits is effected by means of the D-channel link lA
27 of the backplane bus 1.
28 As seen from Figure 1, the interface 29 circuits 3-9 each contain a standard backplane connection that plugs into the backplane 1, which is 31 laid out in a parallel fashion, with all lines going 32 to the same pin numbers on each of the interface 33 circuits 3-9, with the exception of pins provided for 34 carrying 5-bit identification code signals for identifying to the individual circuits 3-9 which slot 36 of the backplane 1 the circuit has been plugged into, 37 as discussed below.
38 According to a successful prototype of the 1333~18 02 present invention, only 32 pins were required for each 03 slot to provide backplane access for each of the 04 interface circuits 3-9. The 32 pins were laid out on 05 a 0.2 inch x 0.2 inch matrix for reducing the 06 possibility of accidental short circuits, as follow:
07 Pin Assignments 08 PIN NUMBER ROW "A" ROW "C"
13 10 C4 SPRl 14 D0 Dl 16 16 D0 Bl 18 20 B4 B5(T) 19 22 ID0 IDl 22 28 +5V +5V
23 30 +5V E -5V E
25 Note: E indicates extended pre-charge pin 26 As discussed above, and in greater detail 27 below with reference to Figure 3, the telephone system 28 of the present invention utilizes bidirectional 29 information signaling along the parallel backplane bus 1. According to the successful prototype, 31 five bidirectional PCM data buses and a single 32 unidirectional PCM tone bus are provided on the 33 backplane for effecting bidirectional signal 34 translation.
Bidirectional signal translation allows 36 for greater bandwidth signal transmission over prior 37 art unidirectional systems, as seen with reference to 38 Figures 2A-2C.
01 _ 7_ 1333418 02 Turning to Figure 2A, a typical prior art 03 unidirectional PCM transmission scheme is illustrated 04 utilizing a central time/space switch 11 connected to 05 a plurality of PCM links such as PCM highways 13A and 06 13B. PCM highway 13A carries signals received from a 07 plurality of codecs such as codec 14 and codec 15 on 08 pre-designated time slot channels (eg. channel O from 09 codec 14 and channel 1 from codec 15) . A typical PCM
communication system will utilize 32 channel PCM
11 frames of data applied to each of the PCM highways in 12 a cyclic recurring manner. Thus, each of the transmit 13 and received PCM highways 13A and 13B carry 32 time 14 slots for accomodating 16 simultaneous conversations over 32 ports (ie. codecs). PCM information signals 16 are generated by codec 14 during time slot O for 17 reception by time/space switch 11 via transmit PCM
18 highway 13A. Likewise, codec 14 receives from 19 time/space switch 11 PCM information signals during time slot 0, via receive PCM highway 13B. Similarly, 21 codec 15 received and transmits PCM signals during 22 time slot channel 1. In like fashion, additional 23 codecs may be provided, in number up to 32.
24 Thus, a telephone system configured as in Figure 2A, running at 2MHZ, would be characterized by 26 a signal bandwidth of 4 megabits per second.
27 Turning to Figure 2B, a bidirectional 28 single wire system is illustrated in which time/space 29 switch 11 has been replaced by a predetermined time slot connection of codecs 14 and 15 to bidirectional 31 PCM highway 16. PCM information signals transmitted 32 during time slot O from codec 14 are carried by PCM
33 highway 16 and received by codec 15 during the same 34 time slot. Likewise, codec 15 generates and applies PCM signals to the highway 16 during time slot channel 36 1 for reception by codec 14. In this way, a 37 conversation is established between codecs 14 and 15 38 utilizing the single wire highway 16, without 02 requiring a dedicated central switching matrix. In 03 this manner, up to 16 conversations between 32 ports 04 (ie. codecs) may be accomodated utilizing a single 05 wire PCM highway 16. The system of Figure 2B is 06 characterized by a bandwidth capability of 2 megabits 07 per second yet utilizes only one wire as opposed to 08 the 2-wire system of Figure 2A, and eliminates the 09 neccessity for time/space switch 11. Furthermore, the number of ports which can be accomodated by the system 11 of Figure 2B, is doubled over the prior art system of 12 Figure 2A.
13 Figure 2C illustrates a 2-wire 14 bidirectional system in which codecs 14 and 15 are connected to a pair of bidirectional PCM highways 17A
16 and 17B. According to the system of Figure 2C, each 17 of the codecs 14 and 15 generates and receives PCM
18 signals on the shared time slot 0, for carrying on a 19 conversation. Thus, according to the 2-wire bidirectional system of Figure 2C, up to 32 21 conversations may be carried on between 64 ports over 22 32 time slots, with a bandwidth of 4 megabits per 23 second. Accordingly, the port handling capability of 24 the 2-wire bidirectional system of Figure 2C is exactly twice that of the prior art unidirectional 26 system shown in Figure 2A.
27 In order to implement the bidirectional 28 PCM signal transmission systems of either Figure 2B or 29 2C, each of the codecs 14 and 15 must be provided with circuitry for selectively enabling transmission and 31 reception of PCM signals via the individual codecs 32 during the predetermined time slot channels.
33 According to the present invention, such 34 time slot allocation circuitry is provided by means of a digital crosspoint switch, as shown in detail with 36 reference to Figures 3 and 4. In particular, a 37 preferred embodiment of the present invention is shown 38 with reference to Figure 3 in which PCM bus 1 is 02 comprised of a plurality of bidirectional PCM highways 03 B0-B4, a unidirectional tone bus B5(T), a 04 bidirectional data lead D0 and a plurality of timing 05 leads C4, F0 and NS. Each of the interface circuits 3 06 and 5 is shown comprised of a digital crosspoint 07 switching matrix (ie. DX chip 21A and 21B), control 08 circuitry (ie. central processor unit 23A and local 09 control unit 23B), a communication controller (ie.
HDLC controllers 25A and 25B) and timing generators 11 26A and 26B. Four unidirectional ST buses (eg. CST
12 and DST) are connected between the digital crosspoint 13 switching circuits 21A and 21B and respective ports, 14 such as tone generator and conference circuit 28 in main control unit 3 and the codecs and interface 16 circuitry 30 within station/trunk interface 5.
17 All of the PCM buses are run at a data 18 rate of preferably 2.048 megabits per second resulting 19 in a total backplane PCM bandwidth of 10.24 megabits per second, which provides a total non-blocking system 21 capacity of 160 voice-only ports, or 80 voice/data 22 (ISDN) ports.
23 The on-board control circuitry (eg. local 24 control unit 23B and central processor unit 23A) provide microprocessor controlled local intelligence.
26 Individual control circuitry of the respective 27 interface circuits communicate with each other over 28 the 2.048 megabit per second packet switched local 29 area network provided by data lead D0 and HDLC
controllers 25A and 25B.
31 In order to better understand the present 32 invention, a typical scenario will be described with 33 reference to Figures 1 and 3, for illustrating a 34 normal call sequence in accordance with the present invention.
36 For example, a remote user of a digital 37 subscriber set (not shown) connected to ISDN port card 38 7 may go off-hook. The off-hook condition is detected 1333~18 02 by the local control unit of ISDN port card 7, which 03 in response formulates a message signal for 04 transmission via the associated HDLC controller for 05 reception by main control unit 3, in order to indicate 06 to the main control unit 3 which one of the remote 07 peripherals has gone off-hook.
08 Meanwhile, tone generator 28 of main 09 control unit 3 is constantly generating and applying dial tone and other supervisory tones during 11 respective time slot channels on unidirectional tone 12 bus B5(T). The ISDN port card 7 extracts the dial 13 tone signal from bus B5(T) via the associated digital 14 switching circuit disposed thereon. The dial tone signal is then transmitted to the remote digital 16 subscriber set (not shown) in a well known manner.
17 In response to dialing predetermined 18 digits at the remote digital subscriber set, ISDN port 19 card 7 transmits dialling digit information via backplane bus 1 for reception by main control unit 3.
21 In the event that the central processor unit 23A of 22 main control unit 3 detects a valid telephone number 23 as identified by the dialling digits, the central 24 processor unit 23A formulates and generates a message signal to station/trunk interface circuit 5 for 26 establishing a connection in accordance with call 27 processing software and transmits dial digit 28 information via HDLC controller 25A and data lead 29 DO to a predetermined idle trunk circuit connected to one of the codecs and interfaces 30. The call 31 processing software may also implement such features 32 as least cost routine, long distance inhibit, etc.
33 The central processor unit 23A of main control unit 3 34 contains a memory map of available time slots within respective ones of the digital switches associated 36 with interface circuits 3-9. The available time slots 37 may be pre-selected for individual ones of the codecs 38 30, tone generator and conference circuit 28, or other - ol - ll - 1333418 02 peripheral interfaces since dynamic time slot 03 assignment is not required in accordance with the 04 present invention due to its non-blocking 05 configuration.
06 Thus, central processor unit 23A generates 07 message signals to station/trunk interface circuit 5 08 as well as ISDN port card 7 for allocating 09 predetermined time slots within the associated digital switching circuits in order to establish a 11 communication channel via a predetermined one of the 12 bidirectional signals buses B0-B4, between the remote 13 digital subscriber set connected to ISDN port card 7 14 and the remote trunk circuit connected to analog station/trunk card 5. Each of the digital switching 16 circuits 21A, 21B, etc., includes 256 memory locations 17 which are split between the backplane buses B0-B4 and 18 B5(T) and the CST and DST buses connected to the 19 remote peripherals.
Thus, a conversation path is established 21 by means of the circuitry shown in Figures 1 and 3 22 between a first remote peripheral such as a digital 23 subscriber set connected to ISDN port card 7 and a 24 second remote peripheral, which in this case is a remote trunk circuit connected to analog 26 station/trunk card 5. Additional connections between 27 a remote party and the trunk circuit are effected in a 28 well known manner.
29 Turning to Figure 4, a schematic block diagram is shown illustrating the HDLC controller 25A
31 and digital crosspoint switching circuit 21A of the 32 main controller connected to the central processor 33 unit 23A. Of course, the configuration of HDLC
34 controller, digital crosspoint switching circuit and control circuitry of Figure 4 is implemented on each 36 of the interface circuits 3-9, resulting in generic 37 access to the universal backplane, as discussed above.
38 According to the successful prototype ~ 01 - 12 - 1333~18 02 shown in Figure 4, the HDLC controller 25A was 03 implemented utilizing a MT8952B HDLC protocol 04 controller and the digital crosspoint switching 05 circuit 21A was implemented utilizing a model MT8980D
06 crosspoint switching circuit, both manufactured by 07 Mitel Corporation.
08 In summary, the system architecture in 09 accordance with the present invention is based on a flexible, wide bandwidth backplane with universal 11 slots. Any card (ie. interface circuits 3-9) may be 12 plugged into any slot on the backplane, and each card 13 has access to the full system bandwidth. The 14 backplane is preferably configured as one or more modules that can be expanded to a maximum of 32 16 slots. The system in accordance with the present 17 invention utilizes distributed processing as well as 18 distributed switching, for facilitating use of the 19 universal backplane. The disadvantages associated with prior art central processing and central 21 switching systems are overcome by the system of the 22 present invention, as discussed in detail above.
23 A person understanding the present 24 invention may conceive of other embodiments or variations therein.
26 For example, the data rate of PCM
27 signals carried by the backplane bus 1 may be 28 increased from 2.048 megabits per second in the 29 preferred embodiment to 4.096 megabits per second or greater. This would increase the system non blocking 31 capacity to upwards of 320 analog voice only ports or 32 160 voice/data (ISDN) ports. This modification would 33 be easy to achieve since the only significant change 34 would be to double the bit rate capacity of the digital crosspoint switch utilized in each of the 36 interface circuits.
37 Other applications of the present invention 38 are possible in connection with high capacity data 13334 ~ 8 02 only PABXs, or Tl digital trunk multiplexers, etc.
03 Also, whereas the block diagram of Figure 04 1 illustrates a representative configuration of 05 interface circuits, many other combinations of 06 interface circuits are possible. For example, Tl 07 digital trunk cards, miscellaneous alarms cards, etc.
08 may be advantageously incorporated into the system of 09 the present invention.
These and other embodiments or 11 modifications are believed to be within the sphere and 12 scope of the present invention as defined by the 13 claims appended hereto.
Claims (10)
1. A digital communication system, comprised of:
(a) a universal backplane bus, (b) one or more interface circuits each including control means for generating and receiving message signals to and from said bus, (c) one or more remote peripherals connected to predetermined ones of said interface circuits, for generating and receiving information signals, (d) switching means included in each of said interface circuits for effecting distributed bidirectional switching of said information signals between said remote peripherals via said bus, and (e) communication controller means included in each of said interface circuits for exchanging said message signals between said control means via said bus in accordance with a bit oriented data link protocol, in response to which said control means supervises said bidirectional switching of said information signals.
(a) a universal backplane bus, (b) one or more interface circuits each including control means for generating and receiving message signals to and from said bus, (c) one or more remote peripherals connected to predetermined ones of said interface circuits, for generating and receiving information signals, (d) switching means included in each of said interface circuits for effecting distributed bidirectional switching of said information signals between said remote peripherals via said bus, and (e) communication controller means included in each of said interface circuits for exchanging said message signals between said control means via said bus in accordance with a bit oriented data link protocol, in response to which said control means supervises said bidirectional switching of said information signals.
2. A digital communication system as defined in claim 1, wherein at least one of said interface circuits includes one or more codecs connected to said remote peripherals and said switching means for receiving said information signals from said remote peripherals in analog format and converting the analog format signals to digital format and transmitting the digital format signals to said switching means, and for receiving the digital format signals from said switching means and converting the digital format signals to said analog format and transmitting said analog format signals to said peripherals.
3. A digital communication system as defined in claim 2, wherein at least one of said interface circuits includes a tone generator and tone detection circuitry connected to said switching means, for generating predetermined tone signals for transmission to said remote peripherals via said switching means and said bus, and for receiving and detecting additional tone signals generated by said remote peripherals.
4. A digital communication system as defined in claim 1,2 or 3, wherein said bit oriented protocol is HDLC protocol.
5. A digital communication system as defined in claim 1, 2 or 3, wherein said switching means is comprised of a time and space digital switch.
6. A digital communication system as defined in claim 1, 2 or 3, wherein at least one of said interface circuits is comprised of an ISDN port card for supporting ISDN communication of said information signals between respective ones of said remote peripherals.
7. A digital communication system as defined in claim 1, 2 or 3, wherein at least one of said interface circuits is comprised of a local area network gateway card for supporting communication of said information signals between predetermined ones of said remote peripherals and a local area network.
8. A digital communication system as defined in claim 1, 2 or 3, wherein said bus is comprised of five bidirectional PCM links connected to said switching means for carrying said information signals transmitted at a rate of approximately 2MHz, thereby resulting in a signal bandwidth on said bus in excess of 10Mbs, and a port handling capability of over 160 analog ports or 80 ISDN ports.
9. A digital communication system as defined in claim 1, 2 or 3, wherein said bus is comprised of five bidirectional PCM links connected to said switching means for carrying said information signals transmitted at a rate of approximately 4MHz, thereby resulting in a signal bandwidth on said bus in excess of 20Mbs, and a port handling capability of over 320 analog ports or 160 ISDN ports.
10. A digital communication system as defined in claim 1, 2 or 3. wherein at least one of said interface circuits is comprised of a Tl digital trunk card for multiplexing and exchanging digital voice and data signals between said system and a digital trunk.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000573618A CA1333418C (en) | 1988-08-02 | 1988-08-02 | Digital key system architecture |
| GB8904889A GB2221596B (en) | 1988-08-02 | 1989-03-03 | Digital key system architecture |
| DE3921573A DE3921573C2 (en) | 1988-08-02 | 1989-06-30 | Digital communication device |
| US07/386,697 US5202883A (en) | 1988-08-02 | 1989-07-31 | Digital key stystem architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000573618A CA1333418C (en) | 1988-08-02 | 1988-08-02 | Digital key system architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1333418C true CA1333418C (en) | 1994-12-06 |
Family
ID=4138474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000573618A Expired - Fee Related CA1333418C (en) | 1988-08-02 | 1988-08-02 | Digital key system architecture |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5202883A (en) |
| CA (1) | CA1333418C (en) |
| DE (1) | DE3921573C2 (en) |
| GB (1) | GB2221596B (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5301303A (en) * | 1990-04-23 | 1994-04-05 | Chipcom Corporation | Communication system concentrator configurable to different access methods |
| US5301057A (en) * | 1990-10-15 | 1994-04-05 | Dsc Communications Corporation | Subscriber interface for a fiber optic communications terminal |
| DE69323661T2 (en) * | 1992-07-17 | 1999-07-22 | Rolm Systems | Method and device for connecting additional devices to a digital telephone |
| US5349579A (en) * | 1993-01-05 | 1994-09-20 | Excel, Inc. | Telecommunication switch with programmable communications services |
| US5410542A (en) * | 1993-03-01 | 1995-04-25 | Diaogic Corporation | Signal computing bus |
| US5453979A (en) * | 1994-01-27 | 1995-09-26 | Dsc Communications Corporation | Method and apparatus for generating route information for asynchronous transfer mode cell processing |
| JPH07250085A (en) * | 1994-03-10 | 1995-09-26 | Fujitsu Ltd | Load distribution method for bus in data communication equipment and bus changeover controller for the data communication equipment |
| GB9408574D0 (en) | 1994-04-29 | 1994-06-22 | Newbridge Networks Corp | Atm switching system |
| DE4438697A1 (en) * | 1994-10-29 | 1996-05-02 | Sel Alcatel Ag | Method for loading multi-computer systems |
| DE4438698A1 (en) * | 1994-10-29 | 1996-05-02 | Sel Alcatel Ag | Method of loading multi-computer systems |
| DE19528067C1 (en) * | 1995-07-31 | 1996-11-14 | Siemens Ag | Error message processing method for communication system |
| AT405231B (en) * | 1996-05-20 | 1999-06-25 | Vaillant Gmbh | ELECTRIC WATER HEATER WITH REMOTE CONTROLLED OUTLET TEMPERATURE |
| US6229822B1 (en) | 1996-10-24 | 2001-05-08 | Newbridge Networks Corporation | Communications system for receiving and transmitting data cells |
| FR2811790A1 (en) * | 2000-07-11 | 2002-01-18 | Schlumberger Systems & Service | Smart card microcontroller secured against current attacks, uses module between processor and external supply which chaotically encrypts supply current fluctuations |
| US20020126709A1 (en) * | 2001-03-06 | 2002-09-12 | Richard Lauder | DWDM network |
| US7697570B2 (en) * | 2001-04-30 | 2010-04-13 | Huawei Technologies Co., Ltd. | Method based on backboard transmitting time division multiplexing circuit data and a bridge connector |
| US6671748B1 (en) * | 2001-07-11 | 2003-12-30 | Advanced Micro Devices, Inc. | Method and apparatus for passing device configuration information to a shared controller |
| US7162554B1 (en) * | 2001-07-11 | 2007-01-09 | Advanced Micro Devices, Inc. | Method and apparatus for configuring a peripheral bus |
| DE10232982B4 (en) * | 2002-07-19 | 2005-11-10 | Rohde & Schwarz Gmbh & Co. Kg | Method and arrangement for receiving-side detection of the associated data channels of time-multiplexed transmitted data signals |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4387425A (en) * | 1980-05-19 | 1983-06-07 | Data General Corporation | Masterless and contentionless computer network |
| US4382295A (en) * | 1981-04-23 | 1983-05-03 | Bell Telephone Laboratories, Incorporated | Digital conference time slot interchanger |
| US4608700A (en) * | 1982-07-29 | 1986-08-26 | Massachusetts Institute Of Technology | Serial multi-drop data link |
| GB2128446B (en) * | 1982-10-02 | 1985-09-04 | Standard Telephones Cables Ltd | Telecommunication exchange |
| DE3301979A1 (en) * | 1983-01-21 | 1984-07-26 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for a telecommunications system, in particular a telephone PBX system, with subscriber and line transmission groups and interface modules |
| US4554658A (en) * | 1983-07-07 | 1985-11-19 | Motorola, Inc. | System for producing encoded and decoded voice, internal audio tones, and data communication within a time division multiplex network |
| GB8601545D0 (en) * | 1986-01-22 | 1986-02-26 | Stc Plc | Data transmission equipment |
| US4791629A (en) * | 1986-06-02 | 1988-12-13 | Ibm Corporation | Communications switching system |
| US4740955A (en) * | 1986-10-29 | 1988-04-26 | Tie/Communications, Inc. | Communications system having voice and digital data capability and employing a plurality of voice and data buses in main service unit and serial packetized transmission to and from telephones |
| US4823338B1 (en) * | 1987-08-03 | 1998-11-10 | At & T Information Systems Inc | Virtual local area network |
| US4908823A (en) * | 1988-01-29 | 1990-03-13 | Hewlett-Packard Company | Hybrid communications link adapter incorporating input/output and data communications technology |
-
1988
- 1988-08-02 CA CA000573618A patent/CA1333418C/en not_active Expired - Fee Related
-
1989
- 1989-03-03 GB GB8904889A patent/GB2221596B/en not_active Expired - Lifetime
- 1989-06-30 DE DE3921573A patent/DE3921573C2/en not_active Expired - Fee Related
- 1989-07-31 US US07/386,697 patent/US5202883A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| GB2221596B (en) | 1992-08-05 |
| DE3921573A1 (en) | 1990-02-08 |
| DE3921573C2 (en) | 1995-02-16 |
| GB2221596A (en) | 1990-02-07 |
| GB8904889D0 (en) | 1989-04-12 |
| US5202883A (en) | 1993-04-13 |
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