CA2007435C - Electronic gaming device with pseudo-stereophonic sound generating capabilities - Google Patents

Electronic gaming device with pseudo-stereophonic sound generating capabilities

Info

Publication number
CA2007435C
CA2007435C CA002007435A CA2007435A CA2007435C CA 2007435 C CA2007435 C CA 2007435C CA 002007435 A CA002007435 A CA 002007435A CA 2007435 A CA2007435 A CA 2007435A CA 2007435 C CA2007435 C CA 2007435C
Authority
CA
Canada
Prior art keywords
sound
data
signal
switching
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002007435A
Other languages
French (fr)
Other versions
CA2007435A1 (en
Inventor
Satoru Okada
Hirokazu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nintendo Co Ltd
Original Assignee
Nintendo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1004453A external-priority patent/JPH02184200A/en
Priority claimed from JP1989002007U external-priority patent/JPH0293893U/ja
Priority claimed from JP1101027A external-priority patent/JP2878306B2/en
Application filed by Nintendo Co Ltd filed Critical Nintendo Co Ltd
Publication of CA2007435A1 publication Critical patent/CA2007435A1/en
Application granted granted Critical
Publication of CA2007435C publication Critical patent/CA2007435C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F13/00Video games, i.e. games using an electronically generated display having two or more dimensions
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F13/00Video games, i.e. games using an electronically generated display having two or more dimensions
    • A63F13/40Processing input control signals of video game devices, e.g. signals generated by the player or derived from the environment
    • A63F13/44Processing input control signals of video game devices, e.g. signals generated by the player or derived from the environment involving timing of operations, e.g. performing an action within a time slot
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F9/00Games not otherwise provided for
    • A63F9/24Electric games; Games using electronic circuits not otherwise provided for
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04RLOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00Circuits for transducers, loudspeakers or microphones
    • H04R3/12Circuits for transducers, loudspeakers or microphones for distributing signals to two or more loudspeakers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04SSTEREOPHONIC SYSTEMS 
    • H04S5/00Pseudo-stereo systems, e.g. in which additional channel signals are derived from monophonic signals by means of phase shifting, time delay or reverberation 
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F9/00Games not otherwise provided for
    • A63F9/24Electric games; Games using electronic circuits not otherwise provided for
    • A63F2009/2448Output devices
    • A63F2009/247Output devices audible, e.g. using a loudspeaker
    • A63F2009/2476Speech or voice synthesisers, e.g. using a speech chip
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F2300/00Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game
    • A63F2300/20Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game characterised by details of the game platform
    • A63F2300/204Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game characterised by details of the game platform the platform being a handheld device
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F2300/00Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game
    • A63F2300/20Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game characterised by details of the game platform
    • A63F2300/206Game information storage, e.g. cartridges, CD ROM's, DVD's, smart cards
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F2300/00Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game
    • A63F2300/60Methods for processing data by generating or executing the game program
    • A63F2300/6063Methods for processing data by generating or executing the game program for sound processing
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F2300/00Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game
    • A63F2300/80Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game specially adapted for executing a specific type of game
    • A63F2300/8047Music games
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S84/00Music
    • Y10S84/27Stereo

Abstract

An electronic gaming (e.g., a video game) device includes a psuedo-stereo sound generator. Plural independent sound generating circuits produce audio signals under microcomputer control. The microcomputer may route the outputs of the plural sound generating circuits independently to one or the other (or both) of two independent audio channel outputs so as to produce pseudo-stereo sound. A selecting circuit automatically mixes the two audio channel outputs together and provides them in monaural form to an internal loudspeaker when no stereophonic headset is connected. A
microcomputer controls generation of sounds and music in accordance with a musical pitch (frequency) data structure, a musical duration data structure and a musical score data structure stored in an interchangeable memory cartridge. The musical score data structure specifies pitch and duration in terms of address offsets into pitch and duration data structures.

Description

~)7~

ELEC~RQNIC G~MING;r~F.~7:t~E WI~I PSEUDO-STE]REOPHC)NIC
SOUNU ~'E~RAl'ING C~PABILITIE:S
FIELD OE l~ INVENTION

The ~resent inventicn relates to el.ectron:ic:
gam.ing devices, and more partisularly to microprocessor cont.rolled electronic cJamin~ devi.ces provi.ding a two-di~.en~ional display. More parti.cularly, the prsse]1t invention I~elates to generation of pseud.o-stl3reophon:ic mus:ic and sourld effec:ts in such an el~ctronic gaminCJ device. St:ill more specifically, the present invention relate~s to a pseudo-ster~aophonic SOUIlCl genel-ating apparatus and method for ~enera-tinc~ music, sollnd effe(:ts and other sound~ in a gaming devi.c,~ ~such as, f~or example, an el~ctronic television yaming device o:r portable hand-held electronic li~uid crystal d.i.sl?lay typ~
ganling devic~) usinc3 an exte~nal memo:ry cartrid,..~e.

B~Kf3ROI~ND .~) Sl~q~ ' OF T~E lNY~Nl.l~M

Cor~ventional ele,~txonic video and oth~sr galllinCJ
devi~es generate scunc.ls sllch as music, sou:nd effects noises and the l:ike,i.n respon.se to souncl-r~spresenting clig.ital data stored in a memory dev.ice. H~wever, in the past the sc,uncl si.,3nals so c3enerated were morlaural rather than stereoF~hc)nic for a variety of reasorls.
As is well kncwn, "s.terecp.l1onic" soun~l gel1erally provides two independent (but related) audio channels (e.g., "left" channel ancl "rigli1t" cha}1n~3l). Eac:h of the audio channels incll.1des inclependent aud:io (clnd ' . . ~ ' -. ' ~ . . !
' . ' ' ~ ' ' ""' . '~ : '. '" ' :;:

. 2 other) signal processing circuitry. The signals generated by the independent stereo audio channels are typically reproduced by spatially separated audio transducers (e.g., "left" and "right" loudspeakers or headset transducers).
In the sound recording industry, the diff~rent stereo channels are typlcally recorded and/or mixed independenkly such that the audio signals eXistinCJ in the two channels upon playback are different but related. Due to the phase and other signal relationships between related sounds generated simultaneously (or nearly simultaneously) in the different channels, the listener perceives a two-dimensional spatial quality to the sound.
Stereophonic sound thus provides a more enjoyable listening experience because the listener perceives he is immersed in an envelope of sound emanating from plural spatially-separated sources. This effect is especially enhanced when listening to the stereophonic sound through a s1:ereophonic headset.
As is well kncwn, it is possible using conventional computer technic~les to synthesize stereophonic sound by providing left and right channel sound generators controlled by left sound data and right sound cdata, respectively, storecl in a dicJital memory device. Un~ortunately, twice as much memory is typically rec~tired ~or producing such stereophonic sound as compared to the case in which only monaural sound i.s being generated. Moreover, it is also necessary to provide separate sound synthesizing circuits ~"sound sources") for the left channel and the right channel, increasing the complexity and cost of the resulting circuit :: : - -: ::' ' ~ . : , . 3 configuration.
A pseudo-stereo sound generating apparatus is disclosed in laid-open Japanese Utility Model Application No. 66~00/1983. This reference discloses receiving an AM broadcast signal with an AM broadcast receiver (tuner) and enhanci.ng the receivecl AM signal (which is monaural) to pro~ide a pseudo-stereophonic sound effect. This document does not acldress the problem of providing stereophonic souncl in a v.ideo gaming device having limitecl memory resources.
The present invention provides a pseudo-st~reophonic s~und gen.erating apparatus and method which generates pseudo-stereo sound usincl inexpensive, relatively uncompl.icated circuitry which actually reduces memory requirements.
The present i~.vent:i.on also prov.ides a novel.
memory cartridge which can be used in a video gaming device having pseudo-stereo sound generating circuitry.
The present invention further provides a nc)vel hand-held video c~a~.ing apparatus including a pseudo-~stereo sound. generator.
A further important and advantageous feature provided by the present invention is a hand-hel.cl video yaming device i.n which sound effects ca.n be generated stereophonically through a stereo heaclset.
In accordance with one aspect of the present invention, a plurality of independent sound synthesizer circuits are provided. Some of the sound synthesizer circuits may be used for gener~ting left-channel output signals, others of the souncl synthesizer circuits may be used for generating r:ight-channel output signals, and still others of the . .

sound synthesizer circuit:s may be used for generating audio signals for application to both the left and the right audio output channels. However~ in the preferred embodiment of the present invention -there is no permanent assiynment of sound synthesizer circuits to audio output chamlels. Instead, audio switching circuits provided at the output of the sound synthesi~er circuits selectively direct the various synthesizer circuit outputs to the left or right audio OUtpllt chamlels as desired. The states of the analog switchiny circuits may be altered under program control to change the audio output channe].
the signal produced by a particular sound synthesizer circuit is directed to.
For example, in accordance with a feature provided by the present invention, a left chamlel audio signal bus and a right channel audio signal bus are provided. The left channel audio signal bus provides left channel audio signals to a left channel audio signal amplifier and associated sound transducer (e.g., the left chatmel transdu,-er of a stereophonic headset~. Similarly, the right channel audio signal bus applies a right channel audio signal to a riyht channel audi.o amplifi.er and associated souncl transducer (e.g., a right channel transduc:er of the same stereopho~ic headset). A plurality of sound synthesizer circuits ("sound sources") are also provided. The sound sources iIl the preferred embodiment independently produce various audio signals (e.y., musical pitches, sound effects, etc.) under program contro].. The output of each (any) of the plurality of sound sources may be coupled to the left channel audio si~nal bus via lef-t channel analog . .

. 5 switches and/or to the right channel. audio signal bus via right channel analoy switches. The states of the analog switches are controlled by program control instructions and thus may be dynamically changecl as desired.
Thus, the output o:E a particular sound source may be applied to only the left channel audio si.gnal bus, to only the right channel audio signal bus, or to both the left an.d the right audio signal buses by simply selecting the states of the analog swîtches coupled to its output: (and these states can be changed as desired under program control). By simultaneously or sel.ectively turning on or off the left channel and right channel analog switches associated with a part.icular sound source, souncl signals may be directed to one, the other or bot:h audio output chalmels.
Since in accordance with the present .invent:ion it is possible to select the channel a particular sound source app].ies its output to, the:re .is no requi.rement to store complete].y different sets of sound generating da.ta (left channel and right channel) corresponding to the two sterephonic musical programs. That is, i.t is only necessary to store different sound generating data for controlling the plural sound generating sources which are to be active duxing a paxti.cular time. The additional data used for selecting which of the audio channels the various sound sources are to apply their outpu-ts to reguires very little additional storage space--al].owing pseudo-stereophonic sound to be provided with only a s]..ight addi-tion in memory storage capacity. Since it is possible to selec:t ~ ~3t~

which channels a particular sound source signal is to be applied to, memory requirements do not increase substantially (in contrast with a situation in which left and right channel signals are stored separately in memory, which genera:Lly requires two times the amount o~ memory neecled to store audio informati.on for a monaural charmel). Moreover, a more versatile and less complex circuit configuration is provicled by the present invention, making it especially suit:ed for generating sou~.d ef:~ects ~rithin a miniaturized porta~le video gaming devlce.
In t~he video gaminy device descrihed above, a sound source signal generated by the sound sourc:e signal generating means i.s thus selectively outputted by the first and second (e.g., left and right) sound signal channels to a switching operation performed by the analog switching means so as to procluce a pseudo-stereophonic sound.
The present invention also provides a memory cartridge detachably engageable to a video gamlng device which provides stereoFhonic sound control signals. The video gaming device includes souncl source signal generating means for generating a sound signal in accordance wi-th data provided by the memory cartridge. SwitchincJ means may connect an outpl.lt of the sound signal generating means to either or both of first and secona. sound output channels, and selectively applies the output of the sound source signal generating means to the first an~/or the second sound signal output channels. For music generation, the memory cartridge preferably stores data representing the duration (length in time) of a musical note or re~t; data associated with musical ~ , : -:
.: -:: : -: : . . . :-pitch; and "direction data" specifying the audio output channel to which the sound generated at t:he speci~ied pitch and for the specified duration is to be directed.
The memory cartridge stores a secluence of such sets of data correcponding to a sequence of musical or sound effect events (i.e., notes and rests) and, in the preferrad embodiment, accesses the data sets in the order of the sequence (wlth time separating the access of differant clata sets in the secluenc:e~ so as to speci~y the sequence of musical or sound effect events. In the prefe3~red em~odiment the memory cartridge may store plural data sets corresponding to a yiven instant in the se~uence of musical or sc)und ~~fect events -- thus providing simul-taneous control over mult:iple sound sources.
The memory cartridge in the preferred embocliment further stores program control instructions ~or readin~ respective data representing sounds for predetermined timi~gs--thus providing a mechanism for applying the len~th (duratioll) associative data, musical pitch associative data and left/right channel specifier ("direc:tion") clata to the vicleo gaming device in accordance with program control instructions reacl from the cartridge.
The mernory c~artridge of the preferred embocliment of the present invention preferably stores multiple data structures representing different aspects of the sound to be generated. In particular, the cartridge preferably stores a musical score data table representing information typically represented by sheet music ~e.g., the pitch and duration of mu~;ical notes, and the duration of rests for a sequence o~

such notes and rests). This musical score data table in turn praferably provides offset addresses into a duration data structure mapping different musical note and rest durations stored in the musical score table into appropriate sound generator circuit timing control signals; and into a frequency data structure mapping different pitches into appropriate souncl generator circuit pitch control signals.
In accordance with the progress of th~s computer program stored within the memory cartridge, the duration associativa data, musical pitch interval associative data and .left/right channel direction specifying data are read from the musical score table at predetermined timings (these timings are o~herwise determined by program flow). Musical p:itch of generated sounds.is cletermined .in accordance wit:h musical pitch associative data and a sustained t:ime period (i.e., length or duration) of that musical pitch is determined in accordance with the lengt:h ~duration) associ.at.ive data. The outpu-t multip].exing (switching) operation as described above i D perf'ormed in accordance with the left/right channel direction specifying data to obtain right channel sound output or left channel sound out,put as desired. Thus~ the se~uence of musical notes stored in the musical score table can be generated in pseudo-stereophonic sound.
Since the left or right channel data is stored i.n the memory cartrid~e and the left/right channel selection data specifies which channel the audio represented by any specific pitch and cluration data is to be directed to, it becomes possible to easily generate or produce pseudo-stereo sound such as music or sound effects.

~ . . .
- ,~ ~. :- , .

~ 9 In accordance wi-th a further feature of the present invention, a stereo/moIIaural changing ci.rcuit is connected to a stereo sound source from which left and right sound signals are independently output:ted.
The stereo/monaural changing circuit preferably includes an earphone jack ~or receiviny a conventional stereo type audio plug. The earphone jack includes at least one s~ltching contact as well as left and right channel audio contacts. The left channel audio contact conducts left channel audio signals to the headset left channel audio trans,clucer, and the right chann.el. audio contact similarly conducts right channel audio signals to the heaclset riyht channel audic trallsducer~ In addition, a monaural audio transducer (e.g., a loudspeaker internal to the vide~ gaming device) may be prc,vided.
When no earphone plug is inserted into the earphone jack, the switchiny contact generates a control signal which automatically deactivates the independent left an.d :right channel audio signal paths connected to the earphone jack left ancl right channel outputs-, and automati.cally activates a combining ("mixing"~ circui.t whic:h com~ines the left and right channel aud.io signals together into a monaural signal. The comhining circuit applie.s the combined audio monaural signal to the video gaming device internal loudspeaker. Vn the o-ther hand, inserting an earphone plug into the earphone jack changes the state of the contrcl signal produced by the earphone jack switching contacl to deactivate the com~ini.ng circuit (and there~y automatically deactivate the internal loudspeaker) and to instead complete the independent leEt and right signal channel paths to - , the earphone jack left and right channel contacts.
Thus, when the earphone plug is not inserted into the earphone jac:k, a monaural synthesized sound signal is provided to the internal speaker. WheI1 the earphone plug is inserted into the earphone jack, on the other ha~d, the left channel and right channel signal paths are not disabled and are instead respectively outputted to the left channel and right channel contacts of the earphone jack--and stereophonic sound is thus outputted to the stereophonic headset plucJged into the earphone jack.
In this way, the u~er may easily play the video gaming device as a completely self-contained uni.t and listen to monaural sound generated by an i:nternal loudspeaker. If on the other hand, the player woulcl like to experience the sound enhancement p:rovided by the pseudo-stereo sound generating capabil.ities described above, he need only insert the plug of stereo headset intc the earphone jack and place the headset on his head..
Thus, this fea.tuxe of the presen-t :inventiorl provides a novel st.ereo/monaural changing circu].t capable of selecting between stereophonic sound and monaural sound ever~ though th.e sound generating data stored in the data cartri.dge controls the sound generating circuitry to generate pseudo-stereophonic sound. Such a stereophonic/monaural selecting circuit is very effective for generating sound effects in a hand-held video type gaming machine.

B~IEF DESCRIPTION OF T~ DR~WINGS

These and other objects, features, aspects and -.:
.: :
.

~ .
,. :
..

3~;

~ 11 advantages of the present invention will become more apparent and better understood from the followlng detailed descripticn of the presently preferred exemplary embodiment of the present invention taken in conjunction with the appended sheets of drawi.ngs, of which:

FIGURE 1 is a side perspective view of an exemplary hand-held liqui.d crystal display type video gaming device with which the present invention may be advantagéously utilized;

F'IGURE 2 is a schematic block diagram of the electronic circuitry contained within the FIGURE: 1 gaming device;

FIGURE 2A is a. more detailed schematic diagram of tthe architecture of the microcomputer shown i.n FIGURE 2;

FIGURES 3A-3D are schematic diagrams of an exemplary map of the address space of the CPU showr in FIGURE 2;

FIGURE 4 is a schematic block diaqram of an exemplary sound generator shown in FIGURE 2;

FIGURE 4A is a schematic diagram of e:~emplary contents of the registers NR50,NR51 and NR52 shown in FIGURE 4;

FIGURE 5 is a more detailed circuit diagram of an exemplary one of t,he ~ound. generating circuit:s , -:, ~ ' ~ - : ' 12 ~t~

shown in FIGURF, 4;

FIGURES 5A-5D are schematic d:iagrams of exemplary contents of the sound control registers within the sound ganeratiny circuits shown in F]:GURE
4;

FIGURE 6 is a graphical illustration of exemplary sheet music also show:ing some of the control parameters used for controlling th~_ dif~erent sound generating circuits shown in FIGURE 4;

FIGU~ES 7A-7B are together a schematic flow chart of exemplary program control s-teps p~srformed by the FIGURE 2 microcomputer in the preferred embodiment to generate the music represented by the FIGURE 6 sheet music;

FIGURE 8 is a schematic circuit diagr~m of an exemplary stereophonic~Jnonaural selecting circui.t arrangement shown in FIGURE 4; and FIGURES 9A-9D are schematic diagrams of exemplary contents of the memory cartriclge showrl in FIGURES 1 and 2.
DETAILED DESCRIE'TION OF PRESENTLY PREEERR~D
EXE.MP~RY EMBODIMENTS

First describecl~ill be the overall electronic gaming system provided by the presently pr~ferred exemplary embodiment of the present invention.
Following will be presented a more detaila~

;~ . ~ :: :.. .

3~

description of the microcomputer arrangement of the preferred embodiment, including the exemplary structure of the microcomputer and an exemplary memory organization for the microcomputer. Then, a detailecl description of the sound generator of the preferred embodiment will be presented. In connection with the sound generator, first described will be the overall architecture and opera-tion of the preferred embodiment sound gene.rator, including the manner in which plural independent sound generating circuits are preferably used in cooperation with one another to provide pseucdo-sterephonic sound. Mext presented will be a detailed description of the structure and operation of an exemplary one of t:he plural independent sound generating circuits.
Following will be presented a clescription of exemplary program control steps which may be performed and associated exemplary data structures which may be acces~ed by the microcomputer of the preferred embodimen.t to generate a line of muslc:.
Finally, a description of an exemplary stereophonic/monaura]. sound changing circuit wi].l be presented.

Overall Stru.cture and Oper~tion of the Presently Preferrecl Exemplary Gamin~ Device Figure 1 is an elevat~d perspective view showing the exterior housing of an exemplary hand-held liquid crystal electronic game m~chine in accordance with an exemplary presently preferred embodiment of the present invention. This hand-held liquid crystal game machine (here.inafter referred to as "game machine") 10 includes a case 12 which is provided with an LCD panel 14 including clot display segments being arranged in accordance with a dot-matrix system cn a frorlt or upper surface thereof.
On a rear or lower surface of the case 12, an insertion port 68 is formed at a portion opposit.e to the LCD panel 14. An external ROM memory cartridge 16 is pluggably inserted in the insertion port 68.
More specifically, a 32-pin connector 20 is pro~ided witllin the insertion port 68. By inserting the external ROM cartridge 16 into the insertioll port 68, a connector (not shown~ formed at an edge of a printed circuit boa.rd of the external ROM cartri.dge 16 is electrically and mechanically connected to the connector 20. Thuc, the external ROM cartridge 16 can be attachably/detachably connected to th.e game machine 10.
~ s referred tG herein, the external ROM
cartridye 16 is a "memory cartridge" and the yame unit 10 into which the memory cartridge is inserted is the "main unit." The cartridge 16 and main ~Init 10 in cornbination comprise an electronic gaming device. Different memory cartridges 16 may be , , ' ''' " '' ' . '_ . ' "' .

3~

inserted into port 68 so as to provide dif.ferent program control instructions -- and thus to change the game being played.
An external ROM 16a (see FIGURE 9A) is incorporated in the external ROM cartridge 16. A
game program is stcred in the external ROM 16a within program control instructions area 310. In add.ition, cartridge may also include additional memory devices (e.g., expansion RAM, a memory bank controller (MBC), etc.) as is well known. When the external ROM
cartridge 16 is inserted into the game machine ].0, the game program is executed such that an image is displayed on the LCD panel 14 and music for the game is generated at speaker 11 or through ear phones connect~d at jack 64.
A six-pin connector 65 is also provid~sd in the case 12, whereby the game machine can be l.inked to other machines by an appropriate cable so that multiple player competition is possible when the external cartridqe~ include multiple-player game programs .
A user input means comprising cross-key swi.tch 18 in tha preferre!d embodiment is provided on the front or upper surface of the case 12 at a left side portion below the LCD panel 14, as shown in Fig~lre 1. The cross-key switch 18 has four direction designating portions or conta.cts and, by depr~ssing any one of the same, it is possible to, for example, move a game charact.er displayed on display 14 upward or downward or left.ward or rightward. In additi.on, ..~.
as shown in Figure 1, two push--button switches 70a and 70b are provided on the front or upper surface of the case 12 at a right side portion below the LC'D

: : , ' ~

panel 14. These pu.sh-button switches 70a and 70b are operated when it is necessary to control the game character being displayed on the LCD panel 14 to perform various predetermined actions. Fo:r example, when the push-button switch 70a is depressed, the displayed character may appear to ~ump, or when the push-buttor.L switch 70b is depressed, the character may appear to throw a stone, or a ball, or launch various other objects. Thus, the cross-key switch 18 is disposed to be operated by the thumb of the ].eft hand, which sandwiches the case 12 in cooperation with the right hand, and the push-button switches 70a and 70b are disposed to be operated by the thumb of the right hand.
Furthermore, a start switch 72 and a select:
switch 74 are provided on the front or upper surface of the case 1~ of the game machine 10. As seen from Figure 3, the start. switch 72 and the select swi.tch 74 are arranged in a reyion 78 below ~the c:ross-key switch 18 and the Fush-button switches 70a and 70b.
These switches 72 a.nd 74 are centrally disposed so as to be operated hy the khumbs of any one of the ].eft hand and the right hand (while the left hand arLd the right hand hold the case 12 of the game machi.ne 10).
In other words, t:he s~itches 72 and 74 may be operated without significantly changing the positioning of the hands. The select switch 74 is used, for exampie, to select the mode of operation of the game ~eing dis~layed through the use of a menu screen. In this regaxd, the select switch 74 may be used to select one of a number of levels of game play. In addition, a f~ ction for selecting a ..
"weapon" usable by a game character can be assigned ~~~ 7~3~

to the select switch 74.
The start switch 72 is operated to start the game as selected. Therefore, it is not typically necessary to operate the start switch 72 and th~
select switch 74 during the game. However, sinc:e a pause (PAUSE) function is also assigned to the start switch 72, the start switch 72 may be depressed when it is desired for the game to be temporarily stopped. To start the game after such a pause, the start switch 72 may be depressed again. Furthermore, it is possible to make the start switch 72 and t:he select switch 74 possess many other functions under program control and to dynamically change the functions assigned to the switches as game play progresses.
The case 12 i~ additionally provided with on/of~
switch 1, battery power level light 13, contrast adjustment 50, and volume adjustment 66.

Exemplary Microcomputer Arrangement The heart of gaming device 10 is microcomputer 22 shown in FIGURE 2 (a detailed schematic diagram of the electronic circuitry within the gaming device).
Microcomputer 10 irlcludes a CPU 24, which may, by way of example only, be implemented with a commercially available microprocessor s~lch as a Z80 type VLSI
integrated circuit microprocessor chip. The CPII 24 is connected to the 32-pin cartridge connector 20 (and thus to the memory and other components wit:hin cartridge 16) via timing unit 25a and control bus 26a, address buffer 2Sb and address bus 26~ and data buffer 25c and data bus 26c (which buses and ,i : ~ ; -.. . , .;

, ; .,: , . . . - . .

associated components also comlect the CPU to a work RAM or scratchpad memory 23). When the external. ROM
cartridge 16 is engaged with the game machine 10, the CPU 24 is coupled to and cooperates with the e~ternal ROM cartridge 16.
Referring now more particularly to F~GURE 2A, CPU 24 cooperates with an address decoder 33 and memory selecting (bank switch) circuit 32 in the preferred embodiment to address the various devices within the address space of the CPU (e.g., an internal ROM 30, an internal RAM 28, and an external ROM 16a within cartridge 16). In addition, address decoder 33 may be used to permit CPU 24 to address various e~ternal ccntroL registers contained wit:hin other blocks shown in FIGURE 2 (e.g., control reglsters within scund generAtor 58) or other similar addres~ decoders may perform th.is function.
As is shown in FIGURE 2A, CPU 24 preferably includes internal ~-bit general purpose and spec:ial purpose r~gisters, a 16-bit program counter PC and a 16-bit stack pointer SP. A register A may be used as an accumulator and another registe]~ F may 'oe used as a flag register. The CPU 2g preferably has an associated instruction set permltting a variety of 8 and 16 bit transfers between registers or register pairs, a variety of 8 and/or 16 bit arithmetic operations (e.g., ~DD, SUB, AND/OR, INC. DEC, etc.), a variety of rotate/shift operations (e.g., rotate specified register contents left/right), a variety of bit control operations (e.g., setting a specified bit in a specified register), conditional and unconditional branch operations, .subroutine call and return operations and a variet~ of program control ,~

19 ~3~

operations (e.g., start, stop, no operation, etc~
all as is well known to those skilled in this art.
CPU 24 in the preferred embodiment performs such operations under control of pxogram colltrol instructions storec~ in memory cartridge 16 to provide game play display on display 14 in response to user inputs provided by the user via user input means 18.
In addition, CPU controls so~nd generator 58 to generate music and/or sound effects correspondirlg to gameplay under control of said same program control instructions stored in cartridge 16.
Referring once again to FIGIJRE 2, cloçk pu].ses are supplied to CPU 24 hy oscillator circuit 24b in response to quart~ crystal element 24a. Clock pulse divider 24c provides one or more clocking pulse rates and may be programmable by C.PU 24 to divide the clock pulses provided by oscillator circuit 24b by a desired ratio.
A programmable e~ternal hardware timer circ:uit 24d may also be provided to allow CPU to determi.ne when preset desired time intervals have elapsed. In the preferrecl embodiment, CPU 24 may load timer circuit ~4d with a value representing the ~urati.on of a time interval and then start the timer. The t:imer circuit 24d may automatically time the interval and when that interval elapses, the timer circuit may generate a interrupt signal which it applies to the CPU 24 (e.g., via interrput controller 24i) to alert the CPU that the time interval has elapsed. In this way, CPU 24 has the capability of timing intervals without having to use software timing loops (whi.ch may occupy CPU processing time and resources). This timer circuit 24d may be used if desirecl to time the .
: ..

duration of musical notes generated by sound generator 58 (as will be explained shortly).
CPU 24 outputs display data to an LCD controller 38 via a line buffer 36 under the control of a DMA
controller 34 in the preferred embodiment. The LCD
controller 38 is connected to a display RAM 42 via an LCD display RAM interface 40 and control, address and data busses.
The LCD control].er 38 operates under the control of CPU 24 via various addressable control/status registers which are located in the CPU address space as shown generally in Figures 3A-3D. These registers may include, for example, th~ followiny: LCD display register, LCD controller status register, horizontal and vertical scroll registers, LCDC vertical line identification register, and moving object and background palette (e.g., 2 bits identifying 1 of 4 gradations of shaded color) data register. The LCD
display register controls the nature of th~s display, and the status register indicates the curr~nt status of the LCD controller. Data corresponding to each dot of the background display data can he made available by changing the data of the hori~onta].
vertical scroll registers. The vertical line identification register indicates and controls t;he vertical line of the display to which data is presently being transferred by way of the dlsplay drivers. The X and Y window position registers control that portion or window of the LCD display area in which the ~BJ (motion picture) character as well as the BG (backyround) character data appears.
The LCD controller 38 converts display related data output from the CPU 24 into an LCD drive signal ' ' which is output from the display RAM 42. More specifi~ally, the display data from the CPU 24 designates addresses of the character RAM and the VRAM (video RAM) such that a character (or objec:t) signal and a background signal are output from the character RAM and the VRAM. Respective LCD drive signals are composed by the LCD controller 38.
The LCD drive signals are applied to an LC~
common driver 46 and an LCD segment driver 48 through an LCD drive signal buffer 44. Therefore, by means of the LCD common driver 46 and the LCD se~nent driver 43, an image in accordance with the display related data from the CPU 24 can be displayed on the LCD panel 14. The LCD panel may, for example, clefine a 144x160 matrix of pixels or dots, each having a corresponding uni.gue "intersecting" common .;
electrode/segment electrocle combination. The LC:D
common driver 46, which clrives the lines connected to the common electrodes, may for example, be a Sharp Corporation type L~ 5076 F inteyrated circuit. The LCD segment driver 48, may for example be a Sharp Corporation type L~ 5,077 F integrated circuit. These display drivers recei.ve data from the LCD drive signal buffer 44, ~hich receives data indirectly from the CPU 24 via the display RAM 42, the LCD RAM
interface 40 and the LCD controller 38.
In addition, a.n intensity level control 50 is connectecl to an LC~ buffer amplifier 52 su~h that the intensity of the display generated by LCD panel 14 can be adjusted.
Referring once again to FIGURE 2A, a reset signal from a reset c:ircuit 55 is applied to the CPU
24 and the memory selec:ting circuit 32. The reset ' -: - :

signal is output when a power switch 1 (see FIGURE 1) of the game machine 10 :is turned on, and therefore, the CPU 24 and the memory selecting circui-t 32 are initially reset at that time. Then, a rea~ signal RD
and write signal W~ are output from the CPU 24, which are suitably input to the external ROM cartridge 16, internal RAM 28, internal ROM 30 and the memory selecting circuit 32. In addition, an address decode signal is applied t.o the memory selecting circui.t 32 via an address decoder 33.

Exemplary Microcomputer Memory Or~anization Now, with referen.ce to Figure 3A-3B, an exemplary CPU address space and the nature of the data stored in internal memory 30 and the exterrlal memory cartridge 16 will be d.escribed in detail. As shown in Figures 3A and 3B, the internal ROM 30 has a first memory area which is designated by the addresses "OOOOH--OOFFH" which. corresponds to a first relatively small address space. The "H" indicat:es that these addresses are represented as a hexadecimal number. In the first memory area, first c:haract:er data for displaying, for example, a trademark "Nintendo", and an external memory authenticity determining program are stored~
The external ROM cartridge 16 includes the external ROM 16a. As shown in Figures 3C and 3D, the memory space of the external ROM 16a is divided into a second memory area which is designated by the address~s ''OOOOH-OOFFHI' ~which correspond identi.cally to the addresses defininy the above-described fi.rst address space) and a third memory area (second : :: . : -~ : :
- .: .. :
: : ~

address space) which is designated by the addresses "OlOOH-7FFFH". In an authorized external memory cartridge, in a region starting at the address "OlOOH" in the third memory area, second charact:er data (which is the same as the first character data) is stor2d. A game program is stored in the remaining region of the third memory area. Preferably, in a few bytes after the second character data storing region, auxiliary data such as a code identifying a manufacturer, the name of the game, the cartridge type, the memory size, etc., are stored. In addition, in the case where the requi.red capacity of a game program is large, the second memory area (''OOOO~-OOFFH'I) of the external ROM 16a may be used to store such a program data for the game.
Sound generator 58 shown in FIGURE 2 is also controlled by CPU 24 in accordance with program control instructions stored in cartridge 16. In the preferred embodiment, sound generator 58 includes a plurality o~ indep~ndent sound generating circuits which CPU can control independently or in ~ombirlation to produce multiple sourlds simultaneously. These registers reside the the "various registers" portion of ihe memory space shown in FIGURE 3B between locations FFOO (Hex) and FF80 ~Hex). CPU 24 controls sound generator 58 by writing appropriate control data to 8-bit registers physically located withi.n the sound generator but directly addressable by the CPU
and located within the CPU address space.
In the preferred embodiment, this sound generator register interface occupies the addresses FF10-FF26 within t~e CPU address space as follows:
Registers NRlC~-NR15 (controlling a first sound :

3~

generating circuit~ are located at addresses FFlO-FEl4;
Registers NR21-NR24 (controlling a second sound generating circuit) are located at addresses FF16-FF19;
Registers NR30-NR34 (controlling a third sound generating circui.t) are located at addresses FFlA-FFlE;
Registers NR41-NR44 (controlling a fourth sound generating circuit) are located at addresses EF20-FF23; and Registers NR5~-~1R52 (which provide overall sound control over the outputs of each of the sound ~enerating circuit~) are located at addresses FF24-FF26.
Some of.the registers ment.ioned above are ~rite only while other registers are read/write. CPU 24 can control various parameters of sound generation (e.g., fre~uency s~eep parameters for certain sound generating circuit~., waveform duty cycle, sound duration, envelope characteristics, sound frequency, polynomial counter parameters for certain sound generating circuits, tha allocation of certain sounds to certain output channels, and sound output levels~
directly by writing control data into the appropriate sound control registers (as will be described shortly).

Exemplary Sound Generator FIGURE 4 is a more detailed schematic diagram of sound generator blGck 58 shown in FIGURE 2. Sound ~enerator block 58 in the preferred embodiment 0~3~

includes a pluralit.y vf sound generator ci:rcuit~, 541-544, an analog multiplexer block 200, left and right solid state volume control blocks 72L,72R, left and right channel audio ampli~iers 60L,60R, and a ;
stereo/mono selection circuit 202.
Sound generator circuits 5~1-544 each independently generate audio signals in th~ preferred embodiment under control of.the contents of control registers NR10-NR44 within th.e address space of CPU
24 as described a~c,ve. The analog multiplexer 200 is controlled by registers NR50-NR52 within the address space of CPU 24 to route each of the sound generator circuit 541-544 out.puts to either or both of the left channel volume control 72L and the right channel volume control 72R. As will be explained in greater detail shortly, the analog multi.plexer 200 provides independent multiplexing control for each sound generator circuits 541-544 output under prograrn control. As one example, one sound generator circuit output may be routed to the left channel volume control 72L, another sound generator circuit output may be routed to t~e right channel volume ~ontrol 72R, yet another sound generator circuit output might be routed to both l.eft and right channel volume controls, and still another sound generator circuit output might be routed to neither of the volume controls (all of these assignments can c:hange under program control~.
The outputs of volume controls 72L,72R are amplified by left channel audio amplifier 60L and right audio amplifier 60R, respectively. The outputs of auclio amplifiers 60 in turn are applied to the stereo/mono selection circuit 202 for application to . , .

.
.

L3~

an internal mo~o loudspeaker 120 or to an optional e~ternal stareo headset 64 via an earphone jack 122.
Analog multiplexer 200 receives the respective outputs of sound generating circuits 541-544 (that is, the sound source signalsl~ Analog multiplexer 200 includes a pair of analog switches for each of sound generatiny circuits 541-544. For example, analog switches 681L, 681R correspond to sound generating circuit 541; analog switch~s 682L, 682R
correspond to sound generating circuit 542; analog switches 683L, 683R correspond to sound generating circuit 543; and ana]~,~g switches 684L, $84R
correspond to sound generating circuit 544. The outputs of one of the al1alog switches in each pair of analog switches (e.g., analo~ switches 6alL, 68,'L, 683L, 684L) are commonly connected to the left audio bus 300. The left audio bus 300 in turn is connected to -the input of volume control block 72L. Similarly, the output of the other analog switch in e~ch pair of the analog switches (analog switches 681R, 682R, 683R
and 684R) is connected to a rig11t audio bus 302 (i.e., so that all of these mentioned analog switches have their outputs connected iIl common). The right audio bus 302 is, in turn, connected to the output of the right chamlel volume controL block 72R. The respective outputs of solid-state volume control blocks 72L, 72R ~that is, the two sound signals~ are respectively amplified by left and right channe]
amplifiers 60L and 60R and thereafter outputted as first and second sGund outputs SOl, S02. In the embodiment shown, the output SO1 from amplifier 60L
may be utilized as a left channel sound signal, while the output S02 from amplifier 60R may be utilized as a right channel sound signal.
FIGURE 4A is a schematic block diagram depicting ~~~
exemplary registers NR50, NR51 and NR52 shown in FIGURE 4. Registers NRSO-NR52 are used in the preferred embodiment to control some of -the operating parameters of sound generating circuits 541-544, analog multiplexer 200, and volume controls 72L, 72R. Although multiple registers NR50A-NRSOC are depicted in FIGURE 4, NR50A-NR50C actually may comprise a single multi-bit (e.g., eight bit) register as shown in FIGURE 4A, and similarly multiple registers NRS2A-NR52B shown in FIGURE ~ may actually comprise a single multi-bit register MR52 as shown in FIGURE 4A.
Registers NR52A-NR52B (which in the preferred embodiment comprises a single 8-bit register operatively coupled to CPU 24) is used to control the enablement/disablement of sound generating circuits 541-544. As shown in FIGURE 4A, a most signific:ant bit D7 of register NR52 may be used to ena~le/disable all of sound generatlng circuits 541-544. If the most significant bit D7 of register NR52 is set to logic level one, all of the sound generatiny circuits 541-544 become operable; and similarly, if a loc3ic level "zero" value is written to register NR52 most significant bit D7, all of the sound generating circuits 541-544 axe disabled. Tha least significant four bits DO-D3 of register NR52 are utilized as sound generating circuit ON flags for the individual sound generating circuits 541-544, and permit the sound generating circuits to be individually enabled or disabled dependin~ up~n the logic level value written into these ~our bits DO~D3.

, ~, : .

3~

The states o~ analog switches 681L-684L, 681R-684R are controlled in the preferred embodiment by a register NR51 a detailed schematic diagram of which is also shown in FI~URE 4A. Register NR5]. is also 8-bits wide in the preferred embodiment. I,east significant four bits DO-D3 of register NR51 respectively correspond to analog switches 681L-684L
and control those analog switches to turn OM and OFF
(i.e., to pass or not pass) the outputs of respectively corresponding sound generating circuits 541-544 to the left aud:io bus 300. Similarly, the most significant four b.its D4-D7 o~ register NR51 - control analog ~witches 681R-684R, respectively to turn ON and OFF (so as to controllably pass or not pass the outputs of sound generating circuits 541-544, respectively to the riyht audio bus 302).
Suppose, for example, that logic level zero values are written into register ~R51 bits DO and D4 (which correspond to, for example, analog switclles 681L an~ 681R, respectively~. The logic level zero value stored in least siynificant bit DO contro]s analoy s~itch 681L to turn OFF -- thereby e~fect:ively disconnecting the output of sound generating circuit 541 from the input of left channel solid-state volume control block 72L. Likewise, the logic level ~ero stored in register NR51 bit D4 controls analo~ switch 681R to effectively disconnect the output of sound generating circuit 541 Erom the input of right channel solid-state, volume ccntrol block 72R. Hence, whenever these two "~ero" bit values are stored in register NR51, the output of sound generating circuit 541 is passed on tc neither the left channel output SOl nor the right cha~mel S02. Writing a logic level .. . .

2g one to register NR51 bit D0 controls analog switch 681L to pass the output of sound generating circuit 541 to left channel output S01; writing a log.ic level one value to bit D9 of register N~51 con-trols analoy switch 681R to pass the output of soun~ generating circuit 541 to right channel output S02; and writiny logic level one values to both bits D0 and D4 controls analog switches 681L and 681R to pass t:he output of sound gen.erating circuit 541 to ~both) the left and right sound signal outputs S01, S02, respectively.
In s~lmmary, register NR5]. in the preferred embodiment stores two b:its corresponding to each of sound genera-ting circuits 541-544, these t~o bit:s controlling the ana.log switches 681 connected to the sound generating circuit~ to selectively pass or not pass the output of the sound generating circuits to outputs S01, S02. If these two bits are both at logic level zero, t.he sound generating circuit output is not passed to either of the sound outputs S0]., S02. If one of the bits is logic level on~s and the other bit is at logic level zero, the sound generating circuit output is passed to only one of the sound generatiny outputs SOl,S02 (which of t.he sound signaL output.s S01,S02 receives the output: of the sound generating circuik depends upon which of the bits is at logic level on.e). If both of the bits are set to logic level one, on the other harld, hoth of the sound signal outputs SOl,S02 receive the output from the corresponding sound generating circuit.
Registers NR5QA-NR50C shown in FIGURE 4 actually comprise a single 8-bit reyister NR50 in the ,:, . : :
::-~:: . :.

preferred embodiment (as is shown in FIGURE 4A). Two of the bits D3,D7 Qf register NR50 are used to turn ON and OFF a further set of analog switches 70L,70R
the inputs of which are c:onnected to a signal VIN
obtained from an external sound source. For example, an additional sound source signal may be provided in the preferred embodiment from a sound generatiny source other than sound generating circuits 541-544.
This externally-provided sound source signal is inputted as signal VIN which is selectivel.y passed or not passed to left audio bus 300 and right audio bus 30~ by analog switches 70L,70~ respectively. Analog switches 70L,70R in turn have their ON/OFF states selected by register NR50 bits D3,D7/ resp~ctiv~ly.
The remaining si~ bits of register NR50 ln the preferred embodiment are used. to control the degree of amplification/at.tenuation applied by solid-.state volume controls 72L,72R. Thus, in the exempla.ry embodiment register NR50B shown in FIGURE 4 comprises the least significant bits D0-D2 of register NR50, while register NR50C shown in FIGURE 4 comprises bits Dg-D6 of register NR50 shown in FIGURE 4A. By setting hinary values "000"-"111" into these 3-bit fields, it is possible to control the output le~rels of solid-stata volume control blocks 72L,72R from a minimum to a maximum level in eight steps. Thus, for example, writing a value "0Q0" to register NR50 least significant bits D0-D2 in the preferred embodiment controls solid-stat.e control block 72L to provide a minimum amplitude level (which may be zero amplitude if desired) to the input of left channel amplifier 60L. Similarly, writing a value "111'l to regist:er NR50 bits D4-D6 control~ right channel ~olume 35i solid-state volume control 72R to provide the mi.nimum degree of amplification to the signal provided to it from right channal audio bus 302, thus providinc~ the maximum (loudest) signal level ou-tput at right channel sound signal output S02.
Refe.rrinc3 now to EIGURES 4 and 6 together, sound generating circuit 541 may be used ~as one example) as a melody source ("sound 1") -- to provide the top stanza or line of exemplary mu~ical composition shown in FIGURE 6. The remaining sound generatinc~ circuits 542-544 may be used to produce rhythm sounds as shown in the lower three stanzas of music set forth in FIGURE 6. Of course, it is possible to US9 SOUrld generating circuits 541-544 in any combinations desired to produce multiple melodies (i.e., counterpoint), melcdy and harmony together, combi.nations of mu~ic and sound effects, etc.
In the musical notation shown in FIGURE 6, the lines of music labeled S01 correspond to so1lnds apparent in the left channel, and the lines labeled $02 correspond to sounds appeari.ng on the right audio channel. FIGURE 6 shows standard musical notati.on with musical notes and rests depicted in a conventional manner. Four measures of music ar~
shown for purposes of example (although it will be understood that the system described herein is capable of playing musical compositions of any desired length limited only by memory capacity).
As to the four bars or measures of music shown in the top stanza of FIGURE 6 ("Sound 1"), analog switches 681L and 681R shown in FIGURE 4 are controlled to be ON dur.ing all four measures so as to output the melody output generated by sound , . .

,, . ~ ,, .

~3~

generating circuit 541 to both of amplifiers 601.,60R
during all four measures. Thus, the value of "3."
wculd be written into bits DO and D4 of register NR51 for the duration of all four measures.
In contrast, the output of sound cJene:rating circuit 542 altern~tes between the left and the right channels SOl,S02 as shown in stanza labelled "Sound 2" in FIGURE 6. Thus, -the output of sound gsnerating circuit 542 is provided to sound output SO1 but not to sound output S02 cluring the first measure; is provided to both sound outputs SOl,S02 dur.ing the second measure; is prov:ided to only sound output: S02 and not to sound output SOl during the third measure;
and is provided to both of sound outputs SOl,SO~' during the fourth measure. Eence, in the .first measure the CPU writes the value of "1" into rec~ister NR51 bit Dl and the value of "O" into register ~IR51 bit D5. In the ~econd measure values of "1" are w~itten to both bits DO and ~5 of register NR51 so that analog ~witches 682L,682R are both turned ON and output of sound generating circuit 542 is passecl to both of output channels S01,~02. During t:he third measure, conversely to the first measure, the "()" is written to register NR51 bit Dl and a "1" is written to bit D5 of register N~51 to turn OFF analog s~itch 682L and turn ON analog switch 682R ~so that the output of sound generating circuit 54~ provided to output channel S02 but not to output channel SO1).
Similarly, the "sound 3" line of musical notation shown in E'IGURE 6 indicates that the output of sound generator circuit 543 is to alter:nate between channels SO1 and S02. That is, during the first measure, ana10cJ switch 683L is turned ON [by 3~

writing a logic level "1" to register NR51 bit D2) and analog switch 683R is turned OFF (by writinq a bit "O" value to register NR51 bit D6). Therefore during the first measure, the output of sound generating circuits 543 is applied -to sound output channel SOl but not to sound output channel S02. But in the second measure, conversely, the value "O" and "1" are respectively written into register NR51 bits D2 and D6 to turn OFF analog switch 683L and turn ON
analog sw.itch 683R. Therefore, the output of sound generating circuit 543 is provided only to souncl output channel S02 and not to sound output channel ~01 .
In a similar manner, the output sound generatiny circuit 544 may he routed as is shown in the lowest line of musical notation ("sound 4") of FIGURE 6) by writing the values "1" and "O" to register NR51 bits D3,D7 during the first measure; thereafter writing the values "O" and "1" to bits D3,D7, respectively during the second measure; writing the value "1" and "O" to bits D3,D7 during the third measure, et cetera.
It will be understood that registers NR50-NR52 are typically written in parallel so that, for example, all of bits DO-D7 of' register NR51 are typically rewritten each time any channel allocation bit is to be changed.
Thus, the melody sounds produced by sound generating circuit 541 in accordance with exemplary music shown in FIGURE 6 and the rhythm sounds produced by sound generatin~ circuits 542-544 in accordance with that exemplary music are selecti.vely turned ON and OFF ~y means of analog switches 681L-684R, and the four sound source signals are ,. , ., - - i ~ .:

.
,~: . . ~ . ::

~3~i ~ 34 mixed appropriately by left and right audio buses 300,302 and provided respectively to solid-state volume controls 72L,72R. The output levels of these mixed signals are independently controlled by solid-state volume control blocks 72L,72R in accordance with the contents of register NR50 bi.ts D0-D2, D4-D6 such that the separate sound output;s S01 and S02 for the left and right audio channels (in which the melody and rhythm sounds are combined or synthesized) can be outputted from amplifiers 60L,60R. By changing the amplification of one of volume control blocks 72 with respect to the amplification of other volume control block, it is possible to alter t.he spatial relationship perceived by the wearer of headset 64 ~so that the sound source appears to have moved in position with respect to the user's head).

Exemplar~ Sound Generatinq Circuits FIGURE 5 is a detailed schematic bloc:k diaqram of an exemplary cor..figuration for an exemplary one of sound generator circuits 541--544. Although only one sound generator circuit i.s illustrated in FIGURE 5, the four so~md generator circuits 541-54g may be similar to one anot.her in structure and operation and in any event, description of one of the generator circuits will provide sufficient details to one of ordinary skill in t.he art with respect to all four of the circuits. Thus, only one o~ the four sound generator circuits needs to ke described in det~il herein. In the prefe.rred em~odiment, sound generator circuits 541-544 are not in fact identical to one : " ~ ' :: ' ' :, 1I t ~

3~

another as some of the sound generator circuits include enhanced capabilities in order to provicle varied sound effects. Sound generator cir~uit S41 may, for example, include a sweep oscillator, sound generator 5~3 may include no duty cycle control, and sound generator 544 may include a polynomial counte clock type fre~uency selector -- all as is well understood by those skilled in this art.
Referring now to FIGURE 5, sound generator circuit 542 includes various counters, dividers and other components controlled by control registers NR21~NR24. Briefly, components 74-94 provide a clocking signal used to enable/disable conversion by a D/A converter 96 of the contents of an enveloF)e counter 102 into a sound output signal. Thus, componen-ts 74-94 control timincJ parameters assoc:iated with the sound output signal, and envelope counter 102 and associated components 98-106 control the amplitude of the scund output signal. Decoder ].08 is used to reset the ~ound generator circuit 542, as will be explained.
A reference clock signal at frequency f (which preferably is provid~d by the crystal controllecl oscillator 24a and associated components shown in Figure 2 in the preferred en~odiment) provides a time base for the sound generating circuit 542 shown in Figure 5. This clock frequency signal may be, for example, 4.194,304 M~z in the preferred embodiment.
In addition, additional fixed frequency cl~ck si.gnals (e.g., having frequencies of 64 ~z and 256 Hz) obtained by dividirg ~lown clock frequency f, for example, may also kle provided to sound generating circuit 542.

.. : ~ ~ ~ .: ,.
.: . . ~
. .

36 2~ 3~

The reference clock signal f is applied in the preferred embodiment to the inpu-t of a divide-by-four divider circuit 74 (which may comprise, for example, a pair of flip-floFs forming a two-bit counter~.
Divide-by-four circuit 74 divides clock frequenc:y f by a factor of 4 in a well-known manner, and applies this divided-frequency signal to one input of an AND
gat~ 76. The other input of AND gate 76 is connected to the Q output of a flip-~10p 80. Flip-flop 80 is used in the preferred embodiment to enable and disable sound generating circuit 542 by e~.fecti~ely gating (via AND gat.e 76) the divided clock frequency f to the input of fre~uency counter 82. Flip-f].op 80 is set in accordance with the value of the most significant bit D7 of register NR 24 (see Figure 5b). Thus, when a logic level "1" is written into register NR24 most si.gnificant bit D7, flip-flop 80 sets -- thereby turning AND gate ON so as to pass the divided clock frequency output from divide:r 74 to the clocX input of freguency counter 82. Flip-flop 80 resets in response to the output of decode:r 108 in ~ the preferred embod.iment, as will be explained shortly.
A frequency counter 82 in the preferred embodiment control~ the frequency (pitch) of the audio output si.gnal.-to be produced. In the preferred embodiment, irequency counter 82 comprises a programmable frequency divider of con~entional design. The division ratio of the dividing periormed by frequency counter 82 is determined by frequency data contained within registers NR23 and NR24. In particular, the J.ea.st significant three bits DO~-D2 of register NR24 contain the three ~ost significant bits ~, ~

- '. .:':, ' . :

of an ll-bit frequency data value, while all eight bits DO-D7 of register N~23 are used as the lower 8-bit portion of this ~reguency data value. In the exemplary circuit shown, the 11-bit frequency data value stored within registers NR23, NR24 controls frequency counter 82 to produce an output signal of frequency fd at a frequency fcl - 419~304/(4 * 23(204~-X)~

where fd is in Hz and x is the 11-bit frequency value. This frequency data value ~ controls the musical pitch (i.e., "interval") of the signal produced by sound generating circuit 542.
The output of frequency counter 82 is applied to the input of a duty cycle circuit 88. Duty cycle circuit 88 controls the ~uty cycle of the audio output signal produced by sound generating circuit 542 in response to the contents of a duty ratio setting register 86. In the exemplary arrangement shown, the duty cycle is specified by the two most significant bits D6-D7 of re~ister NR21. As is well known, a waveform duty cycle relates to the amount of time a periodic waveform is ON with respect to t:he amount of time that periodi~ waveform is OFF. Thus, a 50% duty cycle (set by a value of "00" in register NR21's most significant bits D6-D7) means that t:hs periodic waveform is ON as o~ten as it is OFF.
Writing a value of ~ '' into register NR21 most signific,ant bits D6-D7 selects a waveform duty c:ycle of 75% in the preferred embodiment ~thus provicling an output waveform that is ON one and a half times as much as it is OFF). In similar fashion, writiny a . , :

. .
1. :

3~

value of "Ol" into regi~ter NR21 most significant bits D6-D7 provides a 25% waveform duty cycl~ (i.e., the waveform is ON only half as much as it is OFF), and writing a value of "Ol" into these most significant bits provides a waveform duty cycle of 12.5%. As is well known, changing the duty rati.o of an audio signal changes its tone color -- thereby providing a variety of different sound possi~ilities for the same frequency signal.
In the preferred embodiment, duty circuit 88 is a conventional circui.l, ~rrangement which varies the duty cycle of the periodi.c signal provided by freç~lency counter ~2 to provide one of ~t:he four duty cycles described ak~ove.
The outpu-t of duty circuit 88 is p:rov.ided t:o one input of an.AND gat.e ~O, which AND gate gates the output of the duty ci.rcuit under control o.f a length duration gating signal produced by a length counter 94. Length counter 94 produces this ~uration gating signal in response to the contents of a length setting register 92. L~ngth setting register 92 in the preferred emboc}.iment actually comprises the least significant hits DO-D5 of register NR21 shown in FI~URE 5B. The cor..tents of length ~.etti.ng register 92 control~ the division ratio of length counte~
94 -- which counter acts as a conventional programmable divider to clivide the freq~lency of a length clock frsquency ,signal of 256 Hz. In the preferred embodimerlt, sound length ~ield DO-D5 of register NR21 controls the duration of sounds produced by sound generating circuit 542 in sixty-~our steps in accordance with the followirlg relation:

:..: i - ..-. . .: :
~ : -,:: ~ : ~ :

, . :- . ~ ~, . :: :

Dura~ion =(64 - Tl)*(l/256~ seconds where "Duration" is the length of a musical sound and Tl is the value specified by register NR21 bits DO-D5. By gating the output of duty circuit 88 via AND gate 90, length. counter 94 controls the duration of sounds produced by sound generating circuit 542.
Thus, the sound ger-erating circuit 542 may "turn OFF"
automatically at the end of aach musical note to save tha CPU the effort of turning the sound generati.ng circuit OFF at the appropriate time. By writincJ
appropriate values into length setting regi~ter 92, the CPU can control sound generating circu.it 542 to produce, for example, a musical note o~ any desi.red duration ~for example~ a sixtaenth note, an eight note, a quarter not.e, a dotted half note, or a whole note) -- and similarly, the length of a musical rest may also be set in this manner.
The resulting gated signal provided for at the output of AND gate 90 i5 applied to the enable i.nput of digital-to-analog (D/A) converter 96. D/A
converter 96 actually produces an analo~ output level corresponding to the sound output of sound yenera-ting circuit ~42 at timings controlled by the output of AND gate 90 (and t~us depending upon the selected freg~lency, duty cycle and duration discussed above).
The amplitude of the signal produced by D/A con~rerter 96 may be fixed for some notes, but is capable of increasing or decr~a~ing automatically to produc:e other musical notes or sound effect~ in the preferred embodiment.
Envelope counter 102 and associated components 98-106 provide para.llel data to the parallel data ".
:~. : , . ~
:, ' :-. ' ~ : ~

input of D/A converter 96 so as to control automatically the amplitude "level" of the sound output signal produced by the converter with respect to time (the "envelope" of a sound refers to the amplitude envelope containing it~.
A reLatively slow (e.g., 64 H7.) envelope c].ocX
signal is applied to the input of a programmable 1/N
divider 100 in the preferred embodiment. The division ratio provided by 1/N divider 100 is selected by the contents of envelope step number register 98. Envelope step register 98 in the preferred embodime~t comprises the least significant three bits D0-D2 of register NR22. In the preferred embodiment, l/64th of a second is the fastest that the envelope "amplitude" of the sound may be chancJed. However, the contents of envelope step number register 98 selects the rate of change o~ the sound output amplitude in each step in accordance with the ~ollowing relation:

Duration of step - N * (1/64) seconds where N is the value stored in bits D0-D3 of reyister NR22. In the preferred embodiment, the value of "000" stored in th~,se hits s~tops the operation of the envelope counter (so that the amplitude of the sound output produced by D/A converter 96 remains constant).
The output of 1/N divider ].00 controls the rate at which an envelope counter 102 counts up or down.
A 4-bit initial value is loaded in parallel into envelope counter 102 from envelope initial value regi~ter 104 (which in the preferred embodiment 3~

comprises the four most significant bits D4-D7 of register NR2~). In addition, an up/down register 106 (which in the pref~rred embodiment comprises bit D3 of register NR22) selects whether envelope count:er 102 is to count up or instead is to count down (thus providing two options: an amplitude which begins at the initial value and increases to maximum, ancl an amplitude which begins at the initial value and decreasas to zero). In the preferred embodiment, up/down register 106 may control the direction of counting of envelope counter 102, or alternatively may provide an inpu.t to D/A converter 96 which instructs the D/A converter how to interpret (i.e., attenuate or amplify) the value presented to it by envelope counter 102.
Envelope count.er lO~ thus starts counting at the initial value provided by envelope initial value register 104 and counts up (or down) at a rate determine by the ou.tput frequency o~ l/N divider lO0. As envelope counter 102 counts, its paral].el output value c,hanges -- and since its parallel ~alue is conver-ted into an analog signal level by D/A
con~erter 96, the a.mplitude of the sound output signal produced by the converter li}cewise changes.
A decoder 108 receives the paralle]. data provided by envelope initial v~lue register 104 and the data provided by up/down register 106. Decoder 108 decodes this data and, when the envelope ini.tial value is zero and a down direction is designated, the decoder 108 applies a decoded output to the reset input of ~1ipflop 80 and to ~/A converter 96. The effect of this rese:t signal is to disable the opera~ion of D/A ccnverter 96 ~so that no sound :., ~
-, ....

3~

output is provided) and to disable AND gate 76 ~thereby disabling the eIltire sound generating circuit 542).

Exemplary Sound Generation Proyram Control Instructions and Data Structures E~emplary program control steps and associated data structures for controlling the operation of exemplary sound generato.r 58 will now be described in connection with FIC~RES 7A~9D.
Referring now more particularly to FIGURE 9A, in the external read only memory lROM) 16a within memory cartridge 16 are stored suitahle program contro].
instructions 310 for controlling sound generation (in addition to other a.spects of video game play, such as control of the video game displayed by I,CD display panel 14, response to user inputs provided by control 18, and the like).
In addition, ROM 16a stores three data structures in the pre~erred embodiment relating to sound generation: a ~requency data tabla 312, a duration data table 314 and a musical scors data table 316. Briefly, musical score data table 316 provides the musical pitch, duration and "sound direction" (left channe:L, right channel or both~ set forth in FIGURE 6 ~or each of sound converting CilCUitS 541-544. Fre~lency data table 31.2 performs a mapping or convexsion between the musical pitch information stored in musical score data table 316 and the digital values that need to be loaded into fre~uency settiny register 84 of sound generating circuits 541-544 to provide the musical pitches . :, . .

specified by the musical score data table 3~6.
Duration data table 314 provides a mapping or conversion between the duration information set forth in musical score data table 316 and the sound length data that needs to be written into sound length setting register 92.
FIGURE 9B is an exemplary schematic block diagram of the contents of frequency data table 312 shown in FIGURE 9A. In the preferred embodiment, each musical pitch is defined by a sequence of four hexadecimal values scored in fre~uency data tab]e 312. For e~ample, a musical rest (i.e., no sound) may be represented by the value of "0000", the musical pitch of C may be represented by "AB01", the musical of C sharp may be represented by "0193", etc. In the pre~erred embodiment, frequency data table 312 stores such values in the order of a chromatic scale beginning with the musical rest, followed by the pitch of C, and ascending in pitch through each half step (e.g., C, C#, D, Eb ~ .
(D~), E, E, etc.). The hexadecimal data values stored in frequency data tables 312 correspond to the digital values which, when loaded into the fre~lency data registers asscciated with sound generating circuits 541-544 (e.g., bits D0-D7 of re.gister NR23 and bits D0-D2 of register NR24 as discussed previously) will result in the generation of a frequency by the associated sound generating circuit corresponding to the defined musical pitch. That is, for example, when the hexadecimal value "AB01" is written to register NR23,NR24, sound generating circuit 542 will produce a sound having the frequency (pitch) of C. By ~torin~ the digital values in . ..

. .

s frequency data table 312, the programmer writin~
program control instruction 310 need not worry about the specific digital values that must be loaded into the sound control registers to provide notes of desired pitches. As will be understood shortly, the programmer need only specify the appropriate address index from the base address EREQD where frec~uency data table 312 begins into the frec~uency data table to specify the appropriate pitches he desires.
Fre~uency data table 312 then provides automatic:
conversion of this addre~s offset into the appropriate data for writing to, for example, registers NR23 and N~24.
Similarly, duration data table 314 stores data corresponding to commonly-used note durations (e.g., sixteenth not~ or rest, eight note or rest, quarter note or rest, half note or rest, whole note or rest, dotted quarter note or rest, dotted half note or rest, etc). In the exemplary embodiment shown, duration data table, 314 is stored beginning at a base address QNPU and stores as its first entry the hexadecimal value "06" corresponding to the duration of a sixteenth note. That is, the duration of t:he value "06" when loaded into the least significarlt six bits of reyister N~2] described previously, wil]
cause sound generat:ing circuit 542 to produce a note or a rest having a length corresponding to a sixteenth note at ~,ome predetermined fixed tempo in the preferred embocliment. ~ifferent commonly-used musical durations are stored in duration data table 314 in a predetermined order. The programmer need not, therefore, ~rorry about the specific values that need to be written to sound length bits D0-D5 of ~:.. .. : - .

x~

register NR21 (~or example) to obtain a desired musical duration. Rather, he need only specify the appropriate offset into duration data table 314 to select which of the commonly-used musical durations he wishes to use.
FIGURE 9D is an exemplary schematic diagranl of musical score data table 316. Musical score dat:a ta~le 316 shown in FI W RE 9~ corresponds to the "sound 2l' (second) lina of exemplary music shown in FIGURE 6. As will be understood, similar is dat:a preferably provided for the other three line~, and data corresponding to all fvur lines of music are read substantially in parallel from ROM 16a to provide four simultaneously lines of music. In the preferred embodiment, musical score data tqble 316 begins at a base address o~ RASE and includes tllree entries of two hexadecimal numbers each for each note or rest represented within the FIGURE 6 musical score. The first two-number hexadecimal value corresponds to the offset into duration data tahle 314 corresponding to the duration of the note or the rest. The second two-m1mber hexadecimal value corresponds to the offset into frequency data ta~le 312 corresponding to the desired pitch. The last two-number hexadecimal value (which may actually be a binary value in the preferred embodiment since only four states need to be represented) specifies the "sound direction" of the sound (i.e., left channel, right channel, both channels, or no channels~.
Thus, for exa~lple, the first note in the fi.rst measure of the "sound 2" line of music shown in EIGURE 6 is a quarter rest. Accordingly, the first entry in musical score data table 316 specifies the , ,~ .; ., , . .: - :
, . : , offset into duration data table 314 of "01", corresponding to a quarter note or rest. The second entry in musical data table 316 specifies a zero offset into ~req~tency data table 312 to speci~y a rest (as opposed tc a note). The third and last entry corresponding to the first measure, first note, is the value "02" -- specifying that the sound is to be directed only to output sound channel SO1 ~ncl not to output sound channel S02.
Musical score data table 316 provides a sec~ence of such sets of data corresponding to the seguence of notes of a melody or rhythmical line. Thus, for example, the next three two-number hexadecimal values stored in the musical score data table 316 correspond to the second note of the first measure of the '~sound 2" line shown in FIGURE 6 -- a quarter note having the pitch of E. ~he first two-number hexadecimal value in this data set is "02" -- corresponding to the offset into dur~tion data table 314 specifying the duration of a ~uarter note. The second two-number hexadecimal value in this data set specifies an offset of "OA" into frequency data table 312 -- corresponding to the pitch of E. The last value in this data set corresponds to sound direction "01" -- specifyiny that the note is to be provlcled only to sound output channel SO1 and not to sound output channel S02.
It will thus be understood that an entire ].ine of music may be transcribed and stored int~ musical score data table 316 ln the form shown in FIGVRE 9D.
To "play" the mu.sic represented by the score, it is only necessary to read the data sets in the order set forth in the musical score data table 316, reference ~7 the duration data 314 and frequency data table 312 -to map the duration and pitch information into the corresponding values to be loaded into the appropriate sound control registers, and then actually load sound registers with the resultincJ
data. Onca a note has terminated, the data set corresponding to the next note in the musical se~uence may then ~e read from the musical score data table 316 ~nd the entire process repeats once again to generate the ne~t note. This overall proces~; may be repeated continually until the end of the musical score data table 316 is reached (at which time, if desired, the musical score data table 316 may be read again from the beginning to result in repetition of the musical piece over and over again).
FIGURES 7A ana 7~ together are a schematic flow-chart of exemplary program control step~ embodied in the program control instructions 310 shown in FIGURE
9A resulting in sound control of (for example) the line of music stored in the musical score ~ata tabe 316 shown in E'IGURE 9D. It will be understood that several versions of the exemplary program control steps shown in FIGURE 7A-7B should preferably be executed csimllltanec,usly (essentially in parallel) to provide multiple ~usical line generations via individual sound generating circuits 541-544. ]:n other words, the e~emplary program control steps shown in FIGURE 7A-7B control only a single sound generating circuit (e.g., circuit 542). Other iterations of the exemplary program steps should be preformed by CPU 24 to control the other sound generating circuits (e.g., 541,543,544).
Upon initializing the routine shown in FIGU~ES

, - . .

7A-7B, the BASE address (i.e., the starting address) of the appropriate musical score data table 316 is obtained and written to a memory pointer register (block 350) to designate a particular musical score data table (as will be understood, more than one musical score data table 316 may be stored in program ROM 16a to provide multiple different possible pieces of music or sound effects that may be reproducecl). A
musical note trace counter CNT (preferahly a register withln CPU 24 or a location in RAM) is then cleared and a timer (e.q., the timer ~4d shown in FI~U~E 23 is initialized ~blcck 352~. Initially, the value of the timer may be set to "01" so that it can immediately be decremented ancl the remainder o~ the routine shown executed. The timer is then decremented (block 3~) and it~ value tested to determine whether it is yet zero (decision block 356). If the timer is greater than zero, control returns to block 354 to once again decrement the timer and blocks 354,356 are repeatedly ex,3cuted until the timer ha~ been decrementecl-to the value of zero. The loop formed by blocks 354,356 times the duration of the current note or rest, as will be understood, and may be interrupt driven by hardware timer 24d in a well-known manner if desired.
I'he first two-number hexadecimal va].ue stored in thP mu~ical ~core data table 316 is then a~cessed by adding the BASE address to the current CNT value, accessing the program ~OM 16a to read the contents stored at that location, and storing those cont~3nts into a temporary lccation called H (block 358). The contents of H are then compared with the value of "FF" to cletexmine whethl3r the encl of musical score ~3 data table 316 has been reached (decision block 36Q) (in the preferred embodiment the end of the table may be marked by writing the value of "FF" or some other value not a valid offset into the duration data table 314). Assuming the contents of ~ is a valid offset into the duration data table 314, an address int:o the durat.ion data table is calculated using H as an offset from the base address ONPU of the table, the contents stored within the duration data table 314 at the resulting calculated address is read, and those ~contents are loaded into the timer (block 362). The timer thus is initialized with the duration of t:he next note or rest to be produced. This retrieved value may also be loaded into the sound control regi.ster sound length data (e.g., NRll bits DO-D5) to relieve CPU 24 fro~ having to activaly turn OFF the .
sound generating circuit when. the end of the nota is reached.
The value of counter CNT is then incremented (block 364) so as t.o access the ne~t two-number value within the musical score data table 316. This next location in the musical score data table is accessed (e.g., by calculating an address based on the BASE
address and the sum of CNT), and its conte.nts are read and stored into a temporary holding locatic)n Q
(block 366). The offset into the fre~uency data tahle 312 now stored in temporary storage locati.on Q
is used to address the frequency data table 312 (blocks 368,370). In the preferred embodiment, a double read of two seq~lential locations of the frequency data table 312 is required at this point to retrieve enough information to specify the ll-bi.t fre~uency data storecl in, for example, NR13-NR14.

. , . :

These values are retrieved from frequency data table 312 and stored in temporary storage locations X,Y
(blocks 368,370), and the contents of the temporary storage locations X,Y are then tested to determine whether they are all zero, indicating that the current sound to ba procluced is a rest rather than a note (decision block 372). If the current sound is a rest, the envelope initial value register and the up/down register 104,106 o~ the correspondincJ sound generating circuit (e.g., 542~ are cleared to disable the sound generating circuit from generating sounds (block 374). If, cn the other hand, the retrie~red value corresponds to a pitch instead of to a rest (the "N" exit of decision block 372), the frequency settiny register 84 is set with the value stored in temporary value storage locations X,~ (block 376) so as to define the pitch of the musical note to be produced.
The CNT counter is then incremented ~block 378) and the third value! stored in the musical score data table 316 is read corresponding to "sound direction"
data (block 380). This retrieved data is then tested to determine whether it corresponds to new outp~tt direction data (decision block 382). In the preferred embodiment, although the left or right:
"sound direction" data is shown in FIGURE 9D as being explicitly specified for each and every note ancl rest defined by the muslcal score data table 316, it may be desired (e.g., for the purposes of conserving memory~ to specify sound direction data only when the sound direction corresponding to a particular sound generating circuit has chanyed with respect to the prior notes in the sequence. Thus, it is possi~le in ~. .: . i the preferred embodiment for some of the data sets stored in the musica]. score data table 316 to have only two two-number hexadecimal values instead of three (with sound direction data thus omitted if the sound direction is the same as that of the last note played). Decision block 382 shown in FIGURE 7B
determinas whether new sound direction data has been read, and if so, the appropriate bits of the appropriate sound control register (eOg., regist:er NR51 bits Dl,D5) are set in accordance with the values obtained by block 380 (block 384), and the counter CNT is incremented ~block 386~ so tha-t i.t now points to the begin.ni.ng of the next data set stored in the musical score data table 316. I:~ the va].ue read by block 380, on the other hand, is not new sound direction data, the incrementing of counter CNT
is not performed by block 386 and control returns to block 354,356 shown in FIGURE 7A.
Once control returns to block 35~,356, the timer is decremented to time the duration of the current note or rest. Once, that duration lapses, the process of blocks 358-386 are repeated again for the next musical note or rest to be generated.

Stereo/Mono Selecting Circuit FIGURE 8 is a schematic circuit diagram of the stereo/mono selectinq circuit 202 shown in FIGURE 4.
Selecting circuit 202 receives the left channel sound signal S01 from amF~lifi~3r 60L and the right charmel sound signal S02 from amplifier 60R, and routes appropriate signal2; to either loudspeaker 120 or to stereophonic headset 6g. In particular, if no - . . , , ~, . .

::: -:~ - -: . ~ -52 ~3S

stereophonic headset 64 plug is connected to earphone jack 122, stereo~mono selecting circuit 202 mixes the left and right channel sound signals S01, S02 together to provide a morlophonic signal and applies the monophonic signal to loudspeaker 120. If, on the other hand, a stereophonic headset 64 is connected to earphone jack 122, then stereo/mono selecting ci.rcuit 202 couples the left channel sound signal S01 to the left ear transducer of the headset and couples the right channel sound signal S02 to the right ear transducer of the headset.
In the preferred embodiment, the output of amplifier 60L shown i.n FIGURE 4 is coupled to the input of an amplifier 114L through a series resi.stor 112L, and similarly, the output of amplifier 60R
shown in FIGURE 4 is coupled to the input of an amplifier 114R through a series resistor 112R.
Resistors 116L, 116R are connected in series across the inputs of amplifi.ers 114L, 114R. The node cormecting resistors :116L, 116R together is coupled to the input of a mono amplifier 118. The effec:t of resistors 116L, 116R is to mix together the S01 and S02 signals and prcvide the resulting mixed (monophonic) signal to amplifier 118. Amplifier 118 drives loudspeaker 120.
An earphone ja.ck 122 includes a left channel audio contact 112L, a xight channel audio contac:t 122R, and a pair of switchina contacts 122:P. An earphone plug 124 couple~ to earphone 124 is designed to accept and mate wi.th earphone jack 122. Earphone jack 122 may for example be a female mating part which mates with earphone plug 124 as a male mating part. Earphone plug 124 may thus be inserted into ':
; ~ -. .

earphone jac,k 122 to connect the headset 64 to t:he outputs of amplifiers 114L, ll~R, and may thereafter be removed from the earphone jack to disconnect the headset from the amplifiers. For example, somet:imes the user may wish to listen to the sound produced by sound generator block 58 in the headset 64 (and may at that time connect the earphone plug 124 into the jack 122~. At oth~r times the user may not wish to use the headset and may di~connect the earphone plug 124 from the earphone jack 122 (so as to listen to the souncds on loudspeaker 120 rather than on the headset 64).
Earphone plug 124 includes a left channel contact 124L which establishes electrical contact with earphone jack left channel audio contact 112L
when the plug and jack are mated; and a right channel contact 124R which establishes electrical contact with earphone jack right channel audio contact 112R
when -the plug and jack are mate~. A grounded portion 124G is preferably connected to ground. The plug laft channel contact 124L is connected via a left channel leacl 126L to the left channe.l transducer of headset 64; and the plug right channel contact 124R
is connected via a right channel lead 126R to the right channel transducer of headset 6~.
Whenever the ~arphone plug 124 is inserted into the earphone jack 122, contacts 122P contact one another to establish an electrical connec-tion between ground and the inputs oE inverting amplifier 130 and non-inverting amplifier 132. This ground connec:tion causes inverting amplifier 130 to generate a logic level ~'1" signal whlich it ap~lies to enable amplifiers 114L, 114R to operate. The ground - ~ .

connection also causes non-inverting amplifier 132 to generate a logic level "0" signal to disable amplifier 118 from operating. In this state, a stereophonic signal is supplied by amplifiers 114L, 114R to headset 64 via contacts 122L, 122R and 124L, 124R, and loudspeaker 120 is disabled.
Whenever earphone plug 124 is disconnected from earphone jack 122, on the other hand, contacts 112P
no longer contact one another. A pull-up resi~t:or 128 connected to power supply potential pulls up both the input of inverting amplifier 130 and the input of non-inverting amplifier 132 to logic level "1". This logic level high level causes inverting amplifier 130 to apply a logic level "0" signal to amplifiers 114R, 114L (thereby disak,ling them from operating) and causes the non-inverting amplifier 132 to apply a logic level "1" signal to amplifier 118 (thereby enabling the amplifier to operate). In thi~ state, a monaural signal is synthesized (mixed) by mpli~ier llfl and is applied to loudspeaker 120. No signals are applied by amplifiers 114L, 114R to earphone jack contacts 112L, 112~ since the earphone is not connected to the jack.
While the invention has been describecl in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments, but on -the contrary, is inten~ed to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

,. ~ ,.
, ~
- . .:

Claims (23)

1. A pseudo-stereo sound generating apparatus comprising:
an initial sound source signal generator for generating a single independent audio signal at a single output thereof;
an initial first switching means having an input terminal connected to the single output of the initial sound source signal generator, and being coupled to a first sound signal output terminal, said initial first switching means selectively coupling the single independent audio signal of said initial sound source signal generator to said first sound signal output terminal by a switching operation thereof;
an initial second switching means having an input terminal connected to the single output of the initial sound source signal generator, and being coupled to a second sound signal output terminal, said initial second switching means selectively coupling the single independent audio signal of said initial sound source signal generator to said second sound signal output terminal by a switching operation thereof; and, a switching control means coupled to said initial first switching means and initial second switching means for generating switching signals selectively turning on and off at least one of said initial first switching means and said initial second switching means, and for applying the switching signals to said first and second switching means.
2. A pseudo-stereo sound generating apparatus in accordance with claim 1, further comprising:
at least one additional sound source signal generator, each additional sound source signal generator generating a respective single independent audio signal at a respective single output thereof;

an additional first switching means for each additional sound source signal generator, each additional first switching means having an input terminal connected to the single output of the respective additional sound source generator, and being coupled to the first sound signal output terminal, each additional first switching means selectively coupling the single independent audio signal of the respective additional sound source generator to said first sound signal output terminal by a switching operation thereof; and, an additional second switching means for each additional sound source signal generator, each additional second switching means having an input terminal connected to the single output of the respective additional sound source generator, and being coupled to the second sound signal output terminal, each additional second switching means selectively coupling the single independent audio signal of the respective additional sound source generator to said second sound signal output terminal by a switching operation thereof;
wherein the switching control means is also coupled to each additional first switching means and each additional second switching means for generating switching signals selectively turning on and off at least one of, firstly, said initial and all additional first switching means and, secondly, said initial and all additional second switching means, and for applying the switching signals to said first and second switching means.
3. A pseudo-stereo sound generating apparatus in accordance with claim 1, further comprising:
a first level controlling means coupled to said first sound signal output terminal for controlling a level of the signal applied by said initial first switching means to said first sound signal output terminal, and for applying said level-controlled signal to a further first output terminal;

a second level controlling means coupled to said second sound signal output terminal for controlling a level of the signal applied by said initial second switching means to said second sound signal output terminal, and for applying said level-controlled signal to a further second output terminal.
4. A pseudo-stereo sound generating apparatus in accordance with claim 1, further comprising:
a storing means operatively coupled to said switching control means for storing switching control data specifying the switching operation of said initial first switching means and said initial second switching means, said switching control means generating and switching signals in response to said switching control data stored in said storing means.
5. A pseudo-stereo sound generating apparatus in accordance with claim 2, further comprising:
a storing means operatively coupled to said switching control means for storing switching control data specifying the switching operation of said initial and additional first switching means and said initial and additional second switching means, said switching control means generating and switching signals in response to said switching control data stored in said storing means.
6. A memory cartridge capable of being attachably/detachably inserted into a main unit of a game machine of the type including:
a sound source signal generating means for generating a sound source signal in accordance with data provided by the memory cartridge, first and second sound signal output portions, and switching means having an input terminal connected to said sound source signal generating means and having output terminals connected to said first and second sound signal output portions, said switching means for selectively outputting the output of said sound source signal generating means to at least one of said first and second sound signal output portions through a switching operation thereof, said memory cartridge comprising:
a first storing means for storing data associated with duration of a sequence of musical notes or rests, data associated with musical pitch corresponding to each of said musical notes in said sequence, and left or right data so as to represent a sequence of musical events; and a second storing means for storing program control instructions for reading said data from said first storing means at a predetermined timing, whereby said duration associative data, said musical pitch associative data and said left or right data are provided to said game machine main unit in accordance with data read from said first storing means, and said game machine main unit sound signal generating means is controlled in accordance with said duration associative data and said musical pitch associative data, and said switching means is controlled in accordance with said left or right data read from said first storing means.
7. A memory cartridge in accordance with claim 6, wherein said first storing means includes first table storing means for storing a duration associative data table and a second table storing means for storing a musical pitch associative data table, said first table storing means storing a plurality of duration associative data representative of plurality of usable durations, said second table storing means storing a plurality of musical pitch associative data representative of a plurality of usable musical pitches, said first storing means further including musical score data table storing means for storing a musical score data table representative of said sequence of musical events, said musical score data table including offset addresses into said duration associative data table and offset addresses into said music pitch associative data table and said left or right data, whereby said duration associative data, said musical pitch associative data and said left or right data can be read in accordance with said program control instructions.
8. A memory cartridge capable of being attachably/detachably coupled to a game machine main unit of the type comprising:
a sound source signal generating means for generating a sound source signal in response to data provided by the memory cartridge, said sound source signal generating means having an output, and a switching means input terminal connected to said sound signal generating means output and having output terminals connected to first and second sound signal outputs, said switching means for selectively coupling said sound signal generating means output to said first and second sound signal outputs by switching operation thereof, said memory cartridge comprising:
a first storing means for storing duration associative data, musical pitch associative data and channel selection data representing sequence of stereophonic musical events; and a second storing means for storing program control instructions for reading said data from said first storing means at a predetermined timing;
whereby said duration associative data, said musical pitch associative data and said channel selection data are provided in accordance with data read from said first storing means, and said game machine main unit sound signal generating means is controlled by said duration associative data and said musical pitch associative data and said switching means is controlled in accordance with said channel selection data.
9. A memory cartridge in accordance with claim 8, wherein said first storing means includes duration storing means for storing a duration associative data table and pitch storing means for storing a musical pitch associative data table, said duration storing means for storing in advance a plurality of duration associative data representative of a plurality of usable durations and said pitch storing means for storing in advance a plurality of musical pitch associative data representative of a plurality of usable musical pitches, and said first storing means further includes musical score storing means for storing a music score data table representative of said sequence of stereophonic musical events, said musical score storing means for storing addresses of said duration associative data table and said musical interval associative data and said channel selection data whereby said duration associative data, said musical pitch associative data and said channel selection data can be read in accordance with said program control instructions.
10. A game machine comprising in combination:
a game machine main unit; and a memory cartridge including a first storing means for storing data representing duration, pitch and channel selection data so as to represent a sequence of stereophonic musical events and a second storing means for storing program control instructions for reading said stored data from said first storing means, said memory cartridge being attachably/detachably coupled to said game machine main unit:
said game machine main unit including:
a sound signal generating circuit operatively coupled to said memory cartridge when said cartridge is coupled to said game machine main unit, for generating a sound source signal in accordance with said data from said memory cartridge;
plural output channels; and a switching arrangement coupled between said sound signal generating circuit and said plural output channels, said switching arrangement routing said sound source signal to ones of said plural output channels selected in response to said channel selection data.
11. A game machine comprising in combination:
a game machine main unit; and a memory cartridge including a first storing means for storing data representing duration, pitch and channel selection data so as to represent a sequence of stereophonic musical events and a second storing means for storing program control instructions for reading said stored data from said first storing means at a predetermined timing, said memory cartridge being attachably/detachably coupled to said game machine main unit;
said game machine main unit including:
a sound signal generating circuit operatively coupled to said memory cartridge when said cartridge is coupled to said game machine main unit, for generating a sound source signal in accordance with said data from said memory cartridge, wherein:
said sound signal generating circuit includes an output; and said game machine further comprises:
a first sound signal output terminal;
a second sound signal output terminal; and switching means having an input terminal connected to said source signal generating circuit and output having an output connected to said first and second sound signal output terminals, said switching means for selectively coupling said sound source signal generating circuit output to said first and second sound source signal output terminals by switching operation thereof;
wherein said first storing means includes means for storing left and right channel selection data; and said game machine further includes means for coupling said first sound signal output terminal to a left signal output and for coupling said second sound signal output terminal to a right signal output when said switching means is controlled in accordance with said left or right channel selection data.
12. A game machine comprising in combination:
a game machine main unit; and a memory cartridge including a first storing means for storing data representing duration, pitch and channel selection data so as to represent a sequence of stereophonic musical events and a second storing means for storing program control instructions for reading said stored data from said first storing means at a predetermined timing, said memory cartridge being attachably/detachably coupled to said game machine main unit;
said game machine main unit including:
a sound signal generating circuit operatively coupled to said memory cartridge when said cartridge is coupled to said game machine main unit, for generating a sound source signal in accordance with said data from said memory cartridge;
an earphone jack including left and right contacts connected to said left and right signal outputs for coupling to left and right channel transducers or a stereophonic earphone when said earphone is coupled thereto, said earphone jack having at least one further contact;
a left signal path connecting said left signal output to said left contact of said earphone jack;
a right signal path connecting said right signal output to said right contact of said earphone jack;
a synthesized signal path connected to said left signal path and said right signal path to synthesize said left signal and said right signal with each other, said synthesized signal being coupled for application to a speaker; and a disabling means connected to said earphone jack further contact for disabling said synthesized signal path when said earphone is coupled to said earphone jack and for disabling said left signal path and said right signal path when said earphone is not coupled to said earphone jack.
13. In an electronic gaming system of the type comprising a main unit including a digital processor connected to control a two-dimensional display and connected to receive input from an input device manipulable by a user, said main unit disengageably coupling with a interchangeable memory cartridge, said memory cartridge supplying program control instructions to said digital processor, said digital processor providing a changing game display on said two-dimensional display at least partially in response to said received input and said program control instructions, a method of generating stereophonic sound effects including the following steps:
(a) providing data representing an audio signal;
(b) generating said audio signal in response to said provided data;
(c) providing sound direction data specifying whether said audio signal is to be provided at a first audio channel output and specifying whether said audio signal is to be provided at a second audio channel output; and (d) routing said audio signal to said first audio channel output and/or to said second audio channel output in response to said sound direction data.
14. A method as in claim 13, wherein said providing steps (a) and (c) each include the following steps:
storing data beforehand in said memory cartridge, and supplying said stored data from said memory cartridge to said digital processor.
15. A method as in claim 13, wherein said generating step (b) includes the step of electronically synthesizing said audio signal in response to said provided data.
16. A method as in claim 13, wherein said routing step includes the following steps:
operating a first switching element to couple said audio signal to said first audio channel output in response to said first sound direction data; and operating a second switching element to couple said audio signal to said second audio channel output in response to said second sound direction data.
17. In an electronic gaming system of the type comprising a main unit including a digital processor connected to control a two-dimensional display and connected to receive input from an input device manipulable by a user, said main unit disengageably coupling with an interchangeable memory cartridge, said memory cartridge supplying program control instructions to said digital processor, said digital processor providing a changing game display on said two-dimensional display at least partially in response to said received input and said program control instructions, a method of generating stereophonic sound effects including the following steps:
(a) providing, within said cartridge, first data representing characteristics of a sound and sound direction data selecting any of a first audio channel output and a second audio channel output;
(b) supplying said first data and sound direction data to said digital processor;
(c) generating an audio signal in response to said supplied first data; and (d) controlling application of said audio signal to said first audio channel output and/or to said second audio channel output in response to said sound direction data.
18. In an electronic gaming system of the type comprising a main unit including a digital processor connected to control a two-dimensional display and connected to receive input from an input device manipulable by a user, said main unit disengageably coupling with an interchangeable memory cartridge, said memory cartridge, supplying program control instructions to said digital processor, said digital processor providing a changing game display on said two-dimensional display at least partially in response to said received input and said program control instructions, said memory cartridge comprising:
means for storing first data representing characteristics of a sound and sound direction data selecting any of a first audio channel output and a second audio channel output and for supplying said first data and sound direction data to said digital processor; and means for operative coupling to said digital processor for controlling said processor to control generation an audio signal in response to said supplied first data for controlling said processor to control application of said audio signal to said first audio channel output and/or to said second audio channel output in response to said sound direction data.
19. A memory cartridge as in claim 18, wherein said processor controlling means comprises means for storing predetermined program control instructions.
20. A memory cartridge capable of being attachably/detachably loaded to a main unit of a game machine of the type including a sound source signal generating means for generating a sound source signal in accordance with program data, a first sound output portion for outputting sound of a left channel, a second sound output portion for outputting sound of a right channel, a first switching means having an input terminal, said first switching means being turned-on in response to a first switching signal and applying a sound source signal from said sound source signal generating means to said first sound output portion, and a second switching means having an input terminal which is connected to said sound source signal generating means, said second switching means being turned-on in response to a second switching signal and applying a sound source signal from said sound source signal generating means to said second sound output portion, said memory cartridge comprising:
first storing means for storing a musical score table, said musical score table including at least data associated with duration of a sequence of musical notes or rests, data associated with musical pitch corresponding to each of said musical notes in said sequence, and said first and second switching signals for controlling said first and second switching means for each of said musical notes so as to represent a sequence of musical events; and second storing means for storing program control instructions for reading said data and said first and second switching signals from said first storing means at a predetermined timing, whereby said first and second switching signals read from said first storing means in accordance with said program control instructions are applied to said first and second switching means in association with that said sound source signal is generated by said sound source generating means in accordance with said duration associative data and said musical pitch associative data read from said first storing means in accordance with said program control instructions, and sound is generated from at least one of said first and second sound output portions.
21. A memory cartridge in accordance with claim 20, wherein said game machine includes a plurality of said sound source signal generating means, a plurality of said first switching means correspondingly to said plurality of said sound source signal generating means, a plurality of said second switching means correspondingly to said plurality of said sound source signal generating means, first connecting means for synthesizing outputs of said plurality of first switching means to apply to said first sound output portion, and second connecting means for synthesizing outputs of said plurality of said second switching means to apply to said second sound output portion, and said music score table of said first storing means includes said duration associative data, said musical pitch associative data and said first and second switching signals for each of said plurality of said sound source signal generating means.
22. A memory cartridge in accordance with claim 21, wherein said game machine includes a first register for controlling each of said plurality of said sound source signal generating means and a second register for controlling said plurality of said first and second switching means, said first and second registers being set by said musical score table read from said first storing means.
23. A memory cartridge capable of being coupled to an electronic gaming machine, said gaming machine including a sound source which generates at least one audio signal under program control, a left channel sound output terminal for outputting left channel sound, a right channel sound output terminal for outputting right channel sound, a first switch coupled between said sound source and said left channel sound output terminal for selectively coupling an audio signal from said sound source to said left channel output terminal in response to a first switching signal, and a second switch coupled between said sound source and said right channel output terminal, said second switch selectively coupling an audio signal from said sound source to said right channel output terminal in response to a second switching signal, said memory cartridge comprising:
a first memory storage which stores a musical score table representing a sequence of musical events, said musical score table including:
data indicating durations of a sequence of musical notes or rests, data indicating musical pitch corresponding to musical notes in said sequence, and first and second switching signals for controlling said first and second switches for each of said musical notes in said sequence; and a second memory storage area for storing program control instructions which control sequential reading of said data indicating said sequence of notes and said first and second switching signals from said first storage area, whereby, in use, said first and second switching signals read from said first storage area in accordance with said program control instructions are applied to control said first and second switches, and said duration indicating data and said musical pitch indicating data read from said first storage area are applied to control said sound source in accordance with said program control instructions, pseudo-stereophonic audio signals representing said sequence of notes being generated at said first and second sound output terminals in response to the data provided by said table.
CA002007435A 1989-01-10 1990-01-09 Electronic gaming device with pseudo-stereophonic sound generating capabilities Expired - Fee Related CA2007435C (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP1004453A JPH02184200A (en) 1989-01-10 1989-01-10 Pseudo stereo sound generator
JP2007/1989 1989-01-10
JP1989002007U JPH0293893U (en) 1989-01-10 1989-01-10
JP4453/1989 1989-01-10
JP1101027A JP2878306B2 (en) 1989-04-20 1989-04-20 Memory cartridge
JP101027/1989 1989-04-20

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CA2007435C true CA2007435C (en) 1998-07-21

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KR (1) KR0127299B1 (en)
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Families Citing this family (141)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0149503B1 (en) * 1989-04-20 1999-05-15 야마우찌 히로시 Memory cartridge
IL96553A (en) * 1989-12-07 1994-04-12 Q Sound Ltd Sound imaging system for a video game
JP3047185B2 (en) * 1990-01-26 2000-05-29 任天堂株式会社 Digital sound source device and external memory cartridge used therein
JPH04176235A (en) * 1990-11-08 1992-06-23 Nintendo Co Ltd Communication adaptor for game machine
JPH04306697A (en) * 1991-04-03 1992-10-29 Kawai Musical Instr Mfg Co Ltd Stereo system
JP3219860B2 (en) * 1992-09-11 2001-10-15 パイオニア株式会社 Video game equipment
US8626521B2 (en) * 1997-11-21 2014-01-07 Robert Bosch Healthcare Systems, Inc. Public health surveillance system
US8027809B2 (en) 1992-11-17 2011-09-27 Health Hero Network, Inc. Home power management system
US6196970B1 (en) * 1999-03-22 2001-03-06 Stephen J. Brown Research data collection and analysis
US5832448A (en) * 1996-10-16 1998-11-03 Health Hero Network Multiple patient monitoring system for proactive health management
WO2001037174A1 (en) * 1992-11-17 2001-05-25 Health Hero Network, Inc. Method and system for improving adherence with a diet program or other medical regimen
US6968375B1 (en) * 1997-03-28 2005-11-22 Health Hero Network, Inc. Networked system for interactive communication and remote monitoring of individuals
US8078431B2 (en) 1992-11-17 2011-12-13 Health Hero Network, Inc. Home power management system
US8078407B1 (en) 1997-03-28 2011-12-13 Health Hero Network, Inc. System and method for identifying disease-influencing genes
US5956501A (en) * 1997-01-10 1999-09-21 Health Hero Network, Inc. Disease simulation system and method
US7970620B2 (en) * 1992-11-17 2011-06-28 Health Hero Network, Inc. Multi-user remote health monitoring system with biometrics support
US6330426B2 (en) 1994-05-23 2001-12-11 Stephen J. Brown System and method for remote education using a memory card
US20030212579A1 (en) * 2002-05-08 2003-11-13 Brown Stephen J. Remote health management system
US20040019259A1 (en) * 1992-11-17 2004-01-29 Brown Stephen J. Remote monitoring and data management platform
US20010011224A1 (en) 1995-06-07 2001-08-02 Stephen James Brown Modular microprocessor-based health monitoring system
US5307263A (en) * 1992-11-17 1994-04-26 Raya Systems, Inc. Modular microprocessor-based health monitoring system
US7624028B1 (en) * 1992-11-17 2009-11-24 Health Hero Network, Inc. Remote health monitoring and maintenance system
US8095340B2 (en) 1992-11-17 2012-01-10 Health Hero Network, Inc. Home power management system
US20070299321A1 (en) * 1992-11-17 2007-12-27 Brown Stephen J Method and apparatus for remote health monitoring and providing health related information
US5951300A (en) * 1997-03-10 1999-09-14 Health Hero Network Online system and method for providing composite entertainment and health information
US6168563B1 (en) * 1992-11-17 2001-01-02 Health Hero Network, Inc. Remote health monitoring and maintenance system
US9215979B2 (en) * 1992-11-17 2015-12-22 Robert Bosch Healthcare Systems, Inc. Multi-user remote health monitoring system
US7613590B2 (en) * 1992-11-17 2009-11-03 Health Hero Network, Inc. Modular microprocessor-based power tool system
US7941326B2 (en) * 2001-03-14 2011-05-10 Health Hero Network, Inc. Interactive patient communication development system for reporting on patient healthcare management
JPH07199320A (en) * 1993-11-24 1995-08-04 Nikon Corp Camera
US5745584A (en) * 1993-12-14 1998-04-28 Taylor Group Of Companies, Inc. Sound bubble structures for sound reproducing arrays
US5517570A (en) * 1993-12-14 1996-05-14 Taylor Group Of Companies, Inc. Sound reproducing array processor system
US5590207A (en) * 1993-12-14 1996-12-31 Taylor Group Of Companies, Inc. Sound reproducing array processor system
US5604517A (en) * 1994-01-14 1997-02-18 Binney & Smith Inc. Electronic drawing device
JP3368967B2 (en) * 1994-01-25 2003-01-20 任天堂株式会社 Conversion device for game machines
US8015033B2 (en) * 1994-04-26 2011-09-06 Health Hero Network, Inc. Treatment regimen compliance and efficacy with feedback
US5820462A (en) * 1994-08-02 1998-10-13 Nintendo Company Ltd. Manipulator for game machine
US5651681A (en) * 1994-08-11 1997-07-29 Scientific Toys Ltd. Toy electronic information storage media and playback system
US5683297A (en) * 1994-12-16 1997-11-04 Raviv; Roni Head mounted modular electronic game system
US6241611B1 (en) 1995-05-10 2001-06-05 Nintendo Co., Ltd. Function expansion device and operating device using the function expansion device
WO1996036060A1 (en) 1995-05-10 1996-11-14 Nintendo Co., Ltd. Operating device with analog joystick
US5802544A (en) * 1995-06-07 1998-09-01 International Business Machines Corporation Addressing multiple removable memory modules by remapping slot addresses
US5556107A (en) * 1995-06-15 1996-09-17 Apple Computer, Inc. Computer game apparatus for providing independent audio in multiple player game systems
JP3524247B2 (en) 1995-10-09 2004-05-10 任天堂株式会社 Game machine and game machine system using the same
JP3544268B2 (en) 1995-10-09 2004-07-21 任天堂株式会社 Three-dimensional image processing apparatus and image processing method using the same
AU734018B2 (en) * 1995-10-09 2001-05-31 Nintendo Co., Ltd. Three-dimension image processing system
JPH09167050A (en) 1995-10-09 1997-06-24 Nintendo Co Ltd Operation device and image processing system using the device
US6007428A (en) 1995-10-09 1999-12-28 Nintendo Co., Ltd. Operation controlling device and video processing system used therewith
US6002351A (en) * 1995-11-10 1999-12-14 Nintendo Co., Ltd. Joystick device
US6155926A (en) 1995-11-22 2000-12-05 Nintendo Co., Ltd. Video game system and method with enhanced three-dimensional character and background control
US6267673B1 (en) 1996-09-20 2001-07-31 Nintendo Co., Ltd. Video game system with state of next world dependent upon manner of entry from previous world via a portal
US6022274A (en) 1995-11-22 2000-02-08 Nintendo Co., Ltd. Video game system using memory module
US6190257B1 (en) 1995-11-22 2001-02-20 Nintendo Co., Ltd. Systems and method for providing security in a video game system
US6139433A (en) * 1995-11-22 2000-10-31 Nintendo Co., Ltd. Video game system and method with enhanced three-dimensional character and background control due to environmental conditions
US6071191A (en) * 1995-11-22 2000-06-06 Nintendo Co., Ltd. Systems and methods for providing security in a video game system
USD380501S (en) * 1996-01-11 1997-07-01 Tiger Electronics, Inc. Hand-held electronic game housing
USD382914S (en) * 1996-01-16 1997-08-26 Tiger Electronics, Inc. Electronic game housing
US5743796A (en) * 1996-01-16 1998-04-28 Tiger Electronics, Inc. Electronic game
USD381702S (en) * 1996-01-16 1997-07-29 Tiger Electronics, Inc. Electronic game
USD378225S (en) * 1996-01-16 1997-02-25 Tiger Electronics, Inc. Electronic game
DE19617993B4 (en) * 1996-05-04 2006-09-14 Bally Wulff Holding Gmbh & Co. Kg By means of coins, tokens or similar means of payment actuatable slot machine
JPH1063470A (en) * 1996-06-12 1998-03-06 Nintendo Co Ltd Souond generating device interlocking with image display
US5795227A (en) * 1996-06-28 1998-08-18 Raviv; Roni Electronic game system
GB9614078D0 (en) * 1996-07-04 1996-09-04 Central Research Lab Ltd Sound effect mechanism
US6139434A (en) 1996-09-24 2000-10-31 Nintendo Co., Ltd. Three-dimensional image processing apparatus with enhanced automatic and user point of view control
US6111959A (en) * 1996-10-31 2000-08-29 Taylor Group Of Companies, Inc. Sound spreader
US20030224852A1 (en) * 2002-04-19 2003-12-04 Walker Jay S. Method and apparatus for linked play gaming with combined outcomes and shared indicia
US6032119A (en) 1997-01-16 2000-02-29 Health Hero Network, Inc. Personalized display of health information
US5798922A (en) * 1997-01-24 1998-08-25 Sony Corporation Method and apparatus for electronically embedding directional cues in two channels of sound for interactive applications
JPH10211358A (en) * 1997-01-28 1998-08-11 Sega Enterp Ltd Game apparatus
US6449368B1 (en) 1997-03-14 2002-09-10 Dolby Laboratories Licensing Corporation Multidirectional audio decoding
US5876351A (en) * 1997-04-10 1999-03-02 Mitchell Rohde Portable modular diagnostic medical device
JP3655438B2 (en) 1997-07-17 2005-06-02 任天堂株式会社 Video game system
US5996033A (en) * 1997-09-04 1999-11-30 Chiu-Hao; Cheng Data compression device comprising input connector for connecting to game player system, output connector for connecting to memory card, and virtual memory page switch
JPH11154240A (en) 1997-11-20 1999-06-08 Nintendo Co Ltd Image producing device to produce image by using fetched image
US6464585B1 (en) 1997-11-20 2002-10-15 Nintendo Co., Ltd. Sound generating device and video game device using the same
US6315669B1 (en) 1998-05-27 2001-11-13 Nintendo Co., Ltd. Portable color display game machine and storage medium for the same
USD425942S (en) * 1998-07-30 2000-05-30 Snk Corporation Hand held game machine
KR100273436B1 (en) * 1998-07-31 2001-04-02 구자홍 Sound generating apparatus and method
US8521546B2 (en) * 1998-09-25 2013-08-27 Health Hero Network Dynamic modeling and scoring risk assessment
US6435969B1 (en) 1998-11-03 2002-08-20 Nintendo Co., Ltd. Portable game machine having image capture, manipulation and incorporation
USD428938S (en) * 1998-12-16 2000-08-01 Snk Corporation Transparent hand held game machine
US6422942B1 (en) 1999-01-29 2002-07-23 Robert W. Jeffway, Jr. Virtual game board and tracking device therefor
US20080201168A1 (en) * 1999-05-03 2008-08-21 Brown Stephen J Treatment regimen compliance and efficacy with feedback
JP3371132B2 (en) * 1999-08-25 2003-01-27 コナミ株式会社 GAME DEVICE, GAME DEVICE CONTROL METHOD, AND COMPUTER-READABLE STORAGE MEDIUM USED FOR THE GAME DEVICE
US6373462B1 (en) 1999-12-07 2002-04-16 Nintendo Co., Ltd. Method and apparatus for displaying higher color resolution on a hand-held LCD device
US7050064B2 (en) * 1999-11-24 2006-05-23 Nintendo Co., Ltd. Method and apparatus for displaying higher color resolution on a hand-held LCD device
US20030129576A1 (en) * 1999-11-30 2003-07-10 Leapfrog Enterprises, Inc. Interactive learning appliance and method
US9640083B1 (en) 2002-02-26 2017-05-02 Leapfrog Enterprises, Inc. Method and system for providing content for learning appliances over an electronic communication medium
US9520069B2 (en) * 1999-11-30 2016-12-13 Leapfrog Enterprises, Inc. Method and system for providing content for learning appliances over an electronic communication medium
JP2001190835A (en) * 2000-01-06 2001-07-17 Konami Co Ltd Game system and computer readable recording medium for storing game program
US6894686B2 (en) 2000-05-16 2005-05-17 Nintendo Co., Ltd. System and method for automatically editing captured images for inclusion into 3D video game play
US7445551B1 (en) 2000-05-24 2008-11-04 Nintendo Co., Ltd. Memory for video game system and emulator using the memory
US6810463B2 (en) 2000-05-24 2004-10-26 Nintendo Co., Ltd. Gaming machine that is usable with different game cartridge types
US6884171B2 (en) * 2000-09-18 2005-04-26 Nintendo Co., Ltd. Video game distribution network
US8157654B2 (en) 2000-11-28 2012-04-17 Nintendo Co., Ltd. Hand-held video game platform emulation
US6672963B1 (en) 2000-09-18 2004-01-06 Nintendo Co., Ltd. Software implementation of a handheld video game hardware platform
JP2002258842A (en) * 2000-12-27 2002-09-11 Sony Computer Entertainment Inc Device, method, and program for sound control, computer- readable storage medium with stored sound control program, and program for executing device executing the sound control program
JP4497264B2 (en) * 2001-01-22 2010-07-07 株式会社セガ Game program, game apparatus, sound effect output method, and recording medium
US7013281B2 (en) * 2001-03-12 2006-03-14 Palm, Inc. Sound generator circuit pre-filter system and method
US7063619B2 (en) * 2001-03-29 2006-06-20 Interactive Telegames, Llc Method and apparatus for identifying game players and game moves
WO2003008060A1 (en) * 2001-07-17 2003-01-30 Nohr Steven P Network communications entertainment system and method
US20030192688A1 (en) * 2002-04-10 2003-10-16 Thomson Michael A. Tubing saver rotator and method for using same
US20030211888A1 (en) * 2002-05-13 2003-11-13 Interactive Telegames, Llc Method and apparatus using insertably-removable auxiliary devices to play games over a communications link
US6805633B2 (en) 2002-08-07 2004-10-19 Bally Gaming, Inc. Gaming machine with automatic sound level adjustment and method therefor
US20060009287A1 (en) * 2002-08-14 2006-01-12 Koninklijke Philips Electronics N.V. Remote control using collectible object
US8131649B2 (en) 2003-02-07 2012-03-06 Igware, Inc. Static-or-dynamic and limited-or-unlimited content rights
US7779482B1 (en) 2003-02-07 2010-08-17 iGware Inc Delivery of license information using a short messaging system protocol in a closed content distribution system
US20100017627A1 (en) 2003-02-07 2010-01-21 Broadon Communications Corp. Ensuring authenticity in a closed content distribution system
US20040267384A1 (en) * 2003-02-07 2004-12-30 Broadon Communications, Inc. Integrated console and controller
US7083420B2 (en) * 2003-02-10 2006-08-01 Leapfrog Enterprises, Inc. Interactive handheld apparatus with stylus
US20050060194A1 (en) * 2003-04-04 2005-03-17 Brown Stephen J. Method and system for monitoring health of an individual
US7399276B1 (en) * 2003-05-08 2008-07-15 Health Hero Network, Inc. Remote health monitoring system
WO2005038749A2 (en) * 2003-10-10 2005-04-28 Leapfrog Enterprises, Inc. Display apparatus for teaching writing
US7422523B2 (en) * 2004-02-10 2008-09-09 Ethan Wood Handheld pinball game having a changeable display
US8016681B2 (en) * 2004-03-31 2011-09-13 Nintendo Co., Ltd. Memory card for a game console
US7837558B2 (en) 2004-03-31 2010-11-23 Nintendo Co., Ltd. Game console and emulator for the game console
US8267780B2 (en) 2004-03-31 2012-09-18 Nintendo Co., Ltd. Game console and memory card
US11278793B2 (en) 2004-03-31 2022-03-22 Nintendo Co., Ltd. Game console
US7771280B2 (en) * 2004-03-31 2010-08-10 Nintendo Co., Ltd. Game console connector and emulator for the game console
US20070060392A1 (en) * 2005-08-11 2007-03-15 Sullivan Paul J Game controller
JP2007060207A (en) * 2005-08-24 2007-03-08 Sanyo Electric Co Ltd Voice signal processing device
US9573067B2 (en) * 2005-10-14 2017-02-21 Microsoft Technology Licensing, Llc Mass storage in gaming handhelds
US20070255659A1 (en) * 2006-05-01 2007-11-01 Wei Yen System and method for DRM translation
EP2033350A2 (en) 2006-05-02 2009-03-11 Broadon Communications Corp. Content management system and method
US7624276B2 (en) * 2006-10-16 2009-11-24 Broadon Communications Corp. Secure device authentication system and method
US7613915B2 (en) 2006-11-09 2009-11-03 BroadOn Communications Corp Method for programming on-chip non-volatile memory in a secure processor, and a device so programmed
US8200961B2 (en) 2006-11-19 2012-06-12 Igware, Inc. Securing a flash memory block in a secure device system and method
JP2008191473A (en) * 2007-02-06 2008-08-21 Sanyo Electric Co Ltd Sound data processing device
US8147322B2 (en) * 2007-06-12 2012-04-03 Walker Digital, Llc Multiplayer gaming device and methods
EP2186237A4 (en) * 2007-08-24 2011-02-09 Tc Digital Games Llc System and methods for multi-platform trading card game
US9038912B2 (en) * 2007-12-18 2015-05-26 Microsoft Technology Licensing, Llc Trade card services
US7909238B2 (en) * 2007-12-21 2011-03-22 Microsoft Corporation User-created trade cards
US20090172570A1 (en) * 2007-12-28 2009-07-02 Microsoft Corporation Multiscaled trade cards
US20090215512A1 (en) * 2008-02-25 2009-08-27 Tc Websites Llc Systems and methods for a gaming platform
TWI425362B (en) * 2010-12-07 2014-02-01 Alpha Imaging Technology Corp Memory interface chip corresponding to different memories and method of establishing memory transmission channel
US10154899B1 (en) * 2016-05-12 2018-12-18 Archer Medical Devices LLC Automatic variable frequency electrolarynx
USD851652S1 (en) 2018-10-24 2019-06-18 elago CO. LTD Stand for electronic device
USD878754S1 (en) 2019-10-02 2020-03-24 elago CO. LTD Protective hang cover skin for electronic device
USD890765S1 (en) 2020-03-18 2020-07-21 elago CO. LTD Cover for electronic device
USD911705S1 (en) * 2020-09-29 2021-03-02 elago CO. LTD Cover for earphone charging case or the like

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3560656A (en) * 1967-05-01 1971-02-02 Dictaphone Corp Binaural phase differential system
US3647928A (en) * 1970-03-16 1972-03-07 William D Turner Electrical musical instrument with ensemble and chief effects and unequal stereophonic outputs
US3818115A (en) * 1971-07-08 1974-06-18 Nippon Musical Instruments Mfg Multi-channel stereophonic sound reproducing system for electronic musical instruments
US4359222A (en) * 1978-10-30 1982-11-16 Smith Engineering Hand-held electronic game playing device with replaceable cartridges
US4347405A (en) * 1979-09-06 1982-08-31 Cbs Inc. Sound reproducing systems utilizing acoustic processing unit
US4308424A (en) * 1980-04-14 1981-12-29 Bice Jr Robert G Simulated stereo from a monaural source sound reproduction system
JPS6019431Y2 (en) * 1980-04-25 1985-06-11 ソニー株式会社 Stereo/monaural automatic switching device
JPH0631959B2 (en) * 1983-09-28 1994-04-27 沖電気工業株式会社 Music equipment
US4685134A (en) * 1985-07-19 1987-08-04 Rca Corporation Multichannel computer generated sound synthesis system
JPH074449B2 (en) * 1985-10-04 1995-01-25 任天堂株式会社 Cartridge for game machine and game machine using the same
JPS62155879A (en) * 1985-12-27 1987-07-10 シャープ株式会社 Personal computer
JPS62155880A (en) * 1985-12-27 1987-07-10 シャープ株式会社 Personal computer
JPS62277981A (en) * 1986-05-28 1987-12-02 テクモ株式会社 Hearing game apparatus
CA1330596C (en) * 1986-11-19 1994-07-05 Yoshiaki Nakanishi Memory cartridge and data processing apparatus
US4817149A (en) * 1987-01-22 1989-03-28 American Natural Sound Company Three-dimensional auditory display apparatus and method utilizing enhanced bionic emulation of human binaural sound localization
US4792974A (en) * 1987-08-26 1988-12-20 Chace Frederic I Automated stereo synthesizer for audiovisual programs
JP3047185B2 (en) * 1990-01-26 2000-05-29 任天堂株式会社 Digital sound source device and external memory cartridge used therein

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KR0127299B1 (en) 1997-12-29
EP0378386B1 (en) 1996-09-11
KR900011493A (en) 1990-08-01
US5095798A (en) 1992-03-17
FI900026A0 (en) 1990-01-03
AU4016393A (en) 1993-08-26
FI900026A (en) 1990-07-11
DE69028419T2 (en) 1997-01-30
CA2007435A1 (en) 1990-07-10
HK1005201A1 (en) 1998-12-24
ES2090091T3 (en) 1996-10-16
AU4776690A (en) 1990-07-26
ATE142837T1 (en) 1996-09-15
FI111789B (en) 2003-09-15
EP0378386A2 (en) 1990-07-18
AU647378B2 (en) 1994-03-24
DE69028419D1 (en) 1996-10-17
AU663191B2 (en) 1995-09-28
EP0378386A3 (en) 1991-10-30

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