CA2013109A1 - Data processing apparatus nulling scalar cache memory - Google Patents
Data processing apparatus nulling scalar cache memoryInfo
- Publication number
- CA2013109A1 CA2013109A1 CA2013109A CA2013109A CA2013109A1 CA 2013109 A1 CA2013109 A1 CA 2013109A1 CA 2013109 A CA2013109 A CA 2013109A CA 2013109 A CA2013109 A CA 2013109A CA 2013109 A1 CA2013109 A1 CA 2013109A1
- Authority
- CA
- Canada
- Prior art keywords
- instruction
- store
- unit
- interval
- issued
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
- G06F15/8061—Details on data memory access
- G06F15/8069—Details on data memory access using a cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Abstract
A data processing apparatus includes an instruction issuing unit, an interval holding unit, a passing control unit, and a nullification processing unit.
The instruction issuing unit tentatively issues a vector store instruction having no definitive data as an instruction not subjected to actual vector store processing. The interval holding unit obtains and holds a store interval block address to be operated by the vector store instruction tentatively issued from the instruction issuing unit. The passing control unit compares a block address indicated by a scalar load/store instruction issued from the instruction issuing unit with the store interval block address held by the interval holding unit. If the block address falls within the range of the store interval block addresses, the passing control unit causes processing for the scalar load/store instruction to wait until the vector store instruction is finally issued from the instruction issuing unit and processed. When a vector store instruction is tentatively issued from the instruction issuing unit, the nullification processing unit nullifies block data present in a store cache memory of a buffer storing unit of the apparatus and corresponding to a store address of the vector store instruction.
The instruction issuing unit tentatively issues a vector store instruction having no definitive data as an instruction not subjected to actual vector store processing. The interval holding unit obtains and holds a store interval block address to be operated by the vector store instruction tentatively issued from the instruction issuing unit. The passing control unit compares a block address indicated by a scalar load/store instruction issued from the instruction issuing unit with the store interval block address held by the interval holding unit. If the block address falls within the range of the store interval block addresses, the passing control unit causes processing for the scalar load/store instruction to wait until the vector store instruction is finally issued from the instruction issuing unit and processed. When a vector store instruction is tentatively issued from the instruction issuing unit, the nullification processing unit nullifies block data present in a store cache memory of a buffer storing unit of the apparatus and corresponding to a store address of the vector store instruction.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1075834A JPH0810451B2 (en) | 1989-03-28 | 1989-03-28 | Information processing device |
JP75834/89 | 1989-03-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2013109A1 true CA2013109A1 (en) | 1990-09-28 |
CA2013109C CA2013109C (en) | 1996-07-30 |
Family
ID=13587617
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002013109A Expired - Fee Related CA2013109C (en) | 1989-03-28 | 1990-03-27 | Data processing apparatus nulling scalar cache memory |
Country Status (5)
Country | Link |
---|---|
US (1) | US5247635A (en) |
EP (1) | EP0396892B1 (en) |
JP (1) | JPH0810451B2 (en) |
CA (1) | CA2013109C (en) |
DE (1) | DE69024994T2 (en) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2622008B2 (en) * | 1990-03-08 | 1997-06-18 | 甲府日本電気株式会社 | Information processing device |
US5418973A (en) * | 1992-06-22 | 1995-05-23 | Digital Equipment Corporation | Digital computer system with cache controller coordinating both vector and scalar operations |
JPH06168263A (en) * | 1992-11-30 | 1994-06-14 | Fujitsu Ltd | Vector processor |
US5420991A (en) * | 1994-01-04 | 1995-05-30 | Intel Corporation | Apparatus and method for maintaining processing consistency in a computer system having multiple processors |
US5818511A (en) * | 1994-05-27 | 1998-10-06 | Bell Atlantic | Full service network |
US5608447A (en) * | 1994-05-27 | 1997-03-04 | Bell Atlantic | Full service network |
US5666506A (en) * | 1994-10-24 | 1997-09-09 | International Business Machines Corporation | Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle |
US5717895A (en) * | 1994-12-01 | 1998-02-10 | Cray Research, Inc. | Associative scalar data cache with write-through capabilities for a vector processor |
US5659793A (en) * | 1994-12-22 | 1997-08-19 | Bell Atlantic Video Services, Inc. | Authoring tools for multimedia application development and network delivery |
US5826102A (en) * | 1994-12-22 | 1998-10-20 | Bell Atlantic Network Services, Inc. | Network arrangement for development delivery and presentation of multimedia applications using timelines to integrate multimedia objects and program objects |
DE69628571T2 (en) * | 1995-10-06 | 2004-05-06 | Advanced Micro Devices, Inc., Sunnyvale | NON-SEQUENTIAL COMMAND ORDER TO REDUCE PIPELINE DELAY |
US5799165A (en) * | 1996-01-26 | 1998-08-25 | Advanced Micro Devices, Inc. | Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay |
US5854914A (en) * | 1996-02-13 | 1998-12-29 | Intel Corporation | Mechanism to improved execution of misaligned loads |
JP3733842B2 (en) * | 2000-07-12 | 2006-01-11 | 日本電気株式会社 | Vector scatter instruction control circuit and vector type information processing apparatus |
US7577816B2 (en) * | 2003-08-18 | 2009-08-18 | Cray Inc. | Remote translation mechanism for a multinode system |
US7437521B1 (en) * | 2003-08-18 | 2008-10-14 | Cray Inc. | Multistream processing memory-and barrier-synchronization method and apparatus |
US7421565B1 (en) * | 2003-08-18 | 2008-09-02 | Cray Inc. | Method and apparatus for indirectly addressed vector load-add -store across multi-processors |
US7543133B1 (en) | 2003-08-18 | 2009-06-02 | Cray Inc. | Latency tolerant distributed shared memory multiprocessor computer |
US8307194B1 (en) | 2003-08-18 | 2012-11-06 | Cray Inc. | Relaxed memory consistency model |
US7743223B2 (en) * | 2003-08-18 | 2010-06-22 | Cray Inc. | Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system |
US7519771B1 (en) | 2003-08-18 | 2009-04-14 | Cray Inc. | System and method for processing memory instructions using a forced order queue |
JP3988144B2 (en) | 2004-02-23 | 2007-10-10 | 日本電気株式会社 | Vector processing device and overtaking control circuit |
US7478769B1 (en) | 2005-03-09 | 2009-01-20 | Cray Inc. | Method and apparatus for cooling electronic components |
JP5206385B2 (en) * | 2008-12-12 | 2013-06-12 | 日本電気株式会社 | Boundary execution control system, boundary execution control method, and boundary execution control program |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1443777A (en) * | 1973-07-19 | 1976-07-28 | Int Computers Ltd | Data processing apparatus |
US4156906A (en) * | 1977-11-22 | 1979-05-29 | Honeywell Information Systems Inc. | Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands |
US4638431A (en) * | 1984-09-17 | 1987-01-20 | Nec Corporation | Data processing system for vector processing having a cache invalidation control unit |
US4722049A (en) * | 1985-10-11 | 1988-01-26 | Unisys Corporation | Apparatus for out-of-order program execution |
JPH0731669B2 (en) * | 1986-04-04 | 1995-04-10 | 株式会社日立製作所 | Vector processor |
US5063497A (en) * | 1987-07-01 | 1991-11-05 | Digital Equipment Corporation | Apparatus and method for recovering from missing page faults in vector data processing operations |
JPS6462764A (en) * | 1987-09-03 | 1989-03-09 | Agency Ind Science Techn | Vector computer |
US5043886A (en) * | 1988-09-16 | 1991-08-27 | Digital Equipment Corporation | Load/store with write-intent for write-back caches |
US5123095A (en) * | 1989-01-17 | 1992-06-16 | Ergo Computing, Inc. | Integrated scalar and vector processors with vector addressing by the scalar processor |
-
1989
- 1989-03-28 JP JP1075834A patent/JPH0810451B2/en not_active Expired - Lifetime
-
1990
- 1990-03-27 US US07/500,003 patent/US5247635A/en not_active Expired - Fee Related
- 1990-03-27 DE DE69024994T patent/DE69024994T2/en not_active Expired - Fee Related
- 1990-03-27 CA CA002013109A patent/CA2013109C/en not_active Expired - Fee Related
- 1990-03-27 EP EP90105795A patent/EP0396892B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CA2013109C (en) | 1996-07-30 |
EP0396892A3 (en) | 1992-09-30 |
EP0396892A2 (en) | 1990-11-14 |
US5247635A (en) | 1993-09-21 |
JPH0810451B2 (en) | 1996-01-31 |
DE69024994T2 (en) | 1996-06-05 |
JPH02253470A (en) | 1990-10-12 |
EP0396892B1 (en) | 1996-01-24 |
DE69024994D1 (en) | 1996-03-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2013109A1 (en) | Data processing apparatus nulling scalar cache memory | |
CA2027226A1 (en) | Information Processing System | |
TW259855B (en) | Data processing device | |
ES8702011A1 (en) | Address translation control system. | |
DE69031433D1 (en) | Memory access exception handling for pre-read command words in the command line of a computer with virtual memory | |
CA2289402A1 (en) | Method and system for efficiently handling operations in a data processing system | |
CA2107056A1 (en) | Method and System for Increased System Memory Concurrency in a Multiprocessor Computer System | |
CA2052559A1 (en) | Vector processing device comprising a reduced amount of hardware | |
JPS643739A (en) | Information processor | |
JPS6467680A (en) | Vector processor | |
CA2012318A1 (en) | Microprocessor system having an extended address space | |
CA2055784A1 (en) | Hierarchical memory controller | |
EP0365281A3 (en) | Cache memory supporting fast unaligned access | |
EP0310446A3 (en) | Cache memory management method | |
JPS6429933A (en) | Store buffer controller for buffer storage system | |
EP1071018A3 (en) | Symmetric multiprocessing system with unified environment and distributed system functions | |
CA2026225A1 (en) | Apparatus for accelerating store operations in a risc computer | |
TW233354B (en) | Data processor with memory cache and method of operation | |
JPS5613576A (en) | Memory access control system | |
JPS559228A (en) | Memory request control system | |
JPS6460190A (en) | Semiconductor storage device | |
CA2032746A1 (en) | Arrangement for translating logical page addresses to corresponding real ones in data processing system | |
EP0375892A3 (en) | Data processing system | |
JPS6486395A (en) | Storage device | |
JPS6467652A (en) | Cache memory eliminating data discordance |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |