CA2013109C - Data processing apparatus nulling scalar cache memory - Google Patents
Data processing apparatus nulling scalar cache memoryInfo
- Publication number
- CA2013109C CA2013109C CA002013109A CA2013109A CA2013109C CA 2013109 C CA2013109 C CA 2013109C CA 002013109 A CA002013109 A CA 002013109A CA 2013109 A CA2013109 A CA 2013109A CA 2013109 C CA2013109 C CA 2013109C
- Authority
- CA
- Canada
- Prior art keywords
- store
- instruction
- scalar
- block address
- interval
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 claims description 11
- 230000003213 activating effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
- G06F15/8061—Details on data memory access
- G06F15/8069—Details on data memory access using a cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Abstract
A data processing apparatus includes an instruction issuing unit, an interval holding unit, a passing control unit, and a nullification processing unit.
The instruction issuing unit tentatively issues a vector store instruction having no definitive data as an instruction not subjected to actual vector store processing. The interval holding unit obtains and holds a store interval block address to be operated by the vector store instruction tentatively issued from the instruction issuing unit. The passing control unit compares a block address indicated by a scalar load/store instruction issued from the instruction issuing unit with the store interval block address held by the interval holding unit. If the block address falls within the range of the store interval block addresses, the passing control unit causes processing for the scalar load/store instruction to wait until the vector store instruction is finally issued from the instruction issuing unit and processed. When a vector store instruction is tentatively issued from the instruction issuing unit, the nullification processing unit nullifies block data present in a store cache memory of a buffer storing unit of the apparatus and corresponding to a store address of the vector store instruction.
The instruction issuing unit tentatively issues a vector store instruction having no definitive data as an instruction not subjected to actual vector store processing. The interval holding unit obtains and holds a store interval block address to be operated by the vector store instruction tentatively issued from the instruction issuing unit. The passing control unit compares a block address indicated by a scalar load/store instruction issued from the instruction issuing unit with the store interval block address held by the interval holding unit. If the block address falls within the range of the store interval block addresses, the passing control unit causes processing for the scalar load/store instruction to wait until the vector store instruction is finally issued from the instruction issuing unit and processed. When a vector store instruction is tentatively issued from the instruction issuing unit, the nullification processing unit nullifies block data present in a store cache memory of a buffer storing unit of the apparatus and corresponding to a store address of the vector store instruction.
Description
20131~39 Background of the Invention The present invention relates to a data processing apparatus capable of processing both scalar and vector instructions.
The following two methods are conventionally reported as a method to be performed in a data processing apparatus of this type when a vector store instruction having no definitive data is output during instruction issuing performed in accordance with an instruction issuing order designated by a program:
(1) Issuing of the vector store instruction and subsequent instructions is waited until data is determined.
The following two methods are conventionally reported as a method to be performed in a data processing apparatus of this type when a vector store instruction having no definitive data is output during instruction issuing performed in accordance with an instruction issuing order designated by a program:
(1) Issuing of the vector store instruction and subsequent instructions is waited until data is determined.
(2) Of instructions subsequent to the vector store instruction, instructions which can be passed are previously issued. After data of the vector store instruction is determined, the vector store instruction is issued as if it is issued in accordance with the instruction issuing order.
If a data processing apparatus of this type has a scalar cache memory which can be accessed by only a scalar instruction, processing according to a vector store instruction is performed for only a main memory.
Therefore, if data corresponding to a store address of a *
A
2C~13~
vector store instruction is present in a scalar cache memory, the data is nullified to ensure data consistency.
Note that nullification of data in the scalar cache memory is performed in units of blocks. This nullification processing of block data in the scalar cache memory is conventionally performed by activating nullification processing means after a vector store instruction is issued so that the means nullifies corresponding block data.
When a vector store instruction having no definitive data is output during instruction issuing performed in accordance with an instruction issuing order designated by a program, a processing speed of a data processing apparatus using the above method (1) is inevitably reduced. In a data processing apparatus using the method (2), a processing speed can be increased since instructions which can be passed are previously issued.
If, however, the data processing apparatus using the method (2), although this is the same as the apparatus using the method (1), has a scalar cache memory which can be accessed by only a scalar instruction, nullification processing must be performed for the scalar cache memory in accordance with an vector store instruction. This nullification processing can be conventionally executed only after the vector scalar instruction is issued and therefore is an obstacle to a higher processing speed.
Summary of the Invention The present invention has been made in conslderatlon of the above situatlon, and has as lts ob~ect to provlde a data processlng apparatus uslng the method (2) descrlbed above and capable of executlng nulllflcatlon processlng of a scalar cache memory accordlng to a vector store lnstructlon passed by lnstructlon passlng lssulng control before lssulng of the vector store lnstructlon.
In order to achleve the above ob~ect of the present lnventlon, there ls provlded a data processlng apparatus whlch lncludes a buffer storage havlng a scalar cache memory whlch can be accessed by only a scalar lnstructlon, comprlslng:
lnstructlon lssulng means for lssulng lnstructlons ln accordance wlth an lnstructlon lssulng order deslgnated by a program, lssulng a tentatlve vector store lnstructlon havlng no deflnltlve data as an lnstructlon not sub~ected to actual vector store processlng sald actual vector store processlng lncludlng fetchlng data from sald scalar cache memory and wrltlng lnto the maln memory, and after data ls determlned, flnally lssulng the tentatlve vector store lnstructlon as an actual vector store instructlon to be sub~ected to the actual vector store processlng by lnterruptlng the lnstructlon lssulng order; lnterval holdlng means, recelvlng sald tentatlve vector store lnstructlon, for obtalnlng and holdlng a store lnterval block address correspondlng to sald tentatlve vector store lnstructlon; passlng control means, recelvlng a scalar block address lndlcated by a scalar load/store lnstructlon lssued from sald lnstructlon lssulng means and sald store lnterval block address held by sald lnterval holdlng means, for comparlng sald scalar block address and A 71180-l lo - 2ol3l~9 sald store lnterval block address lf the scalar block address falls outslde the range of the store lnterval block address, enabllng processlng for the scalar load/store lnstructlon, and lf the block address falls wlthln the range of the store lnterval block addresses, causlng the processlng for the scalar load/store lnstructlon to walt untll the actual vector store lnstructlon ls flnally lssued from sald lnstructlon lssulng means and the block data ln the scalar cache memory whlch corresponds to the lnterval block address ls moved to the maln memory; and nulllflcatlon processlng means, recelvlng sald tentatlve vector store lnstructlon, for nulllfylng block data present ln sald scalar cache memory whlch corresponds to a store address of the tentatlve vector store lnstructlon.
In the data processlng apparatus of the present lnventlon, when a vector store lnstructlon havlng no deflnltlve data ls output durlng lnstructlon lssulng performed ln accordance wlth an lnstructlon lssulng order deslgnated by a program, the lnstructlon lssulng means tentatlvely lssues the vector store lnstructlon as an lnstructlon not to be sub~ected to actual vector store processlng, the lnterval holdlng means obtalns and holds a store lnterval block address to be operated by the tentatlvely lssued vector store lnstructlon, and the nulllflcatlon processlng means nulllfles block data correspondlng to a store address of the vector store lnstructlon present ln the store cache memory. When the scalar load/store lnstructlon for passlng the vector store lnstructlon ls issued by the lnstructlon lssulng means ln accordance wlth lnstructlon passlng lnstructlon, the passlng A
20 1 3 1 ~9 control means compares a block address lndlcated by the scalar load/store lnstructlon wlth the store lnterval block address held ln the lnterval holdlng means. If the block address ls outslde the range of the store lnterval block addresses, processlng for the scalar load/store lnstructlon ls enabled.
If the block data ls lnslde the lnterval, the processlng for the scalar load/store lnstructlon ls walted untll the vector store lnstructlon ls flnally lssued from the lnstructlon lssulng means and processed.
The lnventlon may be summarlzed, accordlng to another broad aspect, as a method of nulllfylng a scalar cache memory comprlslng the steps of: lssulng a tentatlve vector store lnstructlon havlng no deflnltlve data as an lnstructlon not sub~ected to actual vector store processlng; obtalnlng a store lnterval block address from sald tentatlve vector store lnstructlon; comparlng a scalar block address to sald store lnterval block address; processlng a scalar load/store lnstructlon correspondlng to sald scalar block address when sald scalar block address and sald store lnterval address do not overlap; waltlng to process sald scalar load/store lnstructlon untll sald tentatlve vector store lnstructlon ls lssued as an actual vector store lnstructlon and sald actual vector store lnstructlon ls processed by storlng the data ln the cache memory whlch corresponds to the lnterval block address to the maln memory, when sald scalar block address and sald store lnterval address overlap; and nulllfylng block data present ln sald scalar cache memory whlch corresponds to a store address of sald tentatlve vector store lnstructlon.
A 7ll80-llo Brlef Descrlptlon of the Drawlngs Flg. 1 ls a block dlagram showlng a maln part of an embodlment accordlng to the present inventlon;
Fig. 2 is a vlew for explalnlng a format of address data;
Flg. 3 ls a view showlng a detalled arrangement of an lnstructlon strlng; and Flgs. 4A and 4B are vlews for explalnlng operatlons of the embodlment shown ln Flg. 1.
Detalled DescrlPtlon of the Preferred Embodlments An embodlment of the present lnventlon wlll be descrlbed below wlth reference to the accompanylng drawlngs.
Flg. 1 shows a maln part of an embodlment of a data processlng apparatus accordlng to the present lnventlon. The data processlng apparatus accordlng to thls embodlment comprises an lnstructlon lssulng means 1, an - 5a -A
2~
interval holding means 2 connected to the instruction issuing means 1 via a tentative instruction issuing line 11, a passing control means 3 connected to the interval holding means 2 via an interval address data line 13 and connected to the instruction issuing means 1 via a final instruction issuing line 12, a nullification processing means 4 connected to the instruction issuing means 1 via the tentative instruction issuing line 11, a buffer storing means 16 connected to the nullification processing means 4 via a nullification processing data line 16 and connected to the passing control means 3 via an access signal line 14, and a main storing means 6 connected to the passing control means 3 via the access signal line 15.
The buffer storing means 5 includes a scalar cache memory which can be accessed by only a scalar instruction. Assuming that address data is constituted by n bits of 0 to n as shown in Fig. 2 and the block size of block data of the scalar cache memory is 2(n m 1), a block address is constituted by 0 to Q bits, and an intrablock address is constituted by m to n bits. Note that nullification processing of the scalar cache memory is performed in units of block data.
The instruction issuing means 1 issues an instruction in accordance with an instruction issuing order designated by a program. If a vector store instruction having no definitive data is output, the instruction issuing means 1 tentatively issues the vector store 2~
instruction as an instruction not to be subjected to actual vector store processing. After data is determined, the instruction issuing means 1 interrupts the instruction issuing order to finally issue the vector store instruction 5 as an instruction to be subjected to the actual vector store processing. Tentative issuing of the vector store instruction is performed for the tentative instruction issuing line 11 and its final issuing is performed for the final instruction issuing line 12.
The interval holding means 2 receives a vector store instruction tentatively issued from the instruction issuing means l onto the tentative instruction issuing line 11, and generates a continuous store interval address from a store start address to a store end address to be stored by the vector store instruction by using a vector store start address (B), a vector store interelement distance (D), and a vector store element number (L), all of which are designated by the vector store instruction. The interval holding means 2 holds address data of the store interval address except for an address part corresponding to the intrablock address shown in Fig. 2 as a store interval block address and supplies the address data to the passing control means 3 via the interval address data line 13. Note that the store interval block address held by the interval holding means 2 is erased when a corresponding vector store instruction is finally issued and processed.
2~13~19 The passing control means 3 compares address data (scalar load/store block address) of a scalar load/store address indicated by a scalar load/store instruction issued from the instruction issuing means 1 except for an address part corresponding to the intrablock address shown in Fig. 2 with the store interval block address supplied from the interval holding means 2. If the scalar load/store block address falls outside the range of the store interval block address, the passing control means 3 enables the scalar load/store instruction to access the scalar cache memory of the buffer storing means 5 and the main storing means 6. If the scalar load/store block address falls within the range of the store interval block address, the passing control means 3 causes processing for the scalar load/store instruction to wait until a vector store instruction is issued from the instruction issuing means 1 and processed.
When a vector store instruction is tentatively issued from the instruction issuing means 1 onto the tentative instruction issuing line 11, the nullification processing means 4 nullifies block data present in the scalar cache memory of the buffer memory means 5 and corresponding to a store address of the vector store instruction by using a vector store start address (B), a vector store interelement distance (D), and a vector store element number (L), all of which are designated by the tentatively issued vector store instruction.
2~ 3~
An operation of this embodiment will be described below by taking execution of a program including an instruction string as shown in Fig. 3 as an example. In the instruction string shown in Fig. 3, a vector addition instruction VADD, a vector store instruction VST, scalar load instructions LDS A and LDS B, an addition instruction ADD, a scalar store instruction STS, and a scalar load instruction LDS C are arranged in an order of addresses, and store data of the vector store instruction VST
indicates an arithmetic operation result of a vector addition instruction VADD of a previous instruction.
If an instruction issuing order designated by a program is the order as shown in Fig. 3, the instruction issuing means 1 issues the respective instructions from the vector addition instruction VADD. In this case, since an arithmetic operation of the vector addition instruction VADD previous to the vector store instruction VST is not finished and the store data is not determined, the instruction issuing means 1 tentatively issues the vector store instruction VST and issues the subsequent scalar load instruction LDS A and the like in the order of addresses.
Note that if the arithmetic operation by the vector addition instruction VADD is finished and the data is determined at the timing shown in Fig. 3, the vector store instruction VST is finally issued at a position indicated by a broken line in Fig. 3, i.e., next to the scalar store instruction STS by interruption.
2~3~Q9 When the vector store instruction VST is supplied via the tentative instruction issuing line 11, the interval holding means 2 calculates a store interval address {B, B +
D x (L - 1)} on the basis of the vector store start address (B), the vector store interelement distance (D), and the vector store element number (L) of the vector store instruction VST. The interval holding means 2 generates and holds a store interval block address obtained by removing an address part corresponding to the intrablock address from the store interval address and supplies the store interval block address to the passing control means 3 via the interval address data line 13. Referring to Fig. 4A in which the abscissa indicates an address, assuming that the vector store start address (B) of the vector store instruction VST corresponds to a position of "START" and a final start address {B + D x (L - 1)}
corresponds to a position of "END", an operation of removing the address part corresponding to the intrablock address from the store interval address {B, B + D x (L - 1)}
corresponds to a shift to positions of "start" and "end" as indicated by arrows in Fig. 4A. These "start" and "end"
positions correspond to start and end addresses of the store interval block. Note that in Fig. 4A, bQ represents a block boundary; el to eL, elements to be stored by the vector store instruction VST; a and b, scalar load/store accesses; and F0 to FN, nullification block addresses.
2~3~9 When the vector store instruction VST is supplied via the tentative instruction issuing line 11, the nullification processing means 4 obtains the nullification block addresses F0 to FN shown in Fig. 4A on the basis of the vector store start address (B), the vector store interelement distance (D), and the vector store element number (L) of the vector store instruction VST, and nullifies block data present in the store cache memory of the buffer storing means 5 and corresponding to the store address of the vector store instruction VST via the nullification processing data line 16. By this nullification, the block data corresponding to the store address of the vector store instruction VST is no longer present in the store cache memory.
The passing control means 3 receives an instruction supplied from the instruction issuing means 1 via the final instruction issuing line 12 and executes processing such as passing control of the instruction or the like. As a series of operations, the passing control means 3 compares a scalar load/store block address indicated by the scalar load/store instruction subsequent to the tentatively issued vector store instruction VST with the store interval block address supplied from the interval holding means 2, thereby checking an address interval. If the scalar load/store block address of the scalar load/store instruction falls outside the range of the store interval block addresses, the passing control means 3 2~
allows the scalar load/store instruction to access the buffer storing means 5 and the main storing means 6 via the access signal lines 14 and 15, respectively. If the scalar load/store block address falls within the range of the store interval block addresses, the passing control means 3 causes the scalar load/store instruction to wait until the vector store instruction VST in a data standby state in the instruction issuing means 1 is finally issued and processed after data is determined. For example, if the subsequent scalar load instruction LDS B is to access the position of a or b in Fig. 4A, the intrablock address is discarded to update the store load address as indicated by an arrow in Fig. 4A to generate a store load block address, and the created store load block address is compared with the store interval block address. In this case, since the store load block address falls within the range of the interval, the store load instruction LDS B is waited. Assume that the store load instruction LDS B is immediately executed. In this case, if a cache miss occurs in the buffer storing means 5 (i.e., if no corresponding block data is present in the cache memory), block loading of a block data A or B
shown in Fig. 4B is performed, and a block data including data to be rewritten by the vector store instruction VST
indicated by a hatched portion is registered as an effective block data in the buffer storing means 5. As a result, previously performed nullification of the cache memory according to the vector store instruction as an object to be passed becomes meaningless.
As has been described above, in the data processing apparatus of the present invention, a vector store instruction to be passed by instruction passing control is tentatively issued, and processing for a scalar load/store instruction for accessing a store interval block address to be operated by the vector store instruction is waited from a timing at which the vector store instruction is tentatively issued to a timing at which it is finally issued. Therefore, nullification of a scalar cache memory according to the vector store instruction as an object to be passed can be previously controlled to increase a processing speed of the data processing apparatus.
If a data processing apparatus of this type has a scalar cache memory which can be accessed by only a scalar instruction, processing according to a vector store instruction is performed for only a main memory.
Therefore, if data corresponding to a store address of a *
A
2C~13~
vector store instruction is present in a scalar cache memory, the data is nullified to ensure data consistency.
Note that nullification of data in the scalar cache memory is performed in units of blocks. This nullification processing of block data in the scalar cache memory is conventionally performed by activating nullification processing means after a vector store instruction is issued so that the means nullifies corresponding block data.
When a vector store instruction having no definitive data is output during instruction issuing performed in accordance with an instruction issuing order designated by a program, a processing speed of a data processing apparatus using the above method (1) is inevitably reduced. In a data processing apparatus using the method (2), a processing speed can be increased since instructions which can be passed are previously issued.
If, however, the data processing apparatus using the method (2), although this is the same as the apparatus using the method (1), has a scalar cache memory which can be accessed by only a scalar instruction, nullification processing must be performed for the scalar cache memory in accordance with an vector store instruction. This nullification processing can be conventionally executed only after the vector scalar instruction is issued and therefore is an obstacle to a higher processing speed.
Summary of the Invention The present invention has been made in conslderatlon of the above situatlon, and has as lts ob~ect to provlde a data processlng apparatus uslng the method (2) descrlbed above and capable of executlng nulllflcatlon processlng of a scalar cache memory accordlng to a vector store lnstructlon passed by lnstructlon passlng lssulng control before lssulng of the vector store lnstructlon.
In order to achleve the above ob~ect of the present lnventlon, there ls provlded a data processlng apparatus whlch lncludes a buffer storage havlng a scalar cache memory whlch can be accessed by only a scalar lnstructlon, comprlslng:
lnstructlon lssulng means for lssulng lnstructlons ln accordance wlth an lnstructlon lssulng order deslgnated by a program, lssulng a tentatlve vector store lnstructlon havlng no deflnltlve data as an lnstructlon not sub~ected to actual vector store processlng sald actual vector store processlng lncludlng fetchlng data from sald scalar cache memory and wrltlng lnto the maln memory, and after data ls determlned, flnally lssulng the tentatlve vector store lnstructlon as an actual vector store instructlon to be sub~ected to the actual vector store processlng by lnterruptlng the lnstructlon lssulng order; lnterval holdlng means, recelvlng sald tentatlve vector store lnstructlon, for obtalnlng and holdlng a store lnterval block address correspondlng to sald tentatlve vector store lnstructlon; passlng control means, recelvlng a scalar block address lndlcated by a scalar load/store lnstructlon lssued from sald lnstructlon lssulng means and sald store lnterval block address held by sald lnterval holdlng means, for comparlng sald scalar block address and A 71180-l lo - 2ol3l~9 sald store lnterval block address lf the scalar block address falls outslde the range of the store lnterval block address, enabllng processlng for the scalar load/store lnstructlon, and lf the block address falls wlthln the range of the store lnterval block addresses, causlng the processlng for the scalar load/store lnstructlon to walt untll the actual vector store lnstructlon ls flnally lssued from sald lnstructlon lssulng means and the block data ln the scalar cache memory whlch corresponds to the lnterval block address ls moved to the maln memory; and nulllflcatlon processlng means, recelvlng sald tentatlve vector store lnstructlon, for nulllfylng block data present ln sald scalar cache memory whlch corresponds to a store address of the tentatlve vector store lnstructlon.
In the data processlng apparatus of the present lnventlon, when a vector store lnstructlon havlng no deflnltlve data ls output durlng lnstructlon lssulng performed ln accordance wlth an lnstructlon lssulng order deslgnated by a program, the lnstructlon lssulng means tentatlvely lssues the vector store lnstructlon as an lnstructlon not to be sub~ected to actual vector store processlng, the lnterval holdlng means obtalns and holds a store lnterval block address to be operated by the tentatlvely lssued vector store lnstructlon, and the nulllflcatlon processlng means nulllfles block data correspondlng to a store address of the vector store lnstructlon present ln the store cache memory. When the scalar load/store lnstructlon for passlng the vector store lnstructlon ls issued by the lnstructlon lssulng means ln accordance wlth lnstructlon passlng lnstructlon, the passlng A
20 1 3 1 ~9 control means compares a block address lndlcated by the scalar load/store lnstructlon wlth the store lnterval block address held ln the lnterval holdlng means. If the block address ls outslde the range of the store lnterval block addresses, processlng for the scalar load/store lnstructlon ls enabled.
If the block data ls lnslde the lnterval, the processlng for the scalar load/store lnstructlon ls walted untll the vector store lnstructlon ls flnally lssued from the lnstructlon lssulng means and processed.
The lnventlon may be summarlzed, accordlng to another broad aspect, as a method of nulllfylng a scalar cache memory comprlslng the steps of: lssulng a tentatlve vector store lnstructlon havlng no deflnltlve data as an lnstructlon not sub~ected to actual vector store processlng; obtalnlng a store lnterval block address from sald tentatlve vector store lnstructlon; comparlng a scalar block address to sald store lnterval block address; processlng a scalar load/store lnstructlon correspondlng to sald scalar block address when sald scalar block address and sald store lnterval address do not overlap; waltlng to process sald scalar load/store lnstructlon untll sald tentatlve vector store lnstructlon ls lssued as an actual vector store lnstructlon and sald actual vector store lnstructlon ls processed by storlng the data ln the cache memory whlch corresponds to the lnterval block address to the maln memory, when sald scalar block address and sald store lnterval address overlap; and nulllfylng block data present ln sald scalar cache memory whlch corresponds to a store address of sald tentatlve vector store lnstructlon.
A 7ll80-llo Brlef Descrlptlon of the Drawlngs Flg. 1 ls a block dlagram showlng a maln part of an embodlment accordlng to the present inventlon;
Fig. 2 is a vlew for explalnlng a format of address data;
Flg. 3 ls a view showlng a detalled arrangement of an lnstructlon strlng; and Flgs. 4A and 4B are vlews for explalnlng operatlons of the embodlment shown ln Flg. 1.
Detalled DescrlPtlon of the Preferred Embodlments An embodlment of the present lnventlon wlll be descrlbed below wlth reference to the accompanylng drawlngs.
Flg. 1 shows a maln part of an embodlment of a data processlng apparatus accordlng to the present lnventlon. The data processlng apparatus accordlng to thls embodlment comprises an lnstructlon lssulng means 1, an - 5a -A
2~
interval holding means 2 connected to the instruction issuing means 1 via a tentative instruction issuing line 11, a passing control means 3 connected to the interval holding means 2 via an interval address data line 13 and connected to the instruction issuing means 1 via a final instruction issuing line 12, a nullification processing means 4 connected to the instruction issuing means 1 via the tentative instruction issuing line 11, a buffer storing means 16 connected to the nullification processing means 4 via a nullification processing data line 16 and connected to the passing control means 3 via an access signal line 14, and a main storing means 6 connected to the passing control means 3 via the access signal line 15.
The buffer storing means 5 includes a scalar cache memory which can be accessed by only a scalar instruction. Assuming that address data is constituted by n bits of 0 to n as shown in Fig. 2 and the block size of block data of the scalar cache memory is 2(n m 1), a block address is constituted by 0 to Q bits, and an intrablock address is constituted by m to n bits. Note that nullification processing of the scalar cache memory is performed in units of block data.
The instruction issuing means 1 issues an instruction in accordance with an instruction issuing order designated by a program. If a vector store instruction having no definitive data is output, the instruction issuing means 1 tentatively issues the vector store 2~
instruction as an instruction not to be subjected to actual vector store processing. After data is determined, the instruction issuing means 1 interrupts the instruction issuing order to finally issue the vector store instruction 5 as an instruction to be subjected to the actual vector store processing. Tentative issuing of the vector store instruction is performed for the tentative instruction issuing line 11 and its final issuing is performed for the final instruction issuing line 12.
The interval holding means 2 receives a vector store instruction tentatively issued from the instruction issuing means l onto the tentative instruction issuing line 11, and generates a continuous store interval address from a store start address to a store end address to be stored by the vector store instruction by using a vector store start address (B), a vector store interelement distance (D), and a vector store element number (L), all of which are designated by the vector store instruction. The interval holding means 2 holds address data of the store interval address except for an address part corresponding to the intrablock address shown in Fig. 2 as a store interval block address and supplies the address data to the passing control means 3 via the interval address data line 13. Note that the store interval block address held by the interval holding means 2 is erased when a corresponding vector store instruction is finally issued and processed.
2~13~19 The passing control means 3 compares address data (scalar load/store block address) of a scalar load/store address indicated by a scalar load/store instruction issued from the instruction issuing means 1 except for an address part corresponding to the intrablock address shown in Fig. 2 with the store interval block address supplied from the interval holding means 2. If the scalar load/store block address falls outside the range of the store interval block address, the passing control means 3 enables the scalar load/store instruction to access the scalar cache memory of the buffer storing means 5 and the main storing means 6. If the scalar load/store block address falls within the range of the store interval block address, the passing control means 3 causes processing for the scalar load/store instruction to wait until a vector store instruction is issued from the instruction issuing means 1 and processed.
When a vector store instruction is tentatively issued from the instruction issuing means 1 onto the tentative instruction issuing line 11, the nullification processing means 4 nullifies block data present in the scalar cache memory of the buffer memory means 5 and corresponding to a store address of the vector store instruction by using a vector store start address (B), a vector store interelement distance (D), and a vector store element number (L), all of which are designated by the tentatively issued vector store instruction.
2~ 3~
An operation of this embodiment will be described below by taking execution of a program including an instruction string as shown in Fig. 3 as an example. In the instruction string shown in Fig. 3, a vector addition instruction VADD, a vector store instruction VST, scalar load instructions LDS A and LDS B, an addition instruction ADD, a scalar store instruction STS, and a scalar load instruction LDS C are arranged in an order of addresses, and store data of the vector store instruction VST
indicates an arithmetic operation result of a vector addition instruction VADD of a previous instruction.
If an instruction issuing order designated by a program is the order as shown in Fig. 3, the instruction issuing means 1 issues the respective instructions from the vector addition instruction VADD. In this case, since an arithmetic operation of the vector addition instruction VADD previous to the vector store instruction VST is not finished and the store data is not determined, the instruction issuing means 1 tentatively issues the vector store instruction VST and issues the subsequent scalar load instruction LDS A and the like in the order of addresses.
Note that if the arithmetic operation by the vector addition instruction VADD is finished and the data is determined at the timing shown in Fig. 3, the vector store instruction VST is finally issued at a position indicated by a broken line in Fig. 3, i.e., next to the scalar store instruction STS by interruption.
2~3~Q9 When the vector store instruction VST is supplied via the tentative instruction issuing line 11, the interval holding means 2 calculates a store interval address {B, B +
D x (L - 1)} on the basis of the vector store start address (B), the vector store interelement distance (D), and the vector store element number (L) of the vector store instruction VST. The interval holding means 2 generates and holds a store interval block address obtained by removing an address part corresponding to the intrablock address from the store interval address and supplies the store interval block address to the passing control means 3 via the interval address data line 13. Referring to Fig. 4A in which the abscissa indicates an address, assuming that the vector store start address (B) of the vector store instruction VST corresponds to a position of "START" and a final start address {B + D x (L - 1)}
corresponds to a position of "END", an operation of removing the address part corresponding to the intrablock address from the store interval address {B, B + D x (L - 1)}
corresponds to a shift to positions of "start" and "end" as indicated by arrows in Fig. 4A. These "start" and "end"
positions correspond to start and end addresses of the store interval block. Note that in Fig. 4A, bQ represents a block boundary; el to eL, elements to be stored by the vector store instruction VST; a and b, scalar load/store accesses; and F0 to FN, nullification block addresses.
2~3~9 When the vector store instruction VST is supplied via the tentative instruction issuing line 11, the nullification processing means 4 obtains the nullification block addresses F0 to FN shown in Fig. 4A on the basis of the vector store start address (B), the vector store interelement distance (D), and the vector store element number (L) of the vector store instruction VST, and nullifies block data present in the store cache memory of the buffer storing means 5 and corresponding to the store address of the vector store instruction VST via the nullification processing data line 16. By this nullification, the block data corresponding to the store address of the vector store instruction VST is no longer present in the store cache memory.
The passing control means 3 receives an instruction supplied from the instruction issuing means 1 via the final instruction issuing line 12 and executes processing such as passing control of the instruction or the like. As a series of operations, the passing control means 3 compares a scalar load/store block address indicated by the scalar load/store instruction subsequent to the tentatively issued vector store instruction VST with the store interval block address supplied from the interval holding means 2, thereby checking an address interval. If the scalar load/store block address of the scalar load/store instruction falls outside the range of the store interval block addresses, the passing control means 3 2~
allows the scalar load/store instruction to access the buffer storing means 5 and the main storing means 6 via the access signal lines 14 and 15, respectively. If the scalar load/store block address falls within the range of the store interval block addresses, the passing control means 3 causes the scalar load/store instruction to wait until the vector store instruction VST in a data standby state in the instruction issuing means 1 is finally issued and processed after data is determined. For example, if the subsequent scalar load instruction LDS B is to access the position of a or b in Fig. 4A, the intrablock address is discarded to update the store load address as indicated by an arrow in Fig. 4A to generate a store load block address, and the created store load block address is compared with the store interval block address. In this case, since the store load block address falls within the range of the interval, the store load instruction LDS B is waited. Assume that the store load instruction LDS B is immediately executed. In this case, if a cache miss occurs in the buffer storing means 5 (i.e., if no corresponding block data is present in the cache memory), block loading of a block data A or B
shown in Fig. 4B is performed, and a block data including data to be rewritten by the vector store instruction VST
indicated by a hatched portion is registered as an effective block data in the buffer storing means 5. As a result, previously performed nullification of the cache memory according to the vector store instruction as an object to be passed becomes meaningless.
As has been described above, in the data processing apparatus of the present invention, a vector store instruction to be passed by instruction passing control is tentatively issued, and processing for a scalar load/store instruction for accessing a store interval block address to be operated by the vector store instruction is waited from a timing at which the vector store instruction is tentatively issued to a timing at which it is finally issued. Therefore, nullification of a scalar cache memory according to the vector store instruction as an object to be passed can be previously controlled to increase a processing speed of the data processing apparatus.
Claims (2)
1. A data processing apparatus which includes a buffer storage having a scalar cache memory which can be accessed by only a scalar instruction, comprising: instruction issuing means for issuing instructions in accordance with an instruction issuing order designated by a program, issuing a tentative vector store instruction having no definitive data as an instruction not subjected to actual vector store processing said actual vector store processing including fetching data from said scalar cache memory and writing into the main memory, and after data is determined, finally issuing the tentative vector store instruction as an actual vector store instruction to be subjected to the actual vector store processing by interrupting the instruction issuing order;
interval holding means, receiving said tentative vector store instruction, for obtaining and holding a store interval block address corresponding to said tentative vector store instruction; passing control means, receiving a scalar block address indicated by a scalar load/store instruction issued from said instruction issuing means and said store interval block address held by said interval holding means, for comparing said scalar block address and said store interval block address if the scalar block address falls outside the range of the store interval block address, enabling processing for the scalar load/store instruction, and if the block address falls within the range of the store interval block addresses, causing the processing for the scalar load/store instruction to wait until the actual vector store instruction is finally issued from said instruction issuing means and the block data in the scalar cache memory which corresponds to the interval block address is moved to the main memory; and nullification processing means, receiving said tentative vector store instruction, for nullifying block data present in said scalar cache memory which corresponds to a store address of the tentative vector store instruction.
interval holding means, receiving said tentative vector store instruction, for obtaining and holding a store interval block address corresponding to said tentative vector store instruction; passing control means, receiving a scalar block address indicated by a scalar load/store instruction issued from said instruction issuing means and said store interval block address held by said interval holding means, for comparing said scalar block address and said store interval block address if the scalar block address falls outside the range of the store interval block address, enabling processing for the scalar load/store instruction, and if the block address falls within the range of the store interval block addresses, causing the processing for the scalar load/store instruction to wait until the actual vector store instruction is finally issued from said instruction issuing means and the block data in the scalar cache memory which corresponds to the interval block address is moved to the main memory; and nullification processing means, receiving said tentative vector store instruction, for nullifying block data present in said scalar cache memory which corresponds to a store address of the tentative vector store instruction.
2. A method of nullifying a scalar cache memory comprising the steps of: issuing a tentative vector store instruction having no definitive data as an instruction not subjected to actual vector store processing; obtaining a store interval block address from said tentative vector store instruction; comparing a scalar block address to said store interval block address; processing a scalar load/store instruction corresponding to said scalar block address when said scalar block address and said store interval address do not overlap; waiting to process said scalar load/store instruction until said tentative vector store instruction is issued as an actual vector store instruction and said actual vector store instruction is processed by storing the data in the cache memory which corresponds to the interval block address to the main memory, when said scalar block address and said store interval address overlap; and nullifying block data present in said scalar cache memory which corresponds to a store address of said tentative vector store instruction.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1075834A JPH0810451B2 (en) | 1989-03-28 | 1989-03-28 | Information processing device |
| JP75834/89 | 1989-03-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2013109A1 CA2013109A1 (en) | 1990-09-28 |
| CA2013109C true CA2013109C (en) | 1996-07-30 |
Family
ID=13587617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002013109A Expired - Fee Related CA2013109C (en) | 1989-03-28 | 1990-03-27 | Data processing apparatus nulling scalar cache memory |
Country Status (5)
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|---|---|
| US (1) | US5247635A (en) |
| EP (1) | EP0396892B1 (en) |
| JP (1) | JPH0810451B2 (en) |
| CA (1) | CA2013109C (en) |
| DE (1) | DE69024994T2 (en) |
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| JP2622008B2 (en) * | 1990-03-08 | 1997-06-18 | 甲府日本電気株式会社 | Information processing device |
| US5418973A (en) * | 1992-06-22 | 1995-05-23 | Digital Equipment Corporation | Digital computer system with cache controller coordinating both vector and scalar operations |
| JPH06168263A (en) * | 1992-11-30 | 1994-06-14 | Fujitsu Ltd | Vector processor |
| US5420991A (en) * | 1994-01-04 | 1995-05-30 | Intel Corporation | Apparatus and method for maintaining processing consistency in a computer system having multiple processors |
| US5818511A (en) * | 1994-05-27 | 1998-10-06 | Bell Atlantic | Full service network |
| US5608447A (en) * | 1994-05-27 | 1997-03-04 | Bell Atlantic | Full service network |
| US5666506A (en) * | 1994-10-24 | 1997-09-09 | International Business Machines Corporation | Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle |
| US5717895A (en) * | 1994-12-01 | 1998-02-10 | Cray Research, Inc. | Associative scalar data cache with write-through capabilities for a vector processor |
| US5826102A (en) * | 1994-12-22 | 1998-10-20 | Bell Atlantic Network Services, Inc. | Network arrangement for development delivery and presentation of multimedia applications using timelines to integrate multimedia objects and program objects |
| US5659793A (en) * | 1994-12-22 | 1997-08-19 | Bell Atlantic Video Services, Inc. | Authoring tools for multimedia application development and network delivery |
| US5799165A (en) * | 1996-01-26 | 1998-08-25 | Advanced Micro Devices, Inc. | Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay |
| DE69628571T2 (en) * | 1995-10-06 | 2004-05-06 | Advanced Micro Devices, Inc., Sunnyvale | NON-SEQUENTIAL COMMAND ORDER TO REDUCE PIPELINE DELAY |
| US5854914A (en) * | 1996-02-13 | 1998-12-29 | Intel Corporation | Mechanism to improved execution of misaligned loads |
| JP3733842B2 (en) * | 2000-07-12 | 2006-01-11 | 日本電気株式会社 | Vector scatter instruction control circuit and vector type information processing apparatus |
| US7577816B2 (en) * | 2003-08-18 | 2009-08-18 | Cray Inc. | Remote translation mechanism for a multinode system |
| US7743223B2 (en) * | 2003-08-18 | 2010-06-22 | Cray Inc. | Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system |
| US7519771B1 (en) | 2003-08-18 | 2009-04-14 | Cray Inc. | System and method for processing memory instructions using a forced order queue |
| US7437521B1 (en) * | 2003-08-18 | 2008-10-14 | Cray Inc. | Multistream processing memory-and barrier-synchronization method and apparatus |
| US8307194B1 (en) | 2003-08-18 | 2012-11-06 | Cray Inc. | Relaxed memory consistency model |
| US7421565B1 (en) | 2003-08-18 | 2008-09-02 | Cray Inc. | Method and apparatus for indirectly addressed vector load-add -store across multi-processors |
| US7543133B1 (en) | 2003-08-18 | 2009-06-02 | Cray Inc. | Latency tolerant distributed shared memory multiprocessor computer |
| JP3988144B2 (en) | 2004-02-23 | 2007-10-10 | 日本電気株式会社 | Vector processing device and overtaking control circuit |
| US7478769B1 (en) | 2005-03-09 | 2009-01-20 | Cray Inc. | Method and apparatus for cooling electronic components |
| JP5206385B2 (en) * | 2008-12-12 | 2013-06-12 | 日本電気株式会社 | Boundary execution control system, boundary execution control method, and boundary execution control program |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1443777A (en) * | 1973-07-19 | 1976-07-28 | Int Computers Ltd | Data processing apparatus |
| US4156906A (en) * | 1977-11-22 | 1979-05-29 | Honeywell Information Systems Inc. | Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands |
| US4638431A (en) * | 1984-09-17 | 1987-01-20 | Nec Corporation | Data processing system for vector processing having a cache invalidation control unit |
| US4722049A (en) * | 1985-10-11 | 1988-01-26 | Unisys Corporation | Apparatus for out-of-order program execution |
| JPH0731669B2 (en) * | 1986-04-04 | 1995-04-10 | 株式会社日立製作所 | Vector processor |
| US5063497A (en) * | 1987-07-01 | 1991-11-05 | Digital Equipment Corporation | Apparatus and method for recovering from missing page faults in vector data processing operations |
| JPS6462764A (en) * | 1987-09-03 | 1989-03-09 | Agency Ind Science Techn | Vector computer |
| US5043886A (en) * | 1988-09-16 | 1991-08-27 | Digital Equipment Corporation | Load/store with write-intent for write-back caches |
| US5123095A (en) * | 1989-01-17 | 1992-06-16 | Ergo Computing, Inc. | Integrated scalar and vector processors with vector addressing by the scalar processor |
-
1989
- 1989-03-28 JP JP1075834A patent/JPH0810451B2/en not_active Expired - Lifetime
-
1990
- 1990-03-27 US US07/500,003 patent/US5247635A/en not_active Expired - Fee Related
- 1990-03-27 DE DE69024994T patent/DE69024994T2/en not_active Expired - Fee Related
- 1990-03-27 EP EP90105795A patent/EP0396892B1/en not_active Expired - Lifetime
- 1990-03-27 CA CA002013109A patent/CA2013109C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0810451B2 (en) | 1996-01-31 |
| DE69024994D1 (en) | 1996-03-07 |
| EP0396892A2 (en) | 1990-11-14 |
| US5247635A (en) | 1993-09-21 |
| EP0396892B1 (en) | 1996-01-24 |
| CA2013109A1 (en) | 1990-09-28 |
| JPH02253470A (en) | 1990-10-12 |
| EP0396892A3 (en) | 1992-09-30 |
| DE69024994T2 (en) | 1996-06-05 |
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