CA2023669A1 - Device for providing multimedia video on a personal computer - Google Patents
Device for providing multimedia video on a personal computerInfo
- Publication number
- CA2023669A1 CA2023669A1 CA 2023669 CA2023669A CA2023669A1 CA 2023669 A1 CA2023669 A1 CA 2023669A1 CA 2023669 CA2023669 CA 2023669 CA 2023669 A CA2023669 A CA 2023669A CA 2023669 A1 CA2023669 A1 CA 2023669A1
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- Prior art keywords
- signal
- video
- video signal
- recited
- horizontal
- Prior art date
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Abstract
ABSTRACT OF THE DISCLOSURE
A device for providing and displaying multimedia video on a personal computer. The device resides on an electronic printed circuit card which fits into an expansion slot on a personal computer. The device includes inputs for various video signals, such as cable TV and off-air broadband video signals, and for computer video signals. The device also includes an integrated television tuner. The computer signals can be in CGA, EGA or VGA
format. The device converts the video signals into a format which is suitable for display on a computer monitox. The device may be used with either single frequency or multi frequency monitors, such as the VGA type and the multi-Sync type. The user can switch between computer and video mode without effecting the other display mode.
A device for providing and displaying multimedia video on a personal computer. The device resides on an electronic printed circuit card which fits into an expansion slot on a personal computer. The device includes inputs for various video signals, such as cable TV and off-air broadband video signals, and for computer video signals. The device also includes an integrated television tuner. The computer signals can be in CGA, EGA or VGA
format. The device converts the video signals into a format which is suitable for display on a computer monitox. The device may be used with either single frequency or multi frequency monitors, such as the VGA type and the multi-Sync type. The user can switch between computer and video mode without effecting the other display mode.
Description
FI~LD OF_INY~TIO~
This invention relate~ to a multimedia device for a microcomputer. More particularly, this invention relates to a card which fits into the expansion slot of a microcomputer and allows the computer monitor to be used for viewing one of various video signals such as those used in television and video cassette recorders.
BACXGR ~ND OF_TH~ INY~NTIO~
Most microcomputer systems inclucle a display monitor. The display monitor together with a data entry device, such as a keyboard, provide an interactive interface for the user. The user enters co~mands and data u~ing the keyboard, and the computer usually echoes the com~ands and data on the monitor, thereby allowing the user to follow and interact with the computerO
As microcomputers have evolved, so have the associated display technologies. Oisplay monitors have come a long way ~ince the first monochrome monitors. Display technology has moved into colour with higher and higher resolution. The evolution of the high resolution colour monitor ha~ progressed from the Colour ~raphics Adapter (C~A) standard to the Extended Graphics Adapter (EGA -trademark) standard and presently to the industry standard Video Graphics Array (VGA - trademark). ~he focus of developing display technology has been to provide ~uitable vehicle for the high-powered software graphics packages being developed.
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While the evolution Qf display technology has been in step with sof~ware graphics packages, the development of new uses for these high-resolution colour monitors has not been so responsive. Confining the use of VGA colour monitor to software applications does not fully utilize its capabilities.
Accordingly, it is therefore an object of the present invention to provide a new use for a computer display monitor. The invention pxovides a multimedia interface to the display monitor which allows ~he computer user to switch easily between computer mod and video mode.
In video mode, the invention provides the capability to view a multitude of video signals, such as cable TV (CATV~
and off~air video signals. Furthermore, he multimedia interface functions in a transparent mode thereby allowing the computer software to coex~st unimpaired in the background while the user is viewing the video.
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BRI~F SUM~AR~ OF TH~ I~VE~TIO~
In one aspect, the invention provides a device for selecting and displaying multi-media video qignals on a computer monitor adopted to receive video signals of selected frequencies, said device comprising: (a~ a video ignal input stage having means or inputting a first video signal having frequencies outside said selected range; (b) a video signal con~erter stage coupled to said video signal input stage, having means for converting the first video signal to a corresponding second video signal in said selected frequency range; (c) a computer signal input stage having me~ns for inputting a computer video signal having frequencies inside said selected range; (d) a video switch coupled to said computer input stage and to said video signal converter stage, having an ou~put and switching means for producing at the output an output video signal comprising one of said second video signal and said computer video signal; and (e) output means coupled to the output of s~id video switch for outputting the output video signal to the computer monitor.
DE:SCRIPTION OF ~5 DRAWI~GS
For a better understanding of the present invention, and to show more clearly how it may be carried lS into effect, reference will now ~e made by way of example to the accompanying drawings ~hich show alternate embodiments of the present invention. In the drawings, Figure 1 is a diagrammatic view showing the relationship between a typical microcomputer system and the devioe embodying the invention;
Figure 2 i~ a diagrammatic view of the electronic circuitry which comprises a preferred embodimen~
of the invention;
Figure 3 is a diagrammatic view of the ~5 microcomputer interface port with which the microcomputer controls ~he de~ice;
- Figure 4 1 is a diagrammatic view of the electronics for the ~ideo clipping circuit;
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Figure 4-2 is a diagrammatic view of the elec~ronics for the horizontal flybac~ simulator circuit;
~igure 4-3 is a diagrammatic view of the electronics for the horizontal synchronization signal generator;
Figure 4-4 is a diagrammatic view of the electronics for the vertical synchronization signal generator;
Figure 5-l is a timing diagram showing the horizontal drive signal;
Figure 5-2 is a timing diagram showing the horizontal flyback signal;
Figure 5-3 is a timing diagram showing the horizontal pulse position signal;
Figure 5-4 is a timing diagram showing the horizontal synchronization signal in relation to a red video signal;
Figure 5-5 is a ~imi.ng diagram showing the vertical ramp signal;
Figura 5-6 is a timing diagram ~howing the vertical trig~er signal;
Figure 5-7 is a timing diagram showing the vertical synchronization signal in relation to a blue video signal; and Figure 6 is a diagrammatic view of the menu screen for controlling the device.
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D~SCRIPTIO~ OF TE~ PREFERRED EMBODINE~TS
As ~hown in Figure 1, a complete system for displaying multimedia video signals comprises a microcomputer 1 which includes a display monitor 2, and a device 4 for displaying the multimedia video signals. The device 4, as designed, fits on a printed cixcuit card (not shown) which plugs into a peripheral expansion ~lot in the microcomputer 1. A suitable display monitor 2 is any monitor which provides frequency locking over a wide range of frequencies, including a single frequency type monitor 2. For example, a multi-frequency monitor includes the NULTI-SYNC (trademark) type monitor, such as the NEC 3A
(trademark~, and Princeton Gxaphics Systems ULTRA 14 (trademark). In addition, a VGA type monitor is also suitable for use with the device 4. With the device 4 installed in the microcomputer 1, the user can display a number of different types of video signals on the monitor 2, while at the same time, the software running on the microcomputer 1 can coexist in the back~round.
Referring now to Figure 2, the device 4 includes a video signal input stage 10, a first video switch 12, a video si~nal converter stage 14, a computer signal input stage 16, a second video swi~ch 18, and a monitor output stage 20.
The device 4 also includes a bi-directional microcomputer port 22. The po.rt 22 interfaces -the device 4 to the microcomputer l using address/data bus 24. The interface port 22 allows the device 4 to be proqrammed and 202~
controlled by the microcomputer 1 much like any other peripheral device.
As shown in Figure 3, the microcomputer port 22 includes a bus address decoder ~6 and a bi-directional data buff*r 28. The addresq decoder 26 can be a programmable logic array (PLA) integrated circuit which has certain pre-programmed addresses. The address decoder 26 connects to a dual in~line package (DIP) switch 29 which is used to select one of the pre-programmed addresses for the device 4~
The data buffer 28 connects to the data lines of the bus 24 and provides a read and write port to ~he device 4. To enable the data buffer 28 and allow the device 4 ~o accept data from the microcomputer 1, the microcomputer 1 puts the address of the device 4 on the bus 24. The address decoder 28, in turn, decodes this address and if it matches the address as set by the DIP switch 29, the data buffer 28 is enabled. Once the data buffex 28 is enabled, data can be written or read from the device 1, with the microcomputer 20 1 rontrolling the data direction u~ing a read line.
Refexring still to Figure 3, the microcomp~ter interface port 22 also includes a programmable interface adapter (PIA) 30. A suitable PIA is the 82C5~ integrated circuit manufactured by Intel Corporation. The PIA 30 provides a flexible inter~ace to the micxocomputer 1 which can be programmed to control the various circuit blocks compri~ing the device 4. The PI~ 30 controls the device 4 through a series of bi-directional ports. The ports are 2023~G9 bit-mapped and can be programmed as either inputs or outputs by the microcomputer 1 via the port 22.
To facilitats control of certain analog circuit blocks on the device 4, the device 4 incorporates a digital-to-analog (D/A) converter 32 integrated circuit. A
suitable D/A converter is the sin~le package MC144111 manufactured by Notorola Corporation. The D/A converter 32 has a serial digital communication port which interfaces to the PIA 30 via a bi-directional data line 34~ a data clock line 36, and an enable line 38. As shown in Figure 3 , the D/A converter 32 includes a number of analogue voltage output lines. As will be axplained below, the present embodiment of the device 4 uses three analog voltage sutput lines. Specifically, line 40 outputs a horizontal pulse position voltage level, line 42 provides a video clipping level signal, and line 44 provides an audio level control signal.
Referring back to Figure 2, the video signal input stage 10 provides the interface for the multimedia video signal source to be displayed on the monitor 2. The possible video signal sources in the pre~ent embodimenk include a CATV or off air television signal on inpu~ 46, an external baseband video input from a video cassette recorder (VCR) on port 48, and a super VHS format video input on por~ 50.
The external video input and super VHS video input connect directly to the respective ports 48,50, whereas, for the tuner video input port 46, the device 4 : . ., ~.' ; :, 2 ~
includes an integrated tuner device 52 such as the V8-A505 manufactured by Hitachi. A cable TV feed signal or off-air television broadcast signal can be connected to the tuner video input port 46.
The tuner 52 provides an integrated device having the capability to tune in a multitude of television or cable channels, for example CATV signals or off-air ~elevision signals. The tuner 52 includes a bi-directional communication port 55 which allows it to interface with the PI~ 30 and therefore fa~l under control of the microcomputer 1. Similar to the D/A converter 32, the port 55 on ~he tuner 52 has a bi-directional serial data line 54, a data clock line 56 to shift the serial data, and an enable line 58 to select the tuner chip 52.
Having the tuner chip 52 interface to the microcomputer 1 puts ths functions of the tuner 52 under the control of the microcomputer 1. Channels can be programmed and selected using mic:rocomputer l software and keyboard controls. Fox example, a m0nu screen 170 for video mode as shown in Figure 6, allows the user to easily select and control the display of the video signal.
Referring to Figure 6, the menu screen 170 1ncludes various fields and icons to convey ex~ernal video source and television picture control information to the u~ex. The screen 170 includes a field 171 for the current channel selected on the tuner 52. The field 171 has an icon 172 which correspond to the current channel. The screen includes a ~ield 173 for the volume control. An icon 174 in 6 ~;
g .
the form of a bar signal signifies ~he cur.rent volume level.
The menu screen 170 also includes icons for mute control 175, last channel 176, and computer/video mode toggle 178. The mute control 175 may b~ implemented using an assigned key on the keyboard of ~he microcomputer 1. For example~ the ~M~' key can be assigned to the mute control 175. Similarly, the "L~ key can be a~signed to the last channel icon 176. In the present embodiment, the SPACE bar on ~he keyboard of the microcomputer 1 is assigned to the computer/video toggle function. By pressing and releasing the SPACE bar, the user switches between displaying a computer screen and a video screenO
Referring still to Figure 6, the lo~er portion of the menu screen 170 as separated by a bar 179 displays various functions associated with controlling the video picture. There is a brightness control icon 180, which includes a bar signal 184 to signify the current position of the brightness control. ~here is also a contrast control icon 181, a colour control icon 182, and a tin~ control icon 183. A11 of these icons 181,182,183 have respective bar signal icons 185,186,187 which signify the cuxrent position of the associated video picture control. To provide an easily discernable human interface to the menu screen 170, different colours can be used for the various icons to highlight the information the icons relay. As is well known to one skilled in the art, the functions comprising the menu screen 170 can be easily implemented . ~ . ,.: ., ,:
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and integrated as part of the software program which oversees operation of the device 4.
Referring back to Figure 2, to allow the user to select from the various multi-media video signals, the video signal input stage 10 connects to the video switch 12. The video switch 12 provides a multiplex function whereby any of the input signals to the switch 12 are outputted by genera~ing the appropriate 2-bit address on a pair of address lines 13. The microcomputer 1 controls the address l:ines 13 via two select lines 31 on the PIA 30. ~or example, if the user wishes to view a television channel, the microcomputer 1 selects the tuner video input 46 and transmits the user~s channel selection to the tuner chip 52 and to the video switch 12. Similarly, if the user selects an external video signal such the super VHS signal on port 50, the microcomputer 1 translates the user's request into the appropriate control signals which are then applied to the address lines 13 of the video switch 12 via the PIA 30.
The video switch 12 include3 an output line 15 which connects to the next signal processing stage. Since the freguency spectrum of the selected external video signal is incompatible with the signal expected by the display monitor 2, the video signal must be converted into a suitable format. rhe device 4 uses the RED, &REEN, BLUE
(RGB) format for the display monitor 2. The video converter stage 14 performs the signal conversion procedure for the video signal.
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In a fir~t embodiment, the device 4 utilizes a video signal decoder 62, such a the Motorola MC4400 or CHR0MA4 (trademark) integrated circuit, for the signal conversion process. The decoder 62 is a monolithic circuit which performs most of the functions required for colour television. In the present embodiment, the decoder 62 performs the function of converting the Na~ional Television Standards Committee (NTSC) format video signal into its equivalent RGB format. The RG~ output of the converter 62 is in the North American standard 525 interlace format.
For European systems, the device 4 includes a delay line circuit 170. The delay line cixcuit 170 i5 for Phase Alternation Line (PAL) systems and for S~quential Couleur A Memoire (SECAM) systems. For NTSC format signals/
the decoder 62 bypasses the delay line circuit 170. To adapt the device 4 for operation with European systems, the current tuner 52~ which is NTSC compatible, must be replaced by a tuner device which is PAL or SECAM
compa~ible.
As shown in Figure 2, the output 15 of the video switch 12 feeds into the video signal decoder 62.
Internal1y, the decoder 62 performs a conversion process of the NTSC signal into its corresponding ~GB signal equivalents: a red signal 61, a green signal 63, and a blue -~ignal 65. The microcomputer 1, under software control, controls the decoder 62 operation via a bi-directional communication port 69 which interfaces to the PIA. The microcomputer 1 controls the decoder 62 by writing to its : . ' ' ,.
.
internal re~isters which provide contrast, brightness~
tint, colour selection of NTSC or SVHS, and other preset adjustments.
After converting the NTSC format signal into the RGB signal equivalents 61,63,65/ the decoder 62 feeds the signals 61,63,65 into three respective vidèo clipping circuits 66,67,69. The red video clipping circuit 66 limits the negative excursion o~ the red signal 61 during the blanking period, ie. at the end of the horizontal scan. The green video clipping circuit 67 limits the n~gative excursion of the green signal 63. The blue video clipping circuit 69 limits the negative excursion of the blue signal 65.
An appropriate video clipping circuit 66 is shown in Eigure 4-1. Two transistors 68,70 are coupled in a common emitter configuration. The red signal 61 feeds the base of transistor 68, while the video clipping level signal on line 42 from the D/A converter 32 feeds the base of transistor 70. As will be known to those skilled in the art, the red video clipping circuit 66 produces an output signal on lead 75 which connects to a resistor Re that is a function of the positive diffexence between the red sign~l 61 input and the video clipping level signal on line 42.
Since the video clipping level ~ignal on line 42 is set by the D/A converter 32, the clipping level output on line 42 falls under the control of the microcomputer 1.
This provides a flexible method whereby the clipping level ~0%3~
~ 13 -signal on line 42 can be ~asily changed through the softwaxe. Such an approach permits the device 4 to easily function with the display monitor 2 by setting the appropriate black level. In addition, microcomputer control of the clipping level signal on line 42 allows the device 2 to compensate for variations in the RGB signals 61.63,65 from other video signal decoders. Similar video clipping circuits 67,69 clip the blue signal 65 and green signal 63 ~r~m the dacoder 62.
After passing throuyh their respective video clipping circuits, the clipped RGB signals no~ shown at 61',63',65' feed into the second video switch 18. The second video switch 18 selects between the clipped RGB
signals 61',63',65' from the decoder 62 and the output from the computer signal input stage 16. The computer signal stage 16 outputs a RGB format signal for the computer video, which comprises a red signal 70, a green signal 71, and a blue signal 72.
The microcomputer 1 controls the second ~ideo switch via the PIA 30. The PIA 30 uses two lines 33, programmed as outputs, to control the input selection on the video switch 18. The lines 33 connect to two address lines 19 on tha video switch 18 and route either the clipped RGB signals 61',63',65~ from the video stage 10 or the RGB signal 70,71,72 from the computer ~ignal ~tage 16 to ~he monitor output stage 20.
To properly convert one of the video signals 46,48,50 to it~ equivalent RGB signals 61,63,65, ie. NTSC
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20236~9 - 14 ~
format to RGB format, the decoder 62 requir0s certain additional control circuits. The purpose of these control circuits is to simulate electronically a television environment for the decoder 62. The control circuits for ~he decoder 62 comprise a horizontal flyback simulator circui~ 80, a horizontal synchronization signal circuit 82, a vertical synchronization signal circuit ~4, and a horizontal pulRe position circuit 86. The control circuits also include the video clipping level circuits 66,67,69 which were described abo~e.
The flyback pulse simulator circuit 80 simulates the delay of a horizontal flyback circuit in a television set. As is well known to those skilled in the ar~, the flyback is the period during which the electron trace lS returns to its starting point. In television receivers, the trace is suppressed during the flyback period so that no luminous spot is observed on the screen during the return interval. In a regular television set, the horizontal ~lyback is tapped from the line output transformer. 5ince the display monitor 2 is not an ordinary television se~, and therefore, amongst other things, does not include a line output transformer, the horizontal flyback circuit simulates the delay of the horizontal ~lyback tap on the line transformer, thereby tricking the decoder 6~ into behaving a~ if connected to a television setO
Referring to Figure 4-2l the horizontal flyback simulator circuit 80 utilizes a monostable one-shot 81 to generate a horiæontal flyback delay signal 5~. As is known 202~9 to one ~killed in the art, the mono table one-shot 81 is a circuit which has only one stable state. But by applying a signal on a trigger input 81a, the monostable 81 can take a second quasi-stable state. An external resistor Rl and a capacitor C1 set the period of the quasi-stable state. In the present embodiment, the flyback circuit 80 utilizes a 10 Kohm resistor Rl and a lN2 type capacitor C1 to yield a flyback signal 5B as depicted in Figure 5-2.
The decoder 62 uses a horizontal drive pin 88 on the decoder 62 to apply a signal 5A (refer to Figure 5-1) on the trigger input 81a. The signal 5A applied to the trigger input 81a has an approximately even mark-to-space ratio as shown in Figure 5-1. The signal 5A triggers the monostable 81, and the mono~table 81, in turn, generates the horizontal flyback delay signal 5B. The flyback signal 5B ~eeds back into the decoder 62 to simulate the flyback tap on a television line transfoxmer.
In addition to the flyback signal 5B, there are two other synchronization pulses which mu~t be generated on the expansion card to simulate the television environment.
They are a horizontal synchronization signal 5D and a vertical synchronization signal 5E as depicted in Figures 5-4, 5-5, respectively. The horizontal synchronization signal 5D controls the horizontal or line traverse of the electron beam in the display monitor 2. The vertical synchronization signal 5E controls the vertical or field traverse of the electron beam in the display monitor 2.
Since the device 4 does not utilize a line output : ~ .
~' ~1 '.
~23~9 transformer, the synchronization pulses SD,5E mus~ be generated locally by the horizontal synchroniza~ion pulse circuit 82 and the vertical synchronization pulse circuit ~4.
The horizontal synchronization signal circuit 82 uses a monostable one-shot 83, as shown in Fi~ure 4-3, to generate the horizontal synchronization signal 5D. To set the period of the horizontal synchronization signal 5D, the monostable 83 is connected to an external resistor R2 and a capacitor C2. As shown in Figures S-4,5-2, the horizontal synchronization signal 5D occur during the horizontal fl~back period 5B. To achieve the desired pulse width of 4.7 microseconds, the value of the resistor R2 is 10 kOhm and the capacitor C2 is type N5. To account for any component variations, the pulse period and width are easily adjustable by modifying the resistor R2 and capacitor ~2 values as is well-known to one s]cilled in the art.
Referring to Figure 4-3, the horizontal position circuit 86 connects to a tri.gger input 83a on the horizontal synchronization signal circuit 82. Unlike a television picture tube, computer display monitors, such as ~he multi-frequency variety~ require that the horizontal synchroniæation signal 5D be delayed by 1.5 to 8 microseconds. The adjustable delay in the position of the horizontal synchronization signal 5D is necessary to accommodate variations due to the two different horizontal scan rates, ie. one for video signals and one for computer signals, being outputted to the monitor 2. Without such a '' '', ' `'`'``'~ ' , 20~6~
delay, ~he display monitor 2 cannot clamp on~o the input signal. Furthermore, the pos:ition of the horizontal synchronization signal 5D determines the blanking position on the display monitor 2. Accordingly, the horizontal S position circuit 86 correctly positions the pictuxe depending on whether a television picture or a computer screen is being displayed by altering the position of the horizontal synchronization signal 5D.
To position the hori~on~al synchronization signal 5D and thus the blanking position on the display monitor 2, the horizontal position circuit 8S also uses a monostable one-shot 87, as shown in Figure 4-3. Unlike the other control circuits 80,82,84, the monostable 87 has a variable period quasi stable state, which is controlled ~y the microcomputer 1 via the PIA ~0 and the D/A converter 32.
The horizontal position voltage on line 40 of the D/A
convertor 32 controls the voltage drop across an external resistor R7 which together with another external resistor R3 and an external capacitor C3 set the period of the signal on output line 87b from the monostable 87. Having the monostable 87 coupled to the D/A converter 32 allows the microcomputer 1 , through software, to control the position of the horizontal synchronization signal 5D.
Referring still to Figure 4-3, the horizontal position circuit 86 has a trigger input 87a and the outpu-t 87b. The horizontal drive output 88 on ths decoder 62 connects to the trigger input 87a of the monostable 87. In response to the signal SA on drive output pin 88, the 6 ~
~ 18 -monostable 87 generates a signal 5C on the output pin 87b, which is connected to the trigger input 83a of the horizontal synchronization pulse circuit 82.
The position (ie. horizontal blanking position) oi the horizontal synchronization signal SD i5 varied by using the control line 40 on the D/A convertor 32 to change the voltage drop across resistor R7, which in turn, changes the period of the signal 5C generated on the output pin 87b. As can be seen in Figures 5-3,5-4, by Yarying the signal 5C on output pin 87b, the position of ~he horizontal synchronization signal 5D can be changed. As shown in Figure 5 4, the horizontal synchronization signal 5D is delayed by 3.5 microseconds relative to the horizontal flyback signal 5B. Since the horizontal position signal SC
is con~rolled by ~he microcom~ut~er 1 via the D/A convertor 32 and line 40, it can easily be changed to accommodate ~he behaviour of various computer monitors as a result of the two different horizontal scanning frequencies, ie. video mode and computer mode.
Referring now to Figure 4-4, the vertical synchxonization signal 5E is also generated using a monostable one-shot 95. The circuit includes an external resistor R4 and capacitor C4 whîch produce the vertical synchronization signal 5E with a 250 microsecond pulse width. The monostable 9S has a trigger input 95a which receives a trigger signal 9~ generated by a vertical ramp signal 90 outputted by the decoder 62 on line 92. A
transistor circuit 94 shapes the vertical ramp signal 90 to 2i~2~9 yield the trigger signal 96 as shown in Figure 4-4. The transistor 94 includes a decoupling capacitor C5 and two bia~ resis~ors R5,R6.
The horizontal synchronization signal 5D and the vertical syn~hronization signal 5E are fed into a synchronization switch 100 on input line~ 111,113, as shown in Figure 2. The synchroniæation ~witch 100 also has two inputs 115,117 for a computer horizontal synchronization signal 102 and a computer vertical synchronization signal 104~ ~he select lines 101 of the synchroni~ation swit~h 100 connect to output lines 35 on the PIA 30. U~ing the PIA 30, the microcomput2r 1 routes the appropriate horizontal and vertical synchronization signals 5~,5E,102,104, ~o the computer monitor 2. For example, if the user wishe~ to lS switch from computer mode to television mode, the PIA 30 under software control selects the horizontal and vertical synchronization signalæ SD,SE i~)ut for television mode.
The synchronization switch 100 outputs 103,105 feed into the monitor output stage 20 which in turn is connected ~o the computer monitor 2. To pxovide additional dri~e capability, the synchronization switch 100 outputs 103,105 are conditioned by bufferæ 152,153.
Referring still to Figure 2, the device 4 also includes an audio stage 108. The audio stage 108 provides the signal proce-csing circuitry for the audio output 110 from the tuner 52 and for external audio inputs, including an audio input 48a for the external video signal or for the super VH5 video signal. The audio output 110 from the tuner ', ~' ' ' 2~ 0 ~d 3 6 6 9 feeds into a gain ~mplifier 114 having approximately unity gain. The output 116 of the unity gain amplifier 114, in turn, feeds into an external audio output connector 118 and into an audio switch 120.
The audio switch 120, using addrass lines 121 connected ko the select lines 31 of the PIA 30, provides a multiplexer function to select between the ~uner audio signal output 116/ and the external audio so~lrces 48a. Both the audio switch 120 and the first video switch 12 are controlled by the selec~ lines 31 of ~he PI~ 30 so that the audio sîgnal input 110,48a tracks its respective video signal 46,48,50 respectively. The select lines 31 of the PIA 30 connect both to the address lines 13 of the first video switch 12 and to the address line 121 of the audio switch 120. In this way, when the user selects a different video signal source, the microcomputer 1 software will also select the appropriate audio source for that video ~ignal source.
The output 122 of -the audio switch 120 feeds an audio attenuator circuit 124. The audio attenuator 124 controls the output level of the audio signal 116,48a. The audio control level on line 44 from the D/A converter 32 pro~ides ~he control vol~age for the audio at~enuator 124.
The audio signal output on line 126 varies as a unction of the audio control level on line 44.
The audio stage 114 also include~ a mute circuit 128. The mute circuit 128 connects to the audio control level voltage on line 44 of the audio attenuator 114 and 2~3~9 - 21 ~
mutes the audio signal on output line 126 when activated.
The mute circuit 128 is implemented using a single transistor (not shown) with its emitter connected to the audio control voltage on line 44 on the attenuator 124. The PIA 30 provides a mute control line 130 which connects to the base of the transistor (not shown). When the PIA 30 raises the mute control line 130 to a logic ONE, the transistor ~not shown) turns on and overrides the audio level control signal on line 44.
Referring still to Figure 2, the audio stage 108 also includes an audio output amplifier 132. The output amplifier 132 connects to the output 126 of the audio attenuator 124 and provides the drive for an audio speaker 152.
To display the signal generated by the computer 1, the device 4 includes the computer signal input stage 16. The computer signal input stage 16 accepts the computer video signal which can be in either a CGA format signal 131, an EGA format signal 133, or a VGA format 134 signal and routes the computer video ~ignal ~31,133,134 to the monitor output stage 20 according to the user's selection.
For computers which only have an CGA or EGA format signals 131,133, the device 4 pro~-ides a computer signal converter stage 136 as shown in Figure 2.
The computer signal converter stage 136 converts the CGA signal 131 or EGA signal 133 into RGB format signalj 70,71,72. The VGA format signal 134 bypasses the conrerter stage as they are already in RGB format : ., 2~2~
70',71',72'. For computers with CGA 131 or EGA 133 video signals, the converter stage 136 is selected using a DIP
switch or a jumper array (not shown). ~s shown in Figure 2, the converter s$age 136 may be an integrated converter chip, such as the Notorola MC1382, which converts the CGA
~ignal 131 or EGA signal 133 into the RGB format signals 70,71~72. After performing the conversion process, the converter chip 138 feeds the RGB format signals 70,71,72 into the second video switch 18.
The second video switch 18 performs the select function for the video signal to be displayed on ~he computer monitor 2. As ~hown in Figure 2, the ~econd ~ideo switch 18 ha inputs for the YGA format signals 70',71',72', inputs for the converted CGA/~GA format signal~ 70,71,72 and inputs for the RGB format video signals 61,63,65 from the video conversion stage 14. The microcomputer 1 controls the second video switch 18 through the PIA 30. The PIA 30 includes l;wo select lines 37 ~hich are connected to two addrej~ lines 19 on the second video switch 18. Through the software/ the microcompu er performs the ~ideo select function using the second video switch 18 according to the user's request. For example, if the user wishes to display a VGA computer signal 134, ~hen the PIA 30 sets the address lines 19 for the computer ~îgnals 70',71',72'.
When switching between a compu~er screen and a video display, "tearing" may occur. Tearing produces a monitor display which appears to be breaking up. Tearing ~$ 2 ~
usually occurs when there is a loss of synchronization which occurs momentarily when switching the horizontal and vertical synchronization pulses. To prevent tearing, the microcomputer l display a blank screen for approximately one second when switching be~ween computer and video display modes. I~he blank screen is a black colour level signal 145 which feeds inpu~ line 144 on the second video switch 18. As 5hown in Figure 2, the black colour level signal 145 is generated by connecting input line 144 to ground. In operation, for example, when the user switches from video to computer mode, the software, in controlling the second video switch through the PIA 30, momentarily selects the black colour level signal 145 on input line 144 before proceeding with the user's selection.
As shown in Fi~ure 2, the computer signal input stage 16 also includes the input lines 107,109 for the synchronization signals ~enerated for displaying a computer screen. The signal on line 107 is the computer horizontal synchronization pulse 103, and the signal on line 109 is the computer vertical synchronizakion signal 104. These synchronization ~ignals 103,105 are very similar to the synchronization signals 5D,SE required to display a video signal. However, as was discussed earlier, the timing of the horizontal synchronization signal 5D for video mode is different from the timing of the computer horizontal synchronization signal 103. The two lines 107,109 feed the computer synchronization signals 103~105 into the synchronization switch 100.
202e~669 The monitor output stage 20 outputs the selacted video signals 61,63,65 or computer video signals 70,71,72 along with the appropriate horizontal and vertical synchronization siynals 5D~5E,103,10~ to the computer monitor 2. A connector 146 couples the computer monitor 2 to the output stage 20. As previously discussed, the PIA
30, u~ing select lines 33, controls the selection of the video signals through the second video switch 18. The select line~ 33 also control the synchxonization switch 100. As shown in Figure 2, the monitor output stage 20 accepts the outputs from the second video switch 18 and fro~ the synchronization switch 100 and feeds them to the computer monitor 2.
~o provide adequ~te dri.ve for ~he video signals, the output stage includes a video amplifier 148 with an output line 150 for each RGB signal. A suitable video amplifier is the VA-4708 from VTA Corporation. To match the impedance of the computer monitor 2, each amplifier 148 includes a resistor (not shown) hetween the amplifier 150 output and the connector 146.
In a second embodiment of the invention, the video signal converter stage 14 uses the ITT video chip set (not shown) for the ~TSC video conversion process, instead of the Motorola CER0MA4 decoder 62. The ITT chip set runs at the same scan rate as YGA which is double the scan ra~e of the decoder 62~ However, the blank screen, ie. u ing the black colour level signal 145, mus~ s~ill be displayed when switching between display modes because the ITT is not 2~
2~
synchronous with the computer mode, and consequently tearing may result. In addition, the synchroniza~ion control circuits, ie. the horizontal flyback simulator circuit 80, the horizontal synchronization signal circuit 82, the vertical synchronization signal circuit 84, the video clipping circuits 66,67,6g, must be coupled to the I~T video chip set (no~ shown).
It will be evident to those skilled in the art that other e~bodiments of the invention fall within its spirit and scope a~ defined by the following claims.
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This invention relate~ to a multimedia device for a microcomputer. More particularly, this invention relates to a card which fits into the expansion slot of a microcomputer and allows the computer monitor to be used for viewing one of various video signals such as those used in television and video cassette recorders.
BACXGR ~ND OF_TH~ INY~NTIO~
Most microcomputer systems inclucle a display monitor. The display monitor together with a data entry device, such as a keyboard, provide an interactive interface for the user. The user enters co~mands and data u~ing the keyboard, and the computer usually echoes the com~ands and data on the monitor, thereby allowing the user to follow and interact with the computerO
As microcomputers have evolved, so have the associated display technologies. Oisplay monitors have come a long way ~ince the first monochrome monitors. Display technology has moved into colour with higher and higher resolution. The evolution of the high resolution colour monitor ha~ progressed from the Colour ~raphics Adapter (C~A) standard to the Extended Graphics Adapter (EGA -trademark) standard and presently to the industry standard Video Graphics Array (VGA - trademark). ~he focus of developing display technology has been to provide ~uitable vehicle for the high-powered software graphics packages being developed.
:
While the evolution Qf display technology has been in step with sof~ware graphics packages, the development of new uses for these high-resolution colour monitors has not been so responsive. Confining the use of VGA colour monitor to software applications does not fully utilize its capabilities.
Accordingly, it is therefore an object of the present invention to provide a new use for a computer display monitor. The invention pxovides a multimedia interface to the display monitor which allows ~he computer user to switch easily between computer mod and video mode.
In video mode, the invention provides the capability to view a multitude of video signals, such as cable TV (CATV~
and off~air video signals. Furthermore, he multimedia interface functions in a transparent mode thereby allowing the computer software to coex~st unimpaired in the background while the user is viewing the video.
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BRI~F SUM~AR~ OF TH~ I~VE~TIO~
In one aspect, the invention provides a device for selecting and displaying multi-media video qignals on a computer monitor adopted to receive video signals of selected frequencies, said device comprising: (a~ a video ignal input stage having means or inputting a first video signal having frequencies outside said selected range; (b) a video signal con~erter stage coupled to said video signal input stage, having means for converting the first video signal to a corresponding second video signal in said selected frequency range; (c) a computer signal input stage having me~ns for inputting a computer video signal having frequencies inside said selected range; (d) a video switch coupled to said computer input stage and to said video signal converter stage, having an ou~put and switching means for producing at the output an output video signal comprising one of said second video signal and said computer video signal; and (e) output means coupled to the output of s~id video switch for outputting the output video signal to the computer monitor.
DE:SCRIPTION OF ~5 DRAWI~GS
For a better understanding of the present invention, and to show more clearly how it may be carried lS into effect, reference will now ~e made by way of example to the accompanying drawings ~hich show alternate embodiments of the present invention. In the drawings, Figure 1 is a diagrammatic view showing the relationship between a typical microcomputer system and the devioe embodying the invention;
Figure 2 i~ a diagrammatic view of the electronic circuitry which comprises a preferred embodimen~
of the invention;
Figure 3 is a diagrammatic view of the ~5 microcomputer interface port with which the microcomputer controls ~he de~ice;
- Figure 4 1 is a diagrammatic view of the electronics for the ~ideo clipping circuit;
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-- 4 ~
Figure 4-2 is a diagrammatic view of the elec~ronics for the horizontal flybac~ simulator circuit;
~igure 4-3 is a diagrammatic view of the electronics for the horizontal synchronization signal generator;
Figure 4-4 is a diagrammatic view of the electronics for the vertical synchronization signal generator;
Figure 5-l is a timing diagram showing the horizontal drive signal;
Figure 5-2 is a timing diagram showing the horizontal flyback signal;
Figure 5-3 is a timing diagram showing the horizontal pulse position signal;
Figure 5-4 is a timing diagram showing the horizontal synchronization signal in relation to a red video signal;
Figure 5-5 is a ~imi.ng diagram showing the vertical ramp signal;
Figura 5-6 is a timing diagram ~howing the vertical trig~er signal;
Figure 5-7 is a timing diagram showing the vertical synchronization signal in relation to a blue video signal; and Figure 6 is a diagrammatic view of the menu screen for controlling the device.
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5 .
D~SCRIPTIO~ OF TE~ PREFERRED EMBODINE~TS
As ~hown in Figure 1, a complete system for displaying multimedia video signals comprises a microcomputer 1 which includes a display monitor 2, and a device 4 for displaying the multimedia video signals. The device 4, as designed, fits on a printed cixcuit card (not shown) which plugs into a peripheral expansion ~lot in the microcomputer 1. A suitable display monitor 2 is any monitor which provides frequency locking over a wide range of frequencies, including a single frequency type monitor 2. For example, a multi-frequency monitor includes the NULTI-SYNC (trademark) type monitor, such as the NEC 3A
(trademark~, and Princeton Gxaphics Systems ULTRA 14 (trademark). In addition, a VGA type monitor is also suitable for use with the device 4. With the device 4 installed in the microcomputer 1, the user can display a number of different types of video signals on the monitor 2, while at the same time, the software running on the microcomputer 1 can coexist in the back~round.
Referring now to Figure 2, the device 4 includes a video signal input stage 10, a first video switch 12, a video si~nal converter stage 14, a computer signal input stage 16, a second video swi~ch 18, and a monitor output stage 20.
The device 4 also includes a bi-directional microcomputer port 22. The po.rt 22 interfaces -the device 4 to the microcomputer l using address/data bus 24. The interface port 22 allows the device 4 to be proqrammed and 202~
controlled by the microcomputer 1 much like any other peripheral device.
As shown in Figure 3, the microcomputer port 22 includes a bus address decoder ~6 and a bi-directional data buff*r 28. The addresq decoder 26 can be a programmable logic array (PLA) integrated circuit which has certain pre-programmed addresses. The address decoder 26 connects to a dual in~line package (DIP) switch 29 which is used to select one of the pre-programmed addresses for the device 4~
The data buffer 28 connects to the data lines of the bus 24 and provides a read and write port to ~he device 4. To enable the data buffer 28 and allow the device 4 ~o accept data from the microcomputer 1, the microcomputer 1 puts the address of the device 4 on the bus 24. The address decoder 28, in turn, decodes this address and if it matches the address as set by the DIP switch 29, the data buffer 28 is enabled. Once the data buffex 28 is enabled, data can be written or read from the device 1, with the microcomputer 20 1 rontrolling the data direction u~ing a read line.
Refexring still to Figure 3, the microcomp~ter interface port 22 also includes a programmable interface adapter (PIA) 30. A suitable PIA is the 82C5~ integrated circuit manufactured by Intel Corporation. The PIA 30 provides a flexible inter~ace to the micxocomputer 1 which can be programmed to control the various circuit blocks compri~ing the device 4. The PI~ 30 controls the device 4 through a series of bi-directional ports. The ports are 2023~G9 bit-mapped and can be programmed as either inputs or outputs by the microcomputer 1 via the port 22.
To facilitats control of certain analog circuit blocks on the device 4, the device 4 incorporates a digital-to-analog (D/A) converter 32 integrated circuit. A
suitable D/A converter is the sin~le package MC144111 manufactured by Notorola Corporation. The D/A converter 32 has a serial digital communication port which interfaces to the PIA 30 via a bi-directional data line 34~ a data clock line 36, and an enable line 38. As shown in Figure 3 , the D/A converter 32 includes a number of analogue voltage output lines. As will be axplained below, the present embodiment of the device 4 uses three analog voltage sutput lines. Specifically, line 40 outputs a horizontal pulse position voltage level, line 42 provides a video clipping level signal, and line 44 provides an audio level control signal.
Referring back to Figure 2, the video signal input stage 10 provides the interface for the multimedia video signal source to be displayed on the monitor 2. The possible video signal sources in the pre~ent embodimenk include a CATV or off air television signal on inpu~ 46, an external baseband video input from a video cassette recorder (VCR) on port 48, and a super VHS format video input on por~ 50.
The external video input and super VHS video input connect directly to the respective ports 48,50, whereas, for the tuner video input port 46, the device 4 : . ., ~.' ; :, 2 ~
includes an integrated tuner device 52 such as the V8-A505 manufactured by Hitachi. A cable TV feed signal or off-air television broadcast signal can be connected to the tuner video input port 46.
The tuner 52 provides an integrated device having the capability to tune in a multitude of television or cable channels, for example CATV signals or off-air ~elevision signals. The tuner 52 includes a bi-directional communication port 55 which allows it to interface with the PI~ 30 and therefore fa~l under control of the microcomputer 1. Similar to the D/A converter 32, the port 55 on ~he tuner 52 has a bi-directional serial data line 54, a data clock line 56 to shift the serial data, and an enable line 58 to select the tuner chip 52.
Having the tuner chip 52 interface to the microcomputer 1 puts ths functions of the tuner 52 under the control of the microcomputer 1. Channels can be programmed and selected using mic:rocomputer l software and keyboard controls. Fox example, a m0nu screen 170 for video mode as shown in Figure 6, allows the user to easily select and control the display of the video signal.
Referring to Figure 6, the menu screen 170 1ncludes various fields and icons to convey ex~ernal video source and television picture control information to the u~ex. The screen 170 includes a field 171 for the current channel selected on the tuner 52. The field 171 has an icon 172 which correspond to the current channel. The screen includes a ~ield 173 for the volume control. An icon 174 in 6 ~;
g .
the form of a bar signal signifies ~he cur.rent volume level.
The menu screen 170 also includes icons for mute control 175, last channel 176, and computer/video mode toggle 178. The mute control 175 may b~ implemented using an assigned key on the keyboard of ~he microcomputer 1. For example~ the ~M~' key can be assigned to the mute control 175. Similarly, the "L~ key can be a~signed to the last channel icon 176. In the present embodiment, the SPACE bar on ~he keyboard of the microcomputer 1 is assigned to the computer/video toggle function. By pressing and releasing the SPACE bar, the user switches between displaying a computer screen and a video screenO
Referring still to Figure 6, the lo~er portion of the menu screen 170 as separated by a bar 179 displays various functions associated with controlling the video picture. There is a brightness control icon 180, which includes a bar signal 184 to signify the current position of the brightness control. ~here is also a contrast control icon 181, a colour control icon 182, and a tin~ control icon 183. A11 of these icons 181,182,183 have respective bar signal icons 185,186,187 which signify the cuxrent position of the associated video picture control. To provide an easily discernable human interface to the menu screen 170, different colours can be used for the various icons to highlight the information the icons relay. As is well known to one skilled in the art, the functions comprising the menu screen 170 can be easily implemented . ~ . ,.: ., ,:
~ . ,.~ .
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and integrated as part of the software program which oversees operation of the device 4.
Referring back to Figure 2, to allow the user to select from the various multi-media video signals, the video signal input stage 10 connects to the video switch 12. The video switch 12 provides a multiplex function whereby any of the input signals to the switch 12 are outputted by genera~ing the appropriate 2-bit address on a pair of address lines 13. The microcomputer 1 controls the address l:ines 13 via two select lines 31 on the PIA 30. ~or example, if the user wishes to view a television channel, the microcomputer 1 selects the tuner video input 46 and transmits the user~s channel selection to the tuner chip 52 and to the video switch 12. Similarly, if the user selects an external video signal such the super VHS signal on port 50, the microcomputer 1 translates the user's request into the appropriate control signals which are then applied to the address lines 13 of the video switch 12 via the PIA 30.
The video switch 12 include3 an output line 15 which connects to the next signal processing stage. Since the freguency spectrum of the selected external video signal is incompatible with the signal expected by the display monitor 2, the video signal must be converted into a suitable format. rhe device 4 uses the RED, &REEN, BLUE
(RGB) format for the display monitor 2. The video converter stage 14 performs the signal conversion procedure for the video signal.
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In a fir~t embodiment, the device 4 utilizes a video signal decoder 62, such a the Motorola MC4400 or CHR0MA4 (trademark) integrated circuit, for the signal conversion process. The decoder 62 is a monolithic circuit which performs most of the functions required for colour television. In the present embodiment, the decoder 62 performs the function of converting the Na~ional Television Standards Committee (NTSC) format video signal into its equivalent RGB format. The RG~ output of the converter 62 is in the North American standard 525 interlace format.
For European systems, the device 4 includes a delay line circuit 170. The delay line cixcuit 170 i5 for Phase Alternation Line (PAL) systems and for S~quential Couleur A Memoire (SECAM) systems. For NTSC format signals/
the decoder 62 bypasses the delay line circuit 170. To adapt the device 4 for operation with European systems, the current tuner 52~ which is NTSC compatible, must be replaced by a tuner device which is PAL or SECAM
compa~ible.
As shown in Figure 2, the output 15 of the video switch 12 feeds into the video signal decoder 62.
Internal1y, the decoder 62 performs a conversion process of the NTSC signal into its corresponding ~GB signal equivalents: a red signal 61, a green signal 63, and a blue -~ignal 65. The microcomputer 1, under software control, controls the decoder 62 operation via a bi-directional communication port 69 which interfaces to the PIA. The microcomputer 1 controls the decoder 62 by writing to its : . ' ' ,.
.
internal re~isters which provide contrast, brightness~
tint, colour selection of NTSC or SVHS, and other preset adjustments.
After converting the NTSC format signal into the RGB signal equivalents 61,63,65/ the decoder 62 feeds the signals 61,63,65 into three respective vidèo clipping circuits 66,67,69. The red video clipping circuit 66 limits the negative excursion o~ the red signal 61 during the blanking period, ie. at the end of the horizontal scan. The green video clipping circuit 67 limits the n~gative excursion of the green signal 63. The blue video clipping circuit 69 limits the negative excursion of the blue signal 65.
An appropriate video clipping circuit 66 is shown in Eigure 4-1. Two transistors 68,70 are coupled in a common emitter configuration. The red signal 61 feeds the base of transistor 68, while the video clipping level signal on line 42 from the D/A converter 32 feeds the base of transistor 70. As will be known to those skilled in the art, the red video clipping circuit 66 produces an output signal on lead 75 which connects to a resistor Re that is a function of the positive diffexence between the red sign~l 61 input and the video clipping level signal on line 42.
Since the video clipping level ~ignal on line 42 is set by the D/A converter 32, the clipping level output on line 42 falls under the control of the microcomputer 1.
This provides a flexible method whereby the clipping level ~0%3~
~ 13 -signal on line 42 can be ~asily changed through the softwaxe. Such an approach permits the device 4 to easily function with the display monitor 2 by setting the appropriate black level. In addition, microcomputer control of the clipping level signal on line 42 allows the device 2 to compensate for variations in the RGB signals 61.63,65 from other video signal decoders. Similar video clipping circuits 67,69 clip the blue signal 65 and green signal 63 ~r~m the dacoder 62.
After passing throuyh their respective video clipping circuits, the clipped RGB signals no~ shown at 61',63',65' feed into the second video switch 18. The second video switch 18 selects between the clipped RGB
signals 61',63',65' from the decoder 62 and the output from the computer signal input stage 16. The computer signal stage 16 outputs a RGB format signal for the computer video, which comprises a red signal 70, a green signal 71, and a blue signal 72.
The microcomputer 1 controls the second ~ideo switch via the PIA 30. The PIA 30 uses two lines 33, programmed as outputs, to control the input selection on the video switch 18. The lines 33 connect to two address lines 19 on tha video switch 18 and route either the clipped RGB signals 61',63',65~ from the video stage 10 or the RGB signal 70,71,72 from the computer ~ignal ~tage 16 to ~he monitor output stage 20.
To properly convert one of the video signals 46,48,50 to it~ equivalent RGB signals 61,63,65, ie. NTSC
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20236~9 - 14 ~
format to RGB format, the decoder 62 requir0s certain additional control circuits. The purpose of these control circuits is to simulate electronically a television environment for the decoder 62. The control circuits for ~he decoder 62 comprise a horizontal flyback simulator circui~ 80, a horizontal synchronization signal circuit 82, a vertical synchronization signal circuit ~4, and a horizontal pulRe position circuit 86. The control circuits also include the video clipping level circuits 66,67,69 which were described abo~e.
The flyback pulse simulator circuit 80 simulates the delay of a horizontal flyback circuit in a television set. As is well known to those skilled in the ar~, the flyback is the period during which the electron trace lS returns to its starting point. In television receivers, the trace is suppressed during the flyback period so that no luminous spot is observed on the screen during the return interval. In a regular television set, the horizontal ~lyback is tapped from the line output transformer. 5ince the display monitor 2 is not an ordinary television se~, and therefore, amongst other things, does not include a line output transformer, the horizontal flyback circuit simulates the delay of the horizontal ~lyback tap on the line transformer, thereby tricking the decoder 6~ into behaving a~ if connected to a television setO
Referring to Figure 4-2l the horizontal flyback simulator circuit 80 utilizes a monostable one-shot 81 to generate a horiæontal flyback delay signal 5~. As is known 202~9 to one ~killed in the art, the mono table one-shot 81 is a circuit which has only one stable state. But by applying a signal on a trigger input 81a, the monostable 81 can take a second quasi-stable state. An external resistor Rl and a capacitor C1 set the period of the quasi-stable state. In the present embodiment, the flyback circuit 80 utilizes a 10 Kohm resistor Rl and a lN2 type capacitor C1 to yield a flyback signal 5B as depicted in Figure 5-2.
The decoder 62 uses a horizontal drive pin 88 on the decoder 62 to apply a signal 5A (refer to Figure 5-1) on the trigger input 81a. The signal 5A applied to the trigger input 81a has an approximately even mark-to-space ratio as shown in Figure 5-1. The signal 5A triggers the monostable 81, and the mono~table 81, in turn, generates the horizontal flyback delay signal 5B. The flyback signal 5B ~eeds back into the decoder 62 to simulate the flyback tap on a television line transfoxmer.
In addition to the flyback signal 5B, there are two other synchronization pulses which mu~t be generated on the expansion card to simulate the television environment.
They are a horizontal synchronization signal 5D and a vertical synchronization signal 5E as depicted in Figures 5-4, 5-5, respectively. The horizontal synchronization signal 5D controls the horizontal or line traverse of the electron beam in the display monitor 2. The vertical synchronization signal 5E controls the vertical or field traverse of the electron beam in the display monitor 2.
Since the device 4 does not utilize a line output : ~ .
~' ~1 '.
~23~9 transformer, the synchronization pulses SD,5E mus~ be generated locally by the horizontal synchroniza~ion pulse circuit 82 and the vertical synchronization pulse circuit ~4.
The horizontal synchronization signal circuit 82 uses a monostable one-shot 83, as shown in Fi~ure 4-3, to generate the horizontal synchronization signal 5D. To set the period of the horizontal synchronization signal 5D, the monostable 83 is connected to an external resistor R2 and a capacitor C2. As shown in Figures S-4,5-2, the horizontal synchronization signal 5D occur during the horizontal fl~back period 5B. To achieve the desired pulse width of 4.7 microseconds, the value of the resistor R2 is 10 kOhm and the capacitor C2 is type N5. To account for any component variations, the pulse period and width are easily adjustable by modifying the resistor R2 and capacitor ~2 values as is well-known to one s]cilled in the art.
Referring to Figure 4-3, the horizontal position circuit 86 connects to a tri.gger input 83a on the horizontal synchronization signal circuit 82. Unlike a television picture tube, computer display monitors, such as ~he multi-frequency variety~ require that the horizontal synchroniæation signal 5D be delayed by 1.5 to 8 microseconds. The adjustable delay in the position of the horizontal synchronization signal 5D is necessary to accommodate variations due to the two different horizontal scan rates, ie. one for video signals and one for computer signals, being outputted to the monitor 2. Without such a '' '', ' `'`'``'~ ' , 20~6~
delay, ~he display monitor 2 cannot clamp on~o the input signal. Furthermore, the pos:ition of the horizontal synchronization signal 5D determines the blanking position on the display monitor 2. Accordingly, the horizontal S position circuit 86 correctly positions the pictuxe depending on whether a television picture or a computer screen is being displayed by altering the position of the horizontal synchronization signal 5D.
To position the hori~on~al synchronization signal 5D and thus the blanking position on the display monitor 2, the horizontal position circuit 8S also uses a monostable one-shot 87, as shown in Figure 4-3. Unlike the other control circuits 80,82,84, the monostable 87 has a variable period quasi stable state, which is controlled ~y the microcomputer 1 via the PIA ~0 and the D/A converter 32.
The horizontal position voltage on line 40 of the D/A
convertor 32 controls the voltage drop across an external resistor R7 which together with another external resistor R3 and an external capacitor C3 set the period of the signal on output line 87b from the monostable 87. Having the monostable 87 coupled to the D/A converter 32 allows the microcomputer 1 , through software, to control the position of the horizontal synchronization signal 5D.
Referring still to Figure 4-3, the horizontal position circuit 86 has a trigger input 87a and the outpu-t 87b. The horizontal drive output 88 on ths decoder 62 connects to the trigger input 87a of the monostable 87. In response to the signal SA on drive output pin 88, the 6 ~
~ 18 -monostable 87 generates a signal 5C on the output pin 87b, which is connected to the trigger input 83a of the horizontal synchronization pulse circuit 82.
The position (ie. horizontal blanking position) oi the horizontal synchronization signal SD i5 varied by using the control line 40 on the D/A convertor 32 to change the voltage drop across resistor R7, which in turn, changes the period of the signal 5C generated on the output pin 87b. As can be seen in Figures 5-3,5-4, by Yarying the signal 5C on output pin 87b, the position of ~he horizontal synchronization signal 5D can be changed. As shown in Figure 5 4, the horizontal synchronization signal 5D is delayed by 3.5 microseconds relative to the horizontal flyback signal 5B. Since the horizontal position signal SC
is con~rolled by ~he microcom~ut~er 1 via the D/A convertor 32 and line 40, it can easily be changed to accommodate ~he behaviour of various computer monitors as a result of the two different horizontal scanning frequencies, ie. video mode and computer mode.
Referring now to Figure 4-4, the vertical synchxonization signal 5E is also generated using a monostable one-shot 95. The circuit includes an external resistor R4 and capacitor C4 whîch produce the vertical synchronization signal 5E with a 250 microsecond pulse width. The monostable 9S has a trigger input 95a which receives a trigger signal 9~ generated by a vertical ramp signal 90 outputted by the decoder 62 on line 92. A
transistor circuit 94 shapes the vertical ramp signal 90 to 2i~2~9 yield the trigger signal 96 as shown in Figure 4-4. The transistor 94 includes a decoupling capacitor C5 and two bia~ resis~ors R5,R6.
The horizontal synchronization signal 5D and the vertical syn~hronization signal 5E are fed into a synchronization switch 100 on input line~ 111,113, as shown in Figure 2. The synchroniæation ~witch 100 also has two inputs 115,117 for a computer horizontal synchronization signal 102 and a computer vertical synchronization signal 104~ ~he select lines 101 of the synchroni~ation swit~h 100 connect to output lines 35 on the PIA 30. U~ing the PIA 30, the microcomput2r 1 routes the appropriate horizontal and vertical synchronization signals 5~,5E,102,104, ~o the computer monitor 2. For example, if the user wishe~ to lS switch from computer mode to television mode, the PIA 30 under software control selects the horizontal and vertical synchronization signalæ SD,SE i~)ut for television mode.
The synchronization switch 100 outputs 103,105 feed into the monitor output stage 20 which in turn is connected ~o the computer monitor 2. To pxovide additional dri~e capability, the synchronization switch 100 outputs 103,105 are conditioned by bufferæ 152,153.
Referring still to Figure 2, the device 4 also includes an audio stage 108. The audio stage 108 provides the signal proce-csing circuitry for the audio output 110 from the tuner 52 and for external audio inputs, including an audio input 48a for the external video signal or for the super VH5 video signal. The audio output 110 from the tuner ', ~' ' ' 2~ 0 ~d 3 6 6 9 feeds into a gain ~mplifier 114 having approximately unity gain. The output 116 of the unity gain amplifier 114, in turn, feeds into an external audio output connector 118 and into an audio switch 120.
The audio switch 120, using addrass lines 121 connected ko the select lines 31 of the PIA 30, provides a multiplexer function to select between the ~uner audio signal output 116/ and the external audio so~lrces 48a. Both the audio switch 120 and the first video switch 12 are controlled by the selec~ lines 31 of ~he PI~ 30 so that the audio sîgnal input 110,48a tracks its respective video signal 46,48,50 respectively. The select lines 31 of the PIA 30 connect both to the address lines 13 of the first video switch 12 and to the address line 121 of the audio switch 120. In this way, when the user selects a different video signal source, the microcomputer 1 software will also select the appropriate audio source for that video ~ignal source.
The output 122 of -the audio switch 120 feeds an audio attenuator circuit 124. The audio attenuator 124 controls the output level of the audio signal 116,48a. The audio control level on line 44 from the D/A converter 32 pro~ides ~he control vol~age for the audio at~enuator 124.
The audio signal output on line 126 varies as a unction of the audio control level on line 44.
The audio stage 114 also include~ a mute circuit 128. The mute circuit 128 connects to the audio control level voltage on line 44 of the audio attenuator 114 and 2~3~9 - 21 ~
mutes the audio signal on output line 126 when activated.
The mute circuit 128 is implemented using a single transistor (not shown) with its emitter connected to the audio control voltage on line 44 on the attenuator 124. The PIA 30 provides a mute control line 130 which connects to the base of the transistor (not shown). When the PIA 30 raises the mute control line 130 to a logic ONE, the transistor ~not shown) turns on and overrides the audio level control signal on line 44.
Referring still to Figure 2, the audio stage 108 also includes an audio output amplifier 132. The output amplifier 132 connects to the output 126 of the audio attenuator 124 and provides the drive for an audio speaker 152.
To display the signal generated by the computer 1, the device 4 includes the computer signal input stage 16. The computer signal input stage 16 accepts the computer video signal which can be in either a CGA format signal 131, an EGA format signal 133, or a VGA format 134 signal and routes the computer video ~ignal ~31,133,134 to the monitor output stage 20 according to the user's selection.
For computers which only have an CGA or EGA format signals 131,133, the device 4 pro~-ides a computer signal converter stage 136 as shown in Figure 2.
The computer signal converter stage 136 converts the CGA signal 131 or EGA signal 133 into RGB format signalj 70,71,72. The VGA format signal 134 bypasses the conrerter stage as they are already in RGB format : ., 2~2~
70',71',72'. For computers with CGA 131 or EGA 133 video signals, the converter stage 136 is selected using a DIP
switch or a jumper array (not shown). ~s shown in Figure 2, the converter s$age 136 may be an integrated converter chip, such as the Notorola MC1382, which converts the CGA
~ignal 131 or EGA signal 133 into the RGB format signals 70,71~72. After performing the conversion process, the converter chip 138 feeds the RGB format signals 70,71,72 into the second video switch 18.
The second video switch 18 performs the select function for the video signal to be displayed on ~he computer monitor 2. As ~hown in Figure 2, the ~econd ~ideo switch 18 ha inputs for the YGA format signals 70',71',72', inputs for the converted CGA/~GA format signal~ 70,71,72 and inputs for the RGB format video signals 61,63,65 from the video conversion stage 14. The microcomputer 1 controls the second video switch 18 through the PIA 30. The PIA 30 includes l;wo select lines 37 ~hich are connected to two addrej~ lines 19 on the second video switch 18. Through the software/ the microcompu er performs the ~ideo select function using the second video switch 18 according to the user's request. For example, if the user wishes to display a VGA computer signal 134, ~hen the PIA 30 sets the address lines 19 for the computer ~îgnals 70',71',72'.
When switching between a compu~er screen and a video display, "tearing" may occur. Tearing produces a monitor display which appears to be breaking up. Tearing ~$ 2 ~
usually occurs when there is a loss of synchronization which occurs momentarily when switching the horizontal and vertical synchronization pulses. To prevent tearing, the microcomputer l display a blank screen for approximately one second when switching be~ween computer and video display modes. I~he blank screen is a black colour level signal 145 which feeds inpu~ line 144 on the second video switch 18. As 5hown in Figure 2, the black colour level signal 145 is generated by connecting input line 144 to ground. In operation, for example, when the user switches from video to computer mode, the software, in controlling the second video switch through the PIA 30, momentarily selects the black colour level signal 145 on input line 144 before proceeding with the user's selection.
As shown in Fi~ure 2, the computer signal input stage 16 also includes the input lines 107,109 for the synchronization signals ~enerated for displaying a computer screen. The signal on line 107 is the computer horizontal synchronization pulse 103, and the signal on line 109 is the computer vertical synchronizakion signal 104. These synchronization ~ignals 103,105 are very similar to the synchronization signals 5D,SE required to display a video signal. However, as was discussed earlier, the timing of the horizontal synchronization signal 5D for video mode is different from the timing of the computer horizontal synchronization signal 103. The two lines 107,109 feed the computer synchronization signals 103~105 into the synchronization switch 100.
202e~669 The monitor output stage 20 outputs the selacted video signals 61,63,65 or computer video signals 70,71,72 along with the appropriate horizontal and vertical synchronization siynals 5D~5E,103,10~ to the computer monitor 2. A connector 146 couples the computer monitor 2 to the output stage 20. As previously discussed, the PIA
30, u~ing select lines 33, controls the selection of the video signals through the second video switch 18. The select line~ 33 also control the synchxonization switch 100. As shown in Figure 2, the monitor output stage 20 accepts the outputs from the second video switch 18 and fro~ the synchronization switch 100 and feeds them to the computer monitor 2.
~o provide adequ~te dri.ve for ~he video signals, the output stage includes a video amplifier 148 with an output line 150 for each RGB signal. A suitable video amplifier is the VA-4708 from VTA Corporation. To match the impedance of the computer monitor 2, each amplifier 148 includes a resistor (not shown) hetween the amplifier 150 output and the connector 146.
In a second embodiment of the invention, the video signal converter stage 14 uses the ITT video chip set (not shown) for the ~TSC video conversion process, instead of the Motorola CER0MA4 decoder 62. The ITT chip set runs at the same scan rate as YGA which is double the scan ra~e of the decoder 62~ However, the blank screen, ie. u ing the black colour level signal 145, mus~ s~ill be displayed when switching between display modes because the ITT is not 2~
2~
synchronous with the computer mode, and consequently tearing may result. In addition, the synchroniza~ion control circuits, ie. the horizontal flyback simulator circuit 80, the horizontal synchronization signal circuit 82, the vertical synchronization signal circuit 84, the video clipping circuits 66,67,6g, must be coupled to the I~T video chip set (no~ shown).
It will be evident to those skilled in the art that other e~bodiments of the invention fall within its spirit and scope a~ defined by the following claims.
, : . ,
Claims (28)
1. A device for selecting and displaying multimedia video signals on a computer monitor adapted to receive video signals of selected frequencies, said device comprising:
(a) a video signal input stage having means for inputting a first video signal having frequencies outside said selected range;
(b) a video signal converter stage coupled to said video signal input stage, having means for converting the first video signal to a corresponding second video signal in said selected frequency range;
(c) a computer signal input stage having means for inputting a computer video signal having frequencies inside said selected range;
(d) a video switch coupled to said computer input stage and to said video signal converter stage, having an output and switching means for producing at the output an output video signal comprising one of said second video signal and said computer video signal; and (e) output means coupled to the output of said video switch for outputting the output video signal to the computer monitor.
(a) a video signal input stage having means for inputting a first video signal having frequencies outside said selected range;
(b) a video signal converter stage coupled to said video signal input stage, having means for converting the first video signal to a corresponding second video signal in said selected frequency range;
(c) a computer signal input stage having means for inputting a computer video signal having frequencies inside said selected range;
(d) a video switch coupled to said computer input stage and to said video signal converter stage, having an output and switching means for producing at the output an output video signal comprising one of said second video signal and said computer video signal; and (e) output means coupled to the output of said video switch for outputting the output video signal to the computer monitor.
2. A device as recited in claim 1, wherein said video signal converter stage includes a video signal decoder for decoding said first video signal into said second video signal, a horizontal flyback simulation means connected to said video signal decoder and responsive thereto for producing a horizontal flyback waveform at an output thereof, and means connecting the output of said horizontal flyback simulation means to said video signal decoder for producing a horizontal flyback signal in said second video signal.
3. A device as recited in claim 2, wherein said video signal decoder includes means for generating a horizontal drive signal, said horizontal flyback simulation means including means responsive to said horizontal drive signal for producing said horizontal flyback waveform.
4. A device as recited in claim 3, wherein said means responsive to said horizontal drive signal includes a monostable vibrator.
5. A device as recited in claim 1, wherein said video converter stage includes a video signal decoder for decoding said first video signal into said second video signal, means for generating a horizontal synchronization signal, horizontal synchronization position means connected to said video signal decoder and responsive to a horizontal frive input for producing a horizontal pulse position signal, said horizontal synchronization position means including control means responsive to a computer input signal thereat for varying the timing of said horizontal synchronization signal, and said means for generating a horizontal synchronization signal being connected to said horizontal synchronization position means and responsive to said horizontal pulse position signal for generating a horizontal synchronization pulse, so that the timing of the horizontal synchronization pulses in said horizontal synchronization signal can be controlled by a computer input signal.
6. A device as recited in claim 5, wherein said means for generating the horizontal synchronization signal include a monostable vibrator.
7. A device as recited in claim 6, wherein said horizontal synchronization position means include a monostable vibrator.
8. A device as recited in claim 2, 3 or 4, further including means for generating a horizontal synchronization signal, horizontal synchronization position means connected to said video signal decoder and responsive to the horizontal drive input for producing a horizontal synchronization signal, said means for generating the horizontal synchronization signal including control means responsive to a computer input signal thereat for varying the timing of said horizontal synchronization signal, and said means for generating the horizontal synchronization signal being connected to said horizontal synchronization position means and responsive to said horizontal pulse position signal for generating a horizontal synchronization pulse, so that the timing of the synchronization pulses in said horizontal synchronization signal can be controlled by a computer input signal.
9. A device as recited in claim 2 or 5, wherein said video converter stage includes a video signal decoder for decoding said first video signal into said second video signal, means for generating a vertical synchronization signal, vertical ramp means connected to said video signal decoder and responsive to a vertical drive input for producing a vertical synchronization trigger signal, and said means for generating the vertical synchronization signal being connected to said vertical ramp means and responsive to said vertical synchronization trigger signal for generating said vertical synchronization signal.
10. A device as recited in claim 9, wherein said means for generating the vertical synchronization include a monostable vibrator.
11. A device as recited in claim 1, including a microcomputer bus adaptive to be connected to microcomputer, said microcomputer bus being coupled to a microprocessor port.
12. A device as recited in claim 11, wherein said microprocessor port comprises:
(a) an address decoder connected to said microcomputer bus and having means for decoding a device address outputted on the microcomputer bus;
(b) a bi-directional data buffer connected to said microcomputer bus and having means for inputting data from the microcomputer and for outputting data to said microcomputer bus; and (c) a peripheral interface adapter connected to said data buffer and having a plurality of output pins.
(a) an address decoder connected to said microcomputer bus and having means for decoding a device address outputted on the microcomputer bus;
(b) a bi-directional data buffer connected to said microcomputer bus and having means for inputting data from the microcomputer and for outputting data to said microcomputer bus; and (c) a peripheral interface adapter connected to said data buffer and having a plurality of output pins.
13. A device as recited in claim 12, wherein said address decoder includes means for setting the address of said device.
14. A device as recited in claim 13, wherein said microprocessor port includes a plurality of bi-directional control pins and means for programming and controlling said bi-directional control pins.
15. A device as recited in claim 14, wherein said microprocessor port further includes a digital-to-analog converter having a digital data input port and a plurality of analog output ports, and having means for converting digital data received from the microcomputer into a corresponding analog signal and outputting the analog signal, and said digital data input port being connected to an output pin of said peripheral interface adapter.
16. A device as recited in claim 4, wherein said video signal converter stage includes a red signal output port, a green signal output port, and a blue signal output port.
17. A device as recited in claim 16, further including a clipping circuit having a red signal clipping stage coupled to the red signal output port of said video signal converter stage and to said video switch, a green signal clipping stage coupled to the green signal output port of said video signal converter stage and to said second video switch, and a blue signal output port of said video signal converter stage and to said second video switch.
18. A device as recited in claim 17, wherein said clipping circuit stage includes a clipping control port coupled to a first analog output port on said digital-to-analog converter and having means for setting the clipping level of said clipping circuit.
19. A device as recited in claim 2,3 or 4, wherein said horizontal synchronization position means includes a position control port connected to a second analog output portion of said digital-to-analog converter and having means for generating said computer input signal for setting the period of the horizontal position signal.
20. A device as recited in claim 2, wherein said video signal converter stage includes a bi-directional communication port coupled to said peripheral interface adapter, having means for receiving messages from the microcomputer and transmitting messages to the microcomputer.
21. A device as recited in claim 5, further including a tuner circuit coupled to said video signal input stage, having means for outputting National Televisions Systems compatible video signals.
22. A device as recited in claim 21 wherein said tuner circuit includes a bi-directional communication port coupled to said peripheral interface adapter, having means for receiving messages from the microcomputer and transmitting messages to the microcomputer.
23. A device as recited in claim 22, wherein said tuner circuit includes a channel select stage having means responsive to the microcomputer for programming and selecting a broadcast channel.
24. A device as recited in claim 23, further including an audio signal stage coupled to said tuner circuit and to said video signal input stage, having means for outputting the audio signal from an external video source and from said tuner circuit.
25. A device as recited in claim 24, wherein said audio signal stage includes an audio level control port connected to a third analog output port of said digital-to-analog converter and having means responsive to said third analog output port for adjusting the output level of the audio signal outputted from said audio signal stage.
26. A device as recited in claim 25, wherein said audio signal stage includes an audio switch coupled to said tuner circuit and to said video signal input stage, having switching means for selecting the audio signal input to be outputted.
27. A device as recited in claim 26, wherein said audio switch is coupled to said microprocessor port, having means responsive to said microprocessor port for selecting the input audio signal to be outputted.
28. A device as recited in claim 27, further including an audio mute circuit coupled to the output of said audio switch and to said microprocessor port, and having means responsive to said microprocessor port for.
toggling the audio mute on and off.
toggling the audio mute on and off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2023669 CA2023669A1 (en) | 1990-06-26 | 1990-06-26 | Device for providing multimedia video on a personal computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2023669 CA2023669A1 (en) | 1990-06-26 | 1990-06-26 | Device for providing multimedia video on a personal computer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2023669A1 true CA2023669A1 (en) | 1991-12-27 |
Family
ID=4145782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2023669 Abandoned CA2023669A1 (en) | 1990-06-26 | 1990-06-26 | Device for providing multimedia video on a personal computer |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2023669A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5418962A (en) * | 1993-03-31 | 1995-05-23 | International Business Machines Corporation | Video display adapter control system |
| US6222589B1 (en) | 1996-08-08 | 2001-04-24 | Yves C. Faroudja | Displaying video on high-resolution computer-type monitors substantially without motion discontinuities |
-
1990
- 1990-06-26 CA CA 2023669 patent/CA2023669A1/en not_active Abandoned
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5418962A (en) * | 1993-03-31 | 1995-05-23 | International Business Machines Corporation | Video display adapter control system |
| US6222589B1 (en) | 1996-08-08 | 2001-04-24 | Yves C. Faroudja | Displaying video on high-resolution computer-type monitors substantially without motion discontinuities |
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