CA2026605A1 - Multi-level interconnection cmos devices including sog - Google Patents
Multi-level interconnection cmos devices including sogInfo
- Publication number
- CA2026605A1 CA2026605A1 CA002026605A CA2026605A CA2026605A1 CA 2026605 A1 CA2026605 A1 CA 2026605A1 CA 002026605 A CA002026605 A CA 002026605A CA 2026605 A CA2026605 A CA 2026605A CA 2026605 A1 CA2026605 A1 CA 2026605A1
- Authority
- CA
- Canada
- Prior art keywords
- interconnect
- spin
- inorganic
- tracks
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31695—Deposition of porous oxides or porous glassy oxides or oxide based porous glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/974—Substrate surface preparation
Abstract
A method of manufacturing a semiconductor wafer, comprises performing a first metallization to deposit a first layer of interconnect material on a substrate, etching the interconnect material to form interconnect tracks, depositing a first low temperature dielectric layer over the interconnect tracks, planarizing the first low temperature dielectric layer with quasi-inorganic or inorganic spin-on glass by a non-etchback process, depositing a second low temperature dielectric layer over the spin-on glass, etching via holes through the dielectric and spin-on galss layers to reach the tracks of the first interconnect layer, performing an in-situ desorption of physically and chemically bonded water vapour in a dry environment at a temperature of at least 400°C and not more than 550°C for a time sufficient to obtain a negligible desorption rate, the temperature exceeding by at least 25°C the temperature to which the surface of the wafer will be exposed during a subsequent metallization step, and performing the subsequent metallization step to deposit a second interconnect layer extending through the via holes to the first interconnect tracks without re-exposure of the wafer to ambient conditions, and keeping this wafer under vacuum. This technique permits the reliable use of inorganic or quasi-inorganic spin-on glasses in non batch type sputtering equipment.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002026605A CA2026605C (en) | 1990-10-01 | 1990-10-01 | Multi-level interconnection cmos devices including sog |
PCT/CA1991/000343 WO1992006492A1 (en) | 1990-10-01 | 1991-09-25 | Multi-level interconnection cmos devices with sog |
DE69115498T DE69115498T2 (en) | 1990-10-01 | 1991-09-25 | MULTI-LAYER CONNECTION CMOS DEVICE WITH EJECTED GLASS |
US08/039,485 US5457073A (en) | 1990-10-01 | 1991-09-25 | Multi-level interconnection CMOS devices with SOG |
EP91916654A EP0551306B1 (en) | 1990-10-01 | 1991-09-25 | Multi-level interconnection cmos devices with sog |
JP3515201A JPH06504406A (en) | 1990-10-01 | 1991-09-25 | Multilayer wiring CMOS with SOG |
KR1019930701004A KR100213693B1 (en) | 1990-10-01 | 1991-09-25 | Multi-level interconnection cmos devices with sog |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002026605A CA2026605C (en) | 1990-10-01 | 1990-10-01 | Multi-level interconnection cmos devices including sog |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2026605A1 true CA2026605A1 (en) | 1992-04-02 |
CA2026605C CA2026605C (en) | 2001-07-17 |
Family
ID=4146075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002026605A Expired - Fee Related CA2026605C (en) | 1990-10-01 | 1990-10-01 | Multi-level interconnection cmos devices including sog |
Country Status (7)
Country | Link |
---|---|
US (1) | US5457073A (en) |
EP (1) | EP0551306B1 (en) |
JP (1) | JPH06504406A (en) |
KR (1) | KR100213693B1 (en) |
CA (1) | CA2026605C (en) |
DE (1) | DE69115498T2 (en) |
WO (1) | WO1992006492A1 (en) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5504042A (en) * | 1994-06-23 | 1996-04-02 | Texas Instruments Incorporated | Porous dielectric material with improved pore surface properties for electronics applications |
US5554567A (en) * | 1994-09-01 | 1996-09-10 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for improving adhesion to a spin-on-glass |
US5530293A (en) | 1994-11-28 | 1996-06-25 | International Business Machines Corporation | Carbon-free hydrogen silsesquioxane with dielectric constant less than 3.2 annealed in hydrogen for integrated circuits |
US5861345A (en) * | 1995-05-01 | 1999-01-19 | Chou; Chin-Hao | In-situ pre-PECVD oxide deposition process for treating SOG |
JP3369817B2 (en) * | 1995-06-23 | 2003-01-20 | 三菱電機株式会社 | Semiconductor device |
JPH0964037A (en) * | 1995-08-23 | 1997-03-07 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US5847444A (en) * | 1995-09-14 | 1998-12-08 | Nec Corporation | Semiconductor device with reduced aspect ratio contact hole |
CN1107968C (en) * | 1995-10-03 | 2003-05-07 | 德克萨斯仪器股份有限公司 | Intermetal dielectric planarization ULSI circuits |
US6319852B1 (en) | 1995-11-16 | 2001-11-20 | Texas Instruments Incorporated | Nanoporous dielectric thin film formation using a post-deposition catalyst |
US6380105B1 (en) | 1996-11-14 | 2002-04-30 | Texas Instruments Incorporated | Low volatility solvent-based method for forming thin film nanoporous aerogels on semiconductor substrates |
US5807607A (en) * | 1995-11-16 | 1998-09-15 | Texas Instruments Incorporated | Polyol-based method for forming thin film aerogels on semiconductor substrates |
US6130152A (en) | 1995-11-16 | 2000-10-10 | Texas Instruments Incorporated | Aerogel thin film formation from multi-solvent systems |
KR100255659B1 (en) * | 1996-03-30 | 2000-05-01 | 윤종용 | Method of application sog of semiconductor device |
US5789315A (en) * | 1996-07-17 | 1998-08-04 | Advanced Micro Devices, Inc. | Eliminating metal extrusions by controlling the liner deposition temperature |
US5883002A (en) * | 1996-08-29 | 1999-03-16 | Winbond Electronics Corp. | Method of forming contact profile by improving TEOS/BPSG selectivity for manufacturing a semiconductor device |
JP3305211B2 (en) | 1996-09-10 | 2002-07-22 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
JPH10163192A (en) * | 1996-10-03 | 1998-06-19 | Fujitsu Ltd | Semiconductor device and its manufacture |
US5854503A (en) * | 1996-11-19 | 1998-12-29 | Integrated Device Technology, Inc. | Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit |
US5953635A (en) | 1996-12-19 | 1999-09-14 | Intel Corporation | Interlayer dielectric with a composite dielectric stack |
US5985770A (en) | 1997-08-21 | 1999-11-16 | Micron Technology, Inc. | Method of depositing silicon oxides |
TW386295B (en) * | 1997-11-15 | 2000-04-01 | Mosel Vitelic Inc | Method for forming vias in inter metal dielectric containing spin on glass layer |
EP0948035A1 (en) * | 1998-03-19 | 1999-10-06 | Applied Materials, Inc. | Method for applying a dielectric cap film to a dielectric stack |
US6121130A (en) * | 1998-11-16 | 2000-09-19 | Chartered Semiconductor Manufacturing Ltd. | Laser curing of spin-on dielectric thin films |
US6787339B1 (en) | 2000-10-02 | 2004-09-07 | Motorola, Inc. | Microfluidic devices having embedded metal conductors and methods of fabricating said devices |
US6340628B1 (en) * | 2000-12-12 | 2002-01-22 | Novellus Systems, Inc. | Method to deposit SiOCH films with dielectric constant below 3.0 |
DE10146146B4 (en) | 2001-09-19 | 2004-02-05 | Infineon Technologies Ag | Method for electrical insulation of adjacent metallic conductor tracks and semiconductor component with mutually insulated metallic conductor tracks |
US6500770B1 (en) * | 2002-04-22 | 2002-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for forming a multi-layer protective coating over porous low-k material |
US7632548B2 (en) * | 2002-08-02 | 2009-12-15 | Applied Nanotech Holdings, Inc. | Remote identification of explosives and other harmful materials |
US7674628B2 (en) * | 2003-08-01 | 2010-03-09 | Applied Nanotech Holdings, Inc. | Remote identification of explosives and other harmful materials |
US7101754B2 (en) * | 2004-06-10 | 2006-09-05 | Dalsa Semiconductor Inc. | Titanium silicate films with high dielectric constant |
US7678593B1 (en) * | 2006-09-06 | 2010-03-16 | The United States of America, as represented by the Director, National Security Agency | Method of fabricating optical device using multiple sacrificial spacer layers |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4962063A (en) * | 1988-11-10 | 1990-10-09 | Applied Materials, Inc. | Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing |
-
1990
- 1990-10-01 CA CA002026605A patent/CA2026605C/en not_active Expired - Fee Related
-
1991
- 1991-09-25 DE DE69115498T patent/DE69115498T2/en not_active Expired - Fee Related
- 1991-09-25 EP EP91916654A patent/EP0551306B1/en not_active Expired - Lifetime
- 1991-09-25 KR KR1019930701004A patent/KR100213693B1/en not_active IP Right Cessation
- 1991-09-25 WO PCT/CA1991/000343 patent/WO1992006492A1/en active IP Right Grant
- 1991-09-25 US US08/039,485 patent/US5457073A/en not_active Expired - Lifetime
- 1991-09-25 JP JP3515201A patent/JPH06504406A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
KR930702783A (en) | 1993-09-09 |
DE69115498D1 (en) | 1996-01-25 |
KR100213693B1 (en) | 1999-08-02 |
EP0551306A1 (en) | 1993-07-21 |
CA2026605C (en) | 2001-07-17 |
DE69115498T2 (en) | 1996-08-22 |
JPH06504406A (en) | 1994-05-19 |
US5457073A (en) | 1995-10-10 |
EP0551306B1 (en) | 1995-12-13 |
WO1992006492A1 (en) | 1992-04-16 |
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Legal Events
Date | Code | Title | Description |
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EEER | Examination request | ||
MKLA | Lapsed |