CA2051888A1 - Method for Enacting Failover of a 1:1 Redundant Pair of Slave Processors - Google Patents

Method for Enacting Failover of a 1:1 Redundant Pair of Slave Processors

Info

Publication number
CA2051888A1
CA2051888A1 CA2051888A CA2051888A CA2051888A1 CA 2051888 A1 CA2051888 A1 CA 2051888A1 CA 2051888 A CA2051888 A CA 2051888A CA 2051888 A CA2051888 A CA 2051888A CA 2051888 A1 CA2051888 A1 CA 2051888A1
Authority
CA
Canada
Prior art keywords
iop
primary
slave
control signal
output control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2051888A
Other languages
French (fr)
Other versions
CA2051888C (en
Inventor
Paul F. Mclaughlin
Robert W. Bristow
Karl T. Kummer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Paul F. Mclaughlin
Robert W. Bristow
Karl T. Kummer
Honeywell Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Paul F. Mclaughlin, Robert W. Bristow, Karl T. Kummer, Honeywell Inc. filed Critical Paul F. Mclaughlin
Publication of CA2051888A1 publication Critical patent/CA2051888A1/en
Application granted granted Critical
Publication of CA2051888C publication Critical patent/CA2051888C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2017—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where memory access, memory control or I/O control functionality is redundant
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media

Abstract

A primary slave IOP, upon detecting an error, verifies the availability of a secondary slave IOP, and then sets an output control signal to indicate backup is requested. The primary slave IOP then takes itself out of being the primary. A secondary slave IOP, sensing that the output control signal from the other IOP has been set, assumes the role of the primary slave IOP. A master controller, detecting an error with the primary slave IOP, interrogates the primary and secondary slave IOPs for a status input, and then arbitrates between the first and second IOP to determine the IOP that is to take on the primary role. Finally the master controller awards the more operational IOP the role of the primary slave IOP, thereby completing the failover operation.
A primary slave IOP which fails sets the output control signal as part of its failure handling and watchdog timeout function. The output control signal is also set to indicate backup for an unpowered IOP.
CA002051888A 1990-09-26 1991-09-19 Method for enacting failover of a 1:1 redundant pair of slave processors Expired - Fee Related CA2051888C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/588,385 US5136498A (en) 1990-09-26 1990-09-26 Method for enacting failover of a 1:1 redundant pair of slave processors
US07/588385 1990-09-26

Publications (2)

Publication Number Publication Date
CA2051888A1 true CA2051888A1 (en) 1992-03-27
CA2051888C CA2051888C (en) 1998-07-07

Family

ID=24353624

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002051888A Expired - Fee Related CA2051888C (en) 1990-09-26 1991-09-19 Method for enacting failover of a 1:1 redundant pair of slave processors

Country Status (5)

Country Link
US (1) US5136498A (en)
EP (1) EP0478291B1 (en)
JP (1) JPH04314138A (en)
CA (1) CA2051888C (en)
DE (1) DE69125330T2 (en)

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Also Published As

Publication number Publication date
EP0478291A2 (en) 1992-04-01
US5136498A (en) 1992-08-04
DE69125330D1 (en) 1997-04-30
JPH04314138A (en) 1992-11-05
CA2051888C (en) 1998-07-07
DE69125330T2 (en) 1997-09-18
EP0478291B1 (en) 1997-03-26
EP0478291A3 (en) 1993-06-30

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