CA2063000A1 - Method and circuit for demultiplexing digital signals capable of absorbing destuffing jitter - Google Patents

Method and circuit for demultiplexing digital signals capable of absorbing destuffing jitter

Info

Publication number
CA2063000A1
CA2063000A1 CA2063000A CA2063000A CA2063000A1 CA 2063000 A1 CA2063000 A1 CA 2063000A1 CA 2063000 A CA2063000 A CA 2063000A CA 2063000 A CA2063000 A CA 2063000A CA 2063000 A1 CA2063000 A1 CA 2063000A1
Authority
CA
Canada
Prior art keywords
circuit
absorbing
digital signals
jitters
signals capable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2063000A
Other languages
French (fr)
Other versions
CA2063000C (en
Inventor
Kazunori Matsuyama
Naoto Iga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Kazunori Matsuyama
Naoto Iga
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kazunori Matsuyama, Naoto Iga, Nec Corporation filed Critical Kazunori Matsuyama
Publication of CA2063000A1 publication Critical patent/CA2063000A1/en
Application granted granted Critical
Publication of CA2063000C publication Critical patent/CA2063000C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/073—Bit stuffing, e.g. PDH
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]
    • H04J3/1641—Hierarchical systems

Abstract

The present invention provides a method and circuit for demultiplexing digital signals which generates no errors even when destuffing jitters are heavy.
Buffer memory 2 for smoothing performs smoothing of the jitters digitally which are to be periodically generated in lower order signals demultiplexed from higher order signals by demultiplexing circuit 1. An analog IC performs resmoothing of the lower order signals which have been smoothed by the buffer memory, and thereafter performs digital/analog conversion thereof and outputs the lower order signals which have no jitters through a transformer.
CA002063000A 1991-03-15 1992-03-13 Method and circuit for demultiplexing digital signals capable of absorbing destuffing jitter Expired - Fee Related CA2063000C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7431891 1991-03-15
JP74318/91 1991-03-15

Publications (2)

Publication Number Publication Date
CA2063000A1 true CA2063000A1 (en) 1992-09-16
CA2063000C CA2063000C (en) 1997-03-11

Family

ID=13543654

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002063000A Expired - Fee Related CA2063000C (en) 1991-03-15 1992-03-13 Method and circuit for demultiplexing digital signals capable of absorbing destuffing jitter

Country Status (4)

Country Link
US (1) US5383189A (en)
AU (1) AU642590B2 (en)
CA (1) CA2063000C (en)
GB (1) GB2253766B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6741603B2 (en) 2001-07-09 2004-05-25 Overture Networks, Inc. Use of a circular buffer to assure in-order delivery of packets
US6757292B2 (en) 2001-07-11 2004-06-29 Overture Networks, Inc. Automatic adjustment of buffer depth for the correction of packet delay variation
US6728209B2 (en) 2001-07-25 2004-04-27 Overture Networks, Inc. Measurement of packet delay variation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4429386A (en) * 1981-01-05 1984-01-31 Siemens Corporation Buffer arrangement of a PCM exchange system
FR2500240B1 (en) * 1981-02-19 1986-10-31 Billy Jean Claude MULTIPLEXING AND DEMULTIPLEXING SYSTEM WITH JUSTIFICATION
JP2865692B2 (en) * 1989-02-22 1999-03-08 株式会社日立製作所 Switching system and configuration method thereof
JPH0644746B2 (en) * 1988-03-25 1994-06-08 富士通株式会社 Parallel pulse insertion circuit
JPH02165752A (en) * 1988-12-19 1990-06-26 Matsushita Electric Ind Co Ltd Digital equipment
CA1326719C (en) * 1989-05-30 1994-02-01 Thomas E. Moore Ds3 to 28 vt1.5 sonet interface circuit
JP2777929B2 (en) * 1990-07-04 1998-07-23 富士通株式会社 Asynchronous signal extraction circuit

Also Published As

Publication number Publication date
AU642590B2 (en) 1993-10-21
AU1285092A (en) 1992-09-24
US5383189A (en) 1995-01-17
CA2063000C (en) 1997-03-11
GB9205409D0 (en) 1992-04-22
GB2253766B (en) 1994-12-14
GB2253766A (en) 1992-09-16

Similar Documents

Publication Publication Date Title
EP0571180A3 (en) Digital data conversion equipment
ZA924746B (en) Substituted 1h-3-aryl-pyrrolidine-2,4-dione derivatives
GB2308759B (en) Digital delay locked loop circuit using synchronous delay line
AU8353491A (en) Justification decision circuit for an arrangement for bit rate adjustment
AU615872B2 (en) Sample-and-hold digital phase-locked loop for ask signals
EP0467412A3 (en) Line equalizer for digital signals
EP0507385A3 (en) Transmission system for synchronous digital hierarchy
EP0503732A3 (en) Transmission system for synchronous digital hierarchy
GB2284717B (en) Signal-level converting circuit for bidirectional logic signals
EP0476741A3 (en) Miscorrection arrangement for the concealment of misdetected or miscorrected digital signals
DE3572289D1 (en) Space connection network for high bit rate digital signals
EP0495540A3 (en) Multi-level board, especially for high frequency
AU2759892A (en) N-aryl-n1-azabicyclo-ureas as 5-ht3 antagonists
EP0598455A3 (en) Transmission system for synchronous digital hierarchy.
EP0651583A3 (en) Motion compensator for digital image restoration.
CA2063000A1 (en) Method and circuit for demultiplexing digital signals capable of absorbing destuffing jitter
EP0716549A4 (en) Digital video camera device and aspect ratio converting device
SG49169A1 (en) Arrangement for generating digital signals
GB9016114D0 (en) A method of,and system for,altering the rate at which digital circuitry operates
ZA921111B (en) (Carboxyl) alkyloxyalkyl derivatives of cyclodextrins.
GB9000711D0 (en) Crane,preferably offshore crane
EP0450344A3 (en) Method for the production of pilocarpin from vitro-cultures of pilocarpus
ZA929763B (en) Novel imidazoles.
EP0753227A1 (en) Adaptive boundary buffers
GB2250051B (en) Ladder wedge

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed