CA2070405A1 - Ferro-electric non-volatile variable resistive element - Google Patents
Ferro-electric non-volatile variable resistive elementInfo
- Publication number
- CA2070405A1 CA2070405A1 CA002070405A CA2070405A CA2070405A1 CA 2070405 A1 CA2070405 A1 CA 2070405A1 CA 002070405 A CA002070405 A CA 002070405A CA 2070405 A CA2070405 A CA 2070405A CA 2070405 A1 CA2070405 A1 CA 2070405A1
- Authority
- CA
- Canada
- Prior art keywords
- contact
- layer
- polarizable layer
- resistive element
- polarizable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 93
- 230000010287 polarization Effects 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims description 55
- 150000002500 ions Chemical class 0.000 claims description 13
- 230000008859 change Effects 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 230000004044 response Effects 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052790 beryllium Inorganic materials 0.000 claims description 3
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052793 cadmium Inorganic materials 0.000 claims description 3
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 239000011701 zinc Substances 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-M Bromide Chemical compound [Br-] CPELXLSAUQHCOX-UHFFFAOYSA-M 0.000 claims 2
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 claims 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 claims 1
- 229910052451 lead zirconate titanate Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 63
- 239000002305 electric material Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 6
- 229910002113 barium titanate Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 239000000969 carrier Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 230000008672 reprogramming Effects 0.000 description 5
- 230000005641 tunneling Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052714 tellurium Inorganic materials 0.000 description 4
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 3
- 229910001887 tin oxide Inorganic materials 0.000 description 3
- 238000000637 aluminium metallisation Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 235000006696 Catha edulis Nutrition 0.000 description 1
- 240000007681 Catha edulis Species 0.000 description 1
- 241001362574 Decodes Species 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 101100400378 Mus musculus Marveld2 gene Proteins 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 150000001649 bromium compounds Chemical class 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 150000003568 thioethers Chemical class 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
Abstract
An improved non-volatile variable resistance element (10) is disclosed. The resistive element (10) is based on a semiconductor having a resistivity which is determined by the state of polarization of a ferro-electric layer (14).
Description
WO91/06121 ~ PCT/US90/~5523 FERRO-ELECTRIC NON~VOLA~ILE VARIAB~E RESISTIYE ELEMENT
Back~round of the Invention The present invention relates to integrated circuits and, more particularly, to a non-volatile variable resistive element which may be deposited on the surface of an integrated circuit.
The ability to construct large numbers of small variable resistors on the surface of an integrated circuit would be very advantageous. For example, so called "neuro-networksl' can require hundreds of thousands of resistors. If the neuro-network is to be programmab1e, each of these resistors must be capable of being addressed and the resistance value changed in a continuous manner. Prior art solutions to providing such programmable resistors have been less than ideal.
For example, in one prior art solution, each resistor~;is constructed~rom a plurality of'fixed 'resistors and switching,transistors. The fixed resistors typically,,-have resistance values which differ from one another,by '~actors of two. ,The switching transistors are:used to,,~onnect selected resistors in series,to,form the variable resistance. The specific - ,,resistors are specified by digital signals.--:In ~
addition,-such a system must have addressing circuitry ~which decod~s digital signals~specifying~the address of the,specified resistor and routes the ~arious bits of:a binary number to the various switching transistors.
Since each of the fixed resistors requires an area of silico,n which"isilarger than an FET,,,a~,Yariable resistor which provides even 128 resistance~values 35, requires a silicon area which is'larger than that ' needed ! to construct l00 FET transistors. -Hence, a ,:
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., ' ' . ' '. ,,.
.. ,-' ' : . ' ' :
:,. . . . . .
W091/06121 PCr/US~0/05~23 f,r~
Back~round of the Invention The present invention relates to integrated circuits and, more particularly, to a non-volatile variable resistive element which may be deposited on the surface of an integrated circuit.
The ability to construct large numbers of small variable resistors on the surface of an integrated circuit would be very advantageous. For example, so called "neuro-networksl' can require hundreds of thousands of resistors. If the neuro-network is to be programmab1e, each of these resistors must be capable of being addressed and the resistance value changed in a continuous manner. Prior art solutions to providing such programmable resistors have been less than ideal.
For example, in one prior art solution, each resistor~;is constructed~rom a plurality of'fixed 'resistors and switching,transistors. The fixed resistors typically,,-have resistance values which differ from one another,by '~actors of two. ,The switching transistors are:used to,,~onnect selected resistors in series,to,form the variable resistance. The specific - ,,resistors are specified by digital signals.--:In ~
addition,-such a system must have addressing circuitry ~which decod~s digital signals~specifying~the address of the,specified resistor and routes the ~arious bits of:a binary number to the various switching transistors.
Since each of the fixed resistors requires an area of silico,n which"isilarger than an FET,,,a~,Yariable resistor which provides even 128 resistance~values 35, requires a silicon area which is'larger than that ' needed ! to construct l00 FET transistors. -Hence, a ,:
. . . . : : .:
., ' ' . ' '. ,,.
.. ,-' ' : . ' ' :
:,. . . . . .
W091/06121 PCr/US~0/05~23 f,r~
2~ S -2-circuit with lOO,ooo such resistors on a single chip is expensive to fabricate.
. .
Furthermore, if power is lost, the value of each resistor is also lost. As a result, the chip would have to be reprogrammed each time power is lost.
This is time consuming and requires some form of non-volatile storage ~or the various resistance values.
A second proposed prior art solution for providing such variable resistance elements utilizes electrically erasable read only memory cells (EEPROM) for the resistive elements. In this solution,'the EEPROM cells are operated in an analog region. The resistance between the drain and source of each of the cells is determined by the amount of charge on a ~loating gate. Charge is transferred to and from the ~loating gate by tunneling mechanisms.
The EEPROM resistive elements require much smaller areas of'silicon and'are non-volatiie; hence, they solve the above mentioned problems o~ a-variable resistor based on fixed xesistors. Unfortunately, EEPROM-resisti~e elements have two problems. First, -the time needed to prbgram an EEPROM c'an be of the .order of milliseconds. Hence, to program all'o'f the resistors in:a large neuro-network can'require several : seconds.~-Programming suc~ a~network can require;
c S~,reprogramming each resistor as many as thousands of -~30 ~times.-;~Hence,:'EEPROM based neuro-networks can require prohibitively-long programming times. ' ~
. .
Furthermore, if power is lost, the value of each resistor is also lost. As a result, the chip would have to be reprogrammed each time power is lost.
This is time consuming and requires some form of non-volatile storage ~or the various resistance values.
A second proposed prior art solution for providing such variable resistance elements utilizes electrically erasable read only memory cells (EEPROM) for the resistive elements. In this solution,'the EEPROM cells are operated in an analog region. The resistance between the drain and source of each of the cells is determined by the amount of charge on a ~loating gate. Charge is transferred to and from the ~loating gate by tunneling mechanisms.
The EEPROM resistive elements require much smaller areas of'silicon and'are non-volatiie; hence, they solve the above mentioned problems o~ a-variable resistor based on fixed xesistors. Unfortunately, EEPROM-resisti~e elements have two problems. First, -the time needed to prbgram an EEPROM c'an be of the .order of milliseconds. Hence, to program all'o'f the resistors in:a large neuro-network can'require several : seconds.~-Programming suc~ a~network can require;
c S~,reprogramming each resistor as many as thousands of -~30 ~times.-;~Hence,:'EEPROM based neuro-networks can require prohibitively-long programming times. ' ~
3 .~ ,' Second,--EEPROM memory'devices~may only be ;reprogrammed about';lO;OOO times before the dévices ~ail.: As noted:above, EEPROM cells operate by'causing electrons to tunnel between a ~loating gate and some .
, , ~ ;;.. ~ :, , -, ,~ . , :, :, WO 91/06121 PC-r/US90/05~;23 5 -`
other el~ctrode. The space between the floating gate and tunneling electrode is typically filled with silicon oxide. Some of the electrons become trapped in the oxide during each of the tunneling operations. As a result, a space charge which increases with each reprogramming accumulates. This space charge eventually prevents electrons from tunneling between the floating gate and thP tunneling electrode.
However, even before-this chaxge builds-up, the programming voltage needed to transfer a specified charge to the floating gate changes, making it difficult to predict the change in resistance when a ~iven programming signal is applied to the EEPROM.
As noted above, literally thousands of reprogrammings may be needed during the programming stage of setting up a neuro-network. At each reprogramming, a predictable change in the resistance of the element must occur. As noted above, the EEPROM
cell will begin to change after a few thousand reprogrammings. ~Hence, it is not always possible to program the networX be~ore the EEPROM elements wear out. -. .
.
. .
- A third problem inherent in prior art EEPROM
cells is the large.:voltages needed to cause the .,.... ........ ...ele trons-to tunnel during:programming and erasing -.operations.^ Voltages of the order.of 17 to 25 volts ~.lare:.typically.needed. :Such voltages~require isolation -30: of.the circuitry from other low voltage circuitry on .the-.same integrated-~circuit chip.: In addition,.special : circuitry f~r..generating the high -voltage.from the ; normally.available low~voltage supply musttalso be included on-the chip. ..~ 5 ~!.'' -'-35 :- .:. . ..... . . .......... - .
- Efforts to overcome these problems utllizing . . .
.. : .
-~ : . . ' , Wo~1/06121 2 ~ 5 ; PCT/~S~0/05523 ferro~electric material based materials are well known to those skilled in the art. For example, U.S. Patent 2,773,250 describes a device for storing information in which the device consists of a ferro-electric body having a semiconductor layer deposited thereon. The semiconductor layer acts as a variable resistor in an electric circuit. The resistance of the semiconductor layer was controlled by the degree of polarization of the ferro-electric body. The polarization of the ferro-ele~tric body is controlled by generatiny an electric field in the ferro-electric body. The electric fi21d was generated by providing a voltages difference across the ferro-electri~ body. This voltage difference was generated by connecting the semiconductor layer to one voltage and a second programming electrode consisting of a conductive layer which was deposited on the other side of the ferro-electric body to a second voltage.
This resistive element, however, did no~
~unction well over long periods:of time due to the materials selected. The device in-question utilized a barium titanate ferro-electric and a tellurium semiconductor. Tellurium oxidizes readily at room temperature. Hence,-an-oxide layer can form between the tellurium layer and the ferro-electric body as -oxygen atoms drift from the barium titanate into the tellurium under the in~iuence of the electric fields -- - used to-polarize the barium titanate.! Theioxide layer 30 1 has a dielectric conskant which is much less;than that of the barium titanate. Hence, as ~he oxide layer forms, the voltage difference that must be applied between the programming electrode and the semiconductor to change the polarization of the barium titanate increases. After an unacceptably small number of resistive element progamminys, the required voltaye ' , ~ ' ,,'', '' ' .;
'': ':
wos1/06121 Pcr/us9o/o55~3 '`~` 2~
becomes too large for the device to be practical.
A second type O~r EEPROM cell based on ferro-electric materials has been proposed in the prior art.
In this type ~f EEPROM cell, the gate oxide of a field effect transistor (FET) is replaced with a ferro-electric material such as lead lanthium zirconate titanate (PLZT). The material is polarized by placing a voltage difference between the gate of the FET and , l0 the source. The polarization gives rise to an `~- effective space charge at the boundary between the gate oxide and channel region. This magnitude and polarity of the space charge depends on the degree of polarization of the PLZT material and direction of polaxization, respectively. In one direction of polarization, the carrier density in the channel is reduced, leading to an increased resistance between the source and drain of the FET. The resistance value is specified by the~polarizing voltage. The time to switch the polarization of the PLZT material is of the ~ 'order of nanoseconds'and the polarization may-be ~
switched l09 times without damaging the device. -Hence the above mentioned problems encountered with tunnelin~
EEPROM calls are avoided. '` '"~
- , -: Unfortunately, this type of PLZT structure is 'difficult to fabri'cate,and,':in practice, may be r programmed 'only a relatively small'number'of times. In this type of EEPROM the'electric fièld used to'deplete -the channel~region''is the'remnant elcctr'ic field': -resulting from the polar'ization of'the PLZT`layer.
.'` This'électric fiéld-is significantly léss than the ~- electric' field obtaine'd by applying a charge-to'a floating gate. Hence,''the depth of'`the'`channel region 35 - khat can be depleted in response to'this electric' field is ~igni~icantly less than that available in normal , . :., ,; ~ : ., .. . .
2~a~5 ~-EEPROM cells. Channels having small depths are difficult to fabricate.
In addition, this device suffers from the same type of material incompatibilities described above with reference to the barium titanate based resistive element. In particular, no satisfactory manner has been found to protect the channel region from the metal ions in the PLZT material. The PLZT material must be crystallized on the silicon substrate at temperatures of 500 C. At these temperatures, the lead ions diffuse into the channel region. These metal ions change the electrically properties of the channel in a manner analogous to doping the channel with metal ions to control its carr1er density. :
If a barrier such as silicon dioxide is deposited before the PLZT material to protect the channel drifting ions, the programming voltage is increased to an unacceptable value. The EEPROM is normally,programmed-by applying a voltage between the gate of the FET,~and the channel region. Systems , requiring large,,programming voltages are very expensive to fabricate. The available barrier materials are insulators with a dielectric constant significantly less,than that of the PLZ~ material., Consider the case in,which a v,oltage is,,applied-between the channel and ,gate o~the,EEPROM to polarize,the PLZT layer. Part of -~J? ,~the~y~oltage,will appearj"across,the,barri2r material and the remainder,will be-appear across the PLzTrmaterial.
~The fraction;appearing across,the PLZT layer,is, determined by the,,relative dielectric constants,of the b,arrierJmaterial.~and the PLZT m~terial., In general, ~ -,the"PLZT materials.-,have much~higher dielectric,, - constants ,than the available barrier materials. As a result, most,of the voltage appears across the barrier .
, ~ .
:: . , .. ,. , , .,. :. .-WO91/06121 2~ 05 ~cr/us~o/os523 f .
material. It has been found that the inclusion of such a'barrier increases the programming voltage to more than l00 volts.
Although the direction and magnitude of the remnant polarization o~ the PLZT material can be altered more than 109 times, the observed life-time of this type of EEPROM is less than that of conventional EEPROM cells. The short life~time is the result of a different form of ion drift. The PLZT materials include oxygen atoms which can drift in response to the voltages used to change the remnant polarization in the PLZT layer. As noted above, to alter th0 remnant polarization,'a voltage must be applied across the PLZT
layer. This is normally accomplished by applying a voltage between the channel region of the FET and the gaté electrode. The magnitude of this voltage is su~ficient to cause ions to drift. Depending upon the direction of the applied voltage differences, ions will either drift from the PLZT layer into the channel .. . . . . . .
region or from the channel region'into the PLZT layer.
When'oxygen ions drift from the PLZT layer into the ; channel r~gion, they'form a silicon dioxide layer at -``~ the interface betweén the PLZT layer and the channel 'region. As noted'above, silicon dioxide is an . .
insulator'with a low dielectric''constant. As a result, the programming voltage slowly incréases with time.
Accordingly, it''is'an object'of the present invention to provide an improved programmable non-volatiie resistive element. '' ' ~, , , ~ . . ; ,. -,, .; . -- . . . .
It is another object of the presént invéntion to provide a resistive element that can be reprogrammed more times than existing variable'resistive elements.~
'.
~ - , , : ., " : -WO91/06121 Pcr/~s9o/o5~23 ,,, , . f~' ~7~5 It is yet another object of the present invention to provide a resistive element that can be more economically fabricated than resistive ~lements based on EEPROM cells.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
summarY of the Invention The prèsent invention comprises a resistive element comprising a polarizable layer having first and second surfaces. A first contact is bonded ,to the polarizable layer adjacent to the first'surface. The first contact is an electrical conductor. The resistive element also includes a second contact bonded to the polarizable layer adjacent to the second surface~ The second contact comprises a semi-conduct~ng ma,terial. The material of the poljarizable layer and the,semiconducting,material are chosen such that ions drifting between the polarizable layer and , :. . .. ~ .. .
said second contact do not give rise to a layer having a dielectric constant substantially less than that of said first material, said layer being between the polarizable layer,and said second contact.
Brief De ori~tion of the Drawin~s Figure l(a) is a,cross-sectlonal view of a resistive element l0 according to the present inventl,n~ ,, , . J!'l''.`i'i',3 ~
. Figure l(b) is a top view o~ resistive element l0 shown in Figure l(a).
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: ,:
. :,: . .~ .
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,~, . . . .
.: `.
WO91/06121 PCI'/~ /05523 Figure 2 is a top Yiew of an alternati~e embodiment of a resistive element according to the present inve~tion.
Figure 3(a)-(e) are cross-sectional views of a wafer showing the various steps in constructing a resistive alement according to the present invention.
Figure 4 illustrates a memory cell utilizing the present invention.
Figure 5 illustrates a second-memory cell utilizing the present invention. - -l~i .. .
Figure 6 illustrates a memory cell according to the present invention in which the. bottom electrode is also a semiconductor.
Detailed Descri~tion of the Invention .
- The basic geometry of a resistive element -' according to the present invention is illustrated in Figures l(a)-(b). Figure l(a) is a cross-sectlonal view of a resistive element lO according to the present invention. Figure l(b) is a-top view of resistive element lO. Resistive-element lO includes three layers a bottom electrode 12j-a ferro-electric layer 14, and a ~semiconductor contact 16. ;Bottom electrode 12 may be constructed from any conducti~g material, or, as will be~discussed,in more detail below, it can be ~ ,; constructed ~rom a semiconductor material such as that ,~ j, used to construct semiconductor contact 16. ,Ferro-electric layer l4 is~preferably constructed from,a ferro-electric material. PLZT materials are preferred.
- ,For example, a PLZT composition consisting of 98% lead, ~,~
.~' i W091/0612l PCr/~S()0/05523 -lo-2~ lanthanum, 40% zirconium, and 60% titantium may be utilized in constructing a resistive element according to the present invention.
Semiconductor contact 16 can be constructed from any material with an appropriate carrier density in the intended operating temperature range of the device in which resistive element 10 is to be utilized provided the material will interface properly with ' 10 ferro-electric layer 14. The material utilized for semiconductor contact 16 must satisfy three requirements. First the material must provide a resistivity within the range need for the particular circuit in which resistive element 10 is to be utilized.
Second, the material must be substantially electrochemically inert with respect to the ferro-electric material utilized for ferro-electric layer 14.
As noted above, one problem with-prior art EEPROM
devices which utilize ferro-electric materials for the ; gate oxide is'the migration of'ions betwèen the channel region and the ferro-electric region. To prevent such - drift in-resistive~element 10, semiconductor~contact 16 25 '-is preferably constructed from a material which will ` not be effected by ions drifting from ferro-electric layer 14.-'If PLZT materials''are used for ferro-electric layer 14,''semiconductor'contact 16 may be : constructed from àn appropriate metal~oxide`such as the ' oxides of tin,~indium,"beryllium,'-'zinc,'cadmium, ~' nickel; etc. Since'such oxides'are-already stabilized ' against oxygen`;ions,'any:oxygen drifting from the PLZT
' ` '' material-will not result in an:insulator'being~'formed at''the;'interfa'ce of ferro-electric layer and' - semiconductor contact 16. However, it will'be' ' apparent to those skilled in the art that bromides, ' ` ' ' '' : `' '` ' :, . .
.. ~ : , .
WO91/06121 PC~/~90/0;523 ~ - ZC~7~3~0~
11-- - , `
carbides, silicides, nitrides, and sulfides may also be utilized.
Third, semiconductor contact 16 must be capable of deposition on ferro-electric layer 1~ withou~
destroying Eerro-electric 14. For example, if a PLZT
material is used for ferro-electric layer 14, the material used for semiconductor contact 16 must be depositable in a non-reducing atmosphere at a suitably low temperature.
A resistive element according to the present invention may be fabricated on a silicon wafer with conventional CMOS circuit elements. The resistive element is preferably fabricated after the CMOS
fabrication has reached the point at which the metal interconnects are to be d~posited.
Figure 3 illustrates the manner in which a resistive e]ement according to the present invention may be fabricated in conjunction with two conventional FET transistors 22 and 26. Figure 3(a)-(e) are cross-sectional views through a silicon wafer 21 at various stages in the fabrication process. Figure 3(a~ shows the wafer after the wélls gate oxide layers 25 and gate - electrodes 24 have been fabricated.
, , -, ~.
At this point, the wafer is covered with a diffusion barrièr--such as-sillcon oxide or silicon ~nitride. Bottom electrode 26 is then;deposited-using a thin glue layer to bond it to the barrier layer. A
bottom-ëlectrode comprIsing a 0.2-micron thick platinum layer-is prefèrred. ~The-glue layér~is preférably - several hundred~angstroms:of titantium.- After deposition, the bottom electrode is etched to the ~appropriate shape~as shown in Figure 3(b) using . ': .
.
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W0~1/06121 P~r/US90/05~23 .. . . .
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conventional integrated circuit fabrication methods.
Next, the ferroelectric film is deposited and etched to the appropriate shape. Conventional deposition and etching technigues such as those may be utilized. For example, Title, et al. describe a technique for etching PLZT thin films [Mark A. Title, et al., I'Reactive Ion Beam Etching o~ PLZT Electrooptic Substrates with Repeated Self-Aligned Masking", Applied lO optic.s, Vol. 25, No. 9, 1986]. Figure 3(c) shows the ferro-electric layer 27 after etching.
The semiconductor contact 28 is then deposited.
This is preferably accomplished utilizing a conventional sputtering process such as that described by David Fraser ["Sputtered Films for Display Devices", Proceedinas of the IEEE, 61, 1973]. The semiconductor contact is preferably a 200 angstrom thick layer of tin oxide. Once the semiconductor is deposited, it may be . 20 doped to.the desired carrier concentration by conventional diffusion or ion implantation techniques.
; Alternatively, the doping elements can.be included in the material that is deposited. .The semiconductor . contact is then etched to the desired geometry using . 25 conventional integrated circuit techniques. Figure 3(~) shows the devlce aft~r semiconductor.28 contact has been etched.
, .. Next, an..interlayer dielectric 31 which is .30. preferably-.a low temperature.silicon.dioxide,layer is ~: deposited. .Wells in the.interlayer dielectric 31 are ~.{ then opened.at.those locations.which are to.be electrically connected to metalization... A layer-of ~itanlum nitride.30 is deposited as.a-barrier .
bet~een.the.aluminum metalization and contact materials. The aluminum metalization is deposited in ., .
. .
WO9l/06121 PCT/~'S90/05; 3 -13- ~Z~ 5 the final step. The wafer after the deposition o~ the aluminum is shown in Figure 3(e).
Referring again to Figure 1, the resistance, R, of semiconductor contact 16 is determined by the resistivity, p, of the material used to construct semiconductor contact 16, the length, L, width, W, and thickness, T, of.semiconductor contact 16. In general, R = pL/(WT) (1) The length of semiconductor contact 16 may be increased by utilizing a serpentine confiyuration such as that shown in Figure 2 which i5 a top view of an a~ternative resistive element 18 having a semiconductor contact 19 and ferro-electric layer 15.
.
~he resistivity of semiconductor contact 16 is ; determined by the degree of polarization of ferro~
electric layer 14, the density of carriers in ; semiconductor contact 16 in the absence of polarization . of. ferro-electric layer 14, and the type of .~ semiconductor utilized for semiconductor contact 16.
~ The resistivity of:the material utilized to construct ~ 25 semiconductor contact 16 in the absence-of an electric . field will be referred to as the intrinsic resistivity . of.the.material. For example, tin oxide has a-~resistivity of approximately 0.05.ohm-cm in:.the absence : of any doping. This resistivity may be dramatically . 30 - decreased by:doping the material. For example, indium ;~ - doped time oxide may has an intrinsic resistivity of ~ about 10 4 ohm-cm... .... l . --; ., .. .,., , . ^ ... ~ - , . ..
-When ferro-electricAlayer 14 is polarized, an electric ~ield is gen~rated in sPmiconductoricontact 16. This field will either draw additional carriers ' ,, .. . ,, ., j,., :: ,. . ,., : :
Wosl/06121 PCT/~S9~/05;23 ' ' '' J ~- ~ f_ Z ~ 14-into semiconductor contact 16 or repel the existing carriers out of semiconductor contact 16, depending upon the direction of polarization and the type of semiconductor. If additional carriers are drawn into semiconductor contact 16, the resistance of semiconductor contact 16 will be decreased. If the carriers are repelled therefrom, the resistance of semiconductor contact 16 will be increased.
It should be noted that the thickness of the semiconductor contact 16 'affects the operation of the - device in two ways. First, if the thickness is too great, the electric field generated by the ferro-electric layer will not affect the carrier density far ;from the interface of the semiconductor contact and ferro-electric layer. If the resistive element is ' being operated in a depletion mode, i.e., the electric ; field is expelling carriers from semi-conductor contact ~6, then the portion of semiconductor contact far from - 20 the interface will not be depleted. As a result, the - --resistive element will behave in a manner analogous to two resistors in parallel. The first reslstor will be ;~ the depleted region near the interface and the second region will be the non-depleted region. Since the non-25 ' depleted region wilI have a resistance which is'less ~ -than-that of the depleted region, the resistance values - obtainabl2 will be limited by the resistance'of the non-depleted reyion.~ J~
.. '~ .
30- -' l ~r~; Second, if the~thickness of~the semiconductor ~; contact-is sufficiently small to avoid creating:two resistors in parallel, it may be:~shown that the ;-!~
resistivity of the semi-conductor contact is :: ~proportional to the'thickness~thereof. 'Hence, the resistance of the resistive element will no longer '~
~depend on the thickness of the semiconductor contact.
. ' ' ~', ~' ''' ' ' .
WO 91/06121 . PCI~/US90/0;523 -15- ~7vq~5 Ferro-electric layer 14 is polarized by applying a voltage between semiconductor contact 16 and bottom electrode 12. This voltage will be referred to as the programming voltage in the following discussion.
The resistivity of semiconductor contact 16 is a function of the programming voltage. However, since " ferro-electric materials exhibit hysteresis, the programming must be commenced from the same initial state of polarization. This can be accomplished by applying a voltage which saturates the ferro-electric material and then changing the voltage from the value to the desired value.
, Hysteresis effects are less critic~l in digital applications wherein the resistance is to.be set between the minimum and maximum possible values. In this case, the ferro-electric layer is polarized,such that it is pclarized to the maximum possible value, and .- 20 only the direction of the polarization is changed. In ". this case, the prior state of polarization.. will,not '.~ effect the polarization, since the device is programmed : by applying the,.saturating voltage to the ferro-. electric material... ... .-~- 25 .. - . . . .
A resistive element according to the present .invention:;can be used-~c., construct:a non-volatile .~static memoryifor;use in:computers and the-like. A
single-memory cell:in one,embodiment of such a memory 30;~-,islillustrated,in Figure 4~;at 40. Cell 40 includes a :., resisti~e elementlaccording.to the.present invention ` which is constructed.from.a-ferro-electric-layer 60, a '~ semiconductor:!contact 62,~and~,a.bottom electrode 64.
..j ..The:resistive,element.is.isolated from a,bit.line 42 by a first transistor 65 and ~rom ground by a~second ,. transistor 66. The data stored in the resistive .
,, ~: ' , , , ,, : . . : ,. ~
.
WO91/06121 PCT/US90/0~523 : 2~ 5 - -16-element is sensed by sense amplifier 44.
Cell 40 is programmed and read by applying the appropriate voltages to word-lines 46 and 48 and plate 50. To program cell 40, bit-line 42 is set to the desired value, high or low. Word-line 46 is turned on, word-line 48 is turned off. Plate 50 is then pulsed.
When bit-line 42 is low during programming, the pulse on plate 50 will polarize ferro-electric 60 such that the electric field vector is down. Hence, excess ; electrons will be held in semiconductor contact 62.
For an N-type semiconductor material such as tin oxide, this will decrease the resistivity of semiconductor contact 62. If bit-line 42 is high during programming, the ferxo-electric material will be polarized such that ist electric field vector is up. This will deplete semiconductor contact 62 of electrons. For an N-type ; semiconductor, this will result in semiconductor contact 62 being placed in a highly resistive state.
; 20 If a P-type semiconductor were utilized, the opposite states would result.
To read the cell state of cell 40 when an N-type semiconductor-is utilized, bit line 42 is charged ~ 25 to a voltage which is small compared to that used to - program cell 40. The use of a low voltage prevents *ferro-electric layer 60 from changing direction of polarization. Transistors 65-and 66 are then turned on. After a time-depending-on the capacitance of bit-30 ~ line 42 and the minimum resistance:of cell 40, sense`
- --amplifier 44 is-turned on. Sense amplifier 40 is - connected to a reference voltage which is related to the:voltage to which bit-line 42 was charged. By comparing the voltage on the discharged bit-line, the resistance of semiconductor contact 62 in cell 40 may be measured. The dif~erent possible resistance values . . :: .;
.
~.
WO91/06121 PCT/US9~)/0~;23 17~
of semiconductor contact 62 will discharge bit-line 42 at different rates. Hence, the voltage on bit-line 42 after an appropriate time has elapsed will allow the resistance of semiconductor contact 62 to be ascertained.
It should be noted that the first time cell 40 is read after being programmed, the resistance of semiconductor contact 62 may change slightly. If ~he read voltage is in a direction that changes the polarization vector of ferro-electric layer 60, the remnant polarization of some of the domains in ferro-electric layer 60 may be switched to the opposite direction thereby changing the overall remnant polarization. The fraetion of the domains wlll be small if the read voltage is small compared to the that used to program cell 40. In addition, the read voltage must be significantly less than the saturatio~ voltage of ferro-electric layer 60. ~owever, the domains in '-20 question have switched, no further switching occurs on repeated reads.
"- ' 'A ~ne'isolation transistor memory cell is shown in Figure 5 at 70. Cell 70 utilizes a resistive -25 "''''element''comprising a semiconductor contact 72, ferro- --~` electric layer 74, and bottom electrode 76.- Cell 70 is isolated from bit`line 42 by transistor 86 which is ''` ''c'ontroll'ediby word-li'ne"86. -The voltage on the bottom ` electrode'76'~is`specifi'ed by the voltage on plate 84.
''''- 'rCell 70 has the advantage of requiring only one -' -- isolation transistor.:~'''It'i`s'programmed 'in a''manner -' anaIogous'to that described'above'with re'ference to 'cell 40.~ The''data''to'be programmed is place'd on bit-35 line 42;~:;Transi'stor'86 is turned"on, and plate 84 is pulsed.
,.
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,., :: . :., WO91/06l2l PCT/US90/05~Z3 2~7~5 -18- ~''~' Cell 70 is read in an analogous manner. Bit-line 42 is precharged to a voltage which is small compared to thak used to program cell 70. Transistor 86 is turned on. After an appropriate time interval has elapsed, sense amplifier 44 is used to compare the `
voltage on bit-line 42 to a reference value.
Cell 70 differs from cell 40 in that the type of semiconductor used to construct semiconductor . contact 72 is important. Consider the case in which '' semiconductor contact 72 is an N-type semiconductor.
When the cell is programmed with a low voltage, i.e., ground, on bit-line 42, there will not be a voltage ` 15 difference across semiconductor contact 72. That is, both ends, 77 and 78, of semiconductor contact 72 will , be at the same voltage. As a result, the polarization of ferro-electric layer 60 will be uniformly in one , direction and semiconductor contact 72 will be in the ' 20 low resistant state.
i . .: . ' ; Now consider the case in which a high ; programming voltage is present on bit line 42. In this case, there will be a voltage drop across semiconductor ; 25 contact 72. End 78 will be at the high voltage and end -- 77 will be held at ground., In this case, the portion of ferro electric layer 74 under end 77 will be ; ~,polarized ln a direct'ion different from that under end , 78. End 78 will become highly,resistive when,,the the voltage switches. Hence, the voltage drop will be --~ ,concentrated at end 78. Since the voltage drop .. .. . .. . .
determines,the state of,ferro-electric layer 74, only ,,that portion of ferro-electric layer under,end,78 will ,",,~ switch,its direction of polarization. This results in 35 a non unifo~m resistance distribution across semiconductor contact 72.
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' ' ' ' i WO91/06121 PCT/US90/05523 -19- 2~
;.
In the case of an N-type semiconductor and positive programming voltages, the resistance of e~d 78 will be much higher than that of end 77; however, the : 5 resistance of semiconductor contact 72 in the state corresponding to a high programming voltage will still be much higher than that corresponding to a low ~ programming voltage. As a result, the memory device : still functions adequately. However, the difference in resistance of the high and low states is substantially reduced which decreases the performance of cell 70.
.~ . .
Now consider the case in which a P-type :~ semiconductor had been utilized for semiconductor contact 72 with the same positive voltage programming scheme.. Again, when both sides of semiconductor ~ contact 72 are held at ground during programming, the polarization on ferro-electric layer 74 is uniform and . no problems are encountéred. In this. case, the - 20 . resistance of the entire semiconductor contact 72 is uniformly.high. If a high programming voltage is . applied-at end 78, the voltage across ferro-electric layer 74 below end-78 goes high and that at end 77 remains at ground. .The high voltage at end 78 causes 25 .-~..the polarization to.switch directions at the end of : ~erro-electric layer 78 under end 78. This.lowers the resistance:of semiconductor contact 72 at end 78. As this happens, the high voltage then moves toward end 77 . ..and the.process repeats until semiconductor contact 72 -is.uniformly at:a.low resistance state. -Hence, this choice of semiconductor-material.has the same high -.-.ratio of.resistances in the high and low..programming --:. . states as does.the..two:.transistor.version shownSin Figure-4.: !'''', .''',:.j, '';,.''i `~ ,, ~ .; ' , -,, ;
While the above description of memory cells 40 - , . ~ ~ ,, ,, -, :, :. ., :, . . . .
WO91/06121 PCT/~S~()/05523 . . r'`
and 70 utilized voltages between a bit-line and ground, '';' it will be apparent to those skilled in the art that the ground connection could be replaced by a drive line. ~ :
The ability to polarization a ferro-electric layer will decrease with each rPprogramming slightly.
', Hence, the reference voltage utilized by the sense amplifiers shown in Figures 4 and 5 above will slowly ~' lO change with time. This l.imits the number of write cycles to about 101 when PLZT materials are utilized.
The number of write cycles can be increased - significantly by utilizing a memory cell in which the bottom electrode is also a semiconductor. In this case,-the resistance of the bottom electrode acts as a reference when measuring the resistance'of the top electrode.
Figure 6 illustrates a memory cell 100 utilizing a resistive element 110 in which the bottom electrode 112 is a semiconductor. Bottom electrode 112 -is connected to line 115. The top electrode 114 which 'is also a semiconductor is connected to line 116. Cell . ~100 is~isolated from the lines in question,by 25 -- transistors 117 and 118 which are controlled by the - voltage on select line 119. The state of-cell 100 can - b`e sensed by operational~amplifier 121. - - -~ o Cell~100 is programmed by placing the data on - 30 ::line 115 and the complement thereof on line 116 after -selecting cell ,100 with~a high voltage on select line - --119.- Cell lOO~is--re'ad by--precharging;both lines and then reading the voltage,output of amplifier 121 after transistors 118 and 119 ha~e been turned on for a suitable period o~ time.
,- . . , . .. ~ - - , ~ , , , . - , ,.......... , ' ~,,,' '' .: '; " .;' ;. :
WO91/06121 PCr/~;S~n/0~523 ~ ~21- 2~ 5 While the present invention has been described in terms of embodiments utilizing PLZT materials, it will be apparent to those skilled in the art that other polarizable materials may be utilized. For example, lead zirconate titanates may be utilized, as well as other fexro-electric materials.
There has been described herein a novel resistive element. Various modifications to the present invention will become apparent to those skilled ; in the art from the foregoing description and accompanying drawings. Accordingly, the present invention is to be limited solely by the scope of the following claims.
.
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other el~ctrode. The space between the floating gate and tunneling electrode is typically filled with silicon oxide. Some of the electrons become trapped in the oxide during each of the tunneling operations. As a result, a space charge which increases with each reprogramming accumulates. This space charge eventually prevents electrons from tunneling between the floating gate and thP tunneling electrode.
However, even before-this chaxge builds-up, the programming voltage needed to transfer a specified charge to the floating gate changes, making it difficult to predict the change in resistance when a ~iven programming signal is applied to the EEPROM.
As noted above, literally thousands of reprogrammings may be needed during the programming stage of setting up a neuro-network. At each reprogramming, a predictable change in the resistance of the element must occur. As noted above, the EEPROM
cell will begin to change after a few thousand reprogrammings. ~Hence, it is not always possible to program the networX be~ore the EEPROM elements wear out. -. .
.
. .
- A third problem inherent in prior art EEPROM
cells is the large.:voltages needed to cause the .,.... ........ ...ele trons-to tunnel during:programming and erasing -.operations.^ Voltages of the order.of 17 to 25 volts ~.lare:.typically.needed. :Such voltages~require isolation -30: of.the circuitry from other low voltage circuitry on .the-.same integrated-~circuit chip.: In addition,.special : circuitry f~r..generating the high -voltage.from the ; normally.available low~voltage supply musttalso be included on-the chip. ..~ 5 ~!.'' -'-35 :- .:. . ..... . . .......... - .
- Efforts to overcome these problems utllizing . . .
.. : .
-~ : . . ' , Wo~1/06121 2 ~ 5 ; PCT/~S~0/05523 ferro~electric material based materials are well known to those skilled in the art. For example, U.S. Patent 2,773,250 describes a device for storing information in which the device consists of a ferro-electric body having a semiconductor layer deposited thereon. The semiconductor layer acts as a variable resistor in an electric circuit. The resistance of the semiconductor layer was controlled by the degree of polarization of the ferro-electric body. The polarization of the ferro-ele~tric body is controlled by generatiny an electric field in the ferro-electric body. The electric fi21d was generated by providing a voltages difference across the ferro-electri~ body. This voltage difference was generated by connecting the semiconductor layer to one voltage and a second programming electrode consisting of a conductive layer which was deposited on the other side of the ferro-electric body to a second voltage.
This resistive element, however, did no~
~unction well over long periods:of time due to the materials selected. The device in-question utilized a barium titanate ferro-electric and a tellurium semiconductor. Tellurium oxidizes readily at room temperature. Hence,-an-oxide layer can form between the tellurium layer and the ferro-electric body as -oxygen atoms drift from the barium titanate into the tellurium under the in~iuence of the electric fields -- - used to-polarize the barium titanate.! Theioxide layer 30 1 has a dielectric conskant which is much less;than that of the barium titanate. Hence, as ~he oxide layer forms, the voltage difference that must be applied between the programming electrode and the semiconductor to change the polarization of the barium titanate increases. After an unacceptably small number of resistive element progamminys, the required voltaye ' , ~ ' ,,'', '' ' .;
'': ':
wos1/06121 Pcr/us9o/o55~3 '`~` 2~
becomes too large for the device to be practical.
A second type O~r EEPROM cell based on ferro-electric materials has been proposed in the prior art.
In this type ~f EEPROM cell, the gate oxide of a field effect transistor (FET) is replaced with a ferro-electric material such as lead lanthium zirconate titanate (PLZT). The material is polarized by placing a voltage difference between the gate of the FET and , l0 the source. The polarization gives rise to an `~- effective space charge at the boundary between the gate oxide and channel region. This magnitude and polarity of the space charge depends on the degree of polarization of the PLZT material and direction of polaxization, respectively. In one direction of polarization, the carrier density in the channel is reduced, leading to an increased resistance between the source and drain of the FET. The resistance value is specified by the~polarizing voltage. The time to switch the polarization of the PLZT material is of the ~ 'order of nanoseconds'and the polarization may-be ~
switched l09 times without damaging the device. -Hence the above mentioned problems encountered with tunnelin~
EEPROM calls are avoided. '` '"~
- , -: Unfortunately, this type of PLZT structure is 'difficult to fabri'cate,and,':in practice, may be r programmed 'only a relatively small'number'of times. In this type of EEPROM the'electric fièld used to'deplete -the channel~region''is the'remnant elcctr'ic field': -resulting from the polar'ization of'the PLZT`layer.
.'` This'électric fiéld-is significantly léss than the ~- electric' field obtaine'd by applying a charge-to'a floating gate. Hence,''the depth of'`the'`channel region 35 - khat can be depleted in response to'this electric' field is ~igni~icantly less than that available in normal , . :., ,; ~ : ., .. . .
2~a~5 ~-EEPROM cells. Channels having small depths are difficult to fabricate.
In addition, this device suffers from the same type of material incompatibilities described above with reference to the barium titanate based resistive element. In particular, no satisfactory manner has been found to protect the channel region from the metal ions in the PLZT material. The PLZT material must be crystallized on the silicon substrate at temperatures of 500 C. At these temperatures, the lead ions diffuse into the channel region. These metal ions change the electrically properties of the channel in a manner analogous to doping the channel with metal ions to control its carr1er density. :
If a barrier such as silicon dioxide is deposited before the PLZT material to protect the channel drifting ions, the programming voltage is increased to an unacceptable value. The EEPROM is normally,programmed-by applying a voltage between the gate of the FET,~and the channel region. Systems , requiring large,,programming voltages are very expensive to fabricate. The available barrier materials are insulators with a dielectric constant significantly less,than that of the PLZ~ material., Consider the case in,which a v,oltage is,,applied-between the channel and ,gate o~the,EEPROM to polarize,the PLZT layer. Part of -~J? ,~the~y~oltage,will appearj"across,the,barri2r material and the remainder,will be-appear across the PLzTrmaterial.
~The fraction;appearing across,the PLZT layer,is, determined by the,,relative dielectric constants,of the b,arrierJmaterial.~and the PLZT m~terial., In general, ~ -,the"PLZT materials.-,have much~higher dielectric,, - constants ,than the available barrier materials. As a result, most,of the voltage appears across the barrier .
, ~ .
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material. It has been found that the inclusion of such a'barrier increases the programming voltage to more than l00 volts.
Although the direction and magnitude of the remnant polarization o~ the PLZT material can be altered more than 109 times, the observed life-time of this type of EEPROM is less than that of conventional EEPROM cells. The short life~time is the result of a different form of ion drift. The PLZT materials include oxygen atoms which can drift in response to the voltages used to change the remnant polarization in the PLZT layer. As noted above, to alter th0 remnant polarization,'a voltage must be applied across the PLZT
layer. This is normally accomplished by applying a voltage between the channel region of the FET and the gaté electrode. The magnitude of this voltage is su~ficient to cause ions to drift. Depending upon the direction of the applied voltage differences, ions will either drift from the PLZT layer into the channel .. . . . . . .
region or from the channel region'into the PLZT layer.
When'oxygen ions drift from the PLZT layer into the ; channel r~gion, they'form a silicon dioxide layer at -``~ the interface betweén the PLZT layer and the channel 'region. As noted'above, silicon dioxide is an . .
insulator'with a low dielectric''constant. As a result, the programming voltage slowly incréases with time.
Accordingly, it''is'an object'of the present invention to provide an improved programmable non-volatiie resistive element. '' ' ~, , , ~ . . ; ,. -,, .; . -- . . . .
It is another object of the presént invéntion to provide a resistive element that can be reprogrammed more times than existing variable'resistive elements.~
'.
~ - , , : ., " : -WO91/06121 Pcr/~s9o/o5~23 ,,, , . f~' ~7~5 It is yet another object of the present invention to provide a resistive element that can be more economically fabricated than resistive ~lements based on EEPROM cells.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
summarY of the Invention The prèsent invention comprises a resistive element comprising a polarizable layer having first and second surfaces. A first contact is bonded ,to the polarizable layer adjacent to the first'surface. The first contact is an electrical conductor. The resistive element also includes a second contact bonded to the polarizable layer adjacent to the second surface~ The second contact comprises a semi-conduct~ng ma,terial. The material of the poljarizable layer and the,semiconducting,material are chosen such that ions drifting between the polarizable layer and , :. . .. ~ .. .
said second contact do not give rise to a layer having a dielectric constant substantially less than that of said first material, said layer being between the polarizable layer,and said second contact.
Brief De ori~tion of the Drawin~s Figure l(a) is a,cross-sectlonal view of a resistive element l0 according to the present inventl,n~ ,, , . J!'l''.`i'i',3 ~
. Figure l(b) is a top view o~ resistive element l0 shown in Figure l(a).
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WO91/06121 PCI'/~ /05523 Figure 2 is a top Yiew of an alternati~e embodiment of a resistive element according to the present inve~tion.
Figure 3(a)-(e) are cross-sectional views of a wafer showing the various steps in constructing a resistive alement according to the present invention.
Figure 4 illustrates a memory cell utilizing the present invention.
Figure 5 illustrates a second-memory cell utilizing the present invention. - -l~i .. .
Figure 6 illustrates a memory cell according to the present invention in which the. bottom electrode is also a semiconductor.
Detailed Descri~tion of the Invention .
- The basic geometry of a resistive element -' according to the present invention is illustrated in Figures l(a)-(b). Figure l(a) is a cross-sectlonal view of a resistive element lO according to the present invention. Figure l(b) is a-top view of resistive element lO. Resistive-element lO includes three layers a bottom electrode 12j-a ferro-electric layer 14, and a ~semiconductor contact 16. ;Bottom electrode 12 may be constructed from any conducti~g material, or, as will be~discussed,in more detail below, it can be ~ ,; constructed ~rom a semiconductor material such as that ,~ j, used to construct semiconductor contact 16. ,Ferro-electric layer l4 is~preferably constructed from,a ferro-electric material. PLZT materials are preferred.
- ,For example, a PLZT composition consisting of 98% lead, ~,~
.~' i W091/0612l PCr/~S()0/05523 -lo-2~ lanthanum, 40% zirconium, and 60% titantium may be utilized in constructing a resistive element according to the present invention.
Semiconductor contact 16 can be constructed from any material with an appropriate carrier density in the intended operating temperature range of the device in which resistive element 10 is to be utilized provided the material will interface properly with ' 10 ferro-electric layer 14. The material utilized for semiconductor contact 16 must satisfy three requirements. First the material must provide a resistivity within the range need for the particular circuit in which resistive element 10 is to be utilized.
Second, the material must be substantially electrochemically inert with respect to the ferro-electric material utilized for ferro-electric layer 14.
As noted above, one problem with-prior art EEPROM
devices which utilize ferro-electric materials for the ; gate oxide is'the migration of'ions betwèen the channel region and the ferro-electric region. To prevent such - drift in-resistive~element 10, semiconductor~contact 16 25 '-is preferably constructed from a material which will ` not be effected by ions drifting from ferro-electric layer 14.-'If PLZT materials''are used for ferro-electric layer 14,''semiconductor'contact 16 may be : constructed from àn appropriate metal~oxide`such as the ' oxides of tin,~indium,"beryllium,'-'zinc,'cadmium, ~' nickel; etc. Since'such oxides'are-already stabilized ' against oxygen`;ions,'any:oxygen drifting from the PLZT
' ` '' material-will not result in an:insulator'being~'formed at''the;'interfa'ce of ferro-electric layer and' - semiconductor contact 16. However, it will'be' ' apparent to those skilled in the art that bromides, ' ` ' ' '' : `' '` ' :, . .
.. ~ : , .
WO91/06121 PC~/~90/0;523 ~ - ZC~7~3~0~
11-- - , `
carbides, silicides, nitrides, and sulfides may also be utilized.
Third, semiconductor contact 16 must be capable of deposition on ferro-electric layer 1~ withou~
destroying Eerro-electric 14. For example, if a PLZT
material is used for ferro-electric layer 14, the material used for semiconductor contact 16 must be depositable in a non-reducing atmosphere at a suitably low temperature.
A resistive element according to the present invention may be fabricated on a silicon wafer with conventional CMOS circuit elements. The resistive element is preferably fabricated after the CMOS
fabrication has reached the point at which the metal interconnects are to be d~posited.
Figure 3 illustrates the manner in which a resistive e]ement according to the present invention may be fabricated in conjunction with two conventional FET transistors 22 and 26. Figure 3(a)-(e) are cross-sectional views through a silicon wafer 21 at various stages in the fabrication process. Figure 3(a~ shows the wafer after the wélls gate oxide layers 25 and gate - electrodes 24 have been fabricated.
, , -, ~.
At this point, the wafer is covered with a diffusion barrièr--such as-sillcon oxide or silicon ~nitride. Bottom electrode 26 is then;deposited-using a thin glue layer to bond it to the barrier layer. A
bottom-ëlectrode comprIsing a 0.2-micron thick platinum layer-is prefèrred. ~The-glue layér~is preférably - several hundred~angstroms:of titantium.- After deposition, the bottom electrode is etched to the ~appropriate shape~as shown in Figure 3(b) using . ': .
.
.. . .
:,: . . ~ :: . . . :
.- . .. , :.
W0~1/06121 P~r/US90/05~23 .. . . .
2~ 12- ~`
conventional integrated circuit fabrication methods.
Next, the ferroelectric film is deposited and etched to the appropriate shape. Conventional deposition and etching technigues such as those may be utilized. For example, Title, et al. describe a technique for etching PLZT thin films [Mark A. Title, et al., I'Reactive Ion Beam Etching o~ PLZT Electrooptic Substrates with Repeated Self-Aligned Masking", Applied lO optic.s, Vol. 25, No. 9, 1986]. Figure 3(c) shows the ferro-electric layer 27 after etching.
The semiconductor contact 28 is then deposited.
This is preferably accomplished utilizing a conventional sputtering process such as that described by David Fraser ["Sputtered Films for Display Devices", Proceedinas of the IEEE, 61, 1973]. The semiconductor contact is preferably a 200 angstrom thick layer of tin oxide. Once the semiconductor is deposited, it may be . 20 doped to.the desired carrier concentration by conventional diffusion or ion implantation techniques.
; Alternatively, the doping elements can.be included in the material that is deposited. .The semiconductor . contact is then etched to the desired geometry using . 25 conventional integrated circuit techniques. Figure 3(~) shows the devlce aft~r semiconductor.28 contact has been etched.
, .. Next, an..interlayer dielectric 31 which is .30. preferably-.a low temperature.silicon.dioxide,layer is ~: deposited. .Wells in the.interlayer dielectric 31 are ~.{ then opened.at.those locations.which are to.be electrically connected to metalization... A layer-of ~itanlum nitride.30 is deposited as.a-barrier .
bet~een.the.aluminum metalization and contact materials. The aluminum metalization is deposited in ., .
. .
WO9l/06121 PCT/~'S90/05; 3 -13- ~Z~ 5 the final step. The wafer after the deposition o~ the aluminum is shown in Figure 3(e).
Referring again to Figure 1, the resistance, R, of semiconductor contact 16 is determined by the resistivity, p, of the material used to construct semiconductor contact 16, the length, L, width, W, and thickness, T, of.semiconductor contact 16. In general, R = pL/(WT) (1) The length of semiconductor contact 16 may be increased by utilizing a serpentine confiyuration such as that shown in Figure 2 which i5 a top view of an a~ternative resistive element 18 having a semiconductor contact 19 and ferro-electric layer 15.
.
~he resistivity of semiconductor contact 16 is ; determined by the degree of polarization of ferro~
electric layer 14, the density of carriers in ; semiconductor contact 16 in the absence of polarization . of. ferro-electric layer 14, and the type of .~ semiconductor utilized for semiconductor contact 16.
~ The resistivity of:the material utilized to construct ~ 25 semiconductor contact 16 in the absence-of an electric . field will be referred to as the intrinsic resistivity . of.the.material. For example, tin oxide has a-~resistivity of approximately 0.05.ohm-cm in:.the absence : of any doping. This resistivity may be dramatically . 30 - decreased by:doping the material. For example, indium ;~ - doped time oxide may has an intrinsic resistivity of ~ about 10 4 ohm-cm... .... l . --; ., .. .,., , . ^ ... ~ - , . ..
-When ferro-electricAlayer 14 is polarized, an electric ~ield is gen~rated in sPmiconductoricontact 16. This field will either draw additional carriers ' ,, .. . ,, ., j,., :: ,. . ,., : :
Wosl/06121 PCT/~S9~/05;23 ' ' '' J ~- ~ f_ Z ~ 14-into semiconductor contact 16 or repel the existing carriers out of semiconductor contact 16, depending upon the direction of polarization and the type of semiconductor. If additional carriers are drawn into semiconductor contact 16, the resistance of semiconductor contact 16 will be decreased. If the carriers are repelled therefrom, the resistance of semiconductor contact 16 will be increased.
It should be noted that the thickness of the semiconductor contact 16 'affects the operation of the - device in two ways. First, if the thickness is too great, the electric field generated by the ferro-electric layer will not affect the carrier density far ;from the interface of the semiconductor contact and ferro-electric layer. If the resistive element is ' being operated in a depletion mode, i.e., the electric ; field is expelling carriers from semi-conductor contact ~6, then the portion of semiconductor contact far from - 20 the interface will not be depleted. As a result, the - --resistive element will behave in a manner analogous to two resistors in parallel. The first reslstor will be ;~ the depleted region near the interface and the second region will be the non-depleted region. Since the non-25 ' depleted region wilI have a resistance which is'less ~ -than-that of the depleted region, the resistance values - obtainabl2 will be limited by the resistance'of the non-depleted reyion.~ J~
.. '~ .
30- -' l ~r~; Second, if the~thickness of~the semiconductor ~; contact-is sufficiently small to avoid creating:two resistors in parallel, it may be:~shown that the ;-!~
resistivity of the semi-conductor contact is :: ~proportional to the'thickness~thereof. 'Hence, the resistance of the resistive element will no longer '~
~depend on the thickness of the semiconductor contact.
. ' ' ~', ~' ''' ' ' .
WO 91/06121 . PCI~/US90/0;523 -15- ~7vq~5 Ferro-electric layer 14 is polarized by applying a voltage between semiconductor contact 16 and bottom electrode 12. This voltage will be referred to as the programming voltage in the following discussion.
The resistivity of semiconductor contact 16 is a function of the programming voltage. However, since " ferro-electric materials exhibit hysteresis, the programming must be commenced from the same initial state of polarization. This can be accomplished by applying a voltage which saturates the ferro-electric material and then changing the voltage from the value to the desired value.
, Hysteresis effects are less critic~l in digital applications wherein the resistance is to.be set between the minimum and maximum possible values. In this case, the ferro-electric layer is polarized,such that it is pclarized to the maximum possible value, and .- 20 only the direction of the polarization is changed. In ". this case, the prior state of polarization.. will,not '.~ effect the polarization, since the device is programmed : by applying the,.saturating voltage to the ferro-. electric material... ... .-~- 25 .. - . . . .
A resistive element according to the present .invention:;can be used-~c., construct:a non-volatile .~static memoryifor;use in:computers and the-like. A
single-memory cell:in one,embodiment of such a memory 30;~-,islillustrated,in Figure 4~;at 40. Cell 40 includes a :., resisti~e elementlaccording.to the.present invention ` which is constructed.from.a-ferro-electric-layer 60, a '~ semiconductor:!contact 62,~and~,a.bottom electrode 64.
..j ..The:resistive,element.is.isolated from a,bit.line 42 by a first transistor 65 and ~rom ground by a~second ,. transistor 66. The data stored in the resistive .
,, ~: ' , , , ,, : . . : ,. ~
.
WO91/06121 PCT/US90/0~523 : 2~ 5 - -16-element is sensed by sense amplifier 44.
Cell 40 is programmed and read by applying the appropriate voltages to word-lines 46 and 48 and plate 50. To program cell 40, bit-line 42 is set to the desired value, high or low. Word-line 46 is turned on, word-line 48 is turned off. Plate 50 is then pulsed.
When bit-line 42 is low during programming, the pulse on plate 50 will polarize ferro-electric 60 such that the electric field vector is down. Hence, excess ; electrons will be held in semiconductor contact 62.
For an N-type semiconductor material such as tin oxide, this will decrease the resistivity of semiconductor contact 62. If bit-line 42 is high during programming, the ferxo-electric material will be polarized such that ist electric field vector is up. This will deplete semiconductor contact 62 of electrons. For an N-type ; semiconductor, this will result in semiconductor contact 62 being placed in a highly resistive state.
; 20 If a P-type semiconductor were utilized, the opposite states would result.
To read the cell state of cell 40 when an N-type semiconductor-is utilized, bit line 42 is charged ~ 25 to a voltage which is small compared to that used to - program cell 40. The use of a low voltage prevents *ferro-electric layer 60 from changing direction of polarization. Transistors 65-and 66 are then turned on. After a time-depending-on the capacitance of bit-30 ~ line 42 and the minimum resistance:of cell 40, sense`
- --amplifier 44 is-turned on. Sense amplifier 40 is - connected to a reference voltage which is related to the:voltage to which bit-line 42 was charged. By comparing the voltage on the discharged bit-line, the resistance of semiconductor contact 62 in cell 40 may be measured. The dif~erent possible resistance values . . :: .;
.
~.
WO91/06121 PCT/US9~)/0~;23 17~
of semiconductor contact 62 will discharge bit-line 42 at different rates. Hence, the voltage on bit-line 42 after an appropriate time has elapsed will allow the resistance of semiconductor contact 62 to be ascertained.
It should be noted that the first time cell 40 is read after being programmed, the resistance of semiconductor contact 62 may change slightly. If ~he read voltage is in a direction that changes the polarization vector of ferro-electric layer 60, the remnant polarization of some of the domains in ferro-electric layer 60 may be switched to the opposite direction thereby changing the overall remnant polarization. The fraetion of the domains wlll be small if the read voltage is small compared to the that used to program cell 40. In addition, the read voltage must be significantly less than the saturatio~ voltage of ferro-electric layer 60. ~owever, the domains in '-20 question have switched, no further switching occurs on repeated reads.
"- ' 'A ~ne'isolation transistor memory cell is shown in Figure 5 at 70. Cell 70 utilizes a resistive -25 "''''element''comprising a semiconductor contact 72, ferro- --~` electric layer 74, and bottom electrode 76.- Cell 70 is isolated from bit`line 42 by transistor 86 which is ''` ''c'ontroll'ediby word-li'ne"86. -The voltage on the bottom ` electrode'76'~is`specifi'ed by the voltage on plate 84.
''''- 'rCell 70 has the advantage of requiring only one -' -- isolation transistor.:~'''It'i`s'programmed 'in a''manner -' anaIogous'to that described'above'with re'ference to 'cell 40.~ The''data''to'be programmed is place'd on bit-35 line 42;~:;Transi'stor'86 is turned"on, and plate 84 is pulsed.
,.
,.
;:
.. . ..
,., :: . :., WO91/06l2l PCT/US90/05~Z3 2~7~5 -18- ~''~' Cell 70 is read in an analogous manner. Bit-line 42 is precharged to a voltage which is small compared to thak used to program cell 70. Transistor 86 is turned on. After an appropriate time interval has elapsed, sense amplifier 44 is used to compare the `
voltage on bit-line 42 to a reference value.
Cell 70 differs from cell 40 in that the type of semiconductor used to construct semiconductor . contact 72 is important. Consider the case in which '' semiconductor contact 72 is an N-type semiconductor.
When the cell is programmed with a low voltage, i.e., ground, on bit-line 42, there will not be a voltage ` 15 difference across semiconductor contact 72. That is, both ends, 77 and 78, of semiconductor contact 72 will , be at the same voltage. As a result, the polarization of ferro-electric layer 60 will be uniformly in one , direction and semiconductor contact 72 will be in the ' 20 low resistant state.
i . .: . ' ; Now consider the case in which a high ; programming voltage is present on bit line 42. In this case, there will be a voltage drop across semiconductor ; 25 contact 72. End 78 will be at the high voltage and end -- 77 will be held at ground., In this case, the portion of ferro electric layer 74 under end 77 will be ; ~,polarized ln a direct'ion different from that under end , 78. End 78 will become highly,resistive when,,the the voltage switches. Hence, the voltage drop will be --~ ,concentrated at end 78. Since the voltage drop .. .. . .. . .
determines,the state of,ferro-electric layer 74, only ,,that portion of ferro-electric layer under,end,78 will ,",,~ switch,its direction of polarization. This results in 35 a non unifo~m resistance distribution across semiconductor contact 72.
, ~ , .
: , . . . . ...
, ~ , ..
' ' ' ' i WO91/06121 PCT/US90/05523 -19- 2~
;.
In the case of an N-type semiconductor and positive programming voltages, the resistance of e~d 78 will be much higher than that of end 77; however, the : 5 resistance of semiconductor contact 72 in the state corresponding to a high programming voltage will still be much higher than that corresponding to a low ~ programming voltage. As a result, the memory device : still functions adequately. However, the difference in resistance of the high and low states is substantially reduced which decreases the performance of cell 70.
.~ . .
Now consider the case in which a P-type :~ semiconductor had been utilized for semiconductor contact 72 with the same positive voltage programming scheme.. Again, when both sides of semiconductor ~ contact 72 are held at ground during programming, the polarization on ferro-electric layer 74 is uniform and . no problems are encountéred. In this. case, the - 20 . resistance of the entire semiconductor contact 72 is uniformly.high. If a high programming voltage is . applied-at end 78, the voltage across ferro-electric layer 74 below end-78 goes high and that at end 77 remains at ground. .The high voltage at end 78 causes 25 .-~..the polarization to.switch directions at the end of : ~erro-electric layer 78 under end 78. This.lowers the resistance:of semiconductor contact 72 at end 78. As this happens, the high voltage then moves toward end 77 . ..and the.process repeats until semiconductor contact 72 -is.uniformly at:a.low resistance state. -Hence, this choice of semiconductor-material.has the same high -.-.ratio of.resistances in the high and low..programming --:. . states as does.the..two:.transistor.version shownSin Figure-4.: !'''', .''',:.j, '';,.''i `~ ,, ~ .; ' , -,, ;
While the above description of memory cells 40 - , . ~ ~ ,, ,, -, :, :. ., :, . . . .
WO91/06121 PCT/~S~()/05523 . . r'`
and 70 utilized voltages between a bit-line and ground, '';' it will be apparent to those skilled in the art that the ground connection could be replaced by a drive line. ~ :
The ability to polarization a ferro-electric layer will decrease with each rPprogramming slightly.
', Hence, the reference voltage utilized by the sense amplifiers shown in Figures 4 and 5 above will slowly ~' lO change with time. This l.imits the number of write cycles to about 101 when PLZT materials are utilized.
The number of write cycles can be increased - significantly by utilizing a memory cell in which the bottom electrode is also a semiconductor. In this case,-the resistance of the bottom electrode acts as a reference when measuring the resistance'of the top electrode.
Figure 6 illustrates a memory cell 100 utilizing a resistive element 110 in which the bottom electrode 112 is a semiconductor. Bottom electrode 112 -is connected to line 115. The top electrode 114 which 'is also a semiconductor is connected to line 116. Cell . ~100 is~isolated from the lines in question,by 25 -- transistors 117 and 118 which are controlled by the - voltage on select line 119. The state of-cell 100 can - b`e sensed by operational~amplifier 121. - - -~ o Cell~100 is programmed by placing the data on - 30 ::line 115 and the complement thereof on line 116 after -selecting cell ,100 with~a high voltage on select line - --119.- Cell lOO~is--re'ad by--precharging;both lines and then reading the voltage,output of amplifier 121 after transistors 118 and 119 ha~e been turned on for a suitable period o~ time.
,- . . , . .. ~ - - , ~ , , , . - , ,.......... , ' ~,,,' '' .: '; " .;' ;. :
WO91/06121 PCr/~;S~n/0~523 ~ ~21- 2~ 5 While the present invention has been described in terms of embodiments utilizing PLZT materials, it will be apparent to those skilled in the art that other polarizable materials may be utilized. For example, lead zirconate titanates may be utilized, as well as other fexro-electric materials.
There has been described herein a novel resistive element. Various modifications to the present invention will become apparent to those skilled ; in the art from the foregoing description and accompanying drawings. Accordingly, the present invention is to be limited solely by the scope of the following claims.
.
- - - , , ,., , , . - . -: .
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''.' ' . , '~
Claims (10)
[received by the International Bureau on 4 April 1991 (04.04.91), original claims 1 and 7 amended; other claims unchanged (4 pages)]
1. A resisitive element comprising: a polarizable layer having first and second surfaces comprising a first material; a first contact bonded to said polarizable layer adjacent to said first surface said first contact being an electrical conductor; and a second contact bonded to said polarizable layer adjacent to said second surface, said second contact comprising a semiconducting material which is doped such that the resistance of said second contact changes in response to a change in the polarizaiton of said polarizable layer, said second contact further comprising first and second electrical connections disposed on said second contact such that the resistance of said second contact can be determined by connecting an electrical circuit between said first and second electrical connections, wherein first material and said semiconducting material are chosen such that ions drifting between said polarizable layer and said second contact do not give rise to a layer between said polarizable layer and said second contact having a dielectric constant substantially less than that of said first material.
2. The resistive element of Claim 1 wherein said first material comprises a lead zirconate titanate and said semiconducting material comprises an oxide, bromide, carbide, nitride, or sulfide of an element.
3. The resistive element of Claim 2 wherein said element is chosen from the group comprising tin, indium, beryllium, zinc, cadmium, and nickel.
4. The resistive element of Claim 1 wherein said first material comprises a lead lanthium zirconate titanate and said semiconducting material comprises an oxide, bromide, carbide, nitride, or sulfide of an element.
5. The resistive element of Claim 2 wherein said element is chosen from the group comprising tin, indium, beryllium, zinc, cadmium, and nickel.
6. The resistive element of Claim 1 wherein said first contact comprises a semiconductor.
7. A resisitive element comprising: a polarizable layer having first and second surfaces comprising a first material;a first contact bonded to said polarizable layer adjacent to said first surface, said first contact comprising a semiconducting material which is doped such that the resistance of said first contact changes in response to a change in the polarization of said polarizable layer; and a second contact bonded to said polarizable layer adjacent to said second surface, said second contact comprising a semiconducting material which is doped such that the resistance of said second contact changes in response to a change in the polarizaiton of said polarizable layer, said second contact further comprising first and second electrical connections disposed on said second contact such that the resistance of said second contact can be determined by connecting an electrical circuit between said first and second electrical connections wherein first material and said semiconducting material are chosen such that ions drifting between said polarizable layer and said second contact do not give rise to a layer between said polarizable layer and said second contact having a dielectric constant substantially less than that of said first material.
8. A computer memory cell comprising: a resistive element comprising: a polarizable layer having first and second surfaces comprising a first material; a first contact bonded to said polarizable layer adjacent to said first surface said first contact being an electrical conductor; and a second contact bonded to said polarizable layer adjacent to said second surface, said second contact comprising a semiconducting material, said second contact including first and second electrical connections spaced apart thereon, wherein said first material and said semiconducting material are chosen such that ions drifting between said polarizable layer and said second contact do not give rise to a layer having a dielectric constant substantially less than that of said first material, said layer being between said polarizable layer and said second contact; first connecting means for selectively connecting said first electrical connection of said resistive element to a bit line comprising a first conductor; second connecting means for connecting said second electrical connection of said resistive element to a ground line comprising a second conductor and third connecting means for connecting said first contact of said resistive element to a plate line comprising a third conductor.
9. The memory cell of Claim 8 wherein said second connecting means further comprises means for selectively isolating said second electrical contact from said ground line.
10. A computer memory cell comprising: a resistive element comprising: a polarizable layer having first and second surfaces comprising a first material; a first contact bonded to said polarizable layer adjacent to said first surface said first contact being a semiconductor and having first and second electrical connections spared apart thereon, said second electrical connection being connected to a ground line; and a second contact bonded to said polarizable layer adjacent to said second surface, said second contact comprising a semiconducting material, said second contact including first and second electrical connections spaced apart thereon, said second electrical connection being connected to a ground line; means for selectively connecting said first electrical connection of said first contact to a first bit line; and means for selectively connecting said first electrical connection of said second contact to a second bit line.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US424,809 | 1989-10-20 | ||
| US07/424,809 US5070385A (en) | 1989-10-20 | 1989-10-20 | Ferroelectric non-volatile variable resistive element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2070405A1 true CA2070405A1 (en) | 1991-04-21 |
Family
ID=23683960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002070405A Abandoned CA2070405A1 (en) | 1989-10-20 | 1990-09-27 | Ferro-electric non-volatile variable resistive element |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US5070385A (en) |
| EP (1) | EP0496764A4 (en) |
| JP (1) | JP2966088B2 (en) |
| KR (1) | KR100194915B1 (en) |
| AU (1) | AU641604B2 (en) |
| CA (1) | CA2070405A1 (en) |
| WO (1) | WO1991006121A1 (en) |
Families Citing this family (57)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU641205B2 (en) * | 1990-02-09 | 1993-09-16 | Raytheon Company | Ferroelectric memory structure |
| KR960006880B1 (en) * | 1990-05-24 | 1996-05-23 | 가부시키가이샤 도시바 | Semiconductor memory device |
| US5262983A (en) * | 1990-12-19 | 1993-11-16 | The Charles Stark Draper Laboratories | Ferroelectric space charge capacitor analog memory |
| US5309390A (en) * | 1990-12-19 | 1994-05-03 | The Charles Stark Draper Laboratory, Inc. | Ferroelectric space charge capacitor memory |
| US5699035A (en) * | 1991-12-13 | 1997-12-16 | Symetrix Corporation | ZnO thin-film varistors and method of making the same |
| US5926412A (en) * | 1992-02-09 | 1999-07-20 | Raytheon Company | Ferroelectric memory structure |
| JPH0621531A (en) * | 1992-07-01 | 1994-01-28 | Rohm Co Ltd | Neuro element |
| JPH0731705B2 (en) * | 1992-08-24 | 1995-04-10 | 東京工業大学長 | Self-learning multiply-accumulate operation circuit element and circuit |
| US5371699A (en) * | 1992-11-17 | 1994-12-06 | Ramtron International Corporation | Non-volatile ferroelectric memory with folded bit lines and method of making the same |
| USH1543H (en) * | 1993-02-01 | 1996-06-04 | The United States Of America As Represented By The Secretary Of The Army | Ferroelectric/silicide/silicon multilayer and method of making the multilayer |
| US5414653A (en) * | 1993-10-06 | 1995-05-09 | Sharp Kabushiki Kaisha | Non-volatile random access memory having a high load device |
| US5453325A (en) * | 1993-12-09 | 1995-09-26 | Eastman Kodak Company | Nonlinear optical waveguide multilayer structure |
| US5840620A (en) * | 1994-06-15 | 1998-11-24 | Seager; Carleton H. | Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures |
| JPH0963282A (en) * | 1995-08-23 | 1997-03-07 | Sharp Corp | Ferroelectric semiconductor memory element, and storage device and its accessing method |
| KR100326586B1 (en) * | 1995-09-21 | 2002-07-22 | 삼성전자 주식회사 | Method for preventing polarization inversion phenomenon of ferroelectric capacitor |
| US5789775A (en) * | 1996-01-26 | 1998-08-04 | Radiant Technologies | High density memory and double word ferroelectric memory cell for constructing the same |
| US6225655B1 (en) | 1996-10-25 | 2001-05-01 | Texas Instruments Incorporated | Ferroelectric transistors using thin film semiconductor gate electrodes |
| WO1998029902A1 (en) * | 1996-12-27 | 1998-07-09 | Radiant Technologies, Inc. | Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures |
| US5936880A (en) * | 1997-11-13 | 1999-08-10 | Vlsi Technology, Inc. | Bi-layer programmable resistor memory |
| US6205048B1 (en) | 1997-12-31 | 2001-03-20 | Samsung Electronics Co., Ltd. | Single transistor cell, method for manufacturing the same, memory circuit composed of single transistor cells, and method for driving the same |
| KR100261221B1 (en) | 1997-12-31 | 2000-07-01 | 윤종용 | Single transistor unit cell, method for manufacturing thereof,memory circuit constructed the aboved cell and method for driving memory circuit |
| US6548843B2 (en) * | 1998-11-12 | 2003-04-15 | International Business Machines Corporation | Ferroelectric storage read-write memory |
| US6163482A (en) * | 1999-08-19 | 2000-12-19 | Worldwide Semiconductor Manufacturing Corporation | One transistor EEPROM cell using ferro-electric spacer |
| US6333202B1 (en) * | 1999-08-26 | 2001-12-25 | International Business Machines Corporation | Flip FERAM cell and method to form same |
| DE10031947B4 (en) * | 2000-06-30 | 2006-06-14 | Infineon Technologies Ag | Circuit arrangement for balancing different voltages on cable runs in integrated semiconductor circuits |
| JP2004519864A (en) * | 2000-08-24 | 2004-07-02 | コバ・テクノロジーズ・インコーポレイテッド | Single-transistor rare-earth manganite ferroelectric nonvolatile memory cell |
| US6574131B1 (en) | 2000-08-31 | 2003-06-03 | Micron Technology, Inc. | Depletion mode ferroelectric memory device and method of writing to and reading from the same |
| US6587365B1 (en) * | 2000-08-31 | 2003-07-01 | Micron Technology, Inc. | Array architecture for depletion mode ferroelectric memory devices |
| US6515889B1 (en) * | 2000-08-31 | 2003-02-04 | Micron Technology, Inc. | Junction-isolated depletion mode ferroelectric memory |
| US6366489B1 (en) | 2000-08-31 | 2002-04-02 | Micron Technology, Inc. | Bi-state ferroelectric memory devices, uses and operation |
| US20020164850A1 (en) | 2001-03-02 | 2002-11-07 | Gnadinger Alfred P. | Single transistor rare earth manganite ferroelectric nonvolatile memory cell |
| US6953730B2 (en) | 2001-12-20 | 2005-10-11 | Micron Technology, Inc. | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics |
| US7589029B2 (en) | 2002-05-02 | 2009-09-15 | Micron Technology, Inc. | Atomic layer deposition and conversion |
| US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
| US7066088B2 (en) * | 2002-07-31 | 2006-06-27 | Day International, Inc. | Variable cut-off offset press system and method of operation |
| US6825517B2 (en) * | 2002-08-28 | 2004-11-30 | Cova Technologies, Inc. | Ferroelectric transistor with enhanced data retention |
| US6714435B1 (en) | 2002-09-19 | 2004-03-30 | Cova Technologies, Inc. | Ferroelectric transistor for storing two data bits |
| US6888736B2 (en) | 2002-09-19 | 2005-05-03 | Cova Technologies, Inc. | Ferroelectric transistor for storing two data bits |
| US7101813B2 (en) | 2002-12-04 | 2006-09-05 | Micron Technology Inc. | Atomic layer deposited Zr-Sn-Ti-O films |
| JP2004185755A (en) * | 2002-12-05 | 2004-07-02 | Sharp Corp | Nonvolatile semiconductor storage device |
| US6819583B2 (en) * | 2003-01-15 | 2004-11-16 | Sharp Laboratories Of America, Inc. | Ferroelectric resistor non-volatile memory array |
| JP4167513B2 (en) * | 2003-03-06 | 2008-10-15 | シャープ株式会社 | Nonvolatile semiconductor memory device |
| US7304880B2 (en) | 2003-05-08 | 2007-12-04 | Matsushita Electric Industrial Co., Ltd. | Electric switch and memory device using the same |
| JP2005183619A (en) * | 2003-12-18 | 2005-07-07 | Canon Inc | Non-volatile memory device |
| US7494939B2 (en) | 2004-08-31 | 2009-02-24 | Micron Technology, Inc. | Methods for forming a lanthanum-metal oxide dielectric layer |
| US7588988B2 (en) | 2004-08-31 | 2009-09-15 | Micron Technology, Inc. | Method of forming apparatus having oxide films formed using atomic layer deposition |
| JP4375560B2 (en) * | 2004-12-07 | 2009-12-02 | セイコーエプソン株式会社 | Method for manufacturing transistor-type ferroelectric memory |
| US7560395B2 (en) | 2005-01-05 | 2009-07-14 | Micron Technology, Inc. | Atomic layer deposited hafnium tantalum oxide dielectrics |
| KR100695139B1 (en) * | 2005-02-07 | 2007-03-14 | 삼성전자주식회사 | Ferroelectric recording medium, and writing method of the same |
| US7662729B2 (en) | 2005-04-28 | 2010-02-16 | Micron Technology, Inc. | Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer |
| US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
| US7575978B2 (en) | 2005-08-04 | 2009-08-18 | Micron Technology, Inc. | Method for making conductive nanoparticle charge storage element |
| US7989290B2 (en) | 2005-08-04 | 2011-08-02 | Micron Technology, Inc. | Methods for forming rhodium-based charge traps and apparatus including rhodium-based charge traps |
| JP4374549B2 (en) * | 2005-12-20 | 2009-12-02 | セイコーエプソン株式会社 | Ferroelectric memory device, electronic apparatus, and method for driving ferroelectric memory device |
| US20080205179A1 (en) * | 2007-02-28 | 2008-08-28 | Qimonda Ag | Integrated circuit having a memory array |
| KR20180134124A (en) * | 2017-06-08 | 2018-12-18 | 에스케이하이닉스 주식회사 | Ferroelectric Memory Device |
| KR20190099693A (en) * | 2018-02-19 | 2019-08-28 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE627468A (en) * | 1962-01-23 | |||
| US3460103A (en) * | 1966-11-22 | 1969-08-05 | Radiation Inc | Ferroelectric memory device |
| US3623031A (en) * | 1968-03-30 | 1971-11-23 | Hitachi Ltd | Ferroelectric storage device using gadolinium molybdate |
| US3675220A (en) * | 1970-11-30 | 1972-07-04 | Advanced Patent Technology Inc | Planar random access ferroelectric computer memory |
| US3798619A (en) * | 1972-10-24 | 1974-03-19 | K Samofalov | Piezoelectric transducer memory with non-destructive read out |
| US3964033A (en) * | 1974-12-02 | 1976-06-15 | Matsushita Electric Industrial Co., Ltd. | Electrooptic storage device |
| JPS51136248A (en) * | 1975-05-21 | 1976-11-25 | Tokyo Electric Co Ltd | Ferroelectric fet memory device |
| US4144591A (en) * | 1977-08-15 | 1979-03-13 | The United States Of America As Represented By The Secretary Of The Army | Memory transistor |
-
1989
- 1989-10-20 US US07/424,809 patent/US5070385A/en not_active Expired - Lifetime
-
1990
- 1990-09-27 EP EP19900915260 patent/EP0496764A4/en not_active Withdrawn
- 1990-09-27 CA CA002070405A patent/CA2070405A1/en not_active Abandoned
- 1990-09-27 KR KR1019920700901A patent/KR100194915B1/en not_active IP Right Cessation
- 1990-09-27 AU AU65307/90A patent/AU641604B2/en not_active Ceased
- 1990-09-27 WO PCT/US1990/005523 patent/WO1991006121A1/en not_active Application Discontinuation
- 1990-09-27 JP JP2514180A patent/JP2966088B2/en not_active Expired - Fee Related
-
1991
- 1991-05-13 US US07/699,491 patent/US5119329A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR920704354A (en) | 1992-12-19 |
| US5119329A (en) | 1992-06-02 |
| AU641604B2 (en) | 1993-09-23 |
| EP0496764A1 (en) | 1992-08-05 |
| WO1991006121A1 (en) | 1991-05-02 |
| KR100194915B1 (en) | 1999-06-15 |
| AU6530790A (en) | 1991-05-16 |
| EP0496764A4 (en) | 1992-11-19 |
| US5070385A (en) | 1991-12-03 |
| JP2966088B2 (en) | 1999-10-25 |
| JPH05505699A (en) | 1993-08-19 |
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