CA2082771A1 - Method for Forming Interconnect Structures for Integrated Circuits - Google Patents

Method for Forming Interconnect Structures for Integrated Circuits

Info

Publication number
CA2082771A1
CA2082771A1 CA2082771A CA2082771A CA2082771A1 CA 2082771 A1 CA2082771 A1 CA 2082771A1 CA 2082771 A CA2082771 A CA 2082771A CA 2082771 A CA2082771 A CA 2082771A CA 2082771 A1 CA2082771 A1 CA 2082771A1
Authority
CA
Canada
Prior art keywords
layer
metal
interconnect
trenches
conformal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2082771A
Other languages
French (fr)
Other versions
CA2082771C (en
Inventor
Vu Quoc Ho
Gurvinder Jolly
Ismail T. Emesh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Priority to CA002082771A priority Critical patent/CA2082771C/en
Priority to US07/974,760 priority patent/US5354712A/en
Publication of CA2082771A1 publication Critical patent/CA2082771A1/en
Application granted granted Critical
Publication of CA2082771C publication Critical patent/CA2082771C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Abstract

A method is provided for forming interconnect structures for ULSI integrated circuits. Preferably, a barrier layer of a conductive material which forms a seed layer for metal deposition is provided selectively on the sidewalls and bottom of interconnect trenches defined in a dielectric layer, and a conformal layer of metal is selectively deposited on the barrier layer within the interconnect trench. Advantageously, the metal layer forming interconnect comprises a layer of copper which is deposited by chemical vapour deposition from an organo-metallic precursor at low temperature. Etching back and planarization of the barrier layer and the metal layer is accomplished by chemical mechanical polishing. Second and subsequent levels of metallization are provided by repeating the process steps, as required, to provide another dielectric layer defining interconnect trenches, selectively lining the trenches with a conformal barrier layer and then filling the trenches with selective deposition of a conformal conductive layer of metal, with planarization of the resulting conformal layers by chemical mechanical polishing. Preferably, via holes forming contacts to underlying device structures are filled with copper or tungsten.
CA002082771A 1992-11-12 1992-11-12 Method for forming interconnect structures for integrated circuits Expired - Fee Related CA2082771C (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002082771A CA2082771C (en) 1992-11-12 1992-11-12 Method for forming interconnect structures for integrated circuits
US07/974,760 US5354712A (en) 1992-11-12 1992-11-12 Method for forming interconnect structures for integrated circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA002082771A CA2082771C (en) 1992-11-12 1992-11-12 Method for forming interconnect structures for integrated circuits
US07/974,760 US5354712A (en) 1992-11-12 1992-11-12 Method for forming interconnect structures for integrated circuits

Publications (2)

Publication Number Publication Date
CA2082771A1 true CA2082771A1 (en) 1994-05-13
CA2082771C CA2082771C (en) 1998-02-10

Family

ID=25675661

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002082771A Expired - Fee Related CA2082771C (en) 1992-11-12 1992-11-12 Method for forming interconnect structures for integrated circuits

Country Status (2)

Country Link
US (1) US5354712A (en)
CA (1) CA2082771C (en)

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* Cited by examiner, † Cited by third party
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US8796041B2 (en) 2009-08-28 2014-08-05 International Business Machines Corporation Pillar-based interconnects for magnetoresistive random access memory

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