CA2112001C - Universal protocol programmable communications interface - Google Patents

Abstract

A general purpose programmable communications interface designed to support a wide variety of serial synchronous and asynchronous communication protocols. A
universal protocol communications (UPC) interface is designed to operate on a VME bus in conjunction with a CPU board which contains the application software that utilizes the communications capabilities of the UPC interface. Per channel DMA is available on input/output lines of the interface together with bit level control for message processing so that a variety of bit oriented communications protocols may be supported by simple reconfiguration of the receiver/
transmitter of the programmable UPC interface. In a preferred embodiment, a dynamically variable bit length shift register is used to organize the received and transmitted data into serial packets of the appropriate size on a per channel basis independent of the actual width of the shift register.
Reconfiguration for different protocols is accomplished by simply changing a bit count value stored in a bit counter which counts the number of serial data bits received or transmitted in each data word by the dynamically variable bit length shift registers of the transmit and receive circuitry.

Description

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DEC-20-93 hION 12.25 WWKN&N 1 LIBERTY PL 46FL FAX N0, 2155683439 P,04 2~.1~(1~01 LTNIVRItSAL BROTOCOL ~ROGRAId~~HLE COI~t?NICATIONS INTERF~iCR
HACKGROTJND O$ T8$ INVHNTION
Field of the leucstl6n The present invention relates to a programmable communications interface for general purpose communications in any of a wide variety-of serial synchronous and asynchronous communication protocols. More pazticularly, the present invention relates to a communications interface with per channel DMA input/output in conjunction with bit level control ~
~,p whereby the interface is recanfigurable to support a variety of bit oriented communication protocols transmitted aver a communications line.
Dasariptioa of the prior Art . , Data protocol controllers are widely used to allow 1~ data communications between cpmmunications devices over one or a plurality Qf communicatiax~s channels. Such data communications may he synchronous or asynchronous, and accordingly, prior art data protocol controllers typically comprise industry standard universal asynchronous receivers/
20 transmitters (UARTs) or universal synchronous/asynchronous , receivers/tranamitters (USAR.Ts). Generally, UARTS and USARTS
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transmitters (UARTs) or universal synchxonous/asynchronoue receivers/transmitters (USARTa), Generally, UARTS and USART9 operate in accordance with a particular bit-oriented protocol which is standardized for bath the receiver and the transmitter connected to the data channel, For examp7.e, Gulick et al . : describe in U: S. Patent N'o .
4,907,225 a data protocol, controller comprising a uART which supports bit-oriented protocols such as those used in integrated services digital networks (ISDN). The data protocol controller therein described has a bit-oriented protocol and is attached to a computer terminal and the like to allow protocol converaipn/rate adaptation to the communications channel., The data protocol controller of Guliek et al. comprises a commerciaxly available UART connected to a microprocessor 7.5 interface, an internal bus, and a full-duplex de~rice, The UART
also includes a transmitter for parallel reception of data on the internal bus. The DART has an eight bit shift register for parallel to serial conversion of the input data which is Provided to the full-duplex devise as a stream of serial data.
The T,TART further compxi8es a receiver for serial reception of data on the full-duplex device, The receiver has another eight bit shift register for s~rial to para7,7.e1 conversion of the input data which is provided to the internal, bus of the protocol controller. Ths DART thus described by Gulick et al.
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~....~~ , ~..::'.: ;. .:... ' DEC-20-93 hION 12.2'7 WWKM&N 1 LIBERTY PL 46FL FAH N0. 2155683439 p, p6 21~ ~~01 words and provide no mechanism for storing daCa having bit lengths other than 8-bits (plus a 1-bit parity error flag and a 1-bit special character flag?. Aence, the UA12T described by Guliek et al. is not readily configurable to transmit/receive data in data protocols having different bit lengths. As a result, all communications devices communicating through the data protocol controller of Gulick eG al, must have the came number of bits in transmitted/received data words in order to permit proper functioning of the deter pxotoco7. controller.
A communications cpnt~4~,~,ex interface described by Holtey et al. in U.S. Patent No. 4,945,4?3 provides a technique for emulating an interface between a microprocessor control unit and a mufti-line communications unit using dedicated memory for each communications line. However, the 1S communications controllez interface of Holtey et al, is similarly limited to communications in accordance with a predetermined protocol. An improved UART is desired which may be reconfigured to allow communication to/from communication devices having different formats.and different bit lengths in the Gommuzticated data words.
The data protocol limitations of prior art data protocol controllers are particularly traublesome in the SCAbp (supervisory control and data acquisition) industry where numerous monitoring devices in the:field dust communicate over communications lines with a central control computer. Since the monitoring devices are typically replaced at different points in time and thus cannot be assured to have the same protocols as other monitoring devices currently on-line, it is ,.... . ,,.~ .
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DEC-20-93 MON 12.27 WWKM&N 1 LIBERTY PL 46FL FAX N0. 2155683439 p,07 desirable that the communications interface to the central control Computer be able to recogni.xe data words of different formats and bit lengths to Facilitate system design. Such a function would permit ext,erxded use of existing SCADA equipment by a~.~.owing communication between older monitoring devices and central control computers and newer monitoring devices and the like independent of the protocol of the newer devices.
However, to the inventor' s knowledge, such a universal protocol communications interface has heretofore been unavailable in the art.
Acoord~.ngly, a universal protocol communications interface is desired which can be easily reconfigured or reprogrammed to handle communications among communications devices operating under a variety of different bit oriented 7.5 communication protocols. The 'present invention has been designed tv meet these needs, SUI~'ARY OF THE r ~~1T~ON
The present inventor has met the above-mentioned needs in the prior art by designing a universal protocol communi~
cations (UPC) irxterfao~ which is programmable so as to function as a general purpose communications interface for supporting a ~ wide variety of serial synchronous and asynchronous communi cations protocols. In a preferred embodiment, the UPG
interface of the invent~.on operates on a VME bus in conjunct~.on with a CPU board which contains the application software that will utilize the commurlicatians capabilities of the UPC
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DEC-2U-93 MON 12.28 WWKhi&N 1 LIBERTY PL 46FL FRX N0, 2155683439 p,08 ~1~2p~!
of the invention may operate in conjunction with an emulation pf a VMF computer backplane. Features such as pez channel DMA
input/output together with bit level control of message processing result in a very ~~.exible and efEioient input/output Uk~C in~.erface in accordance with the invention ~or applications which must support a variety of bit oriented communications protocols.
Canarally. Ghe functions of the UPG interface of the invention are implemented using a combination of discrete logie~
components and programmable gate array components which are programmed with the logic equations necessary to perform the UPC interface functions. However, the UPC intarfa~e of the invention is particularly characterized by a USART having a programmable word bit length which may be programmed 1S independently for each Gommunicatione channel ao as to provide separate protocol support on a per channel basis for synchronous and asynchronous communication over each data communications channe7~ via an RS-232, RS-X22 ox other line interface standards for word bit lengths varying from 1. to 256 bits and data transmission rates between 300 and 19.2 baud. As will be appreciated by those skilled in the a~'t, although the words have bit lengths which vary in ,accordance with the invention from 1 t.o 256 bits, the serial. data ie transmitted via the line interface in data packets having bit lengths dictated by the line interface standard (e.g.. a bits for an RS-232?
A preferred embod3menG of a universal protocol ~
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.t<.-... , DEC-20 93 NON 12.29 WWKN&N 1 LIBERTY PL 46FL FAX N0. 2155683439 P,09 ~~:~N~~3I
controlled by a host processor to permit serial synchronous and asynchronous data communications over a plurality of data communications channels with data communications devices having the same or different bit oriented data communications protocol as the hose processor. Such a circuit in accordance with the invention preferably comprises a host interface for selectively providing read and write access to the host processor and a data communications controller. Preferably, ~.he data communications controller comprises a data buffer connected to to the host processor via the host interface, a memory for storing data for passage to/from the data cvmmunicatidns devices, a DMA
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DEC-2_0,-193 hION 12.29 WWKM&N,1 LIBERTY PL 46F~, FAX NO, 2155683439 P, 10 ~, , controller comprises one ~of the programmable USARTa for each of the data communicaticins channels, Also, each programmable USART preferably comprises a receiving dynamically variable bit length shift register for shifting onto the data bus from a data communications channel serial input data having a known data word bit length and a transmitting dynamically variable b~.~ length shift regir>ter for shifting from the data bus into the data communications channel ser~.al output data having the known word bit length. Each programmable uSART is further characterized by a reoeive bit counter which stores the known word bit length and counts bits of the serial input data inputted into the receiving dynamically variable bit length shift register and by a transmit bit counter which stores the known word bit length and counts bits of the serial output data output from the transmitting dynamically variable bit length shift register. Preferably, each programmable USART further comprises a receive controller for controlling the receiving dynamically variable bit length shift register to shift onto the data bus the aerial input data in words having the known word bit length for storage in the memory, anal a transmit controller for controlling the transmitting dynamically variable bit length shift register to shift into the data communiaak:ions channel the serial output data in words having the known word b~.t length. In particuXar embodiments, the receiving dynamically variable bit length shift register of the USART of the invention has a physical bit length which does not equal the )mown word bit length and accordingly shifts least significant bits of the serial input data to the least ~z a ~,.s. ,..,.,:;;- ,..:, u. .. _, .: '~ .

DEC-20-93 MON 12.30 WWKM&N 1 LIBERTY PL 46FL FAX N0, 2155683439 P,11 2~~~Q~~
significant bits of the receiving dynamically variable bit length shift registex prior to shifting the serial input data onto the data bua.
In the illustrated embodiment, the host interface of the invention is connected to a VME computer bacl~plane via a VME bus and further includes a~controller for controlling the' direction of data flew between the 'VME bus and the data bus through the host interface and for providing system interrupts to the host interface and the data communications controller in response tv interrupt requests from the host processox.
The scope of the invention also includes a method of transmitting serial synchronous and asynchronous data from a host computer over a plurality of data communications channels to one or more data communications devices having the same or d~.fferent bit oriented data communications protocol as the host computer, comprising the steps vf:
for each data communications channel, loading a word bit length of the data communications device to whioh that channel is connected;
setting a desired data rates starting at a user defined address, 7.oad~.ng a memory of the host computer with data to be transmittad as output data to the data communications devices loading a DMA device with the user defined address and ~25 the number of wQrda ef data which are to be read from the memory starting at the user defined address;
enabling data transmission;
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.iY. :sZ,IA~a~~ft..._.j:;,GM'kf. l:.~:.r~..~f"~. ~5 ,j.M2...y.v;y~n ~~:lty, DEC-20 93 MON 12.31 WWKhI&N 1 LIBERTY PL 46FL FAX N0, 2155683439 P,12 21~~~~.t transferring words of data having a word bit length of the memory to a dynamically variable bit length shift register starting at the user defined address;
ahift.ing data from the dynamically variab7.e bit length shaft register into the data communications channel until a number of bits equal to the word bit length has been transferred; and once l.he number of bits equal tQ the word bit length have been shifted into the communications channel, reloading the dynamically variab~.e bit length shift register with further words of data from the memory.
The scope of the invention further inc7.udes a method of receiving serial synchronous and asynchronous data at a host computer via a plurality of data communications channels, each data communications channel being oonnected to a data communications device having the same ox different bit oriented data communications protocol as. the host computer, comprising the steps of:
for each data communications channel, loading a word bit length of the data communications device to which that , channel is connected;
setting a desired data rata;
determining an address of a memory of the host computer to which input data from the data communications device is to be stored;
loading a 17MA device with the memory address and the number of words of input data from the data communioations ,.. - .:: , -~- . : :, ... ...~ . . -..-- . -__.._.T_ ~~. .. _,_ . _ _ . . .:
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DEC-2093 MON 12.31 WWKM&N 1 LIBERTY PL 46FL FAX N0, 2155683439 P,13 21~~(~~1 device which are to be written into the memory starting at the memory address;
enabling data xeceipt;
transferring words of input data having the word bit length of the data commun~.cationa device to a dynamically variable bit lelgth shift register;
shifting data from the dynamically variable bit length shift register into the memory until a number of bite equal to the word bit length has been stored in the memory; and p once the dynamically variable bit length shift register has shifted the number of bits equal to the word bit length to the memory, loading the dynamically variable bit length shift register with further words of data having the word bit length from the data communications device..
BRILk' D$SCF.xPTION OF TAE DRAT~~NGS
The objects and advantages of the invention will become more apparent and mare readily appreciated from the following detailed description Qf Ghe presently preferred exemplary embodiment of the invention taken in conjunction with the accompanying drawings, of whichs Figure 1 illustrates a preferred embodiment of a UpC

DEC-20 93 MON 12.32 WWKM&N 1 LIBERTY PL 46FL FAX N0, 2155683439 P,14 2I~~Jfl1 m Figure 4 i~.lustrates a flow diagram of a transmit oontrol state machine of the USART illustrated in figure 2.

DETAILEp DESCItIPTIOI~ OF TFiE PREFERRED E~Op~~ENTS

The inventor of the subject matter disclosed and Claimed herein has met the abave-mentioned needs in the art by developing a programmable UPC interface which is easily reconfigurable by resizing the transmit and receive shift register: to accept any of a variety o~ communications protocols used by the communications devices connected to the input/output GQmmuniCations lines of the UPC interface.

Although the present invention will be described with respect to a preferred embodiment of a UPC interface which interfacea to a supervisory computer far a supervisory control end data acquisition (SCADA) system, those skilled in the art will l5 appreciate that the description given herein is for exemplary purposes on~.y and is not intended in any way Go limit the scope of the invention, In other word~, the programmable receive and transmit shift registers of the invention may be used in interfaces to.a variety of other communications devices which support a variety of bit-oriented protocols as described herein. X11 questions regarding the scope of the ~.nvention should be resolved by referring to the appended claims.

In a preferred embodiment of the inventian, the UPC

interfaces described herein is embodied in a single UPC Board arid is connected via a VME bus to a vME
computer processor board (baekplane). The UPC interface of the invention typically prova.des an interface between the VME computer v v . _,: , ;:. ,:,. ,.- .:: : ,....: : : - : . _;. . .. . .
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DEC-20-93 MON 12.33 WWKh!&N 1 LIBERTY PL 46FL FRX N0, 2155683439 P,15 2~~~~~I
7.2 backplane and the communications channels to any of a plurality Qf remote data coJ.lection unite (RTUs) at remote data collection sites. In the implementation il~.ustrated in Figure 1, eight transmit/reGeive lines with conG~ol lines era provided on each UPG Board, where each transmit/receive line communi-cates aria a standard RS-232 line interface to the RTUs, Typically, the RTUs monitor some open or closed loop process to provide control data to the supervisory control (host) computer via the UPG interface of the i;nv~ention.
As noted above, previous SGAbA systems have been limited in that the aupervis~ry control computer and RTUs have had to communicate over the communications lines via a sing7.e predetermined bit-oriented protocol. Such an arrangement has proven to be unaccegtable because as the RTUs are updated and replaced there is no guarantee that the xeplacement RTUs will have the same data protocols as the RTUs which they are replacing, The UPC interface of the invention has thus been designed to support a plurality of bit-oriented protocols by providing a plurality of independently programmabJ.e, highly Configurable input/output channels on each UPC Board. zn other words, the UPG interface o~ the invention may be configured to transmit/recaive a data packet of any size between 1 and 256 bits for the transfer of data to/from the RTUS.
Figure 1 illustrates a preferred embodiment of a UPC
Board including a UPG interface in accordance with the invention. As illustrated, a common VME bus interface l00 interfaces an internal bus of the tTPC aoard to a VME bus connected to the VME. computer backplane pf the supervisory DEC-20-93 MON 12.33 WWKM&N 1 LIBERTY PL 46FL FAX NC, 2155683439 P,16 21~.~~~1 7.3 control. (host) computer. The host computer typical~.y has a bit protocol which i.s known to the system programmer and has previously been used for all communications to/from the RTUs.
However, in accordance with the present invent~.on, the UQC
interface of the invention permits the host computer to communicate with ~tTUs despite any variations in the bit protocols of the RTUs. The UPC Board further includes a VME/acmmunicationa controller 7.02 responsive to a 'clocking signal from a clock 1.04 to control the timing of interface 100 far passing data as well. as to control the read or write direction of the interface 100. Interface 100 may be a ;:'conventional interface which cycles in response to timing ...signals provided by VME/communications controller 102 in a . .
manner known to those skilled in the art. The UPC Board preferably further includes an interrupt Control~.er 106 such as an Intel 82C59 processor which is responsive to a plurality of event driven system interrupts from the host processor to provide appropriate control of data communications to/from the RTUs when various error conditions and the like are detected.
In a pre~errad embodiment, 44 interrupts per tXPC Board are w recognized.
Aa further illustrated i,~. Figure 7., a plurality of input/output (I/O) groups 108-W 4 are connected to the internal bus of the UEC Hoard. Those I/O groups 108->_14 provide 2~ separate z/O channels for communication with the RTUs via an RS.-232 or other known line interf~aca , Tn a prefexx-ed embodiment, each I/0 group 108-114 is identical and comprises two xeaeive/transmit channels and two control channels. Access ~,.; . ; .. , .. _:
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s. . ;: :::, DEC-293 NON 12.34 WWKN&N 1 LIBERTY PL 46FL FAH N0, 2155683439 P,17 ~l~~t~J.l tv these I/Q groups 108-114 is preferably Controlled by separate I/O addresses, bus arbitration and the like provided by vNfE/communications controller 102.
'The circuitry of each I/O group will now be described with further reference to Figure 1. For ease of description, only I/0 group 108 will be described, for, as noted above, I/O
gxoups 110, 17.2, and 114 axe typically identical i.n design to I/c7 group 108. As illustrated in Figure 7., each I/O group includes a buffer 116 which provides a gateway or a pathway to the interface 100 via the UPC Board internal data bus and hence a connection to the VME bus and vME computer backplane. Each :w2/O group further includes a conventional direct memory acceBS.
(pMA1 circuit 118 for providing addresses to data stored in a conventional memory 120. DMA cixcuit 118 and memory 120 are ZS connected via a common data bus 122 to respective USARTs 124 '~. and 126 for each receive/transm3.t line. As will be described in more detail below with respect to Figure 2, USARTs 124 and lab area typically identical and are specially designed in accordance w~.th the invention such that they may be dynamically reconfigured to support a plurality of different bit-oriented .
protocols, Each input/output group further includes a group controller 128 which controls accesses to data bus 122 by arbitrating between DMA transfers and VME communi.cat,ions activity, preferably on a first some-first served basis.
A preferred embodiment of a uSART in accordance with the invention is illustrated in Figuxe 2, As noted above, USART 124 and 126 are typically identical. Each USART in aceordanee with the invention preferably includes a control ,:. . _ _ ~ .. . ,..._ _ ._. _ _ ..... .. .,.-: 5.:. .: . .. _.:... :..- . ::: . , ,. .;: ,-..::_:. <
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~. s DEC-20-93 NON 12.35 WWKh1&N 1 LIBERTY PL 46FL FRX N0, 2155683439 . P,18 2i12~~1 ~.5 register 200 for detecting flags in an input data stream and for providing receive start and transmit start signals and the like. The receive circuitry of each USART is particularly aharacteriaed in accordance w9.~.h the invention by ~ bit counter 202 which can be programmed by the user via the interface to the VMS bus to count a predetermined number of bits in the received serial input data to control grouping and storage of the input data in memory 3.20. In other words, as wiJ.l be described in more detail below with respect to Figure 3, the programmer may set a terminal count (TC) value in bit counter ~
202 so that the nu~er of specified bite in the received aerial input data is grouped arid stored in memory 120 in accordance with the bit protocol of the RTU connected to that particular USART. A receive control state machine 204 responsive to the ~.5 terminal count TG from bit counter 202, a baud rate Clock, a receive start signal from control register 202 and the received serial input data controls the loading and shifting of a fixed bit length (preferably 8-bit) receive shift register 206.
Receive control. state machine.204 and fined bit length receive ohift register 206 together control the saria~. to parallel conversion of the received aerial input data which is to be placed on the data bus 122 ax~a stored in memory x.20. As illustrated in Figure 2, receive control state machine 204 may ' also send interrupt requests to group controller 128 and DMA
requests to the DMA circuit 118. Message interrupts may also be sent via data bus 122 to VME/communicatior~s controller 102.
As wi~l.l be described in more detail below, receive control state machine 204 further controls the loading and clocking of rr..-\ ~1. ':, .'..,T:'.'.
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bit counter 202. Finally, as illustrated, the receive circuitry further includes a latch 2o8 for double buffering the para~.lel output data from the receive shift register 206 before s~.oring it in memory 12Q at an address specified by DMA circuit 11.8 .
The transmit circuitry of each USA1ZT is also ahaxacterized by a bit counter 2~.0 far counting the bits of an output data stream. As illustrated in Figure 2, bit counter 210 is programmed via the VME bus with a terminal count TC
corresponding to the word bit length of the output protoCOl of the RTU connected via the line interface to that particular ' USART. Preferably, the output data is output in the IEEE or ANSI standard format to a line interface which in Gurn transmits the aerial output data to the RTLT at the other end of s5 that communications line. As will be described in morn detail below with respect to Figure 4, a transmit control state machine 212 controls the parallel to serial data conversion via a fixed bit length (e-bits in a preferred embodiment) transmit shift register 214 by providing appropriate ~.oad and clock signals to transmit shaft register 214 and bit counter 210. In a preferred embodiment, the transmit data read from memory 120 ie double buffered at latch 216 before being output via transmit shift register 214, The serial output data fz~om transmit shift register 214 is then provided to the line 3.nt~rfave via latch 218 and transmitted at the specified baud rats under control of a cloak signal from clock 104, w DEC-20-~3 MON 12.36 WWKM&N 1 LIBERTY PL 46FL FRX N0, 2155683439 P,20 ~~~~Ofli 7.7 diagram of a preferred embodiment of receive control state machine 204 is illustrated in, Figure 3. As illustrated, receive control state machine 204 starts its processing at step 300. Tt then determines at step 302 whether a start data rece~.pt signal has been received from control register 200 to enable data reception. When an enable signal has been received, at step 304 the word bit length of tha.serial data input word (i.a.. the bi.t protocol length of the RTU
transmitting to the USART over the current input line) is loaded from a holding register into bit counter 202 as the terminal count TC. In a preferred embodiment, this bit length may range from 1 tv 256 bits in accordance with the bit grotocvl of the remote RTU. Of oouxae, greater bit lengths may be readily supported using the techniques of the invention.
Receive shift register 206 is then initialized. at step 306.
Once a start bit in the serial input data is received at step 308, the b~.t clock 104 is synchronized to the start bit at step alo for the specified baud rate R, The receive circuitry of the USART is then ready to receive data.
When a rising edge of clock 104 is received at stsp 312, the serial input data ~.s clocked into receive shift registeL 206 at step 314 and biG aQunter 202 is incremented by CLK far each bit received. Receive control state machine 204 then determines at step 316 whether the bit counter 202 has reached terminal count TC. T~ not, control state machine 204 determines at step 318 whether the receive shift register 206 is full. if the receive shift register 206 is not full, CLK ~.s checked at steps 320 and 322 fax the next rising clock edge.
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DEC-20-93 MON 12.37 WWKM&N 1 LIBERTY PL 46FL FAX N0, 2155683439 P,21 ~~.liH~~,1 i8 The next bit of serial input data is then clocked at step 314 as before. However, if the receive shift register 206 is determined at step 318 to be full, a DMA request is sent over data bue 122 to pMA circuit 118 at step 322 to request that the contents of the receive shift register 206 be transferred to memory 120 via buffer 208 at the address specified by the.DM~1 circuit 118. The receive shift register 206 is then initiarized at step 324 and control returned to step 31.4 fo,r clocking in the next serial input data bit upon receipt of the DEC-20-93 hlON 12.38 WWKhI&N 1 LIBERTY PL 46FL FAX N0, 2155683439 P, 22 2l:~Nf~J1 the bit length of the receive shift register 206. Since memory 120 generally stores data i~n bytes (e3.ght bits), the data bits remaining in the receive shift register 206 az~e shifted at step 336 to the least significant bit position of the receive shift registex 206 before being transferred to memory 1Z0 at step 338. Steps 336 and 338 help assure that the data stored in memory 120 may be easily xeconf~,gured into a contiguous serial.
hit stream.
As noted above, transm~.ss~.an of aerial output data is controlled by transmit control state machine 212. A flow diagram of a preferred embodiment of transmit control state machine 21.2 is illustrated in Figure 4. As illustrated, transmit control state machine 212 starts its processing at step 400. Once transmission is enabled at step 402 by, for example, receipt of a start transmission signal from control register 200, 'the word bit length of the receiving RTU is then loaded into bit counter 210 at step 404. As with the redeive circuitry, the word bit length may be any value between 1 and 256 bats, A DMA request is then sent to DMA circuit 118 and data is read from memory 1.2d starting at the address specified by the DMA circuit 118. This data is doub~.e buffered by latch 216 and then transferred to transmit shift register 214 at step 406. Af~,er monitoring the clock at steps 408 and 41.0 for the next rising cloak edge, the data stored in transmit shift registex 214 is then shifted out one bit at a time at step 412 at each rising edge of the cl,QCk signal from transmit control state machine 212. Bit counter 210 is also incremented at step 4~.2 by CLK for each bit of data shifted out of transmit shift DEC-2~-93 MON 12.38 WWKM&N 1 LIBERTY PL 46FL FRX N0, 2155683439 P,23 register 214, Transmit control state machine 212 then checks at step 414 whether the terminal count TC has been reached. rf not, it is determined at step 415 whether the transmit shift register 214 is empty. Tf not, the next bit of data ie shifted 5 out of transmit shift register 214 at step 41.2 upon receipt of the next rising clock edge, However, if the transmit shift register 214 is empty, a further DMA request is sent to memory 120 and another byte of data is transferred from memory 120 to transmit shift register 214 via latch 216 at step 418.

10 The above process continues until TC is reached at step 414. It is then determined at step 420 whether there is further data to be transmitted by checking the contents of latch 216, If it is determined at step 420 that latch 27.6 is empty, transmission stops and control returns to step 402.

15 However, if there ie further data to be transmitted, the word bit length for the next data packet is loaded into the bit counter at steg 422 and the next byte of data ie transferred from memory 7.20 into the transmit shift. register 214 via latch 216 in accordance with the techniques described above. The 20 parallel data provided from memory 120 is thus seria~,ized by w transmit shift register 214, output to the line interface via latch 218 and transmitted to the R~'U connected to that transmission line, Those skilled in the art will appreciate that the UPG

hoard described above contains se~rera~. highly configurable r/O

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and receiving RTUs connected to the respective USARTs of the UPG Board of the invention. This technique is in marked contrast to prior art techniques using fixed bit length shaft registers to transmit/receive data in a particular predetermined protocol.
To further illustrate the beneficial features of the invention, operation of the UPC Board will be described for the transmission and receipt of ~2-bit data words via a standard RS-232 line interface using a USART having B-bit shift registers configured as herein described.
TRANSMIT ~XAM~h~
Tn transmit mode, a terminal count of 12 is stored in bit counter 210 and the USAR,T configured for transmission of l2~bit data words, DMA circuit 118 is thus instructed to transfer [((12 MO~ 8) + 1) * (N 12-bit words) bytes from memory 120 to the USART connected to the appropriate communications line. The designated US.ART accepts the bytes transferred from memory 120 and asseml~~.es them into the appropriate 1,2~bit serial data stream as follows.
To transmit ten 12-bit words (where it is assumed that the f first bit is a start bit and the last bit can be a stop bit or a data bit), bit countex 21,0 is first loaded with the value ~.2. An external baud rate generator is then set to the desired rata (T) and provided to transmit control state machine 212.
At a user defined address, memory 120 is then loaded with the transm~.ssion data as fol~.ows (whexe bit 0 is typically set to 0 as the start bit of a word);
address NNNN~.00 WordO bits 0-7 NNNN+O1 WordO bits B-1?.
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DEC-2093 MON 12.40 WWKM&N 1 LIBERTY PL 46FL FAX N0, 2155683439 p, 26 At this point. latch 218 will output a serial stream of data which wilX appear to have come from a 12-bit USART.
However, by changing the terminal count stored in the bit counter 210, the transmit Channel can be easily r~configured t.o transmit words having any number of bits desired.
RECEIVE EXAMPLE ' In receive mode, a terminal count of 12 is stored in bit countsr 202 and the USART configured fox receipt of 12-bit data words. DMA circuit 118 is thus instructed to transfer to (((12 MOD 8) + 1) * (N l2~bit wdrds~] bytes from the appropriate USRRT to memory 120. Memory 120 accepts the bytes transferred from the USART and stores them in the conventional manner. The process of receiving serial input data proceeds as follows.
To receive ten 12-bit words iwhere the fixst bit may be a start bit and the last bit can be a stop bit or a data bit) bit counter 202~is first loaded with the value 1.2. The baud rate genE~rator is glen set to the desired data rate R.
DMA circuit 218 is then requested to provide a pointer to the next ~ree location in memory 120. For example, DMA cix°cuit 118 may spaaify address NNNN for storage of received data, DMA
circuit l28 also has its byte count register loaded with the value of 20 to indicate that 10 words of 2 bytes each are to be stored 3n memory 120. DMA circuit 1~.8 is then enabled and a receive START signal provided to receive control state maahina 204 from aontx°ol register 200. Data receptian may then begin.
Data is then received by receive shift register 206 on a serial basis until bit counter a02 xeaches the terminal r z,.
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DEC-20 93 MON 12.41 WWKM&N 1 LIBERTY PL 46FL FAX N0, 2155683439 p,27 2112!~fll count TC or the receive shift register 206 is full. The receive control state machine 204 then requests the transfer of a byte of data to latch 208 and frow latch 208 into the next memory location in memory 120. ~'he UBART then receives the next word or word fragment of input data and continues receiving data in accordance with the fJ.pw diagram of Figure 3 until the byte count in pMA circuit. 118 is reached. At, that time, memory 120 will have received data in the following form:
address NNNN+oo word0 bits 0-7 NNNN+O1 word0 bits 8-11 NNNN+oa words b~.ts o-'7 +o~ words bits a-7~Z
NNNN+04 word2 bits 0-7 NNNN+05 word2 bite 8-11 +
.
+
NNNN+18 word9 bits 0-7 NNNN+1~ word9 bits 8-17.
To the user and the transmitting RTU, the receiving USAR.T
funotions life a 12-bit device even though it may have a receive shift xegister of only a bits. However, as noted DEC-20-93 MON 12.42 WWKM&N 1 LIBERTY PL 46FL FAX N0. 2155683439 p,28 the like. In addition, the line interfaces may Sae in the XSDN
farmat and the data packets foxmu~.ated in the appropriate protocol.. Accordingly, all such modifications are intended to be included within the scope of this in~rention as defined in 5 the following claims, . _,. . . , , , -,: . ... , . :..., _. . . , _~ ~._ _. _ ___ . . .__.-.
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Claims (12)

1. A universal protocol communications interface controlled by a host processor so as to provide serial synchronous and asynchronous data communication over a plurality of data communications channels between data communications devices having the same or different bit oriented data communications protocol as said host processor, comprising:
a host interface for selectively providing read and write access to said host processor; and a data communications controller comprising:
a data buffer connected to said host processor via said host interface;
a memory for storing data for passage to/from said data communications devices;
a DMA device for providing addresses to data stored in said memory;
a data bus for providing data communication among said buffer, said memory and said DMA device;
controller for arbitrating among different requests for access to said data bus; and at least one programmable synchronous/asynchronous receiver/transmitter connected to said data bus so as to provide data communications between said data bus and a plurality of data communications devices over said plurality of data communications channels, each programmable synchronous/asynchronous receiver/transmitter having a programmable bit protocol length for data packets transmitted or received thereby, said bit protocol length being programmed independently for each of said plurality of data communications channels so as to provide serial data communications over each data communications channel in data packets having the bit protocol length of the data communications device connected thereto.

2. A circuit as in claim 1, comprising a plurality of said data communications controllers, wherein each data communications controller comprises one of said programmable synchronous/asynchronous receiver/transmitters for each of said data communications channels.

3. A circuit as in claim 2, wherein each programmable synchronous/asynchronous receiver/transmitter comprises a receiving dynamically variable bit length shift register for shifting onto said data bus from a data communications channel serial input data in data packets having a known bit protocol length and a transmitting dynamically variable bit length shift register for shifting from said data bus into said data communications channel serial output data in data packets having said known bit protocol length.

4. A circuit as in claim 3, wherein each programmable synchronous/asynchronous receiver/transmitter further comprises a receive bit counter which stores said known bit protocol length and counts bits of said serial input data inputted into said receiving dynamically variable bit length shift register and a transmit bit counter which stores said known bit protocol length and counts bits of said serial output data output from said transmitting dynamically variable bit length shift register.

5. A circuit as in claim 4, wherein each programmable synchronous/asynchronous receiver/transmitter further comprises a receive controller for controlling said receiving dynamically variable bit length shift register to shift onto said data bus said serial input data in data packets having said known bit protocol length for storage in said memory, and a transmit controller for controlling said transmitting dynamically variable bit length shift register to shift into said data communications channel said serial output data in data packets having said known bit protocol length.

6. A circuit as in claim 5, wherein said receiving dynamically variable bit length shift register has a physical bit length which does not equal said known bit protocol length and accordingly shifts least significant bits of said serial input data to the least significant bits of said receiving dynamically variable bit length shift register prior to shifting said serial input data onto said data bus.

7. A circuit as in claim 1, wherein said host processor comprises a VME computer backplane connected to said host interface via a VME bus.

8. A circuit as in claim 7, wherein said host interface comprises a controller for controlling the direction of data flow between said VME bus and said data bus through said host interface and for providing system interrupts to said host interface and said data communications controller in response to interrupt requests from said host processor.

9. A circuit as in claim 1, wherein said programmable bit protocol length is variable to accommodate data packets having from 1 to 256 bits.

10. A method of transmitting serial synchronous and asynchronous data from a host computer over a plurality of data communications channels to one or more data communications devices having the same or different bit oriented data communications protocol as said host computer, comprising the steps of:

for each data communications channel, loading a bit protocol length of the data communications device to which that channel is connected;
setting a desired data rate;
starting at a user defined address, loading a memory of said host computer with data to be transmitted as output data to said data communications device;
loading a DMA device with said user defined address and the number of words of data which are to be read from said memory starting at said user defined address;
enabling data transmission;
transferring words of data having a word bit length of said memory to a dynamically variable bit length shift register starting at said user defined address;
shifting data from said dynamically variable bit length shift register into said data communications channel until a number of bits equal to said bit protocol length has been transferred; and once said number of bits equal to said bit protocol length have been shifted into said communications channel, reloading said dynamically variable bit length shift register with further words of data from said memory.

11. A method of receiving serial synchronous and asynchronous data by a host computer via a plurality of data communications channels, each data communications channel being connected to a data communications device having the same or different bit oriented data communications protocol as said host computer, comprising the steps of:
for each data communications channel, loading a bit protocol length of the data communications device to which that channel is connected;
setting a desired data rate;

determining an address of a memory of said host computer to which input data from said data communications device is to be stored;
loading a DMA device with said memory address and the number of words of input data from said data communications device which are to be written into said memory starting at said memory address;
enabling data receipt;
transferring words of input data having a word bit length of said data communications device to a dynamically variable bit length shift register;
shifting data from said dynamically variable bit length shift register into said memory until a number of bits equal to said bit protocol length has been stored in said memory; and once said dynamically variable bit length shift register has shifted said number of bits equal to said bit protocol length to said memory, loading said dynamically variable bit length shift register with further words of data having said word bit length from said data communications device.

12. A universal protocol communications interface controlled by a host processor so as to provide serial synchronous and asynchronous data communication over a plurality of data communications channels between data communications devices having the same or different bit oriented data communications protocol as said host processor, comprising:
a host interface for selectively providing read and write access to said host processor; and a data communications controller comprising:
a data buffer connected to said host processor via said host interface;

a memory for storing data for passage to/from said data communications devices;
a DMA device for providing addresses to data stored in said memory;
a data bus for providing data communication among said buffer, said memory and said DMA device;
a controller for arbitrating among different requests for access to said data bus; and at least one programmable synchronous/asynchronous receiver/transmitter connected to said data bus so as to provide data communications between said data bus and a plurality of data communications devices over said plurality of data communications channels, each programmable synchronous/asynchronous receiver/transmitter having a programmable bit protocol length which is variable from 1 to 256 bits and programmed independently for each of said plurality of data communications channels so as to provide serial data communications over each data communications channel in the bit protocol length of the data communications device connected thereto.