CA2117693A1

CA2117693A1 - High security counter

Info

Publication number: CA2117693A1
Application number: CA002117693A
Authority: CA
Inventors: John R. Martin
Original assignee: Individual
Current assignee: Arachnid Inc
Priority date: 1992-03-18
Filing date: 1993-02-12
Publication date: 1993-09-30
Also published as: EP0631661A1; US5297178A; EP0833129A3; JPH07507138A; EP0631661A4; KR950701067A; WO1993019346A1; EP0833129A2

Description

W O 93/19346 PC~r/US93/01335 q ~ 1 -HIGH ~UKl'l ~ COUNTER

T~uNTcAL FIELD

The present invention relates to a counter system and more particularly to a high security counter having a count value stored therein that cannot be decreased.

RA~r~Y~UrlV OF THE INVENTION
M~rhAnirAl and ele~-L~ ~nicAl counters are known for counting the number of times an event occurs. These counters have been used in coin operated ~ ~ r~~h;n~c and gaming devices to count coin intake. These types of counters are also used in automobiles to provide odometer records as well as in various other applications. These counters however can be costly. Further, the count value indicated by these types of counters can be easily ~ ~~ed with. For example, known counters can be L,~as~ed by merely dicc~ uLing them. The count value of counters employing mechanical counting wheels can be altered by manual .~ ~ of the wheels. The count value of -- -niCAl and ele~L~ ' ~ni CAl counters can also be altered by subjecting the counter to physical shock. Software counters that count in a binary fashion, i.e., 001, 010, 111... , are also known. m e contents of these counters are typically stored in a random access memory, RAM. This type of counter can be t ~ed with however by Le~LuyL_ ing the count value in the RAM to a lower value.

wo 93~lg3~~ A ~ PCT/US93/01335 SUMMARY OF THE INVENTION
In accordance with the present invention the disadvantages of prior counters as d;ec1-esP~ above have been overcome. The high security counting system of the present invention utilizes a p-u~. hle read only memory counter to maintain a count value that cannot be decreased by tampering.
More particularly, the high security counting system of the present invention counts events l~.ese,.Led by an event signal. The counting system includes a plUyL_ hle memory counter having a number of storage elements, each of which is PIV~L ~hle from a first value to a second value and not plU~L hle from the second value to the first value. A controller is responsive to an event signal for controlling a memory p-vy~ to program a storage element from the first value to the second value wherein each storage element prv~- ' to a second value ,e~lesents a unit of count and the the number of storage elements p~u~. -' to the second value re~.ese..L the total count or count value of the counter.
These and other objects and advantages of the invention as well as details of an illustrative 25: ' '; L will be more fully understood from the following description and the drawings.

r~T~ T~lll OF THE DRAWINGS
Fig. l is a block diagram of the counting system of the present invention;
30Fig. 2 is a flow chart illustrating a routine for p-u~- ;ng the PROMs depicted in Fig. l;
Fig. 3 is a flow chart illustrating a routine for locating the ldst bit p~u~-_ ~' in a PROM; and Fig. 4 is a flow chart illustrating an 35alternate ~ L of the routine to program a PROM in accordance with the present invention.

W 0 93/19346 ~r/US93/01335 ~21 i 76'33 BEST MODE FOR CARRYING OUT ~ V~h~l~
A high security counting system in accordance with the present invention is depicted in Fig. 1.
The system includes a mi~Luplocessor 10 that operates in accordance with software stored in a ROM
12 to control a pLU~ 14 to program a nonerasable p.o~._ hle read only memory 16. The nonerasable pLV~L hle read only memory 16 may take the form of one or more PROMs as illustrated.
Alternatively, the nonerasable p~V~L hle read only memory 16 may take the form of one or more WORNs or the like wherein each storage element within the memory is plV~L_ hle from a first value to a second value but is not prv~L hl D from the second value back to the first value. Under the control of the mi~L~Lv~esso~ 10, the memory 16 is p~OyL ' to form a counter, the count value of which once pro~L -', cannot be decreased so as to provide a relatively t -proof record of the number of events which have ovvuLLèd as detected by an event detector 18. The event detector 18 may be any device that generates a signal upon the ocvuLL~nce of an event which is to be counted. For example, the event dDtector 18 may take the form of a coin detector such as used in gaming ~--hinD~ or other coin o~e~ted ~--h;nD~. Upon detection of the input of a coin or coins of a particular ' 'n~tion, the ADtec~or 18 outputs an event signal that is coupled to the mi~rv~LvcessoL
10.
As shown in Fig. 1, the mi~Lv~LucessoL 10 acaDsses the memory 16 via an input/output port 20 and an address bus 22, data bus 24 and control bus 26 c~nnDrted directly to the PROMs of the memory 16.
Two voltages, VPP and VCC are applied to each of the PRONs of the memory 16. Except when pLv~L_ ing of the PRON8 occur8, VCC and VPP are each set to + 5 volts as provided by a power supply 30 coupled to WO93/193~ C A ~ i i / 6 ~ 3 PCT~US93/01335 the PROMs via respective switches 32 and 34. In order to program the PROMs of the memory 16, VCC is changed from + 5 volts to 6.25 volts as supplied to the PROMs from a 6.25 volt generator 36 and the switch 34. During plVyL ;ng VPP is changed from +
5 volts to 12.75 volts provided to the PROMs of the memory 16 from a 12.75 volt generator 38 through the switch 32. In order to program the PROMs of the memory 16 each of the switches 32 and 34 is responsive to a control signal on a line 40 from the mivLv~.vveSsol 10 to switch the PROMs from the + 5 volt power supply to 12.75 volts and 6.25 volts respectively.
In acco.d~..ce with the present invention, the memory 16 is ~LV~L ~ d to form a counter. Nore particularly, in ~e~ul.se to an event signal from the event det ctor 18, the miv~v~LVce6s~L 10 controls the PL~L ~ 14 to program a storage element in the memory 16 from a first value to a second value wherein each storage element that is pIO~ to a second value ~e~e-e"~s a unit of count and the number of storage ~ VYL ~ d to the second value ~e~Lese--Ls the total count or count value of the counter. Where the memory takes the form of one or more PROMs as illustrated in Fig.
1, a storage element may take the form of one bit in the PROM or the storage element may take the form of a number of bits such as one byte of memory in the PROM. PROMs may be employed for the memory counter 16 such that in their initi A 1; 7A~ or ~I~L V~L
state, i.e., when the memory counter is empty, each bit location stores a 1. As each event signal is ~ot~cted, a single bit in the PROMs is ~1V~L ~' to a 0 starting with the least ~ignificAnt bit in the memory counter 16. The total number of 0's stored in the PROMs thus Le~lese..~ the total count or count value of the memory counter 16. Further, the location of the last ~ O~L ~ ' O bit in the PROMs WO93/193~ PCT~US93/01335 CA21 1 16(t3 Le~lese--ts the total count or count value of the memory counter 16. Once the location of the last pLVyL ~~ o is detDrm;nP~ the miuLu~-ùcesso~ 10 can thus convert the location to a binary count value used for further proc~qfi;ng by the system employing the PROM counter. It is noted that nonerasable plUyL ~le memories having a 0 stored in each bit location in the memories initial or ~LVyL_ -' state may also be employed in accoldance with the present invention.
In order to program one unit of count in one bit location of a PRON counter 16 having a 1 in each bit position in the counter's empty state, the mi~LupLoc6asùI 10 operates in accordance with the routine depicted in Fig. 2. The mi~Lu~.oce~sol 10, at block 42 first d~t rm;n~c whether an event detected by the detector 18 as Lc~Lese.-Led by an event signal coupled to the miuLv~LU~essol 10 should be counted. If so, the mi~Lu~o~essur 10 ploceeds to block 44 to find which of the PROMs, PRO~ 1 through PRON N is to be pLUyL ' with the next unit of count. Thereafter, the mi~ruyLUueasor 10 pt oceeds to block 46 to find the next byte in the PRON to be pLU~ -d and at block 48 the mi~Lu~Iocessur 10 finds the least significant bit of that byte to be P1VYL ', that bit being referred to as bit n. The miu~v~LUcessol ; 1~ Ls blocks 46 and 48 in acuuLdan~é with the routine depicted in Fig. 3 as ~;qc~qqed in detail below. After the bit n that is to be pLOyL ~' is found, the mi~Lu~ocessur pLuuéeds to block 50 to program the bit from a 1 to a 0. It is noted that if each storage element, for example one bit, in the memory counter 16 is not individually sddLeDsable, but a group of storage ~1~ ts such as one byte is =' ~ssable, the mi~Lu~Lvues~uL 10 pLU~L one byte a number of times equal to the number of bits in that byte. More particularly, as shown at block 50, WO93/193~ PCT~US93/01335 CA~l i /6'i3 the miu~upLvcessor pLvyLamD the byte containing bit n with a word having l's in every bit position of greater significance than bit n and having a 0 at bit n as well as every bit position of lesser significance than bit n. Acs-lm;ng that the first byte in the empty PROM counter 16 is LeyLese..~ed by the 8 bit word, ~ , then upon the first event detected, the miuLv~.vCê6s~ 10 controls the p~V~L r 14 and PROM counter 16 to program the least sign;fi~Ant bit of that byte to 0. This is a.~ c~ed by addressing the byte and ~VyL ;nq it with the word 11111110. Upon detecting the OUUULL~.lUë of a second event, the miuLvplocessoL
addLèsses the same byte and ~.o~La~3 it to 11111100.
This operation continues until all 8 bits are 0's after which the miuLv~Loaessvl 10 addLesses the next sequential byte in the memory counter 16.
In one ~ of the present invention, in addition to the PROM counter 16, a software counter in a portion of a battery backed up RAM 60 is utilized to store a binary count value I~plese..Ling the total nu_ber of events detected. Here this term binary count value means a count value that changes from 000 to 001 to 010 to 011 etc., only three sign;f;~nt positions being shown for s; l;city.
The system then may reguire that the count in the RAM 60 agree with the count in the PROM 16. In the event of a di~agL~ , as ~~t~m;n~ by the miuLv~LVve~-vl 10, the miuLv~loaessol 10 can prevent the device u~ ; ng the counting system from operating and/or send an alarm signal.
Further, the battery backed up RAM 60 can store a nunber that is greater than the PROM such that a new PROM bit is pLV~L ' only after n counts. In this . ';- ~ the battery backed up RAM 60 provides the accurate count and the PROM counter 16 provides a tamper-proof count within n of the accurate total, allowing n times the capacity for a WO93/193~ PCT/US93/01335 ~A2i 1 i~'~3 given PRON. In this : 'i L, the miuLv~V~-essvL
10 operates in accordance with the routine depicted in Fig. 4 as follows. After detP~min;ng that an event has been detected that should be counted at block 42, the mi~v~Locessur 10 p~oceeds to block 52 to inur~ ~ the binary count value stored in the counter portion of the RAM 60. Thereafter, at block 54, the miu~v~-v--essol 10 dPtp~m;npc whether the count value in the RAM counter is a multiple of n for example, n = 8. If the count value in the RAM
counter is a multiple of n, the miu~v~lvcessvL 10 ploaeeds to block 56 to program one bit in the PROM
counter 16 in au~v~da-,ce with steps 44, 46, 48 and 50 described above with reference to Fig. 2.
In order to find the location of the last bit yLv~l -' and thus the location of the next bit to be p~v~._ ' in the PROM counter 16, the miuLvy~vcessvL 10 operates in accordance with the routine depicted in Fig. 3. More particularly, the miu~v~vcessv~ at block 62 sets an address to the ~eq;nning of a block of memory. Thereafter, at block 64, the miuLv~LVuessuI ~PtPrminPs the size of the memory block and yLvueeds to block 66 to determine a value that is equal to half of the memory block size. The miu-v~lvce SOl 10 thenn ploceeds to block 68 to set an address to the center of the memory block. At block 70, one-half of the value of the jump size is again de~Prm;nPd, the miu v~luaessv~ then procee~ing to block 72. At block 72, the mi~-v~vcessvL 10 ~PtPmminP~ whether the address is at a correct byte location or one above and if not, the miuLvyLvce~su~ y~uceeds to block 74 to determine whether all of the bits of the byte are occupied by 0's or l's. If the bits of the byte are all 0's, the miu-u~LvcessuL yLuueeds from block 75 to block 76. At block 76, the mi~uyLuc~ssuL 10 increases the address by half of the last change and yLuueeds to block 70. If all of W O 93/19346 Iq~r/US93/01335 Cl~i 1 16~3 the bits in the byte are l's, the miuLu~Loccs60~
~Ioceeda from block 74 to decrease the address by half of the last change and thereafter proceeds to block 70 When it is detPrmin~d that the correct byte or the byte immediately above the correct byte has been found, the correct byte containing the last ~Lu~ -' O, the mi~u~Locessor p,uceeds to block 80 At block 80, the miu.v~.uu~sso~ t~rm;n~C
whether the byte is the correct byte or one above o If the byte is the correct byte, the miuLu~.ucessor ~,uceeds to block 82 However, if the byte is one above the correct byte, the miuLu~-ucesao~ first p.uceeds to block 84 to back the address down to the correct byte At block 82 the mi~-u~-uoessor de~orm;n~c that the byte containing the last _ -' 0 has been found and p.uuLeds to block 86 to determine the bit location of the last o p,u~. -' At block 88, the mi~-vplu-essu~
det~rm;n~c whether the first bit in the byte is equal to a 1 If not, the mi~.u~.ocesso. p.uceeds to block 90 to iru.~ L the bit location by 1 and to return to block 88 After finding the first bit in the byte that is a 1 as opposed to a 0, the miu.vpluueasur ~.uuceds to block 92 If the miu.u~.ùcessur is looking for the next bit to be p.u~, -', the mi~.u~.ocessoI at block 92 determ;n~c that the bit found at block 88 is the bit location that it was looking for If the miu.uU~ocesso~ is lookinq for the last ~-v~ 1 0, the mi~.u~.ocesso. at block 92 merely de~.~ Ls the bit location found at block 88 Thereafter, at block 94, the miuLup~uueaso~ 10 at blocks 94, 96 and 98 ~t rm; n~e the address of the bit that it was searching for The memory counter 16 in accordance with the present invention cannot be t ~d with in a manner to dec. L the count value stored therein because although the memory can be ~o~, -' to WOg3/lg3~ PCT/US93/0133S
iA21 1 76't3 change a bit value from a first value to a second value, it cannot be ~,~yL -~ to change a bit value from the second value to the first value. ~any modifications and variations of the present invention are possible in light of the above tea~h;n~C. Thus it is to be understood that, within the scope of the App n~ ~ claims the invention may be practiced otherwise than as described hereinabove.

Claims

IN THE CLAIMS:

1. A high security counting system for counting events represented by an event signal comprising:
a programmable memory counter having a plurality of sequentially arranged memory locations, each memory location having a unique memory address and including a predetermined number of storage elements, each storage element being programmable from a first value to a second value and not programmable from said second value to said first value, the number of storage elements programmed to said second value representing the count of said programmable memory counter;
a programmer coupled to said programmable memory counter; and a controller responsive to an event signal for controlling said programmer to program a storage element from said first value to said second value, wherein said controller controls said programmer to sequentially program the storage elements within a memory location by reprogramming a respective memory location a predetermined number of times equal to the number of storage elements at said memory location.

2. A high security counting system as recited in claim 1 wherein said controller controls said programmer to program the storage elements within a memory location sequentially starting with a storage element in a least significant position in said memory location.

3. A high security counting system as recited in claim 2 wherein said controller includes means for locating the position of the last storage element programmed to said second value.

4. A high security counting system as recited in claim 1 wherein said memory counter includes a PROM, each addressable memory location represents a byte in said PROM, and each storage element represents a bit in said PROM.

5. A high security counting system for counting events represented by an event signal comprising:
a nonerasable programmable read only memory counter having a plurality of storage elements, each storage element being programmable from a first value to a second value, the number of storage elements programmed to said second value representing the count value of said nonerasable programmable read only memory counter;
a random access memory counter adapted to store a count value;
a programmer coupled to said programmable memory counter; and a controller responsive to an event signal for incrementing said random access counter by one unit and controlling said programmer to program a storage element from said first value to said second value, said controller further being adapted to compare the count value stored in said random access memory counter to the count value of said nonerasable programmable read only memory counter and produce an alarm signal if said count values are not equal.

6. A high security counting system as recited in claim 5 wherein said controller controls said programmer to program the storage elements in said programmable memory counter sequentially starting with a storage element in a least significant position in said memory, the position of the last storage element programmed in said memory representing the count of said counter.

7. A high security counting system as recited in claim 6 wherein said controller includes means for locating the position of the last storage element programmed to said second value.

8. A high security counting system as recited in claim 6 wherein said storage elements are arranged in said memory in groups, each group having a predetermined number of storage elements therein and each group having an associated address, said controller controlling said programmer to program each storage element in a group sequentially by reprogramming said group of storage elements said predetermined number of times.

9. A high security counting system as recited in claim 5 wherein each storage element represents a bit in said programmable read only memory.

10. A high security counting system as recited in claim 5 wherein each storage element represents a byte in said programmable read only memory.

11. A high security counting system for counting events represented by an event signal comprising:

a nonerasable programmable read only memory counter having a plurality of sequentially addressable byte locations, each byte location including a predetermined number of bit locations, each bit location being programmable from a first value to a second value, the number of storage elements programmed to said second value representing the count of said counter;
a programmer coupled to said memory counter;
and a controller responsive to an event signal for controlling said programmer to program said bit locations from said first value to said second value by first selecting a byte location to be programmed and thereafter determining a bit location to be programmed by sequentially checking the bits within said selected byte location to determine if a respective bit location is set to said first value or said second value.

12. A high security counting system as recited in claim 11 wherein said controller controls said programmer to program bit locations in said memory counter sequentially starting with the least significant bit location in said memory counter.

13. A high security counting system as recited in claim 12 wherein the location of the bit last programmed in said memory counter represents the count of said counter, said controller including means for locating the bit last programmed to said second value.

14. A high security counting system as recited in claim 1 wherein said controller controls said programmer to program said memory locations sequentially starting with a memory location in a least significant position in said memory counter.

15. A high security counting system for counting events represented by an event signal comprising:
a nonerasable programmable read only memory counter having a plurality of storage elements, each of which is programmable from a first value to a second value, the number of storage elements programmed to said second value representing the count of said counter;
a random access memory counter adapted to store a count value;
a programmer coupled to said programmable memory counter; and a controller for incrementing said random access counter by one unit in response an event signal and controlling said programmer to program a storage element from said first value to said second value every Nth time said random access counter is incremented, where N is a whole number greater than one.

16. A high security counting system as recited in claim 15 wherein the location of the storage element last programmed in said memory counter represents the count of said counter and said controller includes means for locating the bit last programmed to said second value and converting the location to a binary count value.