CA2123778A1

CA2123778A1 - Headend processing for a digital transmission system

Info

Publication number: CA2123778A1
Application number: CA002123778A
Authority: CA
Inventors: Jay C. Mcmullan, Jr.; David B. Burleson; Donald R. Huntley; Randolph J. Schaubs
Original assignee: Individual
Current assignee: Scientific Atlanta LLC
Priority date: 1991-11-19
Filing date: 1992-11-18
Publication date: 1993-05-27
Also published as: EP0613601A1; US5550825A; AU3142193A; WO1993010606A1; CN1075581A

Abstract

A headend method and apparatus for a digital transmission system is provided which includes inputs for receiving first and second program information from first and second program sources and inputs for receiving first and second control information from first and second control sources. The first and second program information is applied to a switching circuit and a switch control controls the switching circuit to output channels of program information comprising combinations of the first and second program information for output to a subscriber. Processing circuitry allows for selectively providing the first and second control information to the channels output from the switching circuit.

Description

WO g3/10606 PCr/US92/0996~

HEADEND PROCESSING FOR ~
DIGITAL TRANSMISSION SYSTEM
TECHNICAL FELD
The present inventlon generally relates to a headend processor for a digital transmission system and, more particularly, to a headend processor for supplementing or replacing program information from a remote program source with program information from a source local to the headend ~ processor. Additionally, the invention relates to a headend processor for selectively replacing control information from the remote program source ~with control information provided by a sys-tem operator at the location of the headend processor.
BACKGROUND~OF THE INVENTION
The cable~ industry is curren~tly introducing audio-only ser~,ices.
These cable "radio stations" may play a~ continuous successlon of musi-cal selections. Stations may be dedicatedj for example, to different types of music~such as~rock, jazz, blues,~easy listening, e~c. Such ser-vice may be offered as a~premium service in a cable system which also provides standard video services. ;~ ~ ~
One ~ technique ~ for~ dellverlng high ~ quallty audio-only ~services is the;use of digital audio.~ However, maintaining~a~large and diverse digi-tal audio pro~ramming~library is typically too expensive for most local system ~operators.~ Thus,~such~services may be~ provlded by~ a vendo r who~provid~digital~audio programinlng~to a number of svstem opera-tors~using,~for example~,~a sa~telli~e~sys~em. Thelocals~stem operator then need only provide~equipment for combining the digi~al audio pro-grammlng~ with~the~standard video services. ~ ~
However,~since~ the ~dlgltal aud~o~ programming is provided by a vendor at locations remote from a system operatorj the system opera-tor has limlted~con~érol~of the audio service~. ~ For example, control of subs~riber terminals ~is acoomplished via subsari~er terminal control transactions ~forwarded~ from the remote locatiQn~ This reduces the :~ : : : ::

:: ~ :;

WO 93/10606 Pl'/US92/09963 , 212~778 ability of the local operator to effectively service customer problems since the local operator will frequen~ly have to rely on the willingness of the vendor to quickly troubleshoot any problems which may arise.
Delays in servicing individual subscribers results in dissatisfaction with the local system operator.
Additionally, a local operator using digital audio programming from a remote source is limited to providing programming from this remote source. Thus, events such as concerts by local symphonies and the like which may be of interest only to local subscribers are not offered.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a meth~d and apparatus for generating and selectively substituting local subscriber terminal control transactions for subscriber terminal control transactions incorporated with programming originating at a remote program source.
It is another object of the present invention to provide a method and apparatus for adding local programming to programming originat-ing at a remote program source.
It is another object of the present invention to provide a method and apparatus for selectively combining~ a plurality of programming and control Inputs to~output a desired arrangement of the programming and control inputs. ~
Thus, in; accord~nce with the invention, a headend apparatus :
includes a first input for receiYing first channels of program informa-t ion from a f~rst program source and~a second input for receiving sec-ond channels of program information from a second program source.
The first and second channel:s of program information are applied to a switching circuit and a switch control controls the switching circuit to output third channels of program information comprising combinations of program informatlon OI the first and second channels for distribution to a subscriber~
This arrangement provides flexi~ility to a system operator who is abIe to selectively configure the channels for distribution to su~
scribers in a desired manner using a plurality of program sources.

, .

;

WO ~3/10606 Pcr/us92/0~963 Specifically, the present invention p~o~ the capability of combining programming from a remote program source with programming from a local programming source. Thus, for example, a local system operator may provide programs of local interest such as concerts to subscribers.
Also in accordance with the present invention, a headend appa-ratus includes an input for receiving channels of program and first con-trol information from a remote source and a detector for detecting the first control information. A local system control computer located at the headend apparatus generates second control information. Process-ing circuitry seleetively replaces the first control information-~ith ~he second control information.
This arrangement provides significant control capabilities to local system operators who now have the capability to con-trol local systems with a view toward enhanced customer service and an improved ability to troubleshoot problems associated with particular subscribers or groups of subscribers. Additionally, local system opera-tors are able to control subscriber terminals in a manner consistent with features and functions present in existing systems.
Also in accordance with the present invention, a headend appa-ratus includes inputs for~ receiving first and second program informa-tion from first and second program sources and inputs for receiving first and second contro! information ~from first and second control sources. ~he~ first and second program information is applied to a switching circuit ;and a switch control controls the switching circuit to output channels of program information comprising combinations of the first and~second program information for output to a subscriber.
Processing circuitry allows Sor selectively providing the first and sec-ond control information to the channels output from the switching circuit.
This arrangemenl; pr~rides maximum flexibility to a system operator who can ~onfigure the output channels and effect subscriber terminal control at the local le~el.
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete appreciation of the invention and many of the attendant advantages theleof will be readily obtalned as the invention WO 93/10606 P~/US92/09963 2123~

becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings.
Figures lA and lB are block diagrams of a digital transmission system in which ~he headend processor of the present invention may be utilized.
Figure 2 is schematic diagram of a frame format whicll may be utilized in the transmission system of Figure l.
Figure 3 is a block diagram of an audio digital encoder (ADE) illustrated in Figure lB.
Figures 4a and b are block diagrams of headend processor in accordance with the present invention.
Figure S is a block diagram of a transmit framing state machine i11ustrated in Figure 4.
DETAILED DESCRlPI ION OF THE PREFERRED EMBODII~NT
Figures lA and lB illustrate a digital communication system for transmitting digital information to one or more subscriber terminals in which the headend processor of the present invention may be utilized. Specifically, Figures lA and lB illustrate~a digital audio commumcation system, although the present invention is~ not limited in this respect. The teachings of the present invention may ~also be applled to communication systems for transmitting video, text, and other data. Digital communication system 100 includes an uplink location 101, a headend location 102, and one or more subscriber locations 103.
Uplink location 101 is a master source of digital audio program and control Information ~whlch is~ transmitted to one or more headend locations 102.~i ~ Vthff information such as~video, text, and other data~may also be tMnsmitted along with the d1gital al}dio programming and control information. Reference may be made~to commo~y assigned App1ication Serial No. 07/61~,744 for a more detailed~description of ~e operation of ~e headend location, said application incolporated herein by reference. A plurality of digital audio program sources 110 such as compact disk (CD) players are arranged at uplink ` ~ location 101. A typical uplink location may include, for example, thirty compact disk players. The~uplink location may alternatively include thirty pairs of .i~

:
SUBSTITUTE SHEET

WO 93/10606 pcr/us92Jo9963 compact disk players in order to proceed without pause from one com-pact disk or musical number to another without pause. The disk in a first player of a pair may be changed while the disk in a second player of the pair is played. The digital data streams from digital audio pro-gram sources 110 are supplied to respective digital to digital (D/D) con-verters or encoders 111 under the control of sequencing computers 112.
D/D converters 111 perform a number of operations involving the data stream supplied thereto. A time base correction corrects for time base errors caused by differences in the respective clocks of the indivi~ual digital audio program sources. D/D converters 111- compress the digital audio program information and insert error correcting codes in the data stream. The compression may be carried out using a pro-cess described in U.S. Patent No. 4,922,537, which patent is incorpo-rated herein by reference. Various error correction codes such as Bose-Chaudhuri-Hocquenghem (BCH) and Hamming codes may be utilized.
D/D converters 111 format the data stream in a frame format such as that schematically illustrated in Figure 2. ~ach frame consists of a predetermined number of bits N. Various frame formats may be . . , utilized and the format shown in Figure 2 should be viewed as merely illustrative of one such format. Frame 200 of Figure 2 includes a first subframe 201 and a second suMrame 202. Subframe~ 201 and 2û2 each contain the same number of bits, I.e., one half N/2 of the number of bits in frame 200. ~Subframes 201 and 202 include respective frame headers 203 and 204 and respective error correction and digital audio program data portions ~207 and 208. ~Frame header 203 includes channel identification data~209, frarne synchronization data 210, and scrambling data 211 for scrambling and~ descrambling. Scrambling as used herein refers to methods of ~ltering or encrypting the identity of a video or audio signal in order to pret~ent its reception by persons not having authorized~subscriber terminals. If the data stream or portions thereof are encrypted, the scrambling data 211 may include a key for decrypt-ing the data. V arious scrambling methods may be utilized and the presen~ invention is not limited in this respect. Frame header 204 includes includes channel identification data 212 and subscriber WO 93/10606 Pcr/us92/09963 2123~78 terminal control ~ransactions 213. D/D converters 111 appropriately place the digital audio program data and the error correction data within the appropriate portions of the frame, but do not provide any valid data in ~he headers. AS discussed below, the outputs of several D/D converters are multiplexed. Accordingly, the digital audio pro-gram data portio~s of frame 200 are configured to accommodate for this multiplexing. The output of each D/D converter 111 is a data stream of 1.12896 megabits per second.
System data multiplexer 113 provides overall system timing and includes a master clock which controls the output of the data streams from D/D converters 111. Multiplexer 113 time division multiplexes or interleaves the data streams of a predetermined number of D/D con-verters 111 (such as five) within the error correction and digital audio program data portions of the frame. Thus, each channel identified by the channel data in the frame headers includes five stations of audio program data. In:terleaving relates to the transmission of pulses from two or more digital sources in time-division sequence over a single path. The use of this technique in conjunction with error correcting codes can lower the error rates of communication ~hannels that are characterized by error bursts. In the interleaving process, code sym-bols are reordered in such a manner that any two successive code sym-bols are separated by I-1 symbols in the transmitted sequence, where I
is the degree of interleaving. Upon reception, the interleaved code symbols are deinterleaved or reordered into their original sequ~nce using the same degree of interleaving. Interleaving spreads or random-izes the errors~ (in time) and enables an improvement in the error cor-rec~ing capability ~of an error correcting code.
~ System da~a ~multlplexer 113 is coupled to a control computer 11~ which provides the data for frame headers 203 and 204. The data includes: channel identification data indicating the channel associated with audio program~data; frame synchronization data, which is a fixed bit pattern indicating~ the start of a frame; scrambling data used for scrambling and descrambling; and subscriber terminal control transac-tions for controlling a~ subscriber terminal at subscriber location 103.
System data multiplexer 113 inserts the frame synchronization data, ,, . . 1 ~ . . .. . . . . . ..

WO ~3/10606 PCr/~Ss~/09963 -~- 2I2~77~

the channel identification data, and the subscriber terminal control transactions into the frame headers.
Each subscriber terminal has a unique identifier or address. This address permits control computer 114 to generate and forward sub-scriber terminal control transactions to an individual subscri~er termi-nal. These transactions are known as "addressable" transactions. In some instances, a subscriber terminals control transaction may be for-warded to all subscriber terminals in the system. These are known as ~global~' transactions. Su~scri~er terminal control transactions include an address ~nd a sequence of data bits ~lnstructions) which instruct a microprocessor or a dedicated control logic of a subscri~er terminal to carry out one or more~ actions. For example, a first subscriber terminal control transaction may control the authorization/deauthorization of a particular channel. A second subscriber terminal control transaction may control the en~abling/disabling o subscriber terminal features such as remote control or digital output. Thus, subscriber transactions may control basic channel authorizations and other ~eature control.
~ ultiplexer 113 also optlonally scrambles the data stream and inserts the scrambling data into the frame header. If desired, only a portion of the data stream may be scrambled. As noted, scrambling is an option and need not be perfQrmed. System data multiplexer 113 performs a further six to one (6:1) interleave and outputs a 33.8688 megabits per second data stream containing thirty audio stations and a 33.8688 megahertz clock signal. The data stream passes through sat~l-lite~ exciter 115 ~such ~ as an offset quadrature phase shift keying (OQPSK) exciter and is~up-converted by~up-converter ll6. The result-ant signal is transmitted by antenna satellite 117 to sa~ellite 118.
The satellite transmits a signal which is received at headend location io2 shown in Figure 18. Typically, the uplink location described above serves a number of headend locations (not shown) ~: ` :
which are associated with one or more system opsrators.
The satellite sig~nal includlng the thirty audio stations is received ~1 by antenna 130 and is amplified and bloc3c converted in low noise block converter (LNB) 131. The output of I,NB converter 131 is an I,-band ~ signal at 950 to 1450 megahertz which is supplied to splitter 132.
,l ) ,~j .
~3 WO 93/10606 Pcr/us92/o9963 2 1 2 3 7 7 8 8 r ~

Splitter 132 provides the audio signal to receiver 133. Receiver 133 may, for example, be a Model 9430 data receiver available from Scien-tific Atlanta, Inc. As noted above, the uplink location may provide other signals such as video signals which are supplied by splitter 132 to other processing circuitry, e.g., video, text, data processing circuitry (not shown). Receiver 133 demodulates the signal applied thereto and recovers the 33.8688 megabits per second data stream. The data stream and a 33.8688 megahertz clock signal f rom receiver 133 applied to headend digital processor (HDP) 134. A local system control computer 135 is coupled to headend processor 134 via a serial-port and performs the overall control of the local system served by the headend location. As discussed in greater detail below, local system control computer 135 generates local subscriber terminal control transactions whi~h may be used to control the subscriber terminals serviced by the headend location.
Headend processor 134 also receives input from up to six audio digital encoders ~ADEs) 136a-136f. The audio digital encoders may be, for example, Model 9444 cd-X audio digital encoders available from Scientific Atlan~a, Inc. The audio digital encoders provide digital audio program information generated f rom analog sources local to the headend. These~ local sources may include, but are not limited to, con-certs,~ soundtracks to movies, simulcast of music events, and local radio stations. The invention is not limited to local analog program sources and local digital~audio program sources may be utilized. Each audio digital encoder;outputs ~a 5.6448 megabits per second data stream pro-viding one channel of digital audio program information, each channel including up to~;five~ stations. Thus, the local audio program informa-tion input to headend processor 134 ranges from zero to as many as thirty audio stations. ~
Headend processor 134 is capable of processing the above-identifled~inputs~in a number of ways. A firsl capability is tO add lo~ally generated audio program information from audio digital encod-ers 136a-136f ~to the digital audio program information from uplink location 101~ Another capability is to replace subscriber terminal con-trol transactions generated at uplink location 101 with subscriber WO 93/10606 PCr/US92/Og96~

terminal control transactions generated by local system control com-puter 135. Headend processor 134 is capable of receiving a plurality of programming and control inputs and combining these inputs in a desired manner. These capabilities, discussed in greater detail below, afford enhanced system control at a local level.
The channels output from headend processor 134 are respec-tively supplied to modulators 137a-137h. These modulators may be nine state quadrature partial response modulators capable of handling five stations and occupying a three megahertz bandwidth, such as Model 9450 modulators available from Scientific Atlanta, Inc. It will be apparent that phase shift key or other modulation methods may be uti-lized. Modulators 137a-1~3~h respectively digitally filter the data, mod-ulate, and convert ~the data to a~selected output frequency for combin-ing with other modulated carriers by RF combiner 138. The other mod-ulated carriers may include video, text, and other data information.
.
Each channel of five~ audio stations occupies three megahertz of band-width and can be carried in half ~of one :,ix megahertz video channel.
The signal output by RF combiner ~138 is distributed over a coax-ial cable or fiber optic distribution system to a subscriber location 103.
Reference may be made to~ commonly assigned copending Application Serial No. 07/618,~44 ~for additional descriptions of the equipment at a su~scriber location. ~ ~ The ~signal received ~ at ~subscriber location 103 is supplied to directional ~coupler ;l50. The through signal is passed to video set~ top~tèrminal~ lSl whose output is supplied~to television 152.
The~coupled slgnal~is~supplied~to a digital music terminal 153. Terminal 153~selective~y tunes~a three megahertz station containing digital audio program~informatlon~corresponding to a station seIected by the su~
scriber. The three~megahertz station is demodulated to recover syn-chronization information~ and the 5.6448 ~megabit per second data stream. An application specific integrated circuit (ASIC3 deinterleaves the~ f ive~ stations ~ containe ~d ~ln the d~ata~ stream~ of the selected channel.
The~ header information~ is recovered ~and stored in registers. If the audio data is scrambled, descrambhng is ~carried out using the scram-bling data transmitted in thé frame header. The audio data is then error corrected, decompre~ed, and formatted into two separate serial :: ~

WO 93/10606 PCr/US92109963 outputs. The data is decompressed as described in U.S. Patent No.
4,922,53~. The first output LS supplied to a DIA converter and is subse-quently output as left and right analog speaker outputs. The second output is output in the Sony-Philips digital interface format (SPDIF) which is an industry wide format for the digital interchange of digital audio information between consumer audio equipment. Digital termi-naI 153 may be addressed by an IR remote control 154. Remote control 154 may alternatively utilize RF, ultrasonic, or other transmission methods known in the art. Information may also be provided to remote control 154 as described in Application Serial No. 07/618,744. -Subscriber terminal control transactions stored in the appropri-ate register may be processed either by the microprocessor or the application specific integrated circuit. If the control transaction is addressed to that subscriber terminal or is a global transaction, actions are performed in accordance with the instructions contained in the transaction. For example, one subscriber terminal control transaction may enable the use of IR remote 154 with digital music terminal 1~3.
Another subscriber terminal control transaction may enable the SPDIF
output of digital music terminal 153. Yet another subscriber terminal control transact~on may permit a subscriber to receive a pay-per-listen event. ~ ` ~
Figure 3 is a block diagram illustrating the detailed arrangement of audio~ digital enc:oder~ (ADE) 136a shown in Figure lB. Audio digital encoder 136a irScludes f~ve A/D converters 301a-301e respectively receivlng left (L)~and right ~R) analog inputs. The outputs of A/D con-verters 301a-301e are respectively pro~ided to compression circuits 302a-302e. As at the~uplink location, compression is carried out using the technique~;descr~bed in U.S. Patent No. 4,922,537. The outpùts of compression circuits~ 302a-302e are respectively provided to BCH
encoders 303a-303e for adding error correction codes. The outputs of BCH encoders 303a-303e are supplied to multiplex circuit 304 for mul-tiplexing, f raming, and ~ f rame synchronization information under the control of a framlng ~state machine 305. Framing state machine receives clock signal CLK via buffer 430 and synchror~ization informa-tion via transmit framing state machine 416. The frame format ~:

WO 93/10606 PCr/US92/09963 - -21.2371,.~

utilized by the audio digital encoders is the same format which is illustrated in Figure 2. As noted above, the specific frame format is not critical to implemen-tation of the invention. However, the frame format used at the uplink location and the frame forrnat used by the audio digital encoders is preferably ~e same in order to minimize circuit complexit~. The frame headers of the frames output by audio digital encoders 136a-136f do not include valid data and the output data stream is not scrambled. Multiplex circuit 304 outputs a 5.6448 megabits per second data stream including up to five stations of audio information. As shown in Figure lB, six audio digital encoders may coupled to headend processor 134 to provide up to six channels of local audio program information. Since each channel may mclude up to ftve~stations, a total of up to thirty local audio stations may be input.
The audio digital encoders can be driven either by a master clock derived from the satellite signal or by a local~ clock. Smce the audio digita1 encoders may be driven by a~ local ciock, the ;headend processor need not be coupled to a satellite receiver. That is, headend processor 134 tnay be utilized by a system operator to provide~loca1;audlo mformation, even if digital audio program information from~uplink location 101 ~is not~present.
Figures`4a~and~b~are a~block;diagram of headend processor 134 in accordance w~ith ~the present~ invention. ~ The 33.8688 megabits per second datastream~and a~33.8688~ clock~signal *om~receiver 133;~are input to ECL buffer or interface~level r~nverter~401 Buffer 401~ and a 33~.8688 megahertz local clock ; 402~are coupled ~to~a~ ;clock ~select circuit 403 ~whlch outputs an 11.2896 megaliertz ~lock signal CLK;derived~ from ei~ther~e input data stream or ~e local c1Ock 402.~; The clock signal CLK provides an overall timing signal. The data stream from ~buffer~ s supplied to synchronization detector 404 for detecting~tl~e~franie~syncl~onization data in the data stream. The sync detect signal ~is a1so suppliéd~to receive frame state rnachine 406 and to transmit frame state machine 416 às described in greater detail below. An audio digita1 encodersynchronization signal Is~ supplied to framing state mac~ine 305 of audio digital encoders 136a-136f from transmit frame state machine 416.

, SUBSTlTUTE SHEET

WO 93~10606 Pcr/us92/o9963 212377~
The data stream is deinterleaved by deinterleave circwt 405 to produce six channels CH0, CH1, CH2, CH2, CH3, CH4, CH5. Each of these channels is a 5.6448 megabits per second data stream and includes five stations. One of the channels, e.g., CH0, is su'pplied to receive framing state machine 406 which permits recovery of su~
scriber terminal control transactions and scrambling data provided from uplink location 101. The recovered subscriber transactions and the scrambling data are respectively stored in registers 407 and 408.
The operation of receive framing state machine 406 and transmit fram-ing state machine 416 will be discussed in greater detail bel~w with reference to Figure ~. The scrambling data in reg~ster 408 is utilized by descrambling circuit 409 to permit descrambling of the scrambled portions of the incoming data stream. Microprocessor 410 examines register 407 to recover subscriber ~control transactions.
The data streams from audio digital encoders 136a-136f are pro-~,ided to respective interface level converters or buffers 411a-411f.
, Buf f ers 411a-4 l lf may~ comprise, for example, EIA RS-422 level con-vèrters. The ~outputs~ol buffers 411a-411f constitute channels CH6, CH7, CH8, CH9~ ~CH10, ~and CH11. ~The data streams of channels CH0-CH11 are~ ~suppiied ~ to serial-in~ parallel-out shift registers 412a-4121. In a~ présent~ embodiment, shift registers 412a-412f are five bit shift registers which serve;to demultiplex or deinterleave the five stations of ~ each~channel.~ Five ~bits Irom each of the channels CH0-CH~1 are~ shif~ted~in;~to~registers~412a-412e. Accordingly, data from up to sixty~ input stations ~are~available~in parallel. The parallel data of these~ input~ stations may be routed to any of parallel-in serial-out shift régisters~414a-414h 1n accordance with the settings of switch~ 413;.~ ~Switch~ 413~ is~ preferably ~a ~64 x~64 crosspoint switch and permits data~at ~any~ of its 'sixty-four input terminals ta be directed to one~ or more of ~lts six~ty1Our output~ terminals. Other switching mecha-nisms such as~ a tlme- slot~interchange switch may be utilized and the present ~invention~is~not limlted;in this~respect. The output terminals of'switch 413~are respectively~;coupled~to~shift registers 414a-414f.
Thus, the parallel data of shif~t registers 412a-412f may be routed to any ~ one~ or more;~ of shitt;;~registers~4~4a-414f. Shift registers 414a-414f :~

WO g3/10606 PCr/US92/09g63 comprise five bit shift registers in the present embadiment. It is noted that in a present embodiment, twelve shift registers 412 and eight shift registers 414 are utilized, but the present invention is not limited in this respect. ~t will be seen that when the input data is routed to shift registers 414 and subsequently shifted out to scramble and encode cir-cuits 415a-415h, the audio data is multiplexed or interleaved. Since registers 414 are five bit shift registers, a five to one (5:1) interleave is performed and thus each output channel CH0-CH7 includes audio pr~
gram information from five stations. It will be apparent that since the settings of the crosspoint switch are determined locally, a system oper-ator may configure output channels CH0-CH7 in any desired manner.
The above-described inputs total sixty audio stations in a maximum configuration. From these, a minimum of five and a maximum of forty may be output in the present embodiment. These stations may be cho-sen in accordance with the wishes of a local system operator. That is, ; ~ for each output~ channel that is used, any arbitrary combination of five input stations may be selected and placed in any order. Input stations may be appear in more than one output channel and may even be repeated within a~ single channel for, for example, system diagnastic purposes.
The desired configuration is determined via local system control computer 135. The~conIiguration is provided~to microprocessor 410 and is stored in non-volatile~RAM;422. In the event of an interruption in power, microprocessor;410 retrieves the stored configuration and can-figures switch~ 413~in;accordance with the stored configuration. EPROM
421 stores program~ information for~use by the microprocessor.
The outputs af ;registers 414a-414h are provided to scramble and encade clrcults~415a-415h. Scramble and encode circuits 41~a-415h respectively, ~scramble and ~encode the serial data streams from regis ters 414 prior to transmission to subscriber location 103. The encoding utilizes the~same frame format as that of the uplink location. How-ever, the headend processor of the present invention allows for local information to~be mserted mto several portions of the frame format shown in Figure 2. Thus, the channel identification correspanding to the output channel, subscriber terminal control transactions, and :::

WO g3/10606 PCI/US9~/0996 2.12:~778 scramb~ing data may be generated at headend location 102 asld inserted at the appropriate times into the frame format. The channel identifi-cation data is provided to channel registers 419a-419h from micropro-cessor 410. The timing for such functions is provided by transmit frame state machine 416 and will be discussed in greater detail below.
As noted above, subscriber terminal control transactions trans-mitted from uplink location 101 are placed in register 407. In a first mode, headend processor 134 includes these control transactions on the output channels CH0-CH7. In the first mode, microprocessor 410 retrieves the subscriber transaction from register 407 and supplies the tran~action to subscriber register 420. At the appropriate time in framing the output channels CH0-CH~, the contents of this register are retrieved by scramble and encode circuits 415a-415h to provide sub-scri~er terminal control transactions for the output channels. In a second mode, subscriber terminal control transactions are generated by local system controI computer 135 and are provided to microprocessor 410 via serial ports 424. In thls mode, microprocessor 410 writes the subscri~er terminal transaction provided by the computer 135 to sub-scriber register 420. Again, at the appropriate time in framing the ; ~ output channels CH0-CH~, the contents of this register are retrieved by scramble and~ encode circuits 415a-415h to provide su~scriber termi-nal control transact}ons for the output channels.
; The speclflc format of; the subscriber transactions and the num-ber and typ~ ~utilized may be varied and the present invention is not limited in this respect. I t ~is only required that the subscriber terminal be able to~recognize and~ act on the sub6criber transactions and the present invention is~n~t llmited to specific ~implementations for achiev-ing this result.~
It is noted that ~the headend location itself includes an address and may be responsive to a limited number of transactions from uplink locatlon lOl. In this instance,~mlcroprocessor 410 examines the con-trol transactions~stored in~regis~er 407~ to determine if, in fact, the transaction is addressed to the headend itself~ If S07 microprocessor 410 processes ~and~acts~on the instructions. These transactions are capable of controllmg an overall enable/disable for all uplink stations : : . :

: : :

WO 93/10606 Pcr/us92/09963 2~2;377~
provided to the headend processor as well as controlLing individual sta-tions which the headend processor ~s authorized to receive. Channel enable/disable transactions addressed to the headend processor itself have no effect on any channels that are originated from the local audio digital encoders.
R~turning to Figures 4 a ar~ b, scrarrbling data may, for ex~T~le, be generated by a psuedo-random binary sequence generator 425. Thus, the scrambling ~data~ used to scramble the output channels of the headend processor is different than the scrambling data used to scram-ble the data at the uplink location. A scrambling technique different than that used at the uplinl~ location may also be implemented by the local system operator. This further enhances control by the local sys-tem operator.
The outputs of scramble and encode circuits 415a-415h are pro-vided to buffer circuits 417a-~17h. Buffers 417a-417h may, for exam-ple, be EIA RS-422~1eVel converters. Buffer circuits 417a-417h are coupled to modulators~ 13.~a-137h; of Figure lB.
Figure 5 illustrates ~transmit frame state machine 416 which may be utilized in headend processor 134 of the present invention. The state machine~fùnctions ~to keep track of the data stream in order to determine the~location in~a frame at a given instant of time. Toward this end,~state~machine Includes~a~sixteen b~t mod N counter 501, where~as~noted above~N is~the number~of bits per frame. The reset input of cauntèr~501~is;coupled eo~sync~detector 404 which resets the counter ~when~ a~ new ~ ~rame IS started ~so as to maintain synchronization between;the~data~f~rom~upllnk~ location 101 and the output channels of the~headend~processQr il thé satellite~signa~l~ is present. If the satellite signal~ls not~prése`nt~ trar~smit frame state mach~ne~416 is free-running.
Counter 501~also~receives a~5.64~8 megahertz clock signal correspond-ing to the data~ rate of the output channels CH0-CH7. Counter 501 maintains a coun;t~corr:esponding to bit~position within a frame, the count being'~incremented~by the~application~ of the 5.6448 megahertz clock signal.~ The~count o~ the counter is provided to sixteen output lines and is~uséd ~to~drive a~decoder 502 including an arrangement of logic gates. The count;~ on' counter ~S02 determines the inputs to the : `
::

WO 93/10606 Pcr/us92/09963 logic gates. Based on these inputs, decoder 502 outputs signals to J-K
flip flops whose Q and /Q outputs are used to generate timing signals for the headend processor. For example, when the count of counter 501 represents the fram~ portion corresponding to channel identifica-tion data, a signal from state machine 416 to scramble and encode cir-cuits 415a-415h causes the contents of channel registers 419a-419h to be incorporated into the output channels. Similarly, when the count represents ehe frame portion corresponding to scrambling data, state machine 416 causes scramble and encode circuits 415a-415h to examine the scrambling data generator 425 and incorporate the ~sequence obtained into the output channels. Receive frame state machine 406 and framing state machine 305 are similarly configured.
Thus, in accordance with headend processor 134, a first input receives first channels of dlgital program information from a remote uplink program source and a second input receives second channels of digital program information from a local program source. rhe first and second channels of digital information are applied to the crosspoint switch. In accordance ~with the set~ings of the crosspoint switch, an output~ channel~arrangement may ;be delermined by a local system oper-ator. The system operator~;may utillze a ~local system control computer which interfaces~with a mlcroprocessor of the headend processor to configure the~cro~spoint swltch to provide the desired output channe arrangement.
This capabiIity~provides~flexlbility to a system operator who is able~to selectively~conflgure the~channels for distribution to a sub-scriber~in a;deslred~ manner~ using a~ plurality of program sources. Spe-cifically, ~the~present~invention provides the capability of combining programming~from~a;remo~e~program source with programming from a local programming souroe.~ Thus, the local system operator is not lim-ited to provided only~those audio programs provided from the remote uplink location,~but~ able to mclude audio programs of local interest.
These local audio~ programs may be combined with or substituted for audio programs provided from the remote uplink location in any desired manner so that,~for~example, stations appealing to particular groups of subscrlbers may be~included ~in the same channel.

::: :

WO 93/10606 Pcr/us92/09963 ; l 212377~

The headend processor of the present invention receives chan-nels of program and first control information from the remote uplink location and detects the first control information from the incoming data stream. The local system control computer at the headend pro-cessor location generates second control information. The first control information from the remote uplink location may be selectively replaced with the second control information from the local system control computer.
This arrangement provides significant control capabilities to local system opeF~ators who are provided with the capability of-control-ling local systems with a view toward enhanced customer service and an improved ability to troubleshoot problems associated with particular subscribers or groups of subscriffbers. Additionallyj local system opera-tors are able to'control subscriber terminals in a manner consistent with features and functions present in existing systems.
The headend processfor receives first and second program infor-mation from flrst and second program sources and first and second control information from first and second control sources. The first and second program informatlon is appli:ed~ to the crosspoint switch. In accordance with the configuration as determined by the local system operator, program information comprising combinations of the first and second program information are output to a subscriber. Processing circuitry allows~ for selectively~ providing the first and second control information to the~channels~output from the switching circuit. This arrangement provides maximum flexibility to a system operator who can~configure;the output~channels and effect subscriber terminal con-troi at the local level. ~
It is to;be~un~erstood thatlthe lnvention is not limited to the illustrations d~scribed~and shown `herein which are deemed to be merely illustrative. For~example, the above teachings may be applied to video, text,~ other data~and various combinations o~ video, audio, text, and other data. The ~invention~rather is intended to encompass all such modifications;which~are~within its spirit and~scope as defined by the appended claims.~

Claims

WE CLAIM:

1. A headend apparatus comprising:
a first input for receiving one or more first digital channels of program information from a first program source;
a second input for receiving one or more second digital channels of program information from a second program source;
a switching circuit to which the first and second digital channels of program information are applied; and a switch control for controlling said switching circuit to output third channels of program information comprising combinations of program information of the first and second digital channels for distribution to a subscriber.

2. The headend apparatus according to claim 1 wherein said first program source comprises a remote program source.

3. The headend apparatus according to claim 1 wherein said switching circuit comprises a crosspoint switch.

4. The headend apparatus according to claim 1 wherein said first input receives first interleaved channels of multiplexed digital program information.

5. The headend apparatus according to claim 4 further comprising:
a deinterleave circuit for deinterleaving the first interleaved channels of digital program information.

6. The headend apparatus according to claim 4 wherein said second input receives second channels of interleaved digital program information.

7. The headend apparatus according to claim 6 further comprising:
a demultiplexing circuit receiving the interleaved digital program information of the first and second channels and outputting demultiplexed station information to said switching circuit.

8. The headend apparatus according to claim 7 further comprising:
multiplexing circuits coupled to the output of said switching circuit for multiplexing the station information from said switching circuit to the third channels for distribution to a subscriber.

9. The headend apparatus according to claim 1 wherein said switch control comprises a microprocessor.

10. The headend apparatus according to claim 1 further comprising:
a non-volatile memory for storing a configuration of said switching circuit as determined by said switch control.

11. The headend apparatus according to claim 1 wherein the program data of the first and second digital channels includes digital audio information.

12. A headend apparatus comprising:
an input for receiving channels of program and first control information from a remote source;
means for recovering the first control information from the received channels;
means for generating second control information; and means for selectively replacing the first control information with the second control information.

13. The; headend apparatus according to claim 12 wherein said input receives interleave channels of digital program and first control information.

14. The headend apparatus according to claim 13 further comprising:

a deinterleave circuit for deinterleaving the interleaved channels of digital program and first control information.

15. The headend apparatus according to claim 12 wherein said means for generating second control information comprises a local system control computer.

16. The headend apparatus according to claim 15 wherein said means for selectively replacing the first control information comprises a microprocessor coupled to said local system control computer.

17. The headend apparatus according to claim 12 wherein said means for recovering the first control information comprises:
a receive framing state machine synchronized to the input program and first control information.

18. A headend apparatus comprising:
inputs for receiving first and second program information from first and second program sources;
inputs for receiving first and second control information from first and second control sources;
a switching circuit to which said first and second program information is applied;
a switch control for controlling said switching circuit to output channels of program information comprising combinations of the first and second program information for output to a subscriber; and means for selectively providing the first and second control information to the channels output from said switching circuit.

19. The headend apparatus according to claim 18 wherein said switching circuit comprises a crosspoint switch.

20. The headend apparatus according to claim 18 wherein said inputs include an input receiving first program and first control information from a remote program and control source

21. The headend apparatus according to claim 20 wherein said first program and control information comprise interleaved channels of multiplexed first program and first control information.

22 The headend apparatus according to claim 21 further comprising:
a deinterleave circuit for deinterleaving the interleaved channels.

23. A method of generating output channels for distribution to subscribers comprising the steps of:
receiving first channels of program information from a first program source;
receiving second channels of program information from a second program source; and generating third channels of program information comprising combinations of program information of the first and second channels.

24. A method of generating output channels containing control information for distribution to subscribers comprising the steps of:
receiving channels of program and first control information from a remote source;
recovering the first control information;
generating second control information; and selectively replacing the first control information with the second control information.

25. A method of generating output channels containing program and control information for distribution to subscribers comprising the steps of:
receiving first and second program information from first and second program sources;
receiving first and second control information from first and second control sources;
generating output channels of program information comprising combinations of the first and second program information; and selectively providing the first and second control information to the channels output from said switching circuit.

26. A headend apparatus, comprising:
inputs for receiving first and second program information from first and second program sources;
inputs for receiving first and second control information from first and second control sources;
a switching circuit to which said first and second program information is applied;
a switch control for controlling said switching circuit to output channels of program information comprising combinations of the first and second program information for output to a subscriber;
means for selectively providing the first and second control information to the channels output from said switching circuit; and a scrambler for scrambling the channels output from said switching circuit.

27. A headend apparatus, comprising:
inputs for receiving first and second program information from first and second program sources;
inputs for receiving first and second control information from first and second control sources;
a switching circuit to which said first and second program information is applied;
a switch control for controlling said switching circuit to output channels of program information comprising combinations of the first and second program information for output to a subscriber;
means for selectively providing the first and second control information to the channels output from said switching circuit;
wherein said inputs include an input receiving first of first program and first control information from a remote program and control source; and a descrambler for descrambling program information from said remote program and control source.

28. A headend apparatus, comprising:
a first input for receiving one or more first digital channels of program information from a first remote program source;
a second input for receiving one or more second digital channels of program information from a second program source;
a switching circuit to which the first and second digital channels of program information are applied;
a switch control for controlling said switching circuit to output one or more third digital channels of program information comprising combinations of program information of the first and second channels for distribution to a subscriber; and a descrambler got descrambling program information from said first remote program source.

29. A headend apparatus, comprising:
a first input for receiving one or more first digital channels of program information from a first program source;
a second input for receiving one or more second digital channels of program information from a second program source;
a switching circuit to which the first and second digital channels of program information are applied;
a switch control for controlling said switching circuit to output one or more third digital channels of program information comprising combinations of programinformation of the first and second channels for distribution to a subscriber; and a scrambler for scrambling the third channels.

30. A headend apparatus, comprising:
a first input for receiving one or more first digital channels of program information from a first: program source;
a second input for receiving one or more second digital channels of program information from a second program source;
a switching circuit to which the first and second digital channels of program information are applied;
a switch control for controlling said switching circuit to output one or more third digital channels of program information comprising combinations of programinformation of the first and second channels for distribution to a subscriber;
wherein said first input receives interleaved channels of multiplexed digital program information comprising a 33.8688 megabits per second data stream.

31. A headend apparatus, comprising:
a first input for receiving one or more first digital channels of program information from a first program source;
a second input for receiving one or more second digital channels of program information from a second program source;
a switching circuit to which the first and second digital channels of program information are applied;
a switch control for controlling said switching circuit to output one or more third digital channels of program information comprising combinations of program information of the first and second channels for distribution to a subscriber;
wherein said first input receives first interleaved channels of multiplexed digital program information; and a 1:6 deinterleave circuit for deinterleaving the first interleaved channels of digital program information and outputting six channels of digital program information, each channel comprising a 5.6448 megabits per second stream.

32. A headend apparatus, comprising:
a first input for receiving one or more first digital channels of program information from a first program source;
a second input for receiving one or more second digital channels of program information from a second program source;
a switching circuit to which the first and second digital channels of program information are applied;
a switch control for controlling said switching circuit to output one or more third digital channels of program information comprising combinations of program information of the first and second channels for distribution to a subscriber;
wherein said first input receives first interleaved channels of multiplexed digital program information and said second input receives second interleaved channels of multiplexed digital program information;
a demultiplexing circuit receiving the interleaved digital program information of the first and second channels and outputting demultiplexed station information to said switching circuit;
multiplexing circuits coupled to the output of said switching circuit for multiplexing the station information from said switching circuit to the third channels for distribution to a subscriber; and a scrambler for scrambling the third channels.

33. A headend apparatus, comprising:
a first input for receiving one or more first digital channels of program information from a first program source;
a second input for receiving one or more second digital channels of program information from a second program source;
a switching circuit to which the first and second digital channels of program information are applied;
a switch control for controlling said switching circuit to output one or more third digital channels of program; information comprising combinations of program information of the first and second channels for distribution to a subscriber;
wherein said first input receives first interleaved channels of multiplexed digital program information of the first and second channels and outputting the demultiplexed station information to said switching circuit; and multiplexing circuits coupled to the output of said switching circuits for multiplexing the station information from said switching circuit to the third channels for distribution to a subscriber

34. A headend apparatus, comprising:
a first input for receiving one or more first digital channels of program information from a first program source;
a second input for receiving one or more second digital channels of program information from a second program source;
a switching circuit to which the first and second digital channels of program information are applied;
a switch control for: controlling said switching circuit to output one or more third digital channels of program information comprising combinations of program information of the first and second channels for distribution to a subscriber;
wherein said first input recess first interleaved channels of multiplexed digital program information and said second input receives second interleaved channels of multiplexed digital program information;
demultiplexing circuits receiving the interleaved digital program information of the first and second channels and outputting demultiplexed station information to said switching circuit; and multiplexing circuits, comprising shift registers, coupled to the output of said switching circuit for multiplexing the station information from said switching circuit to the third channels for distribution to a subscriber.

35. The headend apparatus according to claim 34 wherein each digital channel comprises five stations of interleaved digital program information.