CA2131668A1 - Isolation Structure Using Liquid Phase Oxide Deposition - Google Patents

Isolation Structure Using Liquid Phase Oxide Deposition

Info

Publication number
CA2131668A1
CA2131668A1 CA2131668A CA2131668A CA2131668A1 CA 2131668 A1 CA2131668 A1 CA 2131668A1 CA 2131668 A CA2131668 A CA 2131668A CA 2131668 A CA2131668 A CA 2131668A CA 2131668 A1 CA2131668 A1 CA 2131668A1
Authority
CA
Canada
Prior art keywords
isolation structure
trench
oxide
liquid phase
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2131668A
Other languages
French (fr)
Other versions
CA2131668C (en
Inventor
Carol Galli
Louis L. Hsu
Seiki Ogura
Joseph F. Shepard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2131668A1 publication Critical patent/CA2131668A1/en
Application granted granted Critical
Publication of CA2131668C publication Critical patent/CA2131668C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

Abstract

A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.
CA002131668A 1993-12-23 1994-09-08 Isolation structure using liquid phase oxide deposition Expired - Fee Related CA2131668C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US173,396 1988-03-25
US17339693A 1993-12-23 1993-12-23

Publications (2)

Publication Number Publication Date
CA2131668A1 true CA2131668A1 (en) 1995-06-24
CA2131668C CA2131668C (en) 1999-03-02

Family

ID=22631817

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002131668A Expired - Fee Related CA2131668C (en) 1993-12-23 1994-09-08 Isolation structure using liquid phase oxide deposition

Country Status (7)

Country Link
US (1) US5516721A (en)
EP (1) EP0660390A3 (en)
JP (1) JP2804446B2 (en)
KR (1) KR0167813B1 (en)
BR (1) BR9405158A (en)
CA (1) CA2131668C (en)
TW (1) TW265457B (en)

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Also Published As

Publication number Publication date
JPH07201979A (en) 1995-08-04
JP2804446B2 (en) 1998-09-24
EP0660390A3 (en) 1997-07-09
US5516721A (en) 1996-05-14
KR950021405A (en) 1995-07-26
BR9405158A (en) 1995-08-01
EP0660390A2 (en) 1995-06-28
CA2131668C (en) 1999-03-02
TW265457B (en) 1995-12-11
KR0167813B1 (en) 1999-02-01

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