CA2134019C - Solder ball connections and assembly process - Google Patents

Solder ball connections and assembly process

Info

Publication number
CA2134019C
CA2134019C CA002134019A CA2134019A CA2134019C CA 2134019 C CA2134019 C CA 2134019C CA 002134019 A CA002134019 A CA 002134019A CA 2134019 A CA2134019 A CA 2134019A CA 2134019 C CA2134019 C CA 2134019C
Authority
CA
Canada
Prior art keywords
contacts
metal
joining
substrate
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002134019A
Other languages
French (fr)
Other versions
CA2134019A1 (en
Inventor
John Acocella
Donald Ray Banks
Joseph Angelo Benenati
Thomas Caulfield
Karl Grant Hoebener
David Paul Watson
John S. Corbin, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2134019A1 publication Critical patent/CA2134019A1/en
Application granted granted Critical
Publication of CA2134019C publication Critical patent/CA2134019C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/42—Printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0215—Metallic fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10234—Metallic balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10992—Using different connection materials, e.g. different solders, for the same connection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0415—Small preforms other than balls, e.g. discs, cylinders or pillars
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0455—PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/082—Suction, e.g. for holding solder balls or components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Geometry (AREA)
  • Combinations Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Pens And Brushes (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

High melting temperature Pb/Sn 95/5 solder balls ale connected to copper pads on the bottom of a ceramic chip carrier substrate by low melting temperature eutectic Pb/Sn solder. The connection is made by quick reflow to prevent dissolving Pb into the eutectic solder and raising its melting temperature. Then the module is placed on a fiberglass-epoxy circuit board with the solder balls on eutectic Pb/Sn solder bumps on copper pads of the board. The structure is reflowed to simultaneously melt the solder on both sides of the halls to allow each ball to center between the carrier pad and circuit board pad to form a more symmetric joint. This process results in structure that are more reliable under high temperature cycling. Also to further improve reliability the balls are made as large as the I/O spacing allows without bridging beam on balls; the two pads are about the same size with more solder on the smaller pad; the pads are at least 75% of the ball diameter; and the eutectic joints are made as large as possible without bridging between pads. For reliability at even higher temperature cycles or larger substrate sizes columns are used instead of balls.

Description

~ ~ 3 4 ~ ~ 9 1 SOLDER BALL CONNI~CTIONS AND ASSEMBLY PROCESS

FIELD OF THIS INVENTION
This invention relates to surface mount solder connections using HMT (high melting temperature) metal-balls between an grid of contacts on a component and a mirror image array of contacts of an eleetrieal intereonneet strueture and more speeifically to the eomposition of the HMT solder balls and LMT (low me]ting temperature) solder joining the balls to the contacts, the speeifie geometry of the connections, FR-4 (glass and epoxy) cireuit boards and MLC
10 (multi-layer ceramie) ehip carriers for such interconncctions, the processes for producing the boards and carriers, and the process for attaching the carriers to the boards.

BACKGROUND OF THIS lNVENTlON
Solder-ball conneetions have been used for mounting lCs (integrated eomputer ehips) using the C-4 (eontrolled eollapse ehip eonneetion) teehnology since first deseribed in U.S. patents 3,401,126 and 3,429,040 by Miller. Paekaging Electronic Systems by Dally (MeGraw-Hill 1990 p. 113) deseribes flip ehip or C-4 eonnections. In Dally, "Chip bond pads are deployed in an area array over the surface of the chip.... These bonding pads are 5 mil in diameter on l 0 mil centers.
Matehing bonding pads are produced on a ceramic s~lbstrate so that the pads on the chip and 20 the eeramie eoineide. Spheres of solder S mil in diameter are plaecd on the eeramie substrate pads ... and the ehip is positioned and aligned relative to the substrate. The assembly is heated until the solder spheres begin to soften and a eontrolle(l collapse of the sphere takes plaee as the solder simultaneously wets both l~ads. A myria(l or sol(lel strllctures have been proposed for mounting IC chips as well as for interconnecti()n to otller Ievels of cireuitry and electronie paekaging."

"Ball Grid Arrays: The Hot New Paekage" hy Terry Costlow and "Solder Bàlls Make Conneetions" by Glenda Derman both in Electronic Engineering Times March 15, 1993, describe using solder balls to connect ceramic or flexible chip carriers to circuit boards.

d~. ~L

~ ~ 3 ~

U. S. patent 4,132,341 to Bratschum describes the self-centering action of conduetors spanning between solder pads of two components when botll pads are simultaneously reflowed. U.S.
patent 4,831,724 describes the self-centeling of a component when it i.s vibrated during reflow.

Fabrication of multi-layer ceramic ehip earriers is desel ihed in U.S. patents 3,51 ~,756; 3,988,405;
and 4,202,007 as well as "A Fabrieation Technique For Multi-Layer Ceramie Modules" by H.D.
Kaiser et al., Solid State Technology, May 1~72, pp. 35-40 and "The Third Dimension in Thiek-Films Multilayer Teehnology" by W. L. Clough, Mieroeleettonies, Vol. 13, No. 9 (1970), pp. 23-30.
Fabrieation of multi-layer eireuit boards is clesel ibed in U.S. pat,ents 3,554,877; 3,791,858; and 3,554,877. Thin film teehniques are deseribed in U.S. patent 3,791,~52.

U.S. patent 4,604,644 to 13eekl1am descrihes materials and structures for encapsulating C-4 eonneetions. U.S. patents 4,701,482 to Itoh and 4,99~,699 to Christ;e ct al. diselose epoxies and guidanee in seleeting epoxies for electronic applications.

Flexible film chip carriers (known in the alt as ATAB) are descl-ibed in U.S. patents 4,681,654;
4,766,670 and 5,159,535. In ATAB (ar-ea tape automaled bolldillg) a flexible eircuit board ehip 20 carrier is mounted on a cireuit board using soklel--ball conneel.

U.S. patent 5,147,084 to Behun, desctibes u~ing a ~IMP (high melting point) solder ball in association with a LMP (low melting poinl) sl)l(ler. F~TC IA of that patent is similar to FIG 4 of this applieation. "A part 10 is to be joine(l to a boal(l 11. Part 1() has hlternal metallurgy 14 whieh terminates a,t the surfaee at a bon(lillg pads 12. A ... LMP ~older 16 isapplied to a bonding pad 12. A ... HMP soldcr ball 1~ is placcd in contact with LMP solder 16 and the assembly is heated to reflow lhe LMP soldel which lhen wets to the non-molten HMP solder ball.... Board 11 is al~so illustrated wilh internal metallurgy 15, terminating on the surfaee bonding pad t7.... the assembled patt 1() ... is brought into contaet with part I I having pad 17 -~, ~ ~ 3 ~

and LMP solder 13, and the two are heated to a temt erature sumcient to reflow the LMP solder but not sufficient to melt the HMP sol(ler ball. The LMP solcler 13 which is attached to the bonding pacl 17, on board l l, will wet the HMP ball and connection will be achieved."

OBJECrS OF THIS INVENTION
Therefore, it is an object of this invenlion to provi(ie a process for manufacturing a rcliable interconnect assembly using ball connection.

More specifically, it is an object to connect two tigid, confrollting substrates using HMT
10 solder-ball connections to form an eleclronic packaging structure.

It is another object of this invention to provi(le a mcthod of reflow soldering to produce solder-ball connections.

It is another object of this invention to provide methods for producing a component for solder-ball connection.

It is another object of thi~s invention lo provi(le methods of llositioning solder-balls on such a component and re~low joining solcler l-alls to the com~-oncJlt fol ~lse in solder ball connection.
It is another object of this invcntion to r~rovide a metl1o(1 of selecting HMT solder-ball size, selecting contact size, and selecting LMl sol(ler voll~me.

It another objcct of this invention ~o r)rovi(le a melho~l Of r~roducing metal contacts on substrates for solder-ball connection.

Furthermore, it is an object of this hlvelllioll lo r~rovi(le a Ieliahle inteleollnect assembly in whieh HMT metal-balls are connccled belween mirror image arlays of contacts of two rigid, confronting substrates.

~ 34 ~ ~

It is more specif;ca]ly an object of this ;nvention to define reliable LMT solder joint configurat;ons between the balls and contacts.

It is another object of this invention to define ball sizes and contact sizes required for reliable connection.

It is another object of this invention to define HMT l~all malerials and LMT solder materials which permit reliable connections to be made.

10 It is another object of this invention to derille subslrates which may be used for reliable HMT
solder-ball connection.

It is another object of this invelltion to define structules in a s,llrrace wiring layer of a substrate to connect between PTHs (plated through-holes) and connection pads for controlling I MT solder volumes for the joints between the pacls and 11MT solder-balls.

Finally, it is an object of this hlvention to describe an information handling system using the connections of the system.

In this invention of applicants" it was discovel ed that sol(ler-ball connections between confronting metal contact grids on rigi-l substr3les which were ma(le USillg a process similar to that which was used for ATAB were not r eliable dlle to lhCI mal latiguc ot' the solder joints between the balls and the contacts. It was discovere(l thclt the jOitlt!7 were not all symmetrical due to mis-registration of contacts (allowable toler.lnces in cont~ct location) causing misalignment between confronting contacts" ancl that the joints could be ma(le more symmetrical and more reliable by simultaneously reflowil1g the top and hottom LMT ~,ol(ler joints between each HMP
metal-ball and both respective contacts of the ball. Thi', allows the balls to be moved by surface tension of the melted solder to more sylllmetrical positions bet~een the centers of the contacts 4 ~ ~ ~

within the plane defined by the arl-ay of the soldcl- balls.

It was discovered that making the l alls larger recluces fatigue, but that the size of the balls is constrained by the specifiecl interconnection spacing and a nominal spacing between balls necessary to reliably prevent electrical connection from (Ieveloping between the balls. Similarly, it was discovered that making the contacts larger tcducc.~i fatigue, but the size of the contacts are constrained by the specified interconnect spacing and the nominal spacing between contacts necessary to reliably prevent eleclrical connection l'rom developing bctween contacts (e.g. solder bridging). For re]iable int~rconnections ratigue is mitlimize(l by making the balls slightly smaller 10 than the spacing between contacts and making lhe contacts slightly sma]ler than the balls. ~t was discovered that the reliability Of the COllllCCtiOIlS were affecled by the relative size between the contacts on either side of each ball and that fatigue could be minimized by making the contacts equal sized. It was discovere(l that ratigue could be minimize(], rOr different sized contacts on each side of the ball, by making the solder volume larger for the joint with the smaller contact.

It was discovered that increasing the CIOSS section Of the solder joints reduced fatigue but the volume increase is constrained by the nece~sity 1(1 r eliably prevent solder bridging from developing between adjacent balls and between ,Idj.lcellt contacts. Finally it was discovered that reducing the cross section of the soldel joints below about 2/3 of the diameter of the ball has a 20 remarkably deleterious effect on the faligue life of thc conncclion.

The invention of applicants inclu(les a plOCCSS fOr plo(lllcing an interconnect structure, comprising the steps of:
producing a rigid substrate with 311 apr)roxilllalely planel~ matrix of multiple, metal contacts on a major surface;
depositing a volume of a joining-tnatcl ial 011 cach Or tllc contacts of the matrix of the rigid substrate;
positioning a conductive metal-ball on the joining-material on each of the contacts on the first substrate to define a plane of mc~al-balls fOr maintaining a pledetermined distance between EN9-93-055 ~
the substrate and a second substrate to whicil the substrate is to be connected;melting the volumes of joining-material without melting the metal-balls to prevent changing the shape of the balls; and cooling the joining-matcrial to fortn a soli(l mechanical joint between the metal-balls and the contacts of the first substrate.

The process for producing an interconrlect stl~ucture, in which there is a metal element which can migrate between the metal-balls and lhe joining-material ancl increase the melting temperature of the joining-material and thc step of mel~ing i.s performc<l at a minimum temperature and for a minimum time required to prOduce reliable joints ror minimizing migration of metal elements between the metal-balls and first joining-malerial lo minimize the increase of the melting temperature of the joining-material.

The process for producing an intercorlnecl structule~ rutthel includi]lg the steps of:
selecting the size of the metal-balls slightly smaller than the spacing between the balls to maximize the size of the balls to minimize fatigue hl the joints; and selecting the size ~f the contacts:
slightly smaller than the size of lhe metal-halls as reguired l.o prcvent joining-material from bridging between contacts; and for confronting contacts, approximately equal in size to minimize fatigue in the joints.

The process for producing an inlelcollnect slluct~lte, furthel hlcluding the steps of:
selecting ceramic for the materi.ll of the rigi(l .sllbs~late;
selecting copper for the material t-f tlle contacls; alld selecting a LMT (low melting ~emperature) solder alloy as the joining-material and a HMT (high melting tempcrature) solder ~or the metal-balls.

The process for produc;ng an intercollnecl structule, Further including the step of selecting re-enforced epoxy for the material ol' the r igid subslralc.

The process for producing an interconnecl structule, in whicll the step of producing a rigid substrate includes the steps of:
producing mult;ple green sheets of gla~s/ceramic parliclcs and an organic binder;
making via holes in the slleets;
screen pr;nting conductive matcrial ;nto the holes and onto one of the surfaces of the sheets to form a conductive pattern including the att.ly Or tOUIl(l contacts;
pressing the sheets together into a stack;
sintering the stack of sheets in an oven lo rOrll1 a m~llti-layer ceramic chip carrier with an array of copper contacts on a major SUI face which are about 0.7 mm in diameter, and are spaced 10 about 1 25 mm apart;
selecting eutectic ( about 37/(~ ercent ) Pb/Sn soldet- alloy for the joining-material;
selecting a material of aboul 9()~/O to abollt 95')/., Pb soldel- alloy and a size of about 0 9 mm for the mctal-balls.

The process for producing an interconnect structure, further including the step of depositing sticky flux onto the contacts befol-e positiolling the melal-balls olltO the contacts for holding the balls in place.

The process of producing an interconllect struclurc, furtller including the step of selecting 20 elongated balls for interconnecting, and reflowing while holding tlle horizontal axis of the balls approximately pcrpendiculat to lhe major sllrface of lhe s-lhstrate.

The process of producing an inletcollllect sll~lctllle, ruttllel including the step of selecting elongated balls for interconnecting, all(l reflowing ~villl tllc substrate horizontal inverted during reflow for gravity to hold the longitu(lincll axi~ of the balls vertically aligned.

The invention further include.s, a process ror fablicating an interconllcct structure, comprising the steps of:
producing a fiberglass re-enfolced epoxy boar(l;

EN9-93-055 ~3 drilling one or more holes through lhc boa~
plating the interior of the through-holes with conductive metal;
forming lands of conductive metal arouncl the holes on a major surface of the board;
forming a reetangular array or grid of multiple circular eonduetive metal eontacts whieh are larger than the lands and posiliol1ed so that four eontacts define a square that surrounds each of the lands;
forming a condllctor extending in a diagonal directioll in relation to the square to one of the contacts between each respect;ve land and one of the surt-oun(lillg contacts.

10 The process for fabricating an interconnect structure in which the steps of plating the holes forming lands forming contacts an(l f(lrming a con(luctor are petforme(l simultaneously in an additive photo-lithographic process.

The process for fabricating an interconnect structllre l'urther comprising the step of depositing joining-material on the contacts.

The immediately preceding process f'or fabricating an intcr-connect structure with deposited joining-material further comprising lhe step of conllecling to the joining- material a metal-ball with a melting temperature substal1tially ahove the melling temperature of the joining-material.
The immediately preceding ptOCCSS r(!l f'abl-icaling an interconnect stt-ucture further comprising the step of heating to melt the joinil1g-lllatel icll to rcflo~ conncct thc balls onto the contacts and then cooling the joining-material to soli~lify il.

The invention also ineludes a process for making an inteteonneet assembly, eomprising the steps of:
produeing an FR-4 board with a multitu(le of wiring layers;
forming eireular eopper lands in a wiring layer on a majol surfaee of the board;making holes through the lan(ls al1d through the board;
seleetively depositing eopper arter clrilling to plate the thl-ough-holes for eonneeting the lands to other wiring layers;
forming a reetangular arlay Or grid of roun(l copper contacts larger than the lands, about 0.7 mm diameter, and spaee(l at ahout 1.25 rmm eenters On the major sutfaee and arranged so that four contaets define a square that surr(lunds each of the lands;
forming a eonduetor which is narr(?wer lhan the contacts and narrower than thc lands whieh extend between eaeh of the lands surroun(ie(l by eontacts i11 a diagonal direetion in relation to the square of surrounding contac~s;
depositing solder resi.st at Ieast parlially covering thc conductor and the lands and extending between the eontaets to prevent soldet hridging;
depositing a joining sokler material eontaining about 37/(~3~/0 Pb/Sn solder alloy on eaeh of the eontacts in the array On the hoar(l;
producing multiple green xheels Of glass/ceralnic particles and an organie binder;
forming via holes througll tllC sheets;
sereen printing eonduetive matelial into the h(lles and onto one of the surfaees of the sheets to form a conduetive pattern;
stacking the sheets together;
sintering the staek of sheets in all OVCIl to rOr,.. a mulli-layel ceramic chip carrier with an array of eopper eontaets on a majol SUI racc whicll alC about ().7 mm wide, are spaeed about 1.25 mm apart, and are arranged approximately mirror illlclgC to the alray of contaets of the board;
forming an array of round contacts On an exterior major surface of the carrier;
depositing solder resist between lhe eontacts to prevellt solder bridging;
depositing a joining solder matel ial containing aboul 37/-3~/0 Pb/Sn solder alloy on eaeh of the contacts in the array On the calriel;

~ ;. , .
,, positioning a ball of about 90/1()% Pb/Sn solder alloy an(l about 0.9 mm diameter in eontact with the joining soldet On each resr~ective colltact in the array of the earrier to define a plane of solder-balls;
reflowing to melt the joining solder material deposited on thc contacts of the carrier without melting the solder-balls in order to soldcr the balls to the contacts of the carrier and using the minimal temperature and t;me rcquitccl to rorm reliahle mcchanical joints in order to minimize diffusion of Pb from the balls intO the melted solder;
cooling the carrier to soli(liry the joining solclcr;
positioning the eeramic calrier pclrallel to the cir-cuit board with the solder-balls about in 10 contact with the joining soldcr depo~ite-l On the array of contacts on thc board so that eaeh solder-ball is between a pair of contacts;
heating the substrates while po.;itione(l togethcr to a temperature at which the solder deposited on the eontaets of both Ihc carrier and board are simultaneously melted and the solder-balls remain solid for moving lhe sol(ler-balls by surrace tension of the melted solder material in directions within the plane orthe solder-ball.(i to positions about midway between the eenters of the pairs of contaets to pro(luce symmctric connections between the substrates; and eooling the substrates below the melting temperaturc of the solder materials to solidify the solder material.
~0 The process for making an interconnecl as.sembly in whicll:
each of the contacts on the board include a ~ery thin exlension ovcr the solder resist;
the solder is deposite(l on the c(~ntacls of IllC boatd including the extensions by wave soldering; and the holes are formed in the board by drillillg and r(:~rmed in the sheets by punching; and the process further comprises the stel-s Or:
reflowing the deposited joining solder On the calriel herore p o~itioning the solder balls;
flattening the joining solder on the carriet herore posilioning the solcler-balls on the earrier;
depositing sticky flux on the rlattene(l joining solder on thc carrier before positioning the solder-balls on the carrier;

reflowing the deposited solder on the boar(l befote positioning the earrier with the board;
flattening the join;ng solder on the boat-cl berote positiotling the earrier with the board;
and applying flux to the nattcncd joinillg solder for joining the balls to the board before positioning the earrier with the board.

The invention also ineludes an intereonnecl assen1bly compt-ising:
a first and seeond intereonneet substtates;
a planer pattern of multiple melal contaets On a major surfaee of eaeh respeetive 10 substrate for intereonneetion bctween the substrate.~ whieh are mirtor images of eaeh other to provide eonfronting pairs of contacts;
a ball of eonduetive metal rot respectiYe paits Or SUCIl conlacts with a diameter about the same as the wiclth of the contacts; and a volume of a first joining-matetial ror each sucl1 pair of contacts conneeted to the respeetive eontaet of the first inteteonneet substtate and a volume of a seeond joining-material for eaeh sueh pair of contaets eonnected to the respective contact of the second intereonneet substrate with melting temperatures of tl1e joining-matcrials of bolh the first and seeond vo]umes substantially less than the melting temperature of the metal-balls with tlte first and seeond volumes of eaeh pair of eontaets contlected to approximately cliametrically opposite ends of a 20 respeetive metal-ball and with the smallest cross seclional alC'c) of eaeh joining- material volumc having a minimum diamcter at Ieast Clbou~ 2/3 Or lhc d'iatllCtC'r ol' the metal-ball.

The intereonnect asscmbly in whicll Ihe balls alC clongatc with their longitudinal axis about perpendieular to the major surrace of cacl1 substtcltc.

The interennncet assembly in wl1icl1 the cliametet of thc metal-b~lls ancl width of the eontaets are about 0.6 mm to about 1.2 mm an(l the minimutn (liameter of such CtOSS .section of eaeh joining-material volume is at Ieast about ().f~ mm. The imme(liately prceeding intereonneet assembly in whieh the eontaets arc routl(l ~ ith a diclmetct of about ().7 mm and the diameter of the metal-balls is about ().9 mm.

The interconnect assembly, hl which Ihe alloy Or the metal-ball includes about ~0% to about 97% Pb with most of the balance being Sn.

The immediately preceding interconnect assembly, in whicll the alloy of the melal-ba]l is from about 90% to about 95~n Pb.

The interconnect as~embly, in which tlle alloy of the joinillg-materials hlclude approximately 10 eutectic solder alloy.

The interconnect assembly, in whicll at least one of the substrates is multi-layer, and the structure further comprises one or more vias connectillg between a surface wiring layer of the multi-layer substrate and another wiring layer of tlle multi-layer substrate which are integral with the contacts of a multi-layer substlate.

The interconnect assembly, in which Ihe first and sec(llld joining-materials have about the same melting tempeiatures.

20 The interconnect assembly, in wllicll a mullilude of the COllt.lCtS are connected with plated through-holes and in which the struct~lte f-llther COIllprii~CS means to control the solder volume.

The interconnect assembly, in which:
the positions Or the contacts are defi1le(1 hy intersections of' a multitude of parallel equally spaced lines in each of two perpen(licul.lr (lirections in a plane of the surface at the contacts; and the first ;nterconnect substrate f~lrlller includes:
multiple wiring layers hlcluding One on a major surface of the substrate in which the contacts are positioned;
a multitude of conducting vias c(lnnecting l~etween (lllC or morc other wiring ]ayers of the . ~.

substrate and the surface wiring layer at about the centets of squares defined by four of the contacts;
a eonductor Or the surface wiring layer rOr each respeclive via, which is substantially narrower than the contacts, and extends, in a diagonal d irection of the square to connect between the via and one of the four contacts sul-roun(ling the via.

The immediately proceeding inlerconnect assembly, in which:
the surface wiring layer containing the contacts furthel- includes lands surrounding the vias;
the conductors extend from the lancls to the contacts; and the via through-holes are internally platecl ~ith a layer of copper sufficiently thick to electrically connect between the lancls and other wirillg layers of the slructure.

The invention also includcs a fabricated interconnecl assembly comprising:
a first and second interconnect substrates;
a planer pattern of multiple, metal contacts on each respective substrate, for interconnection between the substrcltes? which are mirror images of each other to provide confronting pairs of contacts;
a ball of conductive metal r(lr respcctive pail s ol' such contacts with a diameter about the~0 same as the width of the contacts; and a volume of a first joining-m.lterial rOr each such pair of contacts connected to the respective contact Or the first intelconrlect substrate an(l a volume of a second joining-material for each such pair of contact.s comlecte(l lo lhe resr~ective contclct of lhe second interconnect substrate, w;th melting temper-atur-es Of the first an(l sccond j(lining-materials both substantially less than the melting temperature of the metal-balls, ~vitll the volumes of the first and second joining-materials of each pair of contacts con necte(l lo a ppl oxima tely diametrically opposite ends of a respective metal-ball, and wi~h the melting Iemperatules of the first and second joining-materials being about equal.

The fabricated interconnect structure, in which:
the alloy of the meta.l-ball is frolll about ~5~1/o to about. 97"/., Ph and most of the balance being Sn; and the joining-material includes about 37/~?3 percent Pb/Sn sokler alloy.

The immediately preceding fabricated inlerconnect slrLIct-lte, in which the joining-material is about 65 to about 75 percenl. Pb.

The invention also includes an interc~-nllect StlUCt-ll~C comprising:
a substrate;
a planer pattern of multi~le, melal cl~n~acts rOr int.elconnecting the substrate, to another substrate with mirror image contacts;
a ball of conductive metal rOr each contact with a diameter about the same as the width of the contacts;
a volume of a joining-matcrial connected hetween each respeetive contact and therespective metal-ball for that contact, with a melting teml~erature of the joining-material substantially less than the meltin~ t~ml~er.ltul~e Or ~he metal-ball, and with the smallest cross-sectional area of tlle joining-material volul-nes h3ving a minimum cl;ameter at Ieast about 2/3 of the diameter of the melal-ball.
The interconnect structure, in whicl1 the ~liameter ~r the metal-ball and ~idth of the contacts are about 0.6 mm to about 1.2 mm an(l lhe millimul11 diallletel (lr SUCtl cross section of each joining-material volume is at Iea~it. ahout r).~ mm.

The immediately proceeding intercol1llect structule, in which the diameters of the contacts are from about 15 to about 30% smallel tllan the di..lmetels Or the balls.

The immediately proceeding intetcnl1nect structllle, in which the diameter of the metal-ball is about .9 mm and width of the contacts are ahout ().7 mm.

The interconnect structure, in wllich the alloy of thc metal-ball includes about 80% to about 97% Pb with substantially all the balance heing Sn.

The immediately proceeding intcrconnect structllre, 4 in which thc alloy of the metal-ball is from 90% to 95% Pb.

The ;nterconnect structure, in which the joining-matelials include approximately eutectic solder alloy.

10 The interconnect structure, in whicll Ihe joining-matetials are about 25 to 50% Pb most of the balance being Sn.

The interconnect structure, in which:
the positions of the contacts are defined by intersectiol1s of a multitude of parallel equally spaced lines in each of two perpendicular directions in a plane of the surface at the contacts; and the substrate is a multi-layer ceramic substrate, and the structure further comprises OllC or more vias connecting betwccn a surface wiring layer of the multi-layer substrate an(:l anothet wirillg layel of the multi-laycr substrate which are integral with the contacts Of a mul~ yer suhstrclte an(l I'illcd Wit]l a conductivc rnaterial with 20 a melting point significantly high-r thall the mel~illg l-oint of the joining-material.

The interconnect structute, I in whicll:
the positivns of the ColltLlcts are ~Ielined l~y hltelsectiOIls of a multiLu(le of parallel equally spaced lines in each of two perl-el1(liculal dil-ectiolls hl a plane Of the surface at the contacts; and the substrate is an FR-4 circuit hoar~l an(l the SttUCtUlC lurthel includes:
multiple wiring layers including one On the surfclce of the substrate in which the contacts are positioncd;
a multitude of conducLing vias connectillg between onc or more other wiring layers of the substrate and the surface wiring layet at about the centels of squares defined by four of the ~ J~

con tacts;
a conductor of the ~surrace wiring layer ror each respective via which is substantially narrower than the contacts and exten(ls in a diagoncll direction of the square to connect between the via and one of the four contacls surrounding tlle via.

The ;nvention also includes a rabricatecl intetconnect structure comprising:
a multi-layer substrate having a wit-ing layer on the surrace of the substrate;
a multitude of metal contacts in a maltix at positions defined by intersections of a grid of a multitude of parallel cqually snaced line.s in each of two r)erpendicular directions in a plane 10 of the surface wiring layer;
a multitude of conducting ViclS COtltlCCtillg belween one or morc other wiring layers of the substrate and the surface wiring layer at aboLIl the celltc~rs of squares defined by four of the contacts;
a conductor of the surfacc witing layer for each respective via which is narrower than the contacts and extends in a diagonal direction of the square to connect between the via and one of the four contacts surrounding the via.

The fabricated interconnect stt ucture futtllet comr~risillg a layer of solder resist covering most of each surface conductot and with opel1ings ror lhe contacts.

Thefabricatedinterconncctstructute,furlllcrcomptisingrourldlandssurtoundingalldconnected to the vias; and in which the eotllllcl;s ale routl(l lhe lancls are smaller in diameter than the contacts and the diagonal connectors are narrowel th.ln the cliamcter.s of both the contacts and the lands.

The fabricated interconnect struclure in which tlle contacts are about 0.6 mm to about 1.2 mm in diametet the width of the (liagonal con(luctors ale Iess lhan about half the cliameters of the contacts.

~..

The fabricated interconnect structure, in which the vias are partially open.

The fabricated interconnect structure, in which the vias are rilled with a LMT solder.

The fabricated interconnect structure, in which the vias are plated through holes.

The invention includes an information handling system comprising:
one or more central processing units connecle(l in a network;
random access memory communicating thr-ougll a bus with each central processor unit;
input/output means for communicatillg with comr)uter peripherals;
a circuit board ill communication Witll OllC 0r more ~-r the central processing units, with a planer pattern of round, metal contact~ having a diameter of ahout 0.6 mm to about 1.0 mm on a maJor surface;
a chip carrier for OllC or more chips with a planer pattern of multiple, metal contacts on a major surface which is approximately a mirror image of a planer pattern of contacts on the circuit board to provide confronting p airs of contacts for interconnection between the carrier and the board and which are also about ().5 mm tn about 1.0 rnm in width;
a metal-ball for each res~cctive pair of ~uch contacts with a diameter of about 0.6 mm to about 1.3 mm;
a volume of a first joining-material for each pair of contacts connected to a respective contact of the chip carrier an-l a volume of a SCCOIlCI joining-material for each pair of contacts connected to a respective contacl of the circuit board, with meltillg ~emperatures of both the first and second joining-material suhstanlially ies~ lhall tlle meltillg temperat~lre of the metal-balls, with the first and second joining-maleri.lls of cach p.lir of contacts soldered to diametrically opposite ends of the respective metal-~all.

The information handling system or claim in which each joining-matelial volume has a cross section of at least 2/3 the diameter of the metal hall.

t EN9-93-055 1 ~
The information handling system~ in which each joining-material volume has a cross scction of at least aboul 0.6 mm.

The information handling system, in wllicll the mel~ing temperatures Or the first and second joining-materials are about equal.

The information handling system, in wllich the conftonting pairs of cnntacts are of about equal diameters.

10 The information handling system, in ~hicll lhe vol~lmes of joining-material for the respective contacts are about inversely prop~-ltional to the diameleJs of the contacts.

The information handling system, in whicll t,llC diame~er of the contacts are about 15 to 30%
smaller than the diameter of the metal-ball~.

The information handling system, furtl1er comprising:
a layer of solder resist between Ille contacts of each of tlle patterns of contacts.

The information handling syslenl, itl WhiCIl thc CilCUi~ bOar(l iS multi-layered and the contacts 20 are associated with plated through hl)les an(l furtller comprising means to control the volume of the second joining-material.

The information handling system, in ~vhicll:
the circuit board is multi-layere(l;
the positions of the contacts are define(l by inlelsections of a multitude of approximately parallel equally spaced lines in eacl1 of two about petpen(liculal directions in a plane of the surfaces at the contacts; and the c;rcuit board further inclu(les:
a multitude of wiring layers inclu(ling one Oll the surface in which the contacts of the _ .

eireuit board are positione(l;
a multitude plated througll llolcs connecting belween one or more other wiring layers of the eireuit board and the surface wiring layer for sol(lering to the metal-balls;
means to eontrol the minimum diametet Or the ~solder volume of soldered eonneetions for the vias ineluding:
a eireular via land contact in the surface wiring layer for each respective via eonneeted to the end of eaeh via at the .surfaee;
positioning the eonneetion.s of thc vias with tl~e surface wiring ]ayer at about the eenters of squares defined by four of the eontacts;
a metal eonduetor of the surrace wiring layer for eaell r espective via, which is substantially narrower than the eontaets, and exten(ls in a diagonal ditectioll of the square to eonnect between the via land and one of the four contaets surroundillg the via land;
a eovering of solder rcsist over the lands and eonductols ancl which provides windows for the eontaets.

The invention also ineludes intereonneet apparatus eomprising:
a first and seeond intere(lnneet sllh.strales;
a planer pattern of multiple~ mctal contacts on each respeetive substrate, for intereonneetion between the s~lbslrales? whicll ale IllilrOl images of each other to provide~0 eonfronting pairs of eontaets;
a eolumn of eonduetive metal fOr respective pairs of such contaets with a diameter about the same as the width of the contacl.s an(l posiliolle(l \~ith a longitu(linal axis perpendicular to the plane of eontaets;
a volume of a first johling-material for each sucll pair of contacts conneeted to the respeetive eontaet of the first intercollnect substrate alld a volume of a seconcl joining-material for eaeh sueh pair of eontact.s connected to lhe respective contact of the second interconneet substrate, with melting temperatures of the joining-materials of both the finst and seeond volumes substantially less than the melting temperature of the metal-columns, with the first and seeond volumes of each pair of eontacts connec~e(l to oppo.site ends of a re.spective mctal-eolumn.

EN9-93-()55 2() The intereonneet apparatus, in which the width Or the contacts is about .5 to 1.2 mm and cliameter of the metal-eolumns is Iess than or aboul equal to the width of the eontaets.

The immediately proeeeding interconnect apparatus, in which the contacts arc round with a diameter of about .7 mm to .9 mm and the diameter of tlle metal-colllmns is about 0.1 mm to .3 mm less than the contacts.

The interconnect apparatus, in wtlich the alloy of lhe metcll-colunln includes about 8()% to 97%
Pb with most all the balanee bcing Sn.
The immediately proeeeding intelconllecl apparatus, in wllich lhe alloy of the metal-column is from 90% to 95% Pb.

The intereonneet apparatus, in whieh the alloy of the joining-matelials inelude approximately euteetie solder alloy.

The interconnect apparatus, in which each end ol the columns are perpendicular to a longitudinal axis of the eolumn.

20 The intereonneet apparatus, in wlliell the first and second joining-materials have about the same melting temperatures.

The intereonneet apparatus, in wtlicll a mul~ J(le ol' the conlacts arc connected with plated through holes and in whieh tlle StlUC~UlC fuitllel comllrises tllCallS to control the solder volume.

The intereonneet apparatus, in which:
the positions of the eontaets are defi1lecl hy intersectiolls of a multitudc of parallel equally spaced lines in eaeh of two perpen(liclllar dil~ections hl a plane of the surface at the contacts; and the first intereonnect substrate fllrlher includes:

multiple wiring layers inclu(]ing one on a major surfaee of the substrate in which the eontaets are positinned;
a multitude of eonducting vias connectillg between one or more other wiring layers of the substrate and the surface wiring layer al about the centers of squares defined by four of the eontaets;
a eonduetor of the surfaee wiring layer lor each respeetive via, whieh is substantially narrower than the eontaets, and cxtcnds itl c1 diagon.ll dil~ection of the square to eonneet between the via and one of the four eontaets surrollll(ling the via.
~0 The immediately proeeeding interconneet appar,ltu~, in which:
the surfaee wiring layer eontaining the COIltclCtS furthcr incluclcs lands surrounding the vias;
the eonduetors extend from thc lands to the eonductors; and the vias through holes which are internally plated with a layer of eopper surfieiently thiek to eleetrieally eonneet between the lands ancl other wiring layers of the strueture.

The invention also ineludes fabricated interc()nnect apparatus comprising:
a substrate;
a planer pattern of multil~le, metal contacts for intercoll11ecting the substrate, to another~0 substrate with mirror image eontaets;
a eolumn of eonductive metal for each eontact with a cliameter about the same as the width of the contacts and positioned about pe1l-en(liclllar to the plane of contacts;
a volume of a joining-matel ial cOIlnected bel~een each r espective contact an the respeetive metal-eolumn for that eontaet, with a melting Iemr)eralures of the joining-material substantially less than the melting temperature of lhe metal- eolumn.

The fabrieated intereonneet ar)paratus, ill wllicll the ~idth Of the eontaets is about 0.5 mm to about 1.2 mm and the metal colutnns are about .4 rnm Iess to about .1 mm more than the width of the contaets.

The irnmediately proceeding fabricate(l interconnect apparatus, in which the width of the contacts is about 7 mm to aboul .9 mm and width of the metal column is about 0 to about .2 mm less than the width of tll(~ COll~.lCt~.

The fabricated interconnect apparatus, in which tllC alloy of the metal-column includes about 80% to about 97% Pb with suhstantially all the balance being Sn The immediately proceeding fahricaled interconnect apl-alatus, in which the alloy of the metal-column is from 90~/o to 95% Pb The fabricated interconnect ar~paratus, in wllicll the joining-materials include approximately eutect;c solder alloy.
The fabricated interconnect apparalus, in whicll the joining-materials are about 25 to 50% Pb most of the balance being Sm The fabricated interconncct apparatus, in which:
the positions of the contacts are defilled by intersections of a multitude of parallel equally spaced lines in each of two perpendic~llar clirections in a plane of the surface at the contacts; and the substrate is a multi-layer ceramic suhstrate, and the structure further comprises one or more vias connecting between a surface wiring layer of the multi-layer substrate and another wiring layer of the mu]ti-layer substrate which are integral with the contacts of a multi-layel suhst~ te alld filled wilh a concluctive material with a melting point significantly higller thall the meltillg l~oint of Ille joining-material The fabricated interconnect apparatus, in \~hich:
the positions of the contacts are derined by hllersecti(!ns of a multitude of parallel equally spaced lines in each of two perpcn(licul.lr directi(lns in a plane Or ~he SUI face at the contacts; and the substrate is an FR-4 CilCUit boar(l and the structure further includcs:
multiple wiring layers including one on the surface of the substrate in which the contacts are positioned;
a multitudc of eonducting vias conneeting hetween OllC' or more other wiring layers of the substrate and the surfaee wiring l.lyer at about the centers of squares defined by four of the eontaets;
a eonduetor of the surFaee wirhlg layer for eael1 respeetive via, whieh is substantially narrower than the eontaets, and extends in a diagonal dircction of the square to connect between the via and one of the four contacts s-lrr--unding the via.

The invention a]so ineludcs a process for inteteonnecl assembly eom~rising the steps of:
10producing a first substratc witll an apploximately p]ancr pattern of multiple, metal eontaets on a major surfaee;
depositing a volume of a first joining-lllatelial On each of the contaets of the first substrate;
eonneeting a conduetive metal-eolumn to the First joining-material on eaeh of the eontaets on the first substrate for maintaining a prcdetermine(l distanee between the first substrate and a seeond substrate when eonneetcd;
produeing a seeond suhstrate wilh a major surface having an approximately planerpattern of multiple, metal conlacls which alC apl rOXilllatCIy a mirror imagc of the pattern of eontacts of the first substlate;
20deposit;ng a volume of a seconcl joining-material l:'or positioning between the metal-eolumns and eaeh rcspeetive conlact of the secollcl substrate;
positioning the substrates logetller ror intercollnectioll willl contaet patterns parallel, with mirror image pairs of eontacts in conflonlillg arr)l-oxilllalc alignlllent, and with caeh volume of the seeond joining-material approximalely in contact ~vith a resllectivc encl of lhc metal-column and a respeetive eontaet of thc secon-l substtate;
simultaneously melting the firsl an(l secon(l joining-matelials while thc substrates are positioned together, at a temperature in which tlle metal-eolumns remain .solid for providing the predetermined separation between subsllcltes, ror tnoving the encls of the metal-eolumns by surfaee tension of the melted joining-material to l~ositiolls arproximately ccnters of the eontaets;

cooling the substrates bclow the melting temperature.s of the joining-materials to form electrieal interconnections between thc pair~ of conla~ts~

The process for interconnect assembly, in which the volumes of the second joining-material are deposited on the contacts of thc second substrate prior lo posilionillg tlle substrates together for interconnection .

The process for interconnect assembly, in whicll the \~olun1cs of second joining-material are deposited at projecting ends of the melal-columrls arter the columns are connccted to the first 10 substrate prior to positioning the subsllales togetllcl for intel-conneclion~
The process for interconnect assembly, in wllicl~ the ,step of connecting a metal-column to the first ~olumes of joining-material includes the steps Of:
positioning a metal-column on each volume or firsl joining-material;
heating the first substrate up t,o connect the metal-columns to the contacts of the first substrate by melting the first joining-material without melting thc metal-columns; and cooling the first substrate do~n to form a mechanical joint between the metal-columns and the contacts of the first substrate bef'or-e the step of posiliotling the s-lbstrates togcther for intercon nection .
The immediately proceeding prOce.ss for h1tetconnect assembly, in which there is a metal element which can migrate between thc metal-colulllns an(l t,he firsl joinillg-lrlaterial and increase the melting temperature of the fh~~t johlillg-mal,el ial atl(l dul hlg thc lcp Or healing the first substrate up the substrate is heated to a minim~ temperat~lre and for a minimum time for minimizing migration of a metal elemenls bet~een l,he metal-colum~ and firsl joining-material to minimize the increase of the melting tcmperature of lhe firs~, johlillg-matel-ial~

The immediately proceeding proce.ss for interconnect as.sembly, furtller comprising the step, selecting a different joining-material for the first and second joining-matcrials for compensating for migration of the metal element hetween the metal-columtls an(l first joining-material in order for the first and seeond joining-materi.lls to simultalleously melt during the step of heating the substrates up while positioned together.

The proeess for intereonnect assembly, in whieh there is a metal element whieh ean migrate between the metal-columns and the joillillg-materials and which increases the melting temperature of the joining-matet ials, ancl the substrates are heatecl together at a sufficiently high temperatur-e for a sufficiently long time lo allow migration of the metal element between the metal-eolumns and joining-materials t:o substantially raise the melting temperature of the 10 joining-materials so that the hlterconllcctions connections are not remelted during subsequent joining of attachments to the substlates USillg suhstantially the samc joining-material as the volumes of joining-material.

The process for intereonneet assembly, further inclu(lhlg the steps of:
selecting the size of the eont.3ets as large as possible while reliably preventing joining-material bridging between contacts; ancl selecting the size of the metal-columns the same size Or slightly smaller than the spaeing between the eontaets to maximize the size of the columns while reliably preventing solder-bridging and to minimize fatigue in the columns.
The proeess for intereonneet assemhly, further inclulling the steps of:depositing a liquicl encal s-llating materi.al hetweel1 the substrates around the metal-eolumns in the area clelmecl by I hc conlact l-attel n after the stel~ of cooling the substrates below joining-material melting temr~eralures; and hardening the encapsulating material to reduce the stresses in the joints during subsequent thermal eyeling of the eonnectecl substlates.

The proeess for intereonneet assembly, I'urthel eoml7risillg the steps of:
seleeting a shape for the eontacts ~o maximize the size of the eontaets whieh may be EN9-93-055 2(~
reliably conneeted without briclging for making the .~ize of the contact~s larger to reduee thermal fatigue; and depositing solder resist between the contacts ror making the size of the contacts which may be reliably connectecl without bridging larger to recluce thermal fatigue.

Finally the invention ineludes a proce.s.s for buil(ling an intereonneet ~strueture eomprising the steps of:
making a rigid substrate with an approxim.ltely planer malrix of multiple metal eontaets on a major surfaee;
depositing a volume of a joining-material On eaeh of t.he eontaets of the matrix of the rigid substrate;
positioning a eonduetive metal-colutnl1 to the joining-material on each of the contaets on the first substrate for maintaining a pr edetel mine(l distallee between the substrate and a seeond substrate to whieh the substrate is to be connecte(i;
melting the volumes of joining-material witllout melting the metal-eolumns to prevent ehanging the shape of the eolumns; an(l eooling the joining-material to rorm a soli(l meehanical joint between the metal-columns and the contacls of the substrale.

20 The process for building an intercollnect .structule in wllicll there is a metal element whieh ean migrate between the metal-eolumns an(l lhe joining-matetial and inerease the melting temperature of the joining-material an(l during Ihe slep of meltillg is performed at a minimum temperature and for a minimum time re~luile(l to plo(lucc reliable joints for minimizing migration of a metal elements between the melal-columns all(l first joining-m ltetial to minimize the increase of the melting temperatule of the joining-material.

The proeess for building an intereonneet structure furtller including the steps of:
selecting the size of the eontaets as large a.s possible limite(l only by reliably preventing joining-material bridging between eontaet.s; and selecting the size of the melal-colulllns about the same size or slightly smaller than the eontaets to maximize the size of the colurnlls to minimize fatigue in the joints without eausing solder bridging.

The proeess for building an interconnect stlucture? further inclu(-ling the steps of:
selecting eeramie for the material of the rigid substrate;
seleeting eopper for the material of the contacls; and se]ecting a LMT (low melting teml-erature) solder alloy as the joining-material and a HMT (high melting temperature) soldel l'or the metal-columns.
The process for building an interconllect struclule, fut-tller inclu(lillg the step of selecting FR-4 for the material of the rigid substrclte.

The process for building an interconnect struct-lre, in which the step of making a rigid substrate includes the steps of:
produeing multiple green sheets of gla~;s/eeralllie particles and an organic binder;
making via holes in the sheets;
screen printing conductive malerial into the holes and OntO OllC of the surfaces of the sheets to form a conductive pattern inclu(lillg the array of round contacts;
pressing the sheets together into a stack; and sintering the staek of sheets in an oven to rorm a multi-layer ceramie ehip eartier with an array of eopper eontacts on a major sulface wllicll alc about .7 mm in diameter, are spaced about 1.25 mm apart;
seleeting euteetic ( about (~3/37 ) Pb/Sn sol(lcl alloy l'or the joinillg-material;
seleeting a mater;al of 9() lo 95"/.. Pb soklcl alloy an(l a size of about .9 mm for the metal-eolumns.

The proeess for building an inteleonnect stluet~lre, furthcl inelu(ling the step of depositing stieky f~ux onto the eontaets berore positioning ~he metal-columlls onto the eontaets for holding the columns in place.

The process for build;ng an interconnect struclure, further including the step of holding the column vel-tical during reflow to join the column to the module.

The process for building an interco~ ect structure, further including the step of inverting the module during reflow to join the columns to the mo(lule.

This invention will be describe(l in grealer detclil in reference to the following drawing.
BRIEF DESCRIPTION OF THE DRAWINCS
FIG. I is a process diagram which illustrates producillg an multi-layer ceramic chip carrier (MLC) of this invention.
FIG. 2 illustrates the process for pro(lucing an fiberglass-cpoxy circuit board (FR-4) of this invention.
FIG. 3 illustrate the process for producing the connections between the MLC and FR-4 in this invention.
FIG. 4 is a schematic partial cro~s section Of a specific embo(liment of this invention showing part of an MLC chip carliet ~ilh ~oklel- balls attached to contacts and confronting 20 mirror image contacts of an FR-4 circuit boar(l.
FIG. 5 shows the positionillg of sol<lcr balls on tlle solcler contacts prior to attachment to the MLC of FIG. 4.
FIG. 6 shows the MLC all(l FR-4 Of FIG. 4 positione(l together.
FIG. 7 shows the rellow conneclions of the Ml,C to the FR-4 of FIG. 4 in which only the joint between the solder balls and the FR-4 is melted during reflow.
FIG. 2 illustrates the teflow connectiolls of the Ml,C to the FR-4 of FIG. 4 in which both joints of each connection are simultaneously melled to r)rovide a more symmetric connection.
FIG. 9 is a schematic cross SCCtiOIl througll line 9-9 of FIG. 10, illustrating the /'dog bone"
connection between platcd-througll-llole via connection of this invention.

FIG.lOis a schematic plan view illustrating part of the array of metal eontacts and "dog bone" eonneetions between the plated through holes and contaets.
FIG.IIis larger view of the "dog-hone" arrangement of FIG.I0.
FIG. 12 is another embocliment of this invention with different sized contaets and inversely proportional solder volumes.
FIG. 13 is a plan view of a eontaet of this invention for providing suffieient solder volumes for this invention.
FIG. 14 is a eross seetion of the contact of FIG. 13through line 14-14.
FIG.15 schematically illustrates the information handling system of this invention.
FlG. ]6 shows an alternative embodiment for the pl-OCCSS aceording to the present invention, whereby the solder balls repl-esented in Fig. 4 are substituted with hemispherieal ended solder eolumns.
FIG.17shows a vaeuum die rOr positioning solder eolumns on the eontaets of a substrate carr]er.
FIG.18 shows the substrate of Fig. 17 eonneeted to another substrate, without applying the proeess of the present invention.
FIG.I9 shows the results of the proeess of the invention having been applied to the assembly of Fig. 18.

In this invention, as illustrated in FIG 4, a first s-lbs~rate 1() i~ ptodueed with a planer array of eontaets 12 ancl vias 14. In this application substrate rerers to any component with a flat surface for intereonnection whieh will be referred to as a major sutface in contrast to a thin edge surfaee.
Although the invention will increase lhe reliability of connecting flexible circuit boards such as ATAB ~area tape automated bonding) componen~s, preferably the first substrate is a component sueh as an FR-4, plastie, or eeramie ehip earrier, and more preferably a MLC (multi-layer eeramie) ehip earrier for which this inventions of this application are espeeially well suited.

' 7 ~
,, ~.., ~N9-93-055 29~1 As illustrated in FIG. 1, step lOl, in tllC manuracture of cctamic chip carriers, ceramic powders are mixed with binders, solvents and plasticizer ancl cast to form green sheets to form dielectric layers. In step 102, Vias are made prererably by punching and in step 1()3, conductive ink or paste (e.g. Mo frit and solvent) is screenecl lo fill the vias. The wiring pattern may also be screened on the surface at this time an(l/ot exterior wiring layers may be made later using a thin film process. For multi-layer ceramic, in step 1()47 green sheets are stacked and laminated with heat and pressure into a monolithic stlllclure. Then the green sl1eet(s) are sintered, in step 105, 10 by firing in an oven with a reducing atmospllele. Afler sintering the exposed metal is coated for protection (not shown). A thin film ploccss may l~e used to produce an exterior wiring layer (not shown). For example, concluctive mclal may be evaporated or sp~lttered onto the substrate EN9-93-055 3() followed by photolithographic patternillg which may be rollowed by clialectic coating and additional thin film layering.

The contacts 12 (FIG. 4) may be s4uate or more preferably are ar~proximately round to match the shape of the ball and to allow a closer spacing sufricient to reliably prevent solder bridging.
The contacts may be made from any conductive substallce, prefel-ably a metal such as Al or Ti and more preferab]y are macle from or coverecl wilh Cu, Ni, Au, Pd, or alloys of these. The material may be deposited by screenillg Or a pllotolitllograllhic process may be followed by chemical and/or electric deposition processes.
In step 106 (FIG. 1), the contacts 12 are covere(l with a volume of a first joining-material 13, 16 respectively, such as a con(iuclive therm(!r)lastic or a solclcl~ alloy containing Sn, Pb, Bi, In, Ag to form solder contacts or sokler bumps. In the preferrecl elllboclimcnt the joining-material is PblSn solder with 20 to 75 ~/f~ Sn an(l the balance mostly Pb and most preferably is about eutectic 63% Sn and 37% Pb. The solder may be (leposited in the molten state by a mass soldering method such as wave solclering or may be screenecl as solder paste (metal particles in a organic carrier) or may be clecll-ically ancl/ol- chemically depositecl on the contacts following a photolithographic process.

In step 107, as shown in FIG. 5, mel.ll-b311s ale attache(l to the soldcr bumps preferably by applying a layer of sticky flux 2() on whicll the balls are positiolled. The balls may be placed simultaneously by transfer from a vacuulll clie. The flux may be appliecl just on the contacts or in the entire area of the substrclle inlerconnectioll<i. The balls I 8 may be copper prererably coated to prevent oxidatioll, or more ~rererahly ale a llMT solclct alloy with a melting temperature substantially more than that Of the j~)inhlg-lllaterial so that the balls may be reflow joined to the contacts in step 108 without melling the balls. Preferably the balls are Sn and 80 to 97 % Pb most preferably 90 - 95 ~~" Pb. Preferably the altachment i~ ma(le teliable by reflow heating to join the ball to the contact so the ball ~ill not fall ofr cluring later processing. During reflow of the first joining-material 1~1, surface ~ensioll or lhe melte(l joinhlg-material will precisely align EN9-93-055 3 l balls 18 with contacts 12. Centerillg the balls on the pads Or the first substrate helps align the balls with the pads of the second substrate.

For solder joining-materials, during reflow, metal elements will dissolve or be transported between the LMT solder and the metal-balls. In or(ler to prevent thi.s the reflow attachment of the balls 18 to substrate 1() should be done at the lowest temperature and in shortest time required to center the balls and prevent losing the balls durillg subsequent processing.

In step 109 the substrate is coole(l to .solidify the joining-material.
A second substrate 11 is producecl whicll also has vias 15 and a planer array of contacts 17. The array of contacts 17 is approximately a mirror image of the artay of contacts 12. The second substrate may be a flexible circuit boald (e.g. thin polyhllide and copper layers), or more preferably a rigid board such as ceramic and is most prererably a multi-layer FR-4 printed circuit board. This inventions of this al p lication are especially well suited to applieations where there is a significant diffcrence in the lhermal coefficients between rigid first and second substrates.

FIG. 2 illustrates the proeess Or manufactur-ing fiberglass- epoxy cireuit boards (FR-4). In step 20 120, one or more layers of fiberglass cloth are impregnated willl epoxy resin solution to form a dieleetric layer. For boards witll multil-le FR-4 layers llle layels are only partially cured to form stable B-stage layers. In ster~ 121, at ICa~jl the interllal layers are circuitized. FlG's 9 - 11 illustrate the surface wiring of lhis invelltion an(l i~ discussed in more detail later. This step includes forming a rectangular artay or pteferably roull~l contact.~i folming lands for eonnection to the vias at the centers of squalcs derille(l by four surtounding contacts, and forming eonnections between the lands and contacts Usually befote drilling for vias that go through all the layers, the B-stage layers are laminate(l in ster) 122 with heat and pressure to fuse the layers and fully cure the board. Each layer is circuilized by scleer1illg (?I by a photolithographic process in which a metal foil covering i~ subttactively remove(l or metal is selectively chemically and/or '' -electrieally added to form a wiring layel on the surface of the layer. In step 123 holes are drilled at the lands through one or more layers and in step 124 lhe holes are internally plated with metal (preferably copper) to form vias for electrical interconnection between the wiring layers on each side of the dielectric layers.

In step 125 joining-material is dcposited On contacts in a similar manner as previously descr;bed for step 106 in the process Of producing Ml C.

In step 131 substrates 10 11 arc m(!ve(l inlO confr(!tlting rositiotl as showll in FIG. 4 and in 10 step 132 are brought togelher a~ showtl in FIG. (~. Tlle accutc1cy of the placement machine is limited so that the substrates are not precisely alignecl.

FIG. 7 shows the results of rerlow of only joinhlg-ltlatetial 13 which moves substrate 10 in the direction of arrow 40 relative lo substrate 11 intO precise alignment between the substrates. As illustrated the connectiotls such as on either si<le of ball 42 are not symmetric due to tolerances in the positions of the contacts. Tllelerore in step 133 as sllown in FIG. X preferably both joining-materials 13 ancl 16 on either ~ide or the solclcr balls 12 arc simultaneously reflowed to produce more symmetric conneclions Whcll botll joints 51 all(l 52 are simultaneously melteci the su~face tension of lhe joining-maletial will move the ball hl the plane 53 of the balls toward a 2() position halfway bctween the CClltCts 54 55 Or lhe contacls resultitlg in a more symmetric connection. Such symnlctric conncctiolls hllvc a grealer fatigLIe life than the non-symmettie connections of FIG. 7.

In step 134 the substrates are cooled to s--licliry thc j~-ining-lllatetial Or t~e connections. In step 135 the area between the fitsl and secon(l substrales arouncl the metal-balls is filled with an encapsulant such as epoxy. It is crilical to lhe solcler connection configuration invention of applieant that the connections not bc encarJsulated utl~il artet- simllllallc()us reflow of the top and bottom solder joints so that the soldet balls can move inlo alignment between the contacts. After such alignment encapsulating the area between the substtIltes~ around the balls reduces fatigue ~ ' r stress during thermal cycling.

When Balls 18 is reflow attached to contacts 12, some material will be exchanged between the ball and joining-material 16. For example if the ball is 10/90 Sn/Pb and thejoining-material is eutectic 63/37 Sn/Pb then after reflow the joining-material will have a higher Pb content and therefore a higher melting temperature. If joining-material 13 is also eutectic Sn/Pb solder then during reflow for connecting the substrates the joints are going to have to be heated to the higher temperature to simultaneously melt. In order to use a minimum temperature for reflow joining-material 16 may have a lead content reduced 10 below eutectic amounts so that during the first reflow it becomes eutectic and then the simultaneous melting during the second reflow is achieved at minimum temperatures.

Most preferably the balls in FIG's 4-8 are as large as possible to minimize fatigue stress in the connections only limited by the requirement of reliably preventing bridging between the balls. Stresses in the joints on either side of the balls would be minimi~ed by m~king the contacts the same size as the balls, however, to reliably prevent bridging between the contacts, the contacts have to be significantly smaller than the balls. As shown in FIG. 8, preferably a solder mask material 58 which repels liquid solder is placed between the contacts to reduce solder bridging so the contacts may be made as close to the size of the 20 balls as possible. For example, connections with 9 mm balls and round contacts of 7 mm diameter spaced at 1.25 mm centers may be reliably made without bridging.

Solder mask materials are well known in the art.

Solder volumes should be as large as possible to reduce fatigue but are limited by the requirement to reliably prevent bridging and the cost or difficulty of depositing large volumes of solder. Most preferably, as shown in FIG. 9, in plane 62 defined as the cross section of minimum diameter of the joint 64, the diameter is at least 2/3 of the diameter of the ball 66. For example if the ball is 9 mm in diameter, the joint should be at least 6 mm 30 in diameter in plane 62 and more preferably larger.

For eeramic substrates through hole vias are usually fille-l with a HMP metal and for thin film layers on eeramie flex or FR-4 vias are usually rilled or are slightly depressed in relation with eontaets that are not on vias. For multi-layer flexible alld FR-4 substrates wiring layers usually eontain round lands of metal through whieh the via holes are formed and whieh are intereonneeted between wiring layers by plating the hole. Some Or the contaets on FR-4 and flex substrates may occur on such platecl vias. Sincc tlle dian1eter or the solder joint is critical the volume of solder is eritical but lhe volume C.311 not easily be controlled at sueh holes 10 (even if previously filled with solder).

FIG. 10 sehematically shows an alrangetnellt Or plLIled througll hole vias 71 each eonneeted to a solder contact 72. This dog bone al rangement plCVClltS the soklcl on contact 72 from flowing into the through hole 73. In this speeiric emhodiment the ccnters of the eontaets are about at the interseetions Or multiple equally spaced parallel lines 74 and multiple equally spaced parallel lines 75 whieh are perpendicular to lines 74. Vias 71 are located at the centers of squares 76 defined by four eontaets 72 aground ~ia 71. The via s are conneeted lo the eontacts through a wire 77 extending under a layer of sokier mask 7g.

20 FIG. I l schematieally illustrates a single dog bone 80 of this invention prior to depositing joining-material on eontaet 82. A hole Xl (hi(iden) is made by mechanical or laser drilling into the substrate at least to another wil ing I lyet an(l metal is cleposited to fOI m contact 22 land 83 connecting wire 84 and to plate the hole ~5 Ieaving opening g-~. Sokler mask 87 eovers most of eonneeting wire 87 and the ouler eclge ol' land X3 as indic.lte(l by dashed lines to prevent solder bridging.

FIG. 12 schematieally illustrates an alterllative embo(lilnent in whieh metal eontaet 91 is larger than metal eontaet 92. In this ease in orcler lo reduce fatigue alld increase fatigue life of the conneetion a higher volume of joining-matetial 93 is placed between ball 94 and the smaller contact 92, than the volume of solder material 95 between the solder ball aIld larger contact 91. Thus the minimum cross sections of the joints on each side of the solder ball may be made about equal to equalize fatigue at each joint of the connection.

FIG's 13 and 14 illustrate a technique to provide higher levels of solder deposited on a contact than can usually be deposited by wave soldering or electrical or chemical (electroless) deposition. Flash layer 130 extends out from contact pad 132 over the layer of solder resist 134 the thickness of the flash is exaggerated for illustration. Solder 136 is deposited electrically, chemically, or preferably by solder wave. The flash is a conductive substance for electrical deposition, a seed materials such as palladium for electroless plating, and may be a solder wettable material for wave soldering. The flash material is selected to dissolve during reflow resulting in all the solder migrating onto the contact pad.
Preferably for wave soldering the flash is copper of tin which is sufficiently thick to survive during deposition, but thin enough to ffilly dissolve during reflow. The thickness of the solder deposited by molten solder wave generally increases as the size of the flash area increases.

FIG. 15 shows an information handling system 150 in which computer assembly 151 includes central processor module 152 communicating through one or more wiring layers (not shown) in substrate 153 with computer memory module 154. Computer 152 communicates with computer assembly 155 through cable 156. Computer 155 also includes central processor module 152 communicating through one or more wiring layers (not shown) in substrate 158 with computer memory module 158. One or preferably both modules of each co--lE)ulel are connected to the substrate using the preferred solder ball or solder column connections of the invention.

FIG. 16 illustrate solder columns 165 which are similar to the solder balls 18 (FIG. 4) and the previous discussion on materials, geometries, and methods of placement, reflow joining to the modules, reflow connection to the substrates are applicable. They have approximately semi-circular ends and are preferably from 1 to 20 times longer then their diameters. Fatigue is reduced by m~king the columns longer, but longer columns result in higher module profiles, EN9-93-055 3~
reduced Iead cooling and handling problems that mililate against length exceeding that necessary to reliably prevent thermal fatigue failurcs. In this application the term solder-ball includes hemispherical ended solder co]umns. In or(ler to join the columns to the module columns may be teflow heated while attached lo the hottom si(1e of the moclule (i.e. inverted position). This results the columns being closely centere(l on the contacts and very accurately vertically aligned.

In FIG. 17 columns 171 have square ends formed for e~ample rrotn cutting extruded solder wire. Vacuum die 172 includes a flat face 173 willl recesses whicll fit the solder ball or solder column. The recesses commllnicate wilh a vacuum reservoir 175 through passages 176 which are 10 significantly smaller than the sol(lel halls Or columns to reliably prevent the columns from entering vacuum reservoir 175 and prevent jamming. The vacuum die is used to position the balls or columns on the contacts Or a substrate either a~s shown in FIG 17 or in an inverted position.
Either round or s~uare end columns can be reflow joined in inverted position as in FIG 16 or by holding the columns vertical ~luring reflow prererably using the vacuum die. The vacuum can be turned off or even reverse(l during reflow allowing the columns to rest against the solder contacts.

When the roulld or square columns are held in pOSitiOIl during rerlow joining with the contacts of substrate 17~ the column i ale nOt as well centerc(l On the contacts or as vertically aligned 20 or vertically positioned as the joints fot mecl t~y hallgill~. As sllown in FIG. 1~ when the module substrate is connected to anothel sut-strale IXI thC joints are nOt symmetrica]. When the simultaneous reflow Orthe invenlioll is a~ ic(l as sllown in FIG. 19 the joints become much more symmetrical and more reliable.

While this invention has been descril~ed in relation lo prererred embodiments it will be understood by those skilled in the art tllclt changes hl lhe (Ietails of r~rocesses and structures may be made without cleparting from lhe sr~il it an(l sco~e of this invention.

Claims (58)

1. A process for producing an interconnect assembly comprising the steps of:
producing a first substrate with an approximately planar pattern of multiple, metal contacts on a major surface;
depositing a volume of a first joining-material on each of the contacts of the first substrate;
connecting a conductive metal-ball to the first joining-material on each of the contacts on the first substrate to define a plane of metal-balls for maintaining a predetermined distance between the first substrate and a second substrate when connected;
producing a second substrate with a major surface having an approximately planar pattern of multiple, metal contacts which are approximately a mirror image of the pattern of contacts of the first substrate;
depositing a volume of a second joining-material for positioning between the metal-balls and each respective contact of the second substrate;
positioning the substrates together for interconnection with contact patterns approximately parallel, with mirror image pairs of contacts in confronting approximate alignment, and with each volume of the second joining-material approximately in contact with a respective metal-ball and a respective contact of the second substrate;
simultaneously melting the first and second joining-materials while the substrates are positioned together, at a temperature in which the metal-balls remain solid for providing the predetermined separation between substrates, for moving the metal-balls by surface tension of the melted joining-material in directions within the plane of the joining metal-balls to positions approximately between the pairs of approximately aligned contacts; and cooling the substrates below the melting temperatures of the joining-materials to form electrical interconnections between the pairs of contacts.
2. The process of claim 1, in which the step of connecting a metal-ball to the first volumes of joining-material includes the steps of:
positioning a metal-ball on each volume of first joining-material;
heating up the first substrate to connect the metal-balls to the contacts of the first substrate by melting the first joining-material without melting the metal-balls; and cooling down the first substrate to form a mechanical joint between the metal-balls and the contacts of the first substrate before the step of positioning the substrates together for interconnection.
3. The process of claim 1, in which the step of connecting a metal-ball to the first volumes of joining-material includes the steps of:
positioning a metal-ball on each volume of first joining-material;
heating up the first substrate to connect the metal-balls to the contacts of the first substrate by melting the first joining-material without changing the shape of the metal-balls; and cooling down the first substrate to form a mechanical joint between the metal-balls and the contacts of the first substrate before the step of positioning the substrates together for interconnection.
4. The process of claim 2 or 3, in which there is a metal element which can migrate between the metal-balls and the first joining-material and such migration may increase the melting temperature of the first joining-material and during the step of heating up the first substrate the substrate is heated to a minimum temperature and for a minimum time for minimizing migration of a metal element between the metal-balls and first joining-material to minimize the increase of the melting temperature of the first joining-material.
5. The process of claim 4, further comprising the step, selecting a different joining-material for the first and second joining-materials for compensating for migration of the metal element between the metal-balls and first joining-material in order for the first and second joining-materials to be melted simultaneously during the step of heating up the substrates while positioned together.
6. A process for forming an interconnect assembly comprising the steps of:
producing a first substrate having on a major surface, a wiring layer including an array of multiple, metal contacts;
producing a second substrate having on a major surface, a wiring layer including an array of multiple, metal contacts which are arranged approximately mirror image to the contacts of the first substrate and are about the same size as the contacts of the first substrate;
positioning the substrates with the mirror image arrays of contacts in confrontation to define confronting pairs of contacts;
positioning conductive metal other than solder balls between the pairs of confronting contacts; and connecting joining-material between the metal other than solder balls and each of the respective pair of contacts to electrically and mechanically interconnect the pairs of contacts through the balls.
7. A process for building an interconnect assembly comprising the steps of:
producing a first substrate having on a major surface, a wiring layer including an array of multiple, metal contacts;
producing a second substrate having on a major surface, a wiring layer including an array of multiple, metal contacts which are arranged approximately mirror image to the contacts of the first substrate and are larger in size than the contacts of the first substrate;positioning the substrates with the mirror image arrays of contacts in confrontation to define confronting pairs of contacts;
positioning conductive metal-balls between the pairs of confronting contacts;
connecting a volume of joining-material between the metal-balls and the respective contact of the first substrate; and connecting a smaller volume of joining-material between the metal-balls and the respective contact of the second substrate to interconnect the pairs of contacts electrically and mechanically.
8. A process for producing an interconnect structure comprising the steps of:
producing a rigid substrate with an approximately planar matrix of multiple, metal contacts on a major surface;
depositing a volume of a joining-material on each of the contacts of the matrix of the rigid substrate;
positioning a conductive metal other than solder ball to the joining-material on each of the contacts on the first substrate to define a plane of metal other than solder balls for maintaining a predetermined distance between the substrate and a second substrate to which the substrate is to be connected;
melting the volumes of joining-material without melting the metal other than solder balls to prevent changing the shape of the balls; and cooling the joining-material to form a solid mechanical joint between the metal other than solder balls and the contacts of the substrate.
9. A process for fabricating an interconnect structure comprising the steps of:
producing a circuit board;
drilling one or more holes through the board;
plating the interior of the through holes with conductive metal;
forming lands of conductive metal around the holes on a major surface of the board;
forming a rectangular array or grid of multiple, circular, conductive, metal contacts which are larger than the lands and positioned so that four contacts define a square that surrounds each of the lands; and forming a conductor extending in a diagonal direction in relation to the square to one of the contacts between each respective land and one of the surrounding contacts.
10. The process of claim 9, further comprising the step of depositing joining-material on the contacts.
11. The process of claim 10, further comprising the step of connecting to the joining-material, a metal-ball with a melting temperature substantially above the melting temperature of the joining-material.
12. The process of claim 11, further comprising the step of heating to melt the joining-material to reflow connect the balls onto the contacts and then cooling the joining-material to solidify it.
13. A process for making an interconnect assembly comprising the steps of:
producing a circuit board with a multitude of wiring layers;
forming circular copper lands in a wiring layer on a major surface of the board;making holes in the lands and extending through the board;
selectively depositing copper after drilling to plate the through holes for connecting the lands to other wiring layers, forming a rectangular array or grid of round copper contacts larger than the lands about 0.7 mm in diameter and spaced at about 1.25 mm centers on the major surface and arranged so that four contacts define a square that surrounds each of the lands, forming a conductor which is narrower than the contacts and narrower than the lands and which extends between each of the lands surrounded by contacts in a diagonal direction in relation to the square of surrounding contacts;
depositing solder resist at least partially covering the conductor and the lands and extending between the contacts to prevent solder bridging;
depositing a joining solder material containing about 37/63% Pb/Sn solder alloy on each of the contacts in the array on the board;
producing multiple green sheets of glass/ceramic particles and an organic binder;
forming via holes through the sheets;
screen printing conductive material into the holes and onto one of the surfaces of the sheets to form a conductive pattern;
stacking the sheets together;

sintering the stack of sheets in an oven to form a multi-layer ceramic chip carrier with an array of copper contacts on a major surface which are about 0.7 mm wide, are spaced about 1.25 mm apart, and are arranged approximately mirror image to the array of contacts of the board;
forming an array of round contacts on exterior major surface of the carrier;
depositing solder resist between the contacts to prevent solder bridging;
depositing a joining solder material containing about 37/63% Pb/Sn solder alloy on each of the contacts in the array on the carrier;
positioning a ball of about 90/10% Pb/Sn solder alloy and about 0.9 mm diameter in contact with the joining solder on each respective contact in the array of the carrier to define a plane of solder balls;
reflowing to melt the joining solder material deposited on the contacts of the carrier without melting the solder balls in order to solder the balls to the contacts of the carrier and using the minimal temperature and time required to form reliable mechanical joints in order to minimize diffusion of Pb from the balls into the melted solder;
cooling the carrier to solidify the joining solder;
positioning the ceramic carrier approximately parallel to the circuit board with the solder balls about in contact with the joining solder deposited on the array of contacts on the board so that each solder ball is between a pair of contacts;
heating the substrates while positioned together to a temperature at which the solder deposited on the contacts of both the carrier and board are simultaneously melted and the solder-balls remain solid for moving the solder-balls by surface tension of the melted solder in directions within the plane of the solder-balls to positions about midway between the centers of the pairs of contacts to produce symmetric connections between the substrates; and cooling the substrates below the melting temperature of the solder materials to solidify the solder material.
14. The process of claim 13, in which:
each of the contacts on the board include a very thin extension over the solder resist;
the solder is deposited on the contacts of the circuit board including the extensions by wave soldering; and the holes are formed in the circuit board by drilling and formed in the sheets by punching;
and the process further comprises the steps of:
reflowing the deposited joining solder on the carrier before positioning the solder balls on the carrier;
flattening the joining solder of the carrier before positioning the solder balls;
depositing sticky flux on the flattened joining solder on the carrier before positioning the solder balls on the carrier;
reflowing the deposited solder on the board before positioning the carrier with the board;
flattening the joining solder on the board before positioning the carrier with the board; and applying flux to the flattened joining solder on the board for joining the balls to the board before positioning the carrier with the board.
15. An interconnect assembly comprising:
a first and second interconnect substrates;
a planar pattern of multiple, metal contacts on each respective substrate, for interconnection between the substrates, which are mirror images of each other to provide confronting pairs of contacts;
balls of conductive metal for respective pairs of such contacts with a ball diameter about the same as the width of the contacts; and a volume of a first joining-material for each such pair of contacts connected to the respective contact of the first interconnect substrate and a volume of a second joining-material for each such pair of contacts connected to the respective contact of the second interconnect substrate, with melting temperatures of the joining-materials of both the first and second volumes substantially less than the melting temperature of the metal-balls, with the first and second volumes of each pair of contacts connected to approximately diametrically opposite ends of a respective metal-ball, and with the smallest cross sectional area of each joining-material volume having a minimum diameter at least about 2/3 of the diameter of the metal-ball.
16. The assembly of claim 15, in which the diameter of the metal-balls and width of the contacts are about 0.6 mm to about 1.2 mm and the minimum diameter of such cross section of each joining-material volume is at least about 0.6 mm.
17. The assembly of claim 16, in which the contacts are round with a diameter of about 0.7 mm and the diameter of the metal-balls is about 0.9 mm.
18. The assembly of claims 15, 16 or 17, in which the alloy of the metal-ball includes about 80% to about 97% Pb with most all the balance being Sn.
19. The assembly of claim 18, in which the alloy of the metal-ball is from about 90% to about 95% Pb.
20. The assembly of any one of claims 15 to 19, in which:
the positions of the contacts are defined by intersections of a multitude of approximately parallel and about equally spaced lines in each of two about perpendicular directions in a plane of the surface at the contacts; and the first interconnect substrate further includes:
multiple wiring layers including one on a major surface of the substrate in which the contacts are positioned;
a multitude of conducting vias connecting between one or more other wiring layers of the substrate and the surface wiring layer at about the centers of squares defined by four of the contacts; and a conductor of the surface wiring layer for each respective via, which is substantially narrower than the contacts, and extends in a diagonal direction of the square to connect between the via and one of the four contacts surrounding the via.
21. The assembly of claim 20, in which:
the surface wiring layer containing the contacts further includes lands surrounding the vias;
the conductors extend from the lands to the conductors; and the via through holes are internally plated with a layer of copper sufficiently thick to connect electrically between the lands and other wiring layers of the structure.
22. A fabricated interconnect assembly comprising:
a first and second interconnect substrates;
a planar pattern of multiple, metal contacts on each respective substrate, for interconnection between the substrates, which are mirror images of each other to provide confronting pairs of contacts;
a ball of conductive metal for respective pairs of such contacts with a diameter about the same as the width of the contacts; and a volume of a first joining-material for each such pair of contacts connected to the respective contact of the first interconnect substrate and a volume of a second joining-material for each such pair of contacts connected to the respective contact of the second interconnect substrate, with melting temperatures of the first and second joining-materials both substantially less than the melting temperature of the metal-balls, with the volumes of the first and second joining-materials of each pair of contacts connected to approximately diametrically opposite ends of a respective metal-ball, and with the melting temperatures of the first and second joining-materials being about equal.
23. The assembly of claim 22, in which:
the alloy of the metal-ball is from about 85% to about 97% Pb and most of the balance being Sn; and the joining-material includes about 37/63 percent Pb/Sn solder alloy.
24. The assembly of claim 23, in which the joining-material is about 65 to about 75 percent Sn.
25. An interconnect structure for connection to a plane of contacts comprising:
a substrate;
a planar pattern of multiple, metal contacts for interconnecting the substrate, to another substrate with a mirror image pattern of contacts;
balls of conductive metal for respective contacts with ball diameter about the same as the width of the contacts with confronting ends of the balls at respective contacts and distal, exposed ends for connection to the mirror image contacts of another substrate; and an isolated volume of a joining-material connected between the confronting end of each metal-ball and the respective contact for that metal-ball, with a melting temperature of the joining-material substantially less than the melting temperature of the metal-ball, and with the smallest cross sectional area of the joining-material volumes having a minimum diameter at least about 2/3 of the diameter of the metal-ball.
26. The structure of claim 25, in which the diameter of the metal-ball and width of the contacts are about 0.6 mm to about 1.2 mm and the minimum diameter of such cross section of each joining-material volume is at least about 0.6 mm.
27. The structure of claim 26, in which the diameters of the contacts are from about 15 to about 30% smaller than the diameters of the balls.
28. The structure of claim 27, in which the diameter of the metal-ball is about 0.9 mm and width of the contacts are about 0. 7 mm.
29. The structure of any one of claims 25 to 28, in which the alloy of the metal-balls includes more than 80% up to about 97% Pb with substantially all the balance being Sn.
30. The structure of claim 29, in which the alloy of the metal-balls is about 95% Pb.
31. A fabricated interconnect structure comprising:
a multi-layer substrate having a wiring layer at the surface of the substrate;
a multitude of metal contacts in a matrix at positions defined by intersections of a grid of a multitude of approximately parallel and about equally spaced lines in each of two about perpendicular directions in a plane of the surface wiring layer, a multitude of conducting vias connecting between one or more other wiring layers of the substrate and the surface wiring layer at about the centers of squares defined by four of the contacts; and a conductor of the surface wiring layer for each respective via, which is narrower than the contacts, and extends in a diagonal direction of the square to connect between the via and one of the four contacts surrounding the via.
32. An information handling system comprising:
one or more central processor units connected in a network;
random access memory communicating through a bus with each central processor unit;
input/output means for communication between central processor units and with computer peripherals;
a circuit board in communication with one or more of the central processor units, with a planar pattern of round, metal contacts having a diameter of about 0.6 mm to about 1.0 mm on a major surface;
a chip carrier for one or more chips with a planar pattern of multiple, metal contacts on a major surface which pattern is approximately a mirror image of a planar pattern of contacts on the circuit board to provide confronting pairs of contacts for interconnection between the carrier and the board and which are also about 0 5 mm to about 1.0 mm in width;
a metal-ball for each respective pair of such contacts with a diameter of about 0.6 mm to about 1.3 mm; and a volume of a first joining-material for each pair of contacts connected to a respective contact of the chip carrier and a volume of a second joining-material for each pair of contacts connected to a respective contact of the circuit board, with melting temperatures of both the first and second joining-material substantially less than the melting temperature of the metal-balls, with the first and second joining-materials of each pair of contacts soldered to diametrically opposite ends of the respective metal-ball.
33. The system of claim 32, in which:
the circuit board is multi-layered;
the positions of the contacts are defined by intersections of a multitude of approximately parallel and about equally spaced lines in each of two about perpendicular directions in a plane of the surfaces at the contacts; and the circuit board further includes:
a multitude of wiring layers including one on the surface in which the contacts of the circuit board are positioned;

a multitude of plated through holes connecting between one or more other wiring layers of the circuit board and the surface wiring layer for soldering to the metal-balls; and means to control the minimum diameter of the solder volume of soldered connections for the vias including:
a circular via land contact in the surface wiring layer for each respective via connected to the end of each via at the surface;
positioning the connections of the vias with the surface wiring layer at about the centers of squares defined by four of the contacts;
a metal conductor of the surface wiring layer for each respective via, which is substantially narrower than the contacts, and extends in a diagonal direction of the square to connect between the via land and one of the four contacts surrounding the via land; and a covering of solder resist over the lands and conductors and which provides windows for the contacts.
34. Information handling apparatus comprising:
one or more central processing units connected in a network;
random access memory communicating through a bus with each central processor unit;
input/output means for communicating with computer peripherals;
a multi-layer circuit board in communication with one or more of the central processing units, having a wiring layer on the surface of the circuit board;
a multitude of metal contacts in a planar matrix pattern at positions defined byintersections of a grid of a multitude of approximately parallel and about equally spaced lines in each of two about perpendicular directions in a plane of the surface wiring layer;
a multitude of conducting vias connecting between one or more other wiring layers of the circuit board and the surface wiring layer at about the centers of squares defined by four of the contacts;
a conductor of the surface wiring layer for each respective via, which is narrower than the contacts, and extends in a diagonal direction of the square to connect between the via and one of the four contacts surrounding the via;

a chip carrier for one or more chips with a planar pattern of multiple, metal contacts on a major surface which is approximately a mirror image of a planar pattern of contacts on the circuit board to provide confronting pairs of contacts for interconnection between the carrier and the board;
a metal-ball for each respective pair of such contacts; and a volume of a first joining-material for each pair of contacts connected to a respective contact of the chip carrier and a volume of a second joining-material for each pair of contacts connected to a respective contact of the circuit board, with melting temperatures of both the first and second joining-material substantially less than the melting temperature of the metal-balls, with the first and second joining-materials of each pair of contacts soldered to diametrically opposite ends of the respective metal-ball.
35. Interconnect apparatus comprising:
a first and second interconnect substrates;
a planar pattern of multiple, metal contacts on each respective substrate, for interconnection between the substrates, which are mirror images of each other to provide confronting pairs of contacts;
a column of conductive metal for respective pairs of such contacts with a diameter about the same as the width of the contacts and positioned with a longitudinal axis about perpendicular to the plane of contacts; and a volume of a first joining-material for each such pair of contacts connected to the respective contact of the first interconnect substrate and a volume of a second joining-material for each such pair of contacts connected to the respective contact of the second interconnect substrate, with melting temperatures of the joining-materials of both the first and second volumes substantially less than the melting temperature of the metal-columns, with the first and second volumes of each pair of contacts connected to opposite ends of a respective metal-column.
36. The apparatus of claim 35, in which:
the positions of the contacts are defined by intersections of a multitude of approximately parallel and about equally spaced lines in each of two about perpendicular directions in a plane of the surface at the contacts; and the first interconnect substrate further includes:
multiple wiring layers including one on a major surface of the substrate in which the contacts are positioned;
a multitude of conducting vias connecting between one or more other wiring layers of the substrate and the surface wiring layer at about the centers of squares defined by four of the contacts; and a conductor of the surface wiring layer for each respective via, which is substantially narrower than the contacts, and extends in a diagonal direction of the square to connect between the via and one of the four contacts surrounding the via.
37. The apparatus of claim 36, in which:
the surface wiring layer containing the contacts further includes lands surrounding the vias;
the conductors extend from the lands to the conductors; and the via through holes which are internally plated with a layer of copper sufficiently thick to connect electrically between the lands and other wiring layers of the structure.
38. Fabricated interconnect apparatus comprising:
a substrate;
a planar pattern of multiple, metal contacts for interconnecting the substrate, to another substrate with mirror image contacts, a column of conductive metal for each contact with a diameter about the same as the width of the contacts and positioned about perpendicular to the plane of contacts; and a volume of a joining-material connected between each respective contact and therespective metal-column for that contact, with a melting temperature of the joining-material substantially less than the melting temperature of the metal-column.
39. The apparatus of claim 38, in which the alloy of the metal-column includes about 80% to about 97% Pb with substantially all the balance being Sn.
40. The apparatus of claim 39, in which the alloy of the metal-column is from about 90% to about 95% Pb.
41. A process for producing interconnect assemblies comprising the steps of:
producing a first substrate with an approximately planar pattern of multiple, metal contacts on a major surface;
depositing a volume of a first joining-material on each of the contacts of the first substrate;
connecting a conductive metal column to the first joining-material on each of the contacts on the first substrate for maintaining a predetermined distance between the first substrate and a second substrate when connected;
producing a second substrate with a major surface having an approximately planar pattern of multiple, metal contacts which are approximately a mirror image of the pattern of contacts of the first substrate;
depositing a volume of a second joining-material for positioning between the metal-columns and each respective contact of the second substrate;
positioning the substrates together for interconnection with contact patterns approximately parallel, with mirror image pairs of contacts in confronting approximate alignment, and with each volume of the second joining-material approximately in contact with a respective end of the metal-column and a respective contact of the second substrate;
simultaneously melting the first and second joining-materials while the substrates are positioned together, at a temperature in which the metal-columns remain solid for providing the predetermined separation between substrates, for moving the ends of the metal-columns by surface tension of the melted joining-material to positions approximately centers of the contacts;
and cooling the substrates below the melting temperatures of the joining-materials to form electrical interconnections between the pairs of contacts.
42. The process of claim 41, in which the step of connecting a metal-column to the first volumes of joining-material includes the steps of:
positioning a metal-column on each volume of first joining-material;
heating up the first substrate to connect the metal-columns to the contacts of the first substrate by melting the first joining-material without melting the metal-columns; and cooling down the first substrate to form a mechanical joint between the metal-columns and the contacts of the first substrate before the step of positioning the substrates together for interconnection.
43. The process of claim 41 or 42, in which there is a metal element which can migrate between the metal-columns and the first joining-material and such migration may increase the melting temperature of the first joining-material and during the step of heating up the first substrate the substrate is heated to a minimum temperature and for a minimum time for minimizing migration of a metal element between the metal-columns and first joining-material to minimize the increase of the melting temperature of the first joining-material.
44. The process of claim 43, further comprising the step, selecting a different joining-material for the first and second joining-materials for compensating for migration of the metal element between the metal-columns and first joining-material in order for the first and second joining-materials to be melted simultaneously during the step of heating up the substrates while positioned together.
45. A process for producing interconnect structures comprising the steps of:
producing a rigid substrate with an approximately planar matrix of multiple, metal contacts on a major surface;
depositing a volume of a joining-material on each of the contacts of the matrix of the rigid substrate;
positioning a conductive metal-column to the joining-material on each of the contacts on the first substrate for maintaining a predetermined distance between the substrate and a second substrate to which the substrate is to be connected;

melting the volumes of joining-material without melting the metal-columns to prevent changing the shape of the columns; and cooling the joining-material to form a solid mechanical joint between the metal-columns and the contacts of the substrate.
46. A process for producing an information handling system, comprising:
providing one or more central processing units connected in a network;
providing random access memory communicating through a bus with each central processor unit;
providing input/output means for communication between the bus and computer peripherals;
producing a multi-layer circuit board, having a wiring layer on the surface of the circuit board;
producing a multitude of metal contacts in a planar matrix pattern at positions defined by intersections of a grid of a multitude of approximately parallel about equally spaced lines in each of two about perpendicular directions in a plane of the surface wiring layer; and forming a multitude of conducting vias connecting between one or more other wiring layers of the circuit board and the surface wiring layer at about the centers of squares defined by four of the contacts;
forming a conductor of the surface wiring layer for each respective via, which is narrower than the contacts, and extends in a diagonal direction of the square to connect between the via and one of the four contacts surrounding the via;
providing a chip carrier for one or more chips with a planar pattern of multiple, metal contacts on a major surface which is approximately a mirror image of a planar pattern of contacts on the circuit board to provide confronting pairs of contacts for interconnection between the carrier and the board;
providing a metal-ball for each respective pair of such contacts;
dispensing a volume of a first joining-material for each pair of contacts connected to a respective contact of the chip carrier and a volume of a second joining-material for each pair of contacts connected to a respective contact of the circuit board, with melting temperatures of both the first and second joining-material substantially less than the melting temperature of the metal-balls, with the first and second joining-materials of each pair of contacts soldered to diametrically opposite ends of the respective metal-ball; and connecting the multi-layer circuit board in communication with the central processing units.
47. An interconnect structure comprising a first substrate with a first about planar area array of contacts and a second substrate with a second about planar area array of contacts, which second area array is approximately parallel to the plane of the first area array of contacts in positions corresponding to positions of the first area array of contacts; and solder extending between a pair of corresponding contacts, including a first and second cross-sections approximately parallel to the plane of the contacts, with a narrower width than either of the respective contacts of the pair; and a third cross-section approximately parallel to the plane of the contacts, between the first and second cross-sections, with a width wider than the width of either of the respective contacts of the pair.
48. The structure of claim 47 in which the solder at the first and second cross-sections has a substantially lower melting temperature than the solder at the third cross-section.
49. An interconnect structure for connection to a surface with corresponding contacts, comprising:
a first substrate;
a planar pattern of multiple, metal contacts, on said first substrate for interconnecting said first substrate, to a second substrate having a surface with corresponding contacts;
a conductive metal spacer made of a material other than a solder adjacent and extending above each metal contact on said first substrate for maintaining minimum space between said first substrate and said second substrate, and a volume of a solder material connected between each respective metal contact on said first substrate and the respective metal spacer made of a material other than a solder for that metal contact, with a melting temperature of the solder material substantially less than the melting temperature of said metal spacer made of a material other than a solder, the smallest cross-sectional area of the solder material volumes having a minimum diameter of at least 2/3 of the diameter of said metal spacer made of a material other than a solder.
50. The structure of claim 49 in which:
the width of said spacers is between 60 and 85% of the minimum center-to-center spacing between the respective contacts for said spacers;
the maximum width of a plurality of said spacers is between 50 and 150% of the width of the contacts for said spacers; and the width of a pair of contacts is between 35 and 85% of the minimum center-to-center spacing between the contacts for said spacers.
51. The structure of claim 50 in which the maximum width of the spacers is between 70 and 75% of the minimum center-to-center spacing between the contacts.
52. The structure of claim 50 in which the width of contacts is between 65 and 75% of the minimum center-to-center spacing between the contacts.
53. The structure of claim 49 in which a plurality of the spacers have two substantially spherical ends positioned for confronting respective contacts of the first substrate and contacts on the surface of the second substrate and the width of the contacts are between 60 and 150% of the width of the respective spacers.
54. The structure of claim 53 in which the cross-section of the joining material taken approximately parallel to the plane of the pattern of contacts, with minimum width, is between 60 and 100% of the width of the respective spacer.
55. The structure of claim 49 in which a plurality of the spacers have about flat ends in position to connect to the contacts of the surface and the width of the contacts for the spacers are larger than the width of the spacers.
56. The structure of claim 55 in which:
the width of a plurality of the contacts of the substrate is between 120 and 200% of the width of said flat ends of the spacers connected to respective contacts; and the surface of the joining material of a plurality of the contacts at the connection to the contact forms an angle of less than 45° with the plane of the contacts.
57. The structure of claim 50 in which the average position of the centers of the spacers is about half the width of the spacers from an edge of the contacts.
58. The structure of claim 50 in which the spacer is joined directly to the contacts of the surface.
CA002134019A 1993-10-28 1994-10-21 Solder ball connections and assembly process Expired - Fee Related CA2134019C (en)

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BR9404248A (en) 1995-06-27
EP1002610A1 (en) 2000-05-24
DE69434160D1 (en) 2004-12-30
KR0167808B1 (en) 1999-04-15
US5675889A (en) 1997-10-14
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ATE231042T1 (en) 2003-02-15
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DE69434160T2 (en) 2005-12-08
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US6504105B1 (en) 2003-01-07
EP1008414B1 (en) 2004-11-24
EP1008414A3 (en) 2000-08-23
US5591941A (en) 1997-01-07
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DE69432010D1 (en) 2003-02-20
JPH07183652A (en) 1995-07-21
KR950013337A (en) 1995-05-17
CA2134019A1 (en) 1995-04-29
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EP0650795A3 (en) 1996-01-10
EP0650795A2 (en) 1995-05-03

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