CA2134370A1

CA2134370A1 - Video data formatter for a digital television system

Info

Publication number: CA2134370A1
Application number: CA002134370A
Authority: CA
Inventors: Robert J. Gove; Donald B. Doherty; Scott D. Heimbuch; Paul M. Urbanus; Stephen W. Marshall
Original assignee: Individual
Current assignee: Texas Instruments Inc
Priority date: 1993-11-04
Filing date: 1994-10-26
Publication date: 1995-05-05
Also published as: CN1076568C; JPH07284072A; KR950016355A; US5488431A; CN1122553A

Abstract

VIDEO DATA FORMATTER FOR A DIGITAL TELEVISION SYSTEM

ABSTRACT OF THE DISCLOSURE
A digital television system (10) is provided.
System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18).
Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in first out buffer memories (34a) through (34j). One of each channel signal processors (22a) through (22d) may be coupled to two of first in-first out buffer memories (34a) through (34j).
Additionally, each formatter (24a) through (24c) may comprise channel data format units (38a) through (38d), each associated with a channel of, for example, display (24a). Channel data format units (38a) through (38d) are coupled to appropriate of first in-first out buffer memories (34a) through (34j) via multiplexers (36a) through (36d). Each formatter (24a) through (24c) may remove overlap between channels of system (10) and may format the processed video signal into appropriate channels for displays (26a) through (26c).

Description

VIDEO DATA FORM~TTER FOR A DIGITAL T~LEVISION SYSTEM

C~o~g~ LI 8~$~L]Uvi~G~D PATEN~S ~ND APPLICATIONS
The ~oll~wing patents and applications are related to the present application, iand are incorporated by reference herein:
U.S. Patent No. 4,615,595, entitled, "FRAME ADDRESSED SPATIAL LIGHT MODULATOR";
U.S. Pat~nt No. 5,079,544, entitled, "STANDARD INDEPENDENT DIGI~IZED VIDEO SYSTEN";
U.S. Patent No. 4,939,575, entitled, "FA~LT-~OLERANT SE~IAL VIDEO PROCESSOR DEVICE'~;
U.S. Serial No. 07/678,761, Atty DocXet No. TI-15721 "I:MD ARC~IT~ AND TIMING FOE~ USE IN A
PULSE-WIDTR ~ODULAT~D DISP~AY SYSTEM";
U.S. Serial No. _ , Atty Docket No. TI 1?8S5 ~: 15 "DIGITAL TELEVISION SYSTE~"; and U.S. S~rial No. _ , Atty Doc~st No. TI-18108 "SYSTEM AND ~iTHOD FQR PACXING DATA INTO VIDEO ::
PROCESSOR".
: ' ~his invention relates in general to the field o~
electronic devices. ~ore particularly, this invention -:~
relates to vide~ data ~o~matter for a digital telavision system.

SUMM~RY_OF T~E INVENTION
In accordance with the present invention, a digital television system is provided~ In designing tAe digital television system according to the teachings of the pres~nt in~ention~ a heretofore unrecognized problem was discovered. The digital television system may comprise a plurality o~ processing channels each containing a predetermin~d number of pixels. Each channel may overlap by, for example, one to five pixels with an adjacent chann~l for processing purposes. Additionally, the display of the digital television system may have a number o~ chann~ls having a di~ferent pixel width from the processing channels ~uch hat the channels of the display are incompatible with the processing channels.
~he teachings of the present invention relate to a system and me~hod for ~ormatting video data for a digital display of a digital television system.
~ ore speci~ically, the present invention provides a video data ~ormatt~r ~or use in a digital television system having a plurality o~ processing channels and a displ~y having a ~ecQnd plurality of channels. The video data ~ormatter comprises a li~e segment mapper and a data format unit. The line segment ma~per receives processed video data from the processing channels of the digital television system. The line segment mapper is operable to remov~ pixel~ ~rom adjacent processing channels that ~:
are common to bo~h channel and is operable to divide ~ :
each channel into two or more segments. The data fo~mat unit receives the stored line segments from the line seqment mapper. The data format unit is operable to couple the segments to creite a plurality of appropriate channels for the display.
It is a technical advantage of the present invention to provide a video data formatter for a digital :: :

. . ~

television system that removes ovexlap between ad~acent channels before a pxocessed video signal is displayed. .~:
The digital television system processes a video signal in ~-~
a plurality of parallel channels. The channels o~ the S system may correspond to vertical strips o~ a video frame. Each channel may contain an overlap o~, for example, one to ~ive pixels with an adjacent channel. ~ .
The overlap between channels may allow horizontal processing of pixels on the end of a channel. The overlapping pixels may be removed before the processed video signal is displayed such that redundant pixels ar~
not displayed. ~ :~
It is another technical advantage o~ the present invention to reformat the process~d video data for a display. The display may have a plurality o~ associat~d channels that differ in pixel width from the processing channels. The processing channels may be altered to :~
match the pixel without the channels of the display.
It is another technical advantage of the present in~ention to provida one bit plane of data for each ~it of video data associated with a pixel to a display of a diyital television system. The display may provide 2x inten~ity levels for each vide~ signal in response to the bit planes ~ormed ~rom the video dat~ wherein X is the :~
n~mber of bits for each pixel. The first bit plane, corr~sponding to the mqst signi~icant bit ~or each pixel, may control the display for one-hal~ of the time ~or one frame. Successive bit planes may each control the display for a period of time proportionate to the position o~ the bits o~ that bit plane in the pixels making up that bit plane.

`~:

BR_EF DESCRIPTIO~L5~E~D~ DR~WI~GS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which liXe reference numbers indicate liXa features and wherein:
- FIGURE 1 illustrates a digital television system constructing according to the teachings o~ the present invention;
FIGURE 2 illustrates four vertical strips created by the system of FIGURE l;
FIGURE 3 illustrates the overlap in pixels between adjacent channels created by the system of FIGURE l;
FIGURE 4 illustrates an e~bodime~t of a formatter of FIGURE 1 constructed to the teachings of the present invention;
FIGURE 5 illustxates a formatter constructed accordi~g to the teachings of the pres~nt invention;
FIGURE 6 is a timing diagram that illustrates how data is st~red in the ~ormatter o~ FIGURE 5 for a syste~
comprising four processing channels;
FIGURE 7 is a ti~ing diagram that illus~rates how data stored according to the timing diagra~ of FIGURE 6 is ~ormatted ~or channels o~ a display o~ FIGURE l;
FIGURE 8 is a timing diagram that illustrates how data i~ stored in the formatter of FIGURE 5 ~or a system comprising five processinq channels;
FIGURE 9 is a timing diagram that illustxates how data stored accor~ing to the timing diagram of FIGURE 8 is formatted ~or channels o~ a display of FIG~RE l;
FIGURE 10 illustrates an embod.iment of a channel data format unit o~ FIGURE 5 constructed according to the teachings of the present invention;

FIGURE 11 illustrates another embodiment of a formatter constructed according to the teachings of the present invention; and FIGURE 12 illustrates another embodiment of a S formatter constructed according to the teachings of the present invention.

~ '.`', DETAILED DESC~IPTION OF THE INVENTION
FIGUREi 1 illustrates a digital television system indicated generally at 10 and constructed according to the teachings of the present invention. System 10 comprises a parallel architecture wherein input video signals may be divided into channels to b~ processed in parallel. For example, system 10 may implement appropriate functions such that a standard video signal . .
may be used to provid~ a high de~inition video display.
Alternatively, system 10 may sample and display a high de~inition videa signal.
System 10 may receive video signals in composite or component form. For example, syste~ 10 may receive an analog composite video signal, an analog ~ideo signal in component form, or a digital video signal. Syste~ 10 may convert a composite video signal into a plurality of ~ideo signals for processing. For example, an analog composita video signal in the format established by the National Television Standards Committee (hereinafter "NTSC") may be separated into a luminance signal, identi~ied by the symbol Y, and two color difference signals, identified by the symbols I and Q.
Alternatively, system 10 may separate other standard compo~ite video signals into appropriate video signals ~or processing according to Table 1 below.
~~ d LE 1_ Input Video For=at _ _ y, I, Q
P~L and SECA~ _ _ Y, U, V
~P~3 z~0M, SY~E 260M Y, Pr, Pb _ :::
It is noted that the other standard video ~ormats include: Phase Alternating Line, hereina~ter "PAL";

Sequential Color with Me~ory, hereina~ter 'ISEC~M''; and Society of Motion Picture Engineers, hereina~ter "SMPTE".
Each o~ these standard video signals comprise a lu~inance signal, hereina~ter '/luma" or "Y", and a chrominance ~ignal, hereinafter "chroma" or "C". The chroma signal may be further divided into appropriate color di~ference signals as shown in Table 1. For clarity, each ~f the standard video si~nals may hereinafter be referred to as providing a video signal in a "color di~ference color space" or a "Y-I-Q color -~
space." As an alternativ~ to the standard video signals ~f Table 1, a video source may be coupled t~ syste~ 1o to ~ .
provide a red video signal, hereina~ter "R'3, a gr~en ;.
video signal, hereinafter "G", and a blue video signal, --hereinafter "B". Such a video source may hereinafter be refereed to as providing a video signal in an '~R-G-B ;::
color spac~
Syste~ 10 prepares a vidPo signal for parallel proceseing in receiving circuitry 12, and line slicer 14.
Receiving circuit~y 12 may recaive, for example, a ~
composite video signal in the NTSC format from an ~ :
external source (nct explicitly shown). Alternatively, receiving circuitry 12 may receive separate Y and C vid~o signal~. Furthermore, receiving circui~ry 12 may receive ~5 separate video signals in an ~G-B color space~ The format o~ th~ video signal is indicated to receiving circuitry 12 by a mode s~lect input. ~:
Receiving cir~uitry 12 co~pri~es composite video interface ~nd separa~ion circuit 16 coupled to analog to digital converter circuit 18. Composite video interfa~e and separation circuit 16 may separate a composite video signal in~o, for example, three separate video signals.
Analog to digital converter circuit 18 may convert each :
of the separate video signals into ten bit digital video signals. ~nalog to digital converter circuit 18 of receiving circuitry 12 is coupled to provide three ten bit digital video signals to line slicer 14.
Additionally, a digital video signal may be coupled directly to line slicer 14. ~ :
Line slicer 14 divides each digital video signal into a plurality of separate channels ~or each line cf composite video signal. For example, line slicer 14 may ~:
divide each digital video signal into four, ~ive or ;:~
ano~her appropriate numb~r of channels. The number o~
channels may depend on the number of pixels in a line of ;~
video signal, and the number of p~xels ~hat may be simultaneously processed by a video ignal processor of system 10. Line slicer 14 may provide appropriate overlap between the various channels ~or processing as des~ribed below.
System 10 processes the digital ~ideo signals in processing circuitry 20. Processing circuitry 20 is coupled to lin~ slicer 14. Processing circuitry 20 comprises a plurality o~ channel signal processors 22a through 22d. The number o~ ehannel signal prccessors 22 may be equal to the number of channels provided by line slicer 14. Each channel signal pxocessor 22a through 22d receiv~s all thr~e 10 bit digitaL video signals ~or the cha~n~l corresponding to that signal processor 22a through 22d. Proces ng circuitry 20 may conver~ each line of digital video signal into two lines of digital ~ideo signal output~ Each channel signal processor 2~a through 22d, thexe~ore, may have six separate outputs, for example, two ten bit red outputs, two ten bit green outputs, and two ten bit blue outputs. Additionally, processing circuitry 20 may perform the following .~unctions: color space convar~ion, gamma correction, and picture quality control which will be described in detail ~:~
below.
System 10 reconnects and displays the processed . :~
video data. A plurality of formatters 24a through 24c -:
reconnect the video data and a plurality of displays 26a ::~
through 26c display the video data. One formatter ~4a through 24c and on2 display 26a through 26c operate on a different digital video signal as indicated in FIGURE 1.
For example, formatter 24a and display 26a may operate on a red video signal. Formatter 28b and display 26b may ~:
operate on a green video si~nal. Finally, for~atter 24c and display 26c may operate on a blue video signal. ~:
Two ten bit outputs of each channel siynal processor 22a through 22d are coupled to an appropriate formatter 24a through 24c. Forma~ters 24a through 24c remove overlap bqtween adjacent channels, reconnect th~
channels, and prepare the reconnected digital video signals for display on displays 26a through 26c. ~
Formatters 24a through 24c each provide 128 bit words in ~ :
four 32 bit channels to displays 26a through 26c. : :
Displays 26a through 26c may comprise, ~or exa~ple, a Spatial ~ight Modulator (hereinafter 'ISLMI') such as a 2 x 128 pin Digital Micromirror Device (hereinafter "DMD") ~ ~ :
pro~uced by TEXaS INSTRUMENTS INCORPORATED. However, displays 26a through 26c are not limited to digital displays. It is within the scope of the teachings of the present invention for the processed video signal to be displayed on an analog display.
Timing and control circuit 28 is coupled to compasite video interface and separation circuit 16, analog to digital converter circuit 18, line slicer 14, processing circuitry 20, formatters 24a through 24c, and displays 26a through 26c. Timing and control circui~ 28 is operable to control the timing of each aspect of ~,'':::,.,'.,.,.''"','.'''`'''""'" ''''"''`',' '`';

system 10. The timing of system 10 may be accomplished throu~h use of a synchronization (hereinafter "sync") signal supplied to timing and control circuit 23 by composit2 video interface and separation circuit 16.
Additionally, timing and co~trol circuit 28 is operable ~ '~
to accept user inputs to control the timing of various functions of system 10.
In operation, system 10 may prepare a standard video signal to produce a high definition display. As d~scribed previously, system 10 may receive analog or digital video signals in ~omposite or separated form.
For conciseness, the op~ratio~ of syste~ 10 is described in conjunction with receiving an analog composite video `~
signal. System 10 separates a composite video signal into video signals, divides the video signals into a plurality of channels, and processes the channels in :
parallel. An advantage o~ using a parallel ar~hitecture in system 10 is that system 10 is able ~o process the video signals at a low speed while providing a high definition display. Consequently, system 10 may incorporate existing video processor components.
Composite video inter~ace and separation circuit 16 separates the comp~site vide~ signal into, for example, three separata video signals. Composite video inter~ace and separation circ~it 16 may, for example, separate a composite video ~ignal into Y, ~, and Q video signals of the NTSC standard.
Analog to digital converter circuit 18 may sample each video signal at a frequency of, for example, 71.1 MX~. The appropriate sampling rata may depend on the number o~ pixels allocated for a line of video on displays 26a through 25c, and the time for one line of video signal to be received by receiving circuitry 12.
There~ore, the sampling rate may be adjusted to create a predetermined number of pixels for each line of video sign~l. Analog to digital converter circuit 18 may comprise, for example, Analog to Digital Converter board AD9060 produced by ANALOG DEVICES. Alternatively, analog S to digital converter circ~tit 18 may comprise another appropriate analog to digital converter device operable to sample data at an appropriate sampling rate on the order of 75 ~Hz.
Line slicer 14 divides each digital video signal into a plurality o~ separate channels ~or each line o~ :
video signal. For example, line slic~r 14 may divide ~:
each line of the digital video signal into four channels so that the video signal may be processed in parallel. ::
By dividing each line o~ digital video signal in the same manner, each cha.nn~l signal processor 22a through 22d effectively procasses one vertical strip of each video "~ :
frame. FIG~RE 2 shows t~e four vertical strips processed by cha.nnel signal processore 22a through ~2d for the . :
embodiment o~ F~GURE l. Alternatively, line slicer 14 may divida a line o~ a pixel by pixel basis or line .
slicer 14 may divide a video frame into horizontal strips. A~ advantage of dividing a video ~rame into vertical strips is that the related processing steps per~ormed by pro~essing circuitry 20 are simpli~ied.
Addi~ionally, line ~licer 14 may provide for overlap between the vertical channels by providing common pixels to adjacent channels as shown in FIGURE 3. The overlap may comprise, for example, from one to five pixels. The overlapping pixels may be used to provide appropriate data for each channel to perform the various functions described belaw as called for by processing circuitxy 20.
The amount o~ Gverlap between channels may be varied depending o~ the specific functions implemented in processing circuitry 20.

: ' System 10 processes the digital video signals in processing cir uitry 20. Proc~ssing circuitry 20 may perform ~he progressive scan function (hereinafter "proscan"). Proscan "de-interlaces" a video si~nal by creating an entire video frame ~rom a single or ~ultiple :~:
video fields at th~ field rate. As described previously, a standard video signal may comprise two fields of video ~:
data f or each frame. Additionally, processing circuitry 20 may convert the digital video signals into a different color space. For example, processing circuitry 20 may :~
convert digital video signals from a color di~ference color space to an R-G-B color space. Furthermore, processing circuitry may remove a gamma curve from a standard video signal. Finally, processing circuitry 20 may c~ntrol the quality o~ a video display in respons~ to user inputs s~lch as inputs for adjustments to brightness, hue, contrast, sharpness and satura~ion. Each of these functions is described in detail below.
System 10 reconnects and displays the processed di~ital video signal using formatters 24a through 24c and displays 26a ~hrough 26c. Formatters 24a through 24c remove overlap b¢tween adjacent channels. Additionally, for~a~ters 24a through 24c prepare the reconnected digital vide~ signals for-display on displays 26a through 26c. For example, formatters 24a through 24c may produce a plurality o~ bit planes from the reconnected digital video signals. Each bit plane may corresp~nd to a particular ~it for each pixel in a particular video frame. In the embodiment of FIGURE 1, formatters 24a throu~h 24c each may produce 10 bit planes of video data for each separate video signal that ax~ to ~e provided to displays 26a through 26c in 128 bit words. Based on the output of formatker~ 2~a through 24c, displays 26a through 26c may project appropriate images correspondinq to the processed video signals on, for example, a scr~en (not ~hown). The combination of th~ different video :
signals output by displays 24a through 24c result in a single, appropriately colored, image.
It should be understood that system 10 may be ~ :
opera~le to be programmed to accept any appropriate standard analog Qr digital video signal. Alternatively, system 10 ~ay be preprogrammed to accept only a limi~ed number of appropriate standard analog or digital video signals. ~ :~
FIGURE 4 illus~rates an embodiment of a formatter indicated generally at 24' and constructed according to :~
the t~achings of the present invention. one formatter :
24' of the type illustrated in FIGURE 29 may be used for ~:~
each of ~ormatters 24a through 24c of FIGURE 1. For conciseness, ~ormatter 24' will be describad in terms o~
~ormatter 24a of F~GURE 1. It is unders~ood that fo~matter 24' is not so limited, but may be used for formatters 2~b and 24c as well.
Formatter 24~ comprises line segment mapper 30 and :
data format unit 32. Line segment mapper 30 is coupled to two output line~ from each channel signal processor 22a through 22d of FIGURE 1. For example, line segment mapper 30 may be coupled to the two o~tput lines corresponding to the red component video signal from each channel siqnal pro essor 22a through 22d. Line segment mapper 30 is coupled to provide a number o~ outputs equal to the number o~ inputs to data fo~mat unit 32. ~ata format unit 32 provides ~our 32 bit output signals to di~play 26a of FIGURE 1.
In operation, line seg~ent mapper 30 receives processed video data for one of the component video .
signals, such as, for example, the red component. The video signals received ~rom channel signal processors 22a through 22d of FIGURE 1 contain some overlap due to the manner in which line slicer 14 divides the input video :
signals as described previously with respect to FIGURE l.
Line seg~ent ~apper 30 operates to remove the overlap in the various channels caused by line slicer 14. Once the overlap has been re~oved, the video signal is ~or~atted, for example, for display 26a of FIGURE 1 by data format unit 32. For example, data format unit 32 may create a series of bit planes wherein one bit o~ data in each bit plane corresp~nds to each pixel of display 26a. Data format unit 32 may provide these bit planes to display 26a in 128 bit words as described below.
FIGURE S illustrates a formatter indicated generally at 24' and constructed according to the teachings o~ the . .
present invention~ System 10 may comprise one formatter 24' for each formatter 2~a through 24c. For conGiseness, ~ormatter 24' will only be described with respec~ to format er 24a. It is unders ood that the description of formatter 24' is equally applicable to formatters 24b and 24c.
As described previously wi~h respect to FIGURE 1, line slicer 14 may provide, ~or example, two or ~hree pixels of overlap b~tween adjacent channels for processing circuitry 20. Formatter 24' may be used to remove this overlap such that a line of video displayed on displays 26a through 2~ does not display redundant pixels. Additionally, displays 26a through 26c may be divided into a plurality of channels. The pixel width o~
the channels of displays 26a through 26c may b~ different ~rom the pixel width o~ the channels of processing circuitry 20. Formatter 24' may reorganize the channels of processin~ circuitry 20 of FIGURE 1 to pro~ide an appropriate plurality of channels ~or displays 26a thraugh 26c of FIGURE 1.

Formatter 24' may comprise, ~or example, lin~
segment mapper 30' and data format unit 32'. Line segment mapper 30' may comprise, for example, a plurality of first in-first out bu~fer memories 34a through 34j.
Formatter 24' may comprise five separate input c~annels l~belled A through E. Input channels A through E of :~
formatter 24' may be coupled to appropriate channels of ::
processing circuitry 20 o~ FIGURE l. Fox example, input channels A, B, D and E may be coupled to channel signal ~-processors 22a through 22d of FIGURE 1 respectively.
Alternatively, in an embodiment of proc~ssing circuitry 20 comprising five channel signal processors, each channel signal processor may be coupled to an appropriate inpu~ channel A, B, C, D or E.
Each input channel A through ~ may be coupled to ~wo first in first out buf~er memories 34a thro~gh 34j o~
line segment mapper 30'. With each channel A khrough E
coupled to two ~irst in-~irst out buffer memories, line segment mapper 30' may move a plurality of pixels from one end o~ one inp~t channel to the opposite end of a display channel. In the embQdiment of FIGURE 5, input channel A is coupled to first in-~ixst out bu~er memories 34a and 34c~ Input channel 8 is coupled ~o ~irst in-first out bu~fer memories 34~ and 34d. Input channel C is coupled to first in-first out bu~er memoxies 34e and 34~. Input channel D is coupled to first in-first out buffer memories 34g and 34i. Input channel E is coupled to first in-first out buffer memories 34h and 34j. Each input channel ~ through E may be coupled to two lines of output from processing ci~cuitry 20 of FIGURE 1.
Data ~ormat unit 32' may comprise a plurality of channels each corresponding to an appropriate channel or display 26a of FIGURE 1. For example, data format unit 32' may be divided into four separate channels to provide four separate 32 bit outputs to display 26a o~ FIGURE l.
Dat^a format unit 32' may comprise, ~or example, a plurality of multiplexers 36a through 36d, and a plurality of channel data format units 38a through 3~d.
~ach multiplexer 36a through 36d is associated with an appropriate channel data format unit 3~a through 38d.
Each multiplexer 36a through 36d comprises three inputs.
The inputs of multiplexer 36a are coupled to first in-first out buf~er memories 34a and 34b and a constant zero input. Multiplexer 36b is coupled to first in-first out bu~fer memories 34c through 34e. Multiplexer 36c is coupled to first in-first ou~ buffer memories 34f through 34h~ Multiplexer 36d is coupled to firs~t in-first out buf~er memories 34i and 34j and a constant zero input.
Each multiplexer 36a through 36d is coupled to an appropriate chann~1 dat2 ~ormat unit 38a through 38d.
It is noted that ~he embodiment of formatter ~4' illustrated in FIG~RE 5 may be usad in a syste~ having four or five parallel processing channels. However, the teachings o~ the present invention are not intended to be limited to a system having four or five channels. The teachings of the present invention encompass a system having less than four channels as well as a sys~em having more tha~ five channels.
In operation, fo~matter ~4' stoEes a line o~ video data in line ~egment mapper 30'. FIGURE 6 is a timing diagxam that illustrates how the data received from the :~
channels o~ system 10 are stored in first in-~irst out buffer memories 34a through 34j. The timing provided for by FIGURE 6 allows formatter 24' ~o remove overlap between adjacent channels and to prepare appropriate channels for display 26a. Each time unit of FIGURE 6 corresponds to the time for storinq o~e pixel of data in a first in-first out buffer memory 34a through 34j.
Beginning at a time 1 in FI GURE 6, channel s s, D and E
each discard the first pixe1 of video data for their respective channelsO The first pixel of each of these channels corresponds to an overlapping pixel as shown in FIGURE 3. At time 1, channel A begins storing pixels in first in-first out buffer memories 34a. At time 2, channels B, D and E each discard the second pix~l o~
their respective channels. At time 3, channels B, D and lo E each begin s~oring pixels in first in-first out buf~er memories 34b, 34g, and 34h respectively. At time 38, channel E switches to storing pixels in ~irs~ in-first out buffer memoxy 34j. Channel E is switched to compens~te for di~ferences in pixel width between the channels of processing circuitry 20 and the chann~ls of display 26a. Thi~ function allows a p~rtion of channel E
to ~e combined with channel D. At time 442, channel A
switches to stoxing pixels in first in-first out buffer memory 34c to compensate ~or di~ferences in pixel width ~:
b~tween the channels of processing th~ circuitry 20 and thQ channels of display 26a. At time 478, channels ~, a, D and E s~op storing pixels. Thereby, pixels 479 and 480 o~ each cha~nel ar~ discarded to remove overlap bet~een the channels. At ti~e 480, the period for storing data for a particular line of video signal in line se~ment mappcr 30~ terminate~. It is noted that the timing shown ~:
in FIGURE 6 may be adjusted to control the number of pi~els that are removed from the various channe1c. For example, channel A may begin storing pixels at time 4 thereby removing pixels, l, 2 and 3. Additionally, the time at which a channel is switched from one buffer memory to another may be altered to provide appropriate channels for display 26a. Thus, the overlapping pixels are removed from channels A through E and channels A ~;

thxough E are prepared to be combined into appropriate channels for display 26a.
FIGURE 7 is a timing diagram that illustrates how . .
data is received from firs~ in-first out buffer memories 34a through 34j to create appropriate channels for display 26a. The pixels stored in first in-first out b~fer memories 34a through 34j are communicated to channel data format u~its 38a through 38d by multiplexers 36a through 36d, rsspectively.
Multiplexer 36a provides a constant zero input to channal data ~ormat unit 38a from time 1 through time 70.
Therefore, the ~irst 70 pixels of each line correspond to a black strip on a first side o~ a displayed video ~rame.
Multiplexer 36a provides the pixels stored in ~irst in-first out buffer memory 34a to channel data ~ormat unit 38a from time 71 through 512 thereby completing a channel of display 26a.
Multiplexer 36~ provides pixels ~rom channels A and B to channel data rormat unit 38b. Pixels stored in ~irst in-irst out bu~fer memory 34c from channel ~ are : pro~ided to cha~nel data ~ormat unit 38b from time 1 through time 36. 3egin~ing at time 37, pixels stored in ~irst in-first out buffer memory 34b from channel B are provided to chaDnel data ~ormat unit 3~b. In this 2S manner, pixels from channel A are combined with pixels from channel B to for~ another channel ~or display 26a.
Multiplexer 36c combines pixels from channel D with :~
pixels from channel E to form another channel rOr display ~:.
26a. ~eginninq at time 1, multiplexer 36c provides pixels stored in first in-~irst out buffer memory 34g to channel data format unit 38c. At time 476, multiplexer 36C switches to provide pixels from ~irst in-~irs~ out buffer memo~y 3~h channel to data format unit 36c.

Multiplexer 36d provides pixels from channel E to channel data ~ormat unit 38d. From time 1 through time 442, multiplexer 36d provides pixels stored in first in-first out buffer memory 34j to channel data format unit 38d. Beginning at time 443, multiplexer 36d provides a constant zero input to channel data format u~it 38d. The last 70 pixels of each line of video thereby correspond to a black strip on a second side of a displayed video ~rame. Thus, ~ormatter 24' reformats the channels of procassing circuitry 20 ~or use with the channels o~ display 2~a.
FIGURE 8 is a timing diagram that illustrates how data from a syste~ 10 comprising 5 channels is storad in first in-first out buffer memories 34a through 3~j~ The timing provided for by FI~URE 8 allows formatter 24' to .
remove overlap between adjacent channels and to prepare appropriate channels for display 26a. Each time unit of FIGURE 8 corresp~nds to the time for storing one pixel of data in a first in-first out buffer memories 34a through 34j.
Beginning at ~im~ 1 in FI~URE ~, channels A through E each discard the first pixel of video data for their respective channels. The first pixel of channel A may be removed because it is a~ edge pixel that was not fully ~::
processed. As for chan~als B through E, the first pixel ~:
corresponds to an overlapping pixel. At time 3, channels B through E begin storing pixels in first in-first out bu~fer memories 34b, 34e, 34g, and 34j respectively. In :~ ;
this manner, channels B through E remo~e the second pixel of their respective channels. At time 4, channel A
begins storing pixels in first in-first out buffer me~ory 34a thereby xemoving pixels 2 and 3 fro~ channel A. At time lOS, channel B switches to storing pixels in first in-first out buffer memory 34d. Channel B switches to ~' compensate for differences between the channels of processing circuitry 20 and the chann~ls of display 26a.
Similarly, at time 207, channel C switches to store pixels in first in-first out buffer memory 34f. Finally, at time 309, channel D switches to store pixels in first in-first out buffer memory 34i.
At time 411, channel E stops storing pixels thereby removing pixels 412 ~hrough 414 Xrom channel E.
Similarly, channels A through D stop storing pixels at time 412 thereby re~oving pixels 413 and 414 from ~:
channels A through D respecti~ely. As with FIGURE 6, it is noted ~hat the timing shown in ~I~UR~ 8 may be adjusted to control th~ nu~ber o~ pixel5 that are re~oved from the various c~annels. Additionally, the time at which a channel is switched fro~ one buffer memory to another may be altered to provi~e appropriate channels ~or display 26a. Thus, the overlapping pixels are removed from channels A through E and channels A through E are prepared to be combined in appropriate channels ~or display 26a.
FIGURE 9 is a timing diasram for retrieving data from ~irst in-first out bu~fer memories 34a through 34j to create appropriate channels ~or display 26a.
~ultiplexer 36a combines pixels from channel ~ and cha~n~l B to produce a single channel for display ~6a.
~ultiple~er 36a provides the pixels stored in f irqt in- . :
first out buffer memory 34a to channel data format unit 38a from tiMe 1 throllgh time 409. Multiplexer 36a also ~.
provid~s the pixels storad in first in-first out buffer memory 34b to channel data format unit 38a from time 410 : :
through time 512.
Multiplexer 36b combines pixels from channels 8 and C to form a ~ingle channel for display 26a. Multiplexer 36b provides pixels stored in fixst in-first out bu~fer memory 34d to channel data format unit 38b from time 1 through time 307. ~ultiplexer 36b provides pixels from first in-~irst out buf.~er memory 34e to channel data format unit 38b from time 308 through time 512.
S Multiplexer 36c combines pixels from channels C and D to form a single channel for display 26a. ~ultiplexer 3Sc pro~ides pixels stored in first in-first out buffer memory 34d to channel data format unit 38b from time 1 through time 307. ~ultiplexer 36c provides pixels from first in-first out bu~er ~emory 34f to channel data ~ -format unit 38c from time 1 through time 205. ~::: : :~
~ultiplexer 36c provides the pixels stored in first in-~irst out bu ~er memory 34g to chan~el data format unit 38c ~ro~ time 206 to time 512.
Multiplexer 36d combines pixels fro~ channels D and E to form a single channel for display 26a. ~ultiplexer -~
3~d provides pixels stored in first in-first out buffer ~ .
me~ory 34i to c~annel data format unit 38d from time 1 through time 103. Multiplexer 36d provides pixels from ~irst in-~irs~ out bu~fer memory 34j to channel data for~at unit 38d ~rom time 104 through time 512. Thus, formatter 24' re~ormats the c~annels o~ processing circui~ry 20 ~or use with the channels o~ display 26a.
FIGURE lO illustrates an embodiment o~ a channel data for~at unit indicated generally at 38' and con~tructed according to the teachings of the present inventionO Oata for~at units 38a ~hrough 38d may comprise a data format unit 3~' of FIGURE 10. For conciseness, however, channel data format unit 38' will be described in texms of the location o~ data format unit 38a o~ FIGURE 5. Additionally, channQl data format unit 3~' will be described in terms of display 26a o~
FIGURE 1. It should be understoQd that channel data ~ormat unit 38' i~ not so limited, but may be used as , .

channel data format unit 38b through 38d and may be used with display 26b or 26d.
~ata format unit 38 ~ comprises buf~er memory 40 and a plurality of multiplexers 42. Plurality o~
multiplexers 42 may comprise, for example, 32 multiplex~rs controlled by a bit select signal from timing and control circuit 2~ o~ FIGURE 1. Buffer ~emory 40 is coupled to multiplexer 36 as shown in FIGURE 5.
Buffer memory 40 comprises a plurality o~ me~ory locations 44 equal in number to the number of pixels in one channel of ~isplay 26a. Memory locations 44 may, Pox example, be oriented in 16 rows, each comprising 32 columns. Each multiplexer 42 may be coupled to an output o~ buf~er memory 40 corresponding to a colu~n of memory locations 44.
In operation, one channel, for example, a channel of ~.
display 26a associated with channel data ~ormat ~,it 38a, o~ an individual line o~ video signal may be sequentially received and stored in memory locations 44 of bu~fer ~emory 40. Each memory location 44 comprises 10 bits of .:
~ideo data ~or one pixel in a single channel of a line of ~:
a video frame. The video data may be communicated to a channel of display 26a of FIGUR~ or example, one line at a tims to form 10 bit planes. A bit plane corresponds to one bit o~ data for each pixel in a video frame.
~Aerefore, the first bi~ plane, for example, may ~ ~
correspond to the most signi~icant bit ~or each pixel and :
the tenth bit plane may correspond to the least significant bit for each pixel.
Once th,e data for a channel o~ a first line o~ a video frame is stored in bu~fer memory 40, channel data ~ormat un.it 38 ' may create the first line of the appropriate bit planes for one channel of display ~6aO
Channel data foxmat unit 38' may communicate the first line of the ten bit planes for the one channel of display 26a in 32 bit words to display 26a of FIGURE 1. For example, the first 32 bit w~rd used in for2ing a channel of the first line of the first bit plane may correspond the bottom row of memory locations 44 of buffer memory 40. The first bit of each memory location 44 in successive rows of bu~fer memory 40 may be usad to create ~uccessive 32 bit words to fill out the first line of the first bit plane for the channel of display 26a. The first line of a first bit plane for the channel is complete once all of the first bits stored in all of the rows of memory locations 44 have been usèd. This process may be repeated for su~c~ssiva bits in each memory location 44 until all of the data for a channel o~ a ~ingle line o~ video signal has been communicated to display 26a of FIGURE 1. Thereby, the first line of each of the 10 bit planes o~ data for a channel oP a single frame of video signal are communicated to display 26a of FIGURE 1. The rPmaining lines of each o~ the ten bit plane~ associated with a fra~e o~ video may be c~mmunicated to display 26a o~ FIGURE 1 by repeating the above prOGeSS ~or each line in the video frame.
FIGURE 11 illustrates an alternativ~ embodiment of a formatter indicated generally at 24''. Formatter 24'' comprises a single multiplaxer 36' in place o~
mul~iplexers 36a through 36d of F~G~R~ 5. ~ultiplexer 36' may comprise a single output line coupled to digital to analog converter 46. Digital to analog co~verter 46 may be coupled to an approp~iate analog display such as a cathode ray tube (CRT) device.
In operation, first in-first out buffer memories 34a through 34j may store video data as described above with respect to FIGUREs 5, 6, and 8. Video data may be read out of first in-first out bu~fer memsries 34a through 34j i`

by ~ultiplexer 36' so as to provide a single stream of video data for CRT 40. The outE~ut of ~ultiplexer 36~ may be converted to an appropriate analog signal for CRT 40 by digital to analog converter 46. The timing of digital to analog converker 4~ and multiplexer 36~ is controlled by timing and control circuit 28.
FIGURE 12 illustrates an alternative embodi~ent of a formatter indicated generally at 24'''. Formatter 24''' comprises a single multiplexer 36~ in place of :~
multiplexers 3~a through 36d of FIGURE 5. ~utliplexer 36'~ may comprise an appropriate number Or outpu~ lines coupled to liquid c~ystal display (LC~) 50. :
In operation, first in-first out buf~er memories 34a through 34j may stoxe video data as described ahcve with respect to FIGUREs 5, 6, and 8. Video data may be read . .
out o~ first in first out buffer memories 34a through 34j :: :
by multiplexer 3~' so as to pro~ide an appropriate stream of video data for LCD ~0~ The timing of multiplqxer 36'' is controlled by timing and control circuit 28. ::
Although th~ present inve~tion has been described in detail, it sho~ld be understood that various changes, substitutions and alterations may be ~ade hereto without departing from the spirit and scope of the in~ention as defined by the appended claims. For example, th~ number o~ channels provided in processing cixcuitry 20 may be varied without departinq from the spirit and scope of the present inve~tion. Furthermore, the extent ~f overlap between adjacent channels may be varied without departing ~rom the spirit and scope of the invention.
Additionally, the formatter of the present invention may be used to format video data ~or various types of displaye,

Claims

WHAT IS CLAIMED IS:

1. A video data formatter for a video system having a plurality of processing channels, comprising:
a line segment mapper responsive to the plurality of processing channels and operable to remove pixels from adjacent processing channels that are common to both channels, said line segment mapper further operable to divide each of said processing channels into two or more segments; and a data format unit responsive to said line segment mapper and operable to couple said segments so as to create at least one stream of video data for a display.

2. The video data formatter of Claim 1, wherein said line segment mapper comprises a plurality of buffer memories.

3. The video data formatter of Claim 1, wherein said line segment mapper comprises a plurality of first in-first out buffer memories.

4. The video data formatter of Claim 1, wherein said line segment mapper comprises two buffer memories for each processing channel.

5. The video data formatter of Claim 1, wherein said line segment mapper comprises two first in first out buffer memories for each processing channel.

6. The video data formatter of Claim 1, wherein said data format unit comprises:
a plurality of multiplexers operable to output the segments of the processing channels; and a plurality of channel data format units responsive to said multiplexers and operable to store video data such that said stored video data of each channel data format unit corresponds to a channel of the display.

7. The video data formatter of Claim 1, wherein said data format unit comprises:
a multiplexer operable to output the segments of the processing channels; and a digital to analog converter responsive to said multiplexer and operable to provide an analog output to an analog display.

8. The video data formatter of Claim 1, wherein said data format unit comprises a multiplexer operable to output the segments of the processing channels for a liquid crystal display.

9. The video data formatter of Claim 1, wherein said data format unit comprises two additional inputs responsive to a centering signal and operable to center the video data from the processing channels on the display.

10. A video data formatter for use in a digital television system having a plurality of processing channels, comprising:
a plurality of buffer memories responsive to the processing channels and operable to remove pixels from adjacent processing channels that are common to both channels, said plurality of buffer memories further operable to divide each channel into two or more segments, and a data format unit responsive to said line segment mapper and operable to couple said segments so as to create at least one stream of video data for a display.

11. The video data formatter of Claim 10, wherein said plurality of buffer memories comprises a plurality of first in-first out buffer memories.

12. The video data formatter of Claim 10, wherein said plurality of buffer memories comprises two buffer memories for each processing channel.

13. The video data formatter of Claim 10, wherein said plurality of buffer memories comprises two first in-first out buffer memories for each processing channel.

14. The video data formatter of Claim 10, wherein said data format unit comprises:
a plurality of multiplexers operable to output the segments of the processing channels; and a plurality of channel data format units responsive to said multiplexers and operable to store video data such that said stored video data of each said channel data format unit corresponds to a channel of the display.

15. The video data formatter of Claim 10, wherein said data format unit comprises:
a multiplexer operable to output the segments of the processing channels; and a digital to analog converter responsive to said multiplexer and operable to provide an analog output to an analog display.

16. The video data formatter of Claim 10, wherein said data format unit comprises a multiplexer operable to output the segments of the processing channels for a liquid crystal display.

17. The video data formatter of Claim 10, wherein said data format unit comprises two additional inputs responsive to a centering signal and operable to center the video data from the processing channels on the display.

18. A method for formatting video data, comprising the steps of:
processing video data in a plurality of parallel channels, each channel having a predetermined width in pixels and having a predetermined pixel overlap with an adjacent channel;
storing the processed video data in a first plurality of buffer memories such that the overlapping pixels are removed; and multiplexing the stored video data into a second plurality of buffer memories to reformat the plurality of channels to provide at least one stream of output video data to a display.

19. The method of Claim 18, wherein the step of storing the processed video data further comprises the step of storing the processed data in a plurality of first in-first out buffer memories.

20. The method of Claim 18, wherein the step of storing the processed video data further comprises the step of storing the processed data in a plurality of first in-first out buffer memories having two buffer memories associated with each processing channel such that each processing channel may be separated into two parts.

21. The method of Claim 18, wherein the step of multiplexing the stored video data further comprises the step of combining portions of adjacent channels to produce a plurality of channels of a digital display.