CA2137723C

CA2137723C - Display apparatus

Info

Publication number: CA2137723C
Application number: CA002137723A
Authority: CA
Inventors: Kazunori Katakura; Yutaka Inaba
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1993-12-14
Filing date: 1994-12-09
Publication date: 1996-11-26
Anticipated expiration: 2014-12-09
Also published as: EP0658870A2; CA2137723A1; EP0658870B1; CN1126917A; AU693486B2; ATE192875T1; DE69424383D1; EP0658870A3; KR0154356B1; KR950020375A; AU8039994A; US6057824A

Abstract

A display apparatus is constituted by a display device comprising a pair of oppositely disposed substrates having thereon scanning electrodes and data electrodes, respectively, and an optical modulation substance disposed between the substrates so as to form a number of pixels each at an intersection of the scanning electrodes and the data electrodes; and drive means capable of setting one frame period to be divided into different periods of sub-frames. The drive means further includes means for setting a whole picture scanning period for scanning all the scanning electrodes and a partial rewrite period for scanning only scanning electrodes for effecting a required display change so as to allow a partial rewrite in a shorter cycle than a frame cycle.

Description

DISPLAY APPARAT~IS

FIELD QF ~mHE INVENTION ANl~ RELAq'ED ART
The present invention relates to a display 5 apparatus for use in a tPrm;n~l monitor for a computer, a view finder ior a video camera, a light valve for a projector, a television receiver, a car navigation system, etc., particularly a display apparatus capable of gradational display by 10 controlling the time duration of each pixel ~cqllm; ng a bright or a dark state.
Hitherto, as a method of apparently efiecting a gradatlonal display in a display apparatus inherently having no capability of gradational 15 display, there has been known a method of modulating (changing) the ratio of time durations ior displaying two states, e.g., a white display and a dark dispiay.
This is generally called a time moaulation, frame modulation or frame th;nn;n~-out scheme and is 20 diqclosed in, e.g., Japanese Laid-Open Patent Application (JP-A) 61-69036. According to this scheme, however, an additional time is required corr~qp~ ng to an increa6e in number of gradation levels, and a time required for a display of 8 25 gradations or gradation levels at a pixel amounts to a time corresponding to 7 irames according to the conventional binary display scheme.

~`

In contrast thereto, JP-A 62-56936 has proposed a gradational dlsplay scheme lncluding sub-frames (modulatlon time units) for which reset pulses are applied at different timing (i.e., at different 5 time instants), whereby 8 gradation levels are displayed in a time corresponaing to 3 frames of the conventional binary display scheme (see Figure lB).
However, the above-mentioned scheme of di8playing 8 gradation levels in a time of 3 frames 10 requires a long reset perlod so that the average 1, n~nce at the brightest level is decreased by 40 %
from that in the binary display.
Examples of such a time modulation scheme (or frame fh1nnin~-out scheme or frame modulation scheme) are also disclosed in JP-A 64-61180, JP-A 5-127623 and EP-A 319291.
Anyway, in the above-mentioned time modulation scheme, one frame is constituted by scanning each scanning electrode the same number of times, so that it requires a long time for display and the frame frequency is lowered to cause flicker. If the number of scanning electrodes is decreased so as to prevent the occurrence of flicker, the resolution of a picture is lowered.
Further, as all the scannin~ electrodes are scanned the same number of times to constitute one frame, it is impossible to change the rewritlng periodic time in case of changing the display, 80 that the display change cannot be ef fected quickly. More 8pecifically, in operation of OA appliances, such as a computer and a work station, the intentlon of an 5 operator should be quickly communicated to the CPU and reflected on the display, and the response of a moving display as by a pointing device, such as a mouse, should be accelerated.

10 SllMM~RY QF THE ~ NT~oN
An object of the present invention is to provide a display apparatus suitable for gradational display according to the time modulation scheme wherein each gradation level can be displayed in a lS short time and the average l7lm~ nflnr~. at the brightest level is retained comparable to that according to a binary display scheme.
Another ob~ect of the present invention is to provide a display apparatus capable of a good halftone 20 display while suppressing the flicker.
A further object of the present invention is to provide a display apparatus capable of displaying a moving display mark as by a pointing device, etc.
According to the present invention, there is 25 provided a display apparatus comprising:
a display device comprising a pair of oppositely disposed substrates having thereon scanning elf~ctro~ and data electrodes, respectively, and an optical modulation substance disposed between the ~ub2~LLclLe8 80 as to form a number of pi~els each at an intersection of the scanning electrodes and the data S electrodes, and drive means capable of setting one frame perioa to be divided into different period8 of sub-f rames, said drive means further including means for settiny a whole picture &r~nnin~ period for scanning all the scanning electrode8 and a partial rewrite period for scanning only Pr;-nn~ n5 electrode8 for effecting a required display change 80 as to allow a partial rewrite in a shorter cycle than a frame cycle.
According to another aspect of the present inYention, there is provided a data tr~nP~ c~ on apparatus, including:
a graphic controller for outputting data signals and a scanning scheme signal, a scanning signal control circuit ~or outputting s~r;lnn~n~ line address data and a sCilnninq scheme signal, a data signal control circuit for outputting display data and a scanning scEIeme signal, and a display apparatus as described above.
According to still another aspect o~ the present invention, there is provided a display .

apparatus for gradational display according to a frame modulation scheme, comprising:
a display device comprising a plurality of scanning lines and a plurality of data lines 80 as to 5 form a matrix of pixel8 each at an intersection of the scanning lines and the data lines, and drive means f or:
(i) setting one frame including a plurality of sub-frame having different display periods, (ii) dividing saia one frame into a plurality of equal blocks which are time-serially consecutive, (iii) dividing the ~ nn;n~ electrodes into a plurality of groups each ;nrl~l~;ng a plurality of 15 adjacent 8canning lines, and (iv) consecutively selecting scanning electrodes from each group of the adjacent scanning l ines .
These and other ob~ect5, features and 20 advantages of the present invention will become more apparent upon a consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the nying drawings.

BRIEF DESCRIPTI~N OF TE~E DR~TIN~ . _ --Figures lA and lB are respectively a time chart for illustrating a conventional modulation scheme .
Figure 2 is a time chart for illustrating a modulation scheme adopted in an ~ L of the display apparatus according to the invention.
Figure 3 is a drive circuit control diagram according to an F ~-li 3~t of the invention.
Figure 4 is an illu8tration of gradation data for respective pixel8 in one frame according to an embodiment of the inventlon.
Figures 5A - 5C are conceptual illustrations of memories Ml - M3 used in an embodiment of the invention .
Figure 6 is a drive time chart for the circuit shown in Figure 3.
Figure 7 is an illustration of gradational display state8 of respective pixels according to the gradation data shown in Taole 4.
Figure 8 is a waveform diagram for illustrating a set of drive 8ignals used in the circuit shown in Figure 3.
Figures 9 and lO are a sectional view and a plan view, respectively, of a li~auid crystal display device used in an embodiment of the invention.
Figure 11 ib a bloCk diagram for illustrating peripheral appliances surrounding a liquid crystal dibplay device. -Figure 12 is a waveform diagram for illustratlng a scanning signal A and data signals B

and C.
Figure 13 shows waveforms including curves of S transmittance change5 at pixels at (a) and drive signal waveforms (b) and (c) giving the changes at (a) Figure 14 is a chart for illustrating a relationship between the scanning addrel3s and the 10 8canning signal application timing.
Figures 15 and 17 are respectively a chart illustrating a relationship between a gradation and a nAnrf~ at a pixel.
Figure 16 is a chart for illustrating a set 15 of operation5 including 20 time8 of scan selection for 4 scanning addresses Y0 - Y3.
Figure 18 is a block diagram for illustrating another embodiment of the invention.
Figure 19 ic an enlarged view of the display 20 unit (panel ) in the embodiment.
Figure 20 is a sectional view of the display panel shown in Figure 19.

Figures 21 and 22 are respectively a schematic perspective view fQr illustrating an 25 operation principal of a liguid cry8tal device usable in the invention.
Figure 23 is a drive time chart for the embodiment shown in Figure 19.
Figure 24 is a chart for illustrating a relationship between the 8Ci3nnin~ address and the scanning signal application timing in driving the 5 ~ shown in FIgure 18.
Figure 25 is a waveform diagram 8howing a set of drive signal8 used in driving the embodiment shown in Figure 18.
Figure 26 is a drive time chart for another 10 ~ 1 L of the invention, Figure 27 is a chart for illustrating a relationship between the 8canning address and the scanning signal application timing in driving the embodiment of Figure 26.
Figure 28 is a block diagram of still another embodiment of the invention.
Figure Z9 is a view for illustrating a structure of the embodiment shown in Figure 28.
Figure 30 is a drive time chart for the ~ shown in Figure 28.
Figure 31 is a chart for illustrating a relationship between the 8canning address and the scanning signal application timing in driving the embodiment shown in FIgure 28.
Figure 32 is a waveform diagram showing a set of drive signals u8ed in driving the embodiment shown in Figure 28. ~ _ ~ 2137723 Figures 33 and 34 are respectively a waveform diagram 8howing another set of drive signals used in driving the ~ ?i t 8hown in Figure 28.
Figure 35 i8 a arive time chart for a further ~ of the invention.
Figure 36 is another drive time chart for the further ~ ~i L of the invention.
Figures 37 and 38 are respectively a chart for illu8trating a relationship between the g~-~nnf n~
10 address and the scanning signal application time in driving a still further embodiment of the invention.

DESCRIPTIQN OF THE ~ iKK~ EMBODI~ENTS
First of all, a description will be made on a 15 whole picture scanning mode adopted in driving an embodiment of the invention.
The embodiment is directed to a time modulation-type display apparatus which has an electrode matrix comprising scanning electrodes and 20 data electrodes and is driven to effect a gradational display of one picture (frame~ by plural times of scanning. In one picture 8~ nning period, a substantially constant interval ior applying data signal waveform is allotted to all the data 25 electrodes, different display periods are allotted to the respective scanning units, and the scanning units and the scanning electrodes are respectively discontinuously selected. The above-mentioned one picture-scanning period refers to a total period nom~ Ary for displaying one final picture, and the thus-formed one final picture is called one frame while each picture formed by each (scanning unit) of plural times of ~3ri~nnin~ for gradational display i8 called a sub-frame. In other words, one frame is display by 9canning such a sub-frame a prescribed number of times (or effecting a prescribed number of sub-frame operations). The sub-frame may also be called a field.
Figure 2 is a time chart for describing a modulation scheme used in this ~rdi ~t of the display apparatus. The modulation scheme shown in Figure 2 is characterized by a shorter one-frame period when compared with the modulation scheme shown in Figure lA and by a characteristic oi not lowering the lllmi n~nc~ when compared with the scheme shown in Figure lB.
Figure 3 is a drive control circuit diagram.
Referring to Figure 3, the circuit includes a display unit DSP comprising pixels All, A12, ... A44, and f rame memories Ml, M2 and M3 each having a capacity of 4x4 (= 16) bits. The memories Ml - M3 are supplied 25 with data from a data bus DB, and the address control of writing and readout are effected by a control bus CB .

A frame initiation signal FC and sub-frame changing signals SFC are sent to a decoder DC and the deco~ed signals are sent to a multiplexer MPX, where one of the outputs from the memories Ml - M3 i8 selected. A scanning clock signal Hsync is applied to a serial input-and parallel output shift register SR
and a counter CNT which are respectively connected to data drive circuits DRl - DR4 and scanning drive clrcuits DR5 - DR8 through lines Dl - D4 and lines Bl - B4 respectively.
Figure 4 shows an example of gradation data for respective pixels in one frame. The respective gradation data are composed of an upper level bit, a medium level bit and a lower level bit which are inputted to memories M3, M2 and Ml, respectively, through the data bus DB.
Figures 5A - 5C are conceptual illustrations of the memories Ml - M3, and Figure 6 is a drive time chart for the circuit shown in Figure 3.
A picture displaying the content of the memory Ml is called a first sub-frame, a picture displaying the content of the memory M2 is called a second sub-frame, and a picture displaying the content of the memory M3 is called a third sub-frame.
Further, one frame scanning period is divided into 6 sub-periods which are sequentially allotted as scanning periods for the first, third, first, second, 213772~

second and third sub-frames. In the first and third sub-frames, the scanning selection is performed in the order of DR5, DR6, DR7 and DR8 and, in the second sub-frame, the scanning selection is performed in the 5 order of DR7, DR8, DR5 and DR6. In each of the 6 sub-periods formed by the 6-division, only two scanning lines are selected, so that each ~c~nnin~ electrode is selected in either a former half or a latter half of half-divided sub-frame. On a selected sr;~nnin~ line, 10 writing is performed in a period of 1/12 of one frame c~ nn~n~ period and the resultant display state is retained until the same scanning line is scanned in a different sub-frame. As a result, the display periods of the respective sub-frames assume ratios of the first: second: third = 1:3:5 for all the pixels A11 - A44 and, according to a selection of combination of the sub-f rames, 8 types of periods including O/9, 1/9, 3/9, 4/9, 5/9, 6/9, 8/9 and 9/9 can be selected, so that 8 gradational displays can be displayed according 20 to the time modulation.
The gradations at the respective pixels having the gradation data shown in Figures 4 and 5 are shown in Figure 7. The numerical values shown in Figure 7 correspond to the periodical proportion of 25 hright display in one frame-scanning period.
Accordingly, the darl~est display level corresponds to 0 ( = O/9 ) and the bright display level corresponds to 2~37723 ( = 9/9 ) . Figure 8 shows a set of drive signal waveforms used in the above-described type of display including a scanning selection signal waveform which is composed of a reset pulse for resetting a pixel to 5 the dark 6tate and a selection pulse for selecting either the bright Of dark state for the pixel.
E~ereinbelow, the operation of the circuit shown in Figure 3 will be descrlbed.
When a frame initiation signal FC is 10 generated, the data in the memories Ml - M3 are rewritten by the control bus and the data bus. Then, a sub-frame changing signal SFC is generated, and the multiplexer MPX is set by the decoder DC to select data f rom the memory Ml .
In gynchronism with a scanning clock signal lIsync, the counter CNT causes the driver DR5 to supply a scanning selection signal to a line Bl. At this time, the shift register SR is supplied with first row data in the memory M1 so that the drivers DRl, DR2 and 20 DR4 supply a dark state signal waveform and the driver DR3 supplies a bright state signal waveform. As a resnlt, only the pixel A13 is placed in the bright state and the pixel~ A11, A12 and A14 are placed in the dark state. Then, in synchronism with a 25 subsequent scanning clock signal ~Isync, the counter CNT supplies a scanning selection signal waveform to the driver DR6, when the shift register SR is inputted 2~37~23 with second row data in the memory Ml.
Then, when a sub-f rame ~h~n~; n~ signal SFC iB
generated, the decoder DC sets the multiplexer MPX to select data from the memory M3. Thereafter, similarly S a8 de~icribed above, a ~r~nnln~ selection signal and data signals are ~,uL~uLLed in synchronism with a row 8~nnin~ signal F. The order of selecting sub-frames and the order of scanning selectlon in a sub-f rame are p~Lr{ ' according to data pr~l {mln~rily set in a 10 8eparate memory region (not shown). The data set in such a memory in this: ~'i L are as shown in Tables l and 2 shown below.

Table 1 Sub-f rame selection order Sub- f rame ( f rame memory ) ( M1 ) 2 3 (M3) 3 1 (Ml) 4 2 (M2) 2 (M2) 6 3 (M3) Table 2 Scanning selection order in a sub-f rame 1st 2nd 3rd sub- f rame sub- f rame sub-f rame Bl B3 Bl 3 B3 Bl B3 After completion of one frame operation, a frame initiatlon signal is again generated, the data in the memories are rewritten into data for a 15 subse~uent frame.
Incidentally, instead of using the sub-frame-changing signal, it is also possible to change both the sub-frame and scanning address in synchronism with the scanning clock signal Hsync. In this instance, 20 data as shown in Table 3 below are set in a memory region in advance.

Table 3 Sub-frame and 8canning address selection order Sub-frame ~frame memory) Scanning address (Ml) Bl 2 1 (Ml ) B2 3 3 (M3) Bl 4 3 ( M3 ) B2 1 (Ml ) B3 6 1 (Ml ) B4 7 2 ( M2 ) B3 8 2 (M2) B4 2 (M2 ) Bl 2 (M2 ) B2 11 3 (M3) B3 12 3 (M3) B4 According to the above-described gradation 20 drive scheme, it is possible to display the same number of gradations in a shorter period and at a higher ll~mi ni~nrr compared with conventional gradational display scheme. A comparison is given in the following Tables 4 and 5 and in Figure 2 (in 25 comparison with Figures lA and lB) with the level of the binary display as the standard of comparigon.

~ ~ --17- 2137~23 Table ~
Comparison with conventional scheme (8 gradation display) . .

5 Time Brightest l~ n~n~e Invention 3 f rames lOO %
Conventional æcheme 1 7 frames lO0 %
10 " 2 3 frames 58 96 Table 5 Compariæon with conventional scheme n gradation display) Time Briyhtest lll-i n~n~e Invention n frames lOO %

Conventional scheme 1 2n-l frames lOO %
" 2 n frames (2/n~ ~ (l-l/21l~ %
, ~137~23 Ne2t, a display device suitably used in the present invention and a partial rewrite scanning operation to be )~ ned with the above-mentioned modulation scheme will now be described, S Referring to Figure 9, a display device I
includes a pair of oppositely disposed glass aLas 2 and 3 with a prescribed gap therebetween.
The substrates 2 and 3 have thereon scanning electrodes 5 and data el~-:Liodas 6, respectively, in a large number. The electrodes 5 and 6 are respectively in the form of a strlpe as shown in Figure 6 and form a large number of pixels 7 at their intersections.
The electrodes 5 and 6 may be respectively coated, as desired, with an insulating film g and further with an alignment film lO. The peripheral gap between the aubstrates is sealed with a 8ealing member 11 to leave a spacing between the substrates, which spacing is filled with an optical moaulation substance 12.
Further, outside the substrates 2 and 3 are optionally disposed oppositely an analyzer 13 and a polarizer 15, which may be disposed in cross nicols.
The optical modulation substance 12 may for example comprise a liquid crystal material, an electrochromic substance, etc. It is particularly preferred to use a chiral smectic liquid crystal inclusive of a ferroelectric liquid crystal and an anti-ferroelectriG liquid crystal.

-19- ~137~23 The optical modulation substance 12 may suitably have a bistability with respect to an electric field, i.e., a property of ~ in~ either a first optically stable state (e.g., constituting a 5 bright state) or a second optically stable 8tate (e.g., constituting a dark state) in response to an electric field applied thereto.
In the pre8ent lnvention, it is partlcularly preferred to u8e a liquid cry8tal having a 10 bistability, most suitably a chiral smectic liquid crystal having a ferroelectricity in its chiral smectic C phase (SmC*), H phase (SmH*), I phase (SmI*), F phase (SmF*), or G phase (SmG~). Such a ferroelectric liquid crystal has been described, e.g., irl LE JOURNAL DE PHYSIOUE LETTRES, 36 (L-69), 1975, nFerroelectric Liquid Crystals"; Applied Physics Letters 36 (11), 1980, "Submicro-Second Bistable Electrooptic Switching in Liquid Crystals" and Solid State Physics (Kotai 13utsurl), 16 (141), 1981 "Liquid 20 Crystals (Ekisho) " . In the present invention, ferroelectric liquid crystals disclosed in these ref erences can be ~sed .
Specific examples of such a ferroelectric liquid crystal may include decycloxybenzylidene-p'-25 amino-2-methylbutyl-cinnamate (DOBAMBC), hexyloxybenzylidene-p ' -amino-2-chloropropyl-cinnamate ( HOBACPC ) and 4-o- ( 2 -methyl ) -butyl resorci 1 idene- 4 ' -2 13772~

octylaniline (MBRA 8). When a device i8 constitutedby using these materlals, the device may be supported, if nP~P~ ry, with a block of copper, etc., in which a heater is :~ 2CI~ , 50 as to proviae a temperature 5 where such a liquid crystal compound assumes SmC*, SmH*, SmI*, SmF* or SmG*. The basic operation principle of a ferroelectric liquid crystal device will be described later.
A ferroelectric liquid crystal device 10 8ultably used a8 a display device in the present invention will now be described. Hitherto, there has been well known a type of liquid crystal display device comprising an electrode matri~ composed o~
scanning electrodes and data electrodes and a liquid 15 crystal disposed between the scanning electrodes and data electrodes 80 as to form a large number of pixels each at an intersection of the ~c;~nning electrodes and data electrodes. Among these, a ferroelectric liquid crystal device having a bistability and showing a 20 quick respon8e to an electric field has been expected as a display device of a high speed and memory type.
For example, JP-A 61-9023 discloses a liquid crystal display device including two glass substrates each having transparent electrodes thereon and subjected to 25 an aligning treatment which are aispased opposite to each other with a gap of 1 - 3 ,um, and a ferroelectric liquid crystal injected between the glass substrates.

-21- ~13~723 Also many proposals have been made regarding matrix drive methods for sueh a ferroelectrie liquid erystal deviee. For example, praetieal drlve apparatu8 diselosed in U.S. Patents No8. 4,655,561, 4,709,995, 4,800,382, 4,836,656, 4,gZ3,759, 4,938,754 and 5, 058, 994.
A display deviee as deseribed above may be used by inCoL~oLc-t Ing it into a display eontrol deviee as shown in Figure ll. Referring to Figure 11, a liquid ery8tal di8play deviee 1 is eonneeted to a seanning signal applieation eireuit 402 and a data signal applieation eireuit 403, whieh in turn are eonneeted to a seanning signal eontrol eireuit 404 and a data signal control eireuit 406, respeetively, and further 8equentially eonneetea to a arive eontrol eireuit 405 and a graphic controller 407. Further, seanning seheme signals and data are suppliea to the scanning signal eontrol eireuit 404 and the data signal control eireuit 406 ~rom the graphie eontroller 407 via the drive eontrol eireuit 405. The data are converted into address data and display data by the eircuits 404 and 406, and the scanning scheme signals are supplied as they are to the seanning signal applieation circuit 402 and the data signal application circuit 403. Further, the scanning signal application circuit 402 generates a scanning signal A
( Figure 12 ) based on the address data, and the signal -22- ~2 1 3 7 723 A is applied to the scanning electrodes 5. Further, the data signal application circuit 403 generates data signals B and C and supply either one of the data signals B and C to the respective data electrodes 6.
Then, the signals A, B and C will be described based on Figure 12.
The scanning signal A is composed of a reset pulse A1, a selection pulse A2 and an auxiliary pulse A3. The data signal B is a bright data signal, and the other data signal C is a dark data signal. The reset pulse Al has an amplitude Vl, the selection pulse A2 has an amplitude V2, the auxiliary pulse A3 has an amplitude V3, and the data signals B and C
include pulses having amplitudes V4 and V5. The reset pulse Al of the ~ nn;ns signal A has a function of resetting all the pixels or a selected scanning electrode into the dark state, and these pixels are caused to have a sequence of states including data display (bright display or dark display) -- resetting (into the dark state) ~ data display (bright display or dark display). Figure 13(a) shows an example of such sequential display states including a curve D
representing a sequence of bright display ~ dark state ~ bright display and a curve E representing a sequence of dark display -- dark state _ dark display. In Figure 13(a), the abscissa represents time and the ordinate represents a transmitted light quantity .
Incidentally, a aisplay in a strict sense is not effected in a period denoted by a symbol F in Figure 13(a), i.e., a part of the reset period plus a 5 part of the selection period, and an actual display period is given by excluding the period F. However, in case where a period from one scanning selection to a subsequent C~i~nnin~ selection is sufflciently long compared with the reset period, the period may be 10 regarded as a display period without a substantial problem. In the case of using the signals shown in Figure 12, the period F is almost equal to one horizontal scanning period lH. Incidentally, Figure 13(b) shows a voltage waveform applied to a pixel in 15 order to have the pixel exhibit a state change of the curve D, and Figure 13(c), a state change of the curve E. Further, the pulses 301, 302 and 303 are a reset pulse, a selection pulse and an auxiliary pulse, respectively, ana correspond to pulses obtained by 20 combination of the scanning signal and the data signals shown in Figure 12.
NeYt, the timing of scanning selection for odriving a liquid crystal display device having 320 x 200 pixels ~320 aata lines x 200 scanning lines), for 25 example, will be described with reference to Figure 14 wherein the ordinate ~y-axis) represents an address of ~C~nnin~ electrode and the abscissa (x-axis~

represents time with one vertlcal scanning period ( 100 H) as a unlt.
In this: ' ~Ai- nt, one frame includes 600 H
for 600 times of scanning selection and one frame is 5 divided into 6 blocks of first to sixth blocks, 80 that four blocks of the 1st, 3rd, 4th and 6th blocks are used to con8titute a whole picture ~C:Innin~ period and the l~ ~nin~ two blocks of the 2rd and 4th blocks are used to constitute a partlal rewrite f~C~nnin~
lO period. Accordingly, 400 times ( 400 H) of whole picture sc~nnin~ are performed in the whole picture scanning period, and 200 tlmes (200 ~) of partial rewrite scanning are performed in the partial picture scanning period.
In the embodiment of Figure 14, the whole picture sr~nn~n~ is performed by a frame modulation scheme similar to the one adopted in an ' ~fii- L of Figure 36 described hereinafter 80 that the latitude of setting the partial rewrite period is increased.
20 Accordingly, an appropriate period can be selected d~r~nriin~ on the size of a partial rewrite region and the f reS~uency of partial rewriting . More specifically, in the embodiment of Figure 14, a partial rewrite period is placed after the scanning 25 selectlon of the 1st block and tne 4th block, respectively, 80 that the weight of the f rame modulation should identical in the upper portion and -25- 2137~23 the lower portion.
As another embodiment, it is also possible to place a partial rewrite period at a part denoted by an arrow AA, i . e ., only between the 3rd and 4th blocks, S ingtead of placing guch a partial rewrite period twice, i.e., between the 1st and 3rd blocks and between the 4th and 6th blocks as in the embodiment of Figure 14. Alternatively, it 18 also possible to insert such a partial rewrite period at four parts indicated by arrows CC and DD. Further, it is also possible to place two partial rewrite periods at parts of arrows CC and also one partial rewrite period in the 5th blocks. Further, it is also possible to place two partial rewrite perlods at the parts of arrows DD
and one partial rewrite perlod in the 2nd block.
The parts of two arrows CC (or two arrows DD) correspond to the selection time of an identical scanning electrode in the respective blocks to which the arrows belong.
The partial rewrite can be performed according to a binary write scheme but may preferably be performed by a frame modulation scheme 80 as not to cause a contrast d~fference between the case of partial rewrite and the case of no partial rewrite.
In this case, the frame frequency may preferably be at least 20 Hz.
The partial rewrite frequency may preferably -26- 213772~
be at least 60 Hz.
Further, in the whole picture scanning period, it i8 preferred to effect a 2n gradation display (n: a positive integer).
Further, in the partial rewrite period, it i8 preferred to effect a 2n gradation display ~n: a -, positive integer).
It is further preferred to effect a display of identical gradations in both the whole picture scanning period and the partial rewrite period.
Further, it is preferred to effect in~r7zlr scanning in the whole picture scanning period.
It is further preferred to use a ferroelectric liquid crystal as the liquid crystal.
On the other hand, in the present invention, it is preferred to constitute a data transmission apparatus with a graphic controller for outputting data signals and scanning scheme signals, a scanning signal control circuit for outputting scanning line address data and a scanning scheme signal and a data signal control circuit for outputting display data and a scanning scheme signal ~ereinbelow, the whole picture scanning period and the partial rewrite scanning period of Figure 14 will be aescribed in further detail.
In the whole picture sr~lnn~n~ period, 200 scanning addresses are scanned two times each to -27- 2137~23 effect a total of 400 times regardless of whether the display data are changed or not. More specifically, in case where the scanning addresses are divided into an upper half including 0 - 9g and a lower half incluaing 100 - 199, the upper half is first scanned in the 1st block and scanned the second time in the ~rd block, and the lower half i8 first scanned in the 4th block and scanned the second time in the 6th block. By effecting the scanning according to such a schedule, all the scanning addresses (i.e., scanning liens) are caused to have an identical ratio between periods G and H (i.e., a sub-frame ratio) of 1:2.
Accordingly, by combining the periods G and H for dark display/bright display as shown in the following Table 6, four gradations can be displayed, whereby lllminAnr-~
levels as shown in Figure 15 can be displayea with a relative scale of 100 % for the bright display and 0 %
for the dark display. Incidentally, in order to strictly calculate the ratio between the display perioas G and H, it is necessary to consider the reset period. ~owever, the reset period amounts to only 1/200 or l/400 of the total period (from a certain scanning selection to a subse~Iuent scanning selection ) .

-28- 2137~2~
Table 6 Gradation Display period G H
s 0 dark dark bright dark 2 dark bright 3 bright bright In the partial rewrite scanning period of the embodiment of Figure 14, 200 times of scanning selection are performed in two blocks by performing lS 100 times of scanning selection in each block, and each block is further divided into 5 sets each including 20 times of scanning selection.
In each set, four scanning addresses including a display change are arbitrarily selected to 20 effect 20 times of scanning selection. Accordingly, in one block, 20 scanning lines (addresses) a~e partially rewritten. Figure 16 shows the timing of 20 times o~ scanning selection for 4 scanning lines Y0 -Y3 in one set. In Figure 16, represents a dark 25 state period caused by scanning selection, For each scanning address, display periods I and J having a duration ratio of 1:2 are provided twice each 80 as to zg 21~7723 provide a clear gradation. By setting the ratio between the display period8 I and J to 1:2, four gradatLons can be dlsplayed by the combination of the periods I and J for aark/bright display as shown in S Table 7 below.

Table 7 Gradation Display period J

0 dark dark bright dark 2 dark bright 3 bright bright In the ~ i L of Figure 14, four gradations are displayed in both the whole picture scanning and the partial rewrite scannin~ 80 as to retain the same gradation and lllm~n~n~-P, 80 that an operator car. easily recognize the gradation level under display and the occurrence of flicker due to a differQnce in gradation.
In the embodiment of Figure 14, two blocks of the 2nd and 5th blocks are used as the partial rewrite scanning period, and the whole picture scanning period and the partial rewrite scanning period are alternately placed. Accordingly, compared with the Case where the partial rewritten is performed by stopping the whole picture scanning in order to effect 5 a display change, the decrease in display quality can be suppressed and a good halftone di8play can be effected. Further, as the partial rewrite ~r~nnin~
period is evenly disposed in one frame, it is possible to provide an improved response to a display change.
Further, by setting the frame modulation ratio(s) to 2n ~n: a positive integer), the image quality is kept good and the data processing is facilitated.
Further, in the embodiment of Figure 14, the 15 partial rewrite operation is effected at a high Erequency than in the driving method including the whole picture scanning as the normal mode of display, the response of a moving display as by a pointing device can be i ,llov~d. Further, as an appropriate 20 balance is provided between the whole picture scanning period and the partial rewrite scanning period without placing a gap between successive scanning selections, it is possible to obviate a delay in scanning cycle period and also the lowering in frame fre~uency or the 25 occurrence of f 1 ic~er .
Figure I8 shows another display control system used in the present invention. The display apparatus in the system includes a display unit (panel) 101 having an electrode matrix constituting by 8~nn1ng electroaes 201 and data electrodes 202 as shown in Figure 19, a data signal applicatlon circuit 5 for applying data signal to an optical moaulation substance disposed between the scanning electrodes and the data electrodes via the data electrodes 202, a scanning signal application circuit 102 for applying a scanning signal to the optical mediation substance via I0 the scanning electrodes 201, a scanning signal control circuit 104, a data sighal control circuit 106, a drive control circuit 105, a thermistor 108 for detecting the temperature of the display unit 101, and a temperature detection circuit for detecting the 15 temperature of the display unit 101 based on the output of the thermistor 108. The optical modulation 8ubstance disposed between the scanning electrodes 201 and the data electrodes 202 may for e~ample comprise a liquid crystal. The system further includes a graphic 20 controller 107, and data sent from the graphic controller 107 are sent via the drive control circuit 105 and inputted to the scanning signal control circult 104 and the data signal control circuit 106 to be converted into address data and display data. The 25 temperature of the display unit is inputted to the temperature detection circuit 109 via the thermistor 108, and temperature data theref rom are inputted to 213~723 the sc~nnin~ signal application circuit 104 via the drive control circuit 105. Then, scanning signals are generated by the 6r~nnin~ signal application circuit 102 and supplied to the scanning electrodes 201 of the 5 display unit 101 based on the address data and the temperature data. On the other hand, data signals are generated by the data signal applicatlon circuit 103 based on the display data and supplied to the data electrodes 202 of the display unit 101.
Figure l9 shows an electrode matrix constituted by the scanning electrodes 201 and the data electrodes 202 so as to form a pixel 222 at each intersection of the sr~nnin~ electrodes and the data electrodes. In this embodiment, 200 scanning lS electrodes 201 and 640 data electrodes are used to constitute 640 x 400 pixels arranged in a matrix. The structure is basically identical to the one described with reference to Figure 10.
Figure 20 shows a partial sectional structure of the display unit 101. The display unit (panel ) includes an analyzer 301 and a polarizer 305 disposed 80 as to sandwich a cell structure including glass ~:ul,~L-dte 302 and 304 having thereon transparent electrodes 202 and 201 and sandwiching an optical modulation substanCe 203 with a sealant 306 disposed at the periphery. The structure as basically identical to the one described with reference to ~ 2~37723 Figure 9 .
Now, the basic operation principle of a ferroelectric liquid crystal as a preferred e2ample of the optical modulation substance will be described.
Figure 21 is a schematic illustratlon of a ferroelectric liquid crystal cell (device). Reference numerals lla and llb denote ~ub~La~t!s (glass plates) on which a transparent electrode of, e.g., In2O3, SnO2, ITO (indium-tin-oxide), etc., i8 disposed, respectively. A liquid crystal of an SmC*-phase (chiral smectic C phase) in which liquid crystal molecular layers 12 are aligned perpendicular to surfaces of the glass plates is hermetically disposed therebetween. Full lines 13 represent liquid crystal molecules. Each liquid crystal molecule 13 has a dipole moment (Pl) 14 in a direction perpendicular to the axis thereof. The liquld cry8tal molecules 13 continuously form a helical structure in the direction of extension of the substrates. When a voltage higher than a certain threshold level is applied between electrodes formed on the substrates lla and llb, a helical structure oi the liquid crystal molecule 13 is unwound or released to change the alignment direction o~ respective liquid crystal molecules 13 80 that the dipole moments (Pl) 14 are all directed in the direction of the electric i~ield. The liquid crystal molecules 13 have an elongated shape and show ~ ~13772~

ref ractive anisotropy between the long axis and the short axis thereof. Accordingly, it is easily understood that when, for instance, polarizers arranged in a cross nicol relationship, i.e., with 5 their polarizing directions crossing each other, are disposed on the upper and the lower surfaces of the glass plates, the liquid crystal cell thus arranged functions as a liquid crystal optical modulation device of which optical characteristics vary depending 10 upon the polarity of an applied voltage.
Further, when the liquid crystal cell is made sufficiently thin (e.g., ca. 1 ,um), the helical lU~:I,U.L~ of the liquid crystal molecules is unwound to provide a non-helical structure even in the lS absence of an electric field, whereby the dipole moment assumes either of the two states, i.e., Pa in an upper direction 24a or Pb in a lower ~irection 24b as shown in Figure 22, thus providlng a bistable condition. When an electric field Ea or Eb higher 20 than a certain threshold level and different from each other in polarity as shown in Figure 22 is applied to a cell having the above-mentioned characteristics, the dipole moment is directed either in the upper direction 24a or in the lower direction 24b ~rr~n~lin~
25 on the vector of the electric field Ea or Eb. In correspondence with this, the liquid crystal molecules are oriented in either of a first sta~le state 23a and 2~ 37723 a second stable state 23b.
When the above-mentioned ferroelectric liquid crystal is used as an optical modulation element, it is possible to obtain two advantages. First is that 5 the L~ Oll~ speed is quite fast. Second is that the orientation of the liquid crystal shows bistability.
The second a-lvdllLa~ will be further explained, e.g., with reference to Fi~ure 22. When the electric field Ea is applied to the liquid crystal molecules, they 10 are oriented in the first stable state 23a. This state is stably retained even if the electric field is removed. On the other hand, when the electric field Eb of which direction is opposlte to that of the electrlc field Ea is applied thereto, the liquid 15 crystal molecules are oriented to the second stable state 23b, whereby the directions of molecules are changed. This state is similarly stably retained even if the electric field is removed. Further, as long as the magnitude of the electric field Ea or Eb being 20 applied is not above a certain threshold value, the liquid crystal molecules are placed in the respective orlentation states. In order to reali~e such quick responsiveness and bistability the cell may preferably be as thin as possible and generally in a thickness of 0 . 5 - 20 Iym, particularly 1 - 5 ~m. A liquid crystal electrooptical apparatus using such a ferroelectric liquid crystal in combination with an electrode matrix -36- ~137723 has been proposed in, e.g., U.S. Patent No. g,367,924 to Clark and Lagerwall.
Figure 23 is a drive time chart for the system shown in Figure 18 and for displaying 8 5 gradations by using three sub-f rames . Referring to Figure 23, FC denotes a frame initiation signal, Hsync denotes a acanning clock signal, MPX denotes a selection line of a multiplexer (not shown) for selecting one of frame memories Ml, M2 and M3 not 10 8hown, Bl - B200 denote scanning electrodes (or addresses), and COUNT represents a number of ~r~nning times in the display unit.
In operation, a frame initiation signal FC is generated to rewrite data in the memories Ml - M3.
15 Then, in synchronism with the sr~nning clock signal Hsync, the selection of sub-f rame (MPX ) in the multiplexer and the scanning address are changed in the order shown in the following Table 8. Table 9 rewrite the contents of Table 8 for e~planation of the 20 scanning order. The content of MPX is changed se~uentially and cyclically in order to Ml, M2, M3, M1, M2, M3, ... for Hsync, and non-interlaced scanning i8 performed in each sub-frame. The display periods of the 1st, Znd and 3rd sub-frames are set to ratio of 25 approximately 1: 2: 4 by setting the scanning initiat~on addresses of the respective sub-frames to B1, B173 and B116 For example, when a scanning ~ 2~37723 address 331 i8 noted, the display period for the first sub-frame is a period of 84 x Hsync cycle (interval) in the count range of 2 - 85, the display period for the second sub-frame is a period of 171 x Hsync cycle S in the count range of 87 - Z57, and the display period for the third sub-frame i8 a period of 342 x Hsync cycle in the count range of 259 - 600, whereby the ratios among them are 84 :171: 342 - 1: 2: 4 . l .

lS

213~723 Ta~le 8 Count Si~b-fra~ne ~X) Sca~q a~d~sS
(Ml) B I
2 2 CM2) B173 3 3 (M3) B116 4 1 (Ml) B2 2 CM2) B114 6 3 (M3) B117 7 1 (Ml) B3 8 2 CM2) B 175 9 3 CM3) B118 1 (Ml~ B4 S ~ ~
85 1 UMl) B29 86 2 ~M2) Bl 87 3 CM3) B144 88 1 CMI) B30 89 2 CM2) B2 frame go 3 CM3) B145 91 I CMI) B31 257 2 (M2) B58 258 3 (M3) Bl 259 1 (Ml) B87 260 2 (M~) B59 261 3 (M3) B2 262 1 (Ml) B88 ~ ~
- 595 1 (Ml~ Bl99 59~ 2 (1-12) B171 Z5 597 3 (M3) Bl 1~
598 1 (Ml) B200 599 2 (M2) B172 ~00 3 (M3) B115 - V

~ 2137723 Tal~le 9 Scanning ad~ess O~unt Ml M2 M3 Bl S S

86 . Bl 87 B144 Orle S

,- 'S _ ~
595 Bl99 _ -596 B171 = _.
25 597 B 11~1 59g B172 600 ~31 15 = V

_ . . .

Figure 24 is a time chart for illustrating a relationship between the scanning address and the display timing (scanning signal application timing) for the circuit shown in Figure 18. As is understood S f rom Figure 24, the intervals of scanning address selection are unequally set within one frame scanning period .
If the content of the temperature data is not changed, the cycle of Hsync is constant and ~0 corr~srrm--1ngly the interval of data signal waveform application becomes constant.
On the other hand, i f the content of the temperature data is changed, the Hsync cycle i8 changed 80 that the data signal waveform applicatlon interval iB not made constant. However, unle~is the temperature change is intensive, the change in EIsync cycle i8 within 10 % in one frame 80 that the data signal waveform application interval can be regarded as substantially constant.
Figure 25 shows a set of drive signals used in driving the ~ t shown in Figure 18. In this embodiment, the scanning address selection intervals are set to provide ratios of 1:2:4 but the selection interval ratios, i.e., the ratios among display periods for the respective sub-frames can be arbitrarily selected by changing the scanning initiation addresses for the respective sub-frames.

For example, if the starting addresses for the respectlve sub-frame8 are set to be B1, Bl83 and B129, ratios of ca . 1: 3: 7 are obtained .
Incidentally, it is possible to provide the S respective pixels in this ~ - ' i 1. with color filters to constitute a multi-color display apparatuse. Further, by combining the frame modulation scheme with another gradational display scheme, such as a pixel division scheme, it is 10 possible to provide a further increased number of gradations .
Figure 26 is a time chart for driving the system shown in Figure 18 according to a different scanning scheme, in which the scanning addresses and lS MPX are changed in an order shown in Table 10 below.
The content of MPX is changed cyclically in the order of M1, M2, M3, Ml, M2, M3 ... for each Hsync, and interlaced scanning is performed in each sub-frame.
So as.to provide display period ratios of nearly 20 1: 2: 4, the scanning initiation addresses of the respective frames are set to the E~1, B146 and ~32. If interlaced scanning is periormed in a sub-frame, it is possible to suppress the occurrence of flicker in a picture particularly in case o~ a frame frequency as 2S low as 40 - 20 3~z.
Figure 27 shows a relationship between the scanning address and the display timing in such an ~137723 interlaced scanning scheme. Referring to Figure 27, odd-number scanning addresses are selected in a first f ield and even-nun hered scanning addresses are selected in a second field.
A ferroelectric liquid crystal used as an optical modulation substance in this embodiment has a rather Ll ~hle temperature--l~r~n-l~nr~ of response speed 80 that a slow response speed is given at a low temperature. Accordingly, it is desirable to effect a change between a non-interlaced scanning mode and an interlacea scanning mode within a sub-frame depending on the temperature.
An interlaced scanning mode of selecting every other scanning address has been explained to be used in this embodiment. However, the interlaced scanning can also be performed 80 as to skip two or more scanning addresses before each selection of a scanning address (so-called multi-interlaced scanning mode) or a random scannihg mode can also be adopted in a similar manner.

Table 10 Scannin~ a~ress C~unt M I M2 M3 Bl 3 B~2 85 B5~
86 Bl 87 B88 One 88 B59 fralr.e S S
257 Bl 15 258 Bl 262 B1~5 S

596 B14~

599 B1~
600 . B30 . . V

2~37723 Figure 28 is a block diagram of still another eobodiment of the display apparatus according to the present invention. Referring to Figure 28, the display apparatus includes a display unit (panel ) 5 comprising an effective display region lOla and a frame region lOlb.
As illustrated in Figure 29, one sub8trate 123 is provided with frame scanning electrodes 121w on both sides of s- i~nn1n~ electrodes 121, and another I0 substrate 124 is provided with frame data electrodes 122w on both sides of data electrodes 122. By applying the pair of substrates to each other it is po8sible to const~tute the display unit lOl having a frame region lOlb shown in Figure 28. By disposing 15 8uch a frame region lOlb, the following effects may be attained .
A display device is generally held in a chassis or a decorative case for improving the functionality, safety or appearance and also for 20 protecting the electrical system. In this instance, if the chassis or decorative case has a certain thickness, the display face of the display device can be hidden by the thickness when viewed from an obli~ue direction In order to obviate such a difficulty, the 25 display region (effective display region) may be surrounded by a frame region (non-display region) so as not to hide the effective display region unless it ~ 2137723 is viewed from an extreme direction outside a certain angle In case where such a f rame region is provided, however, if the frame region is constituted by an optical modulation substance, such as a ferroelectric liquid crystal, having a memory characteristic, the optical modulation substance remains in an arbitrary uncontrolled state until it is supplied with an electric signal exceeding a threshold, and the frame region exhibits an ununiform display state giving an ugly appearance. In order to obviate the difficulty, it is desirable to uniformize the display state of the frame region by applying certain electric signals. The memory characteristic referred to herein is, however, not necessarily a permanent one, within an extent of retaining the image quality and display function. Accordingly, it is desired to periodically supply drive signals to the f rame region .
ZO For the above purpose, frame-region drive electrodes are disposed outside the effective display region and are supplied with electric signals to drive the liquid crystal, thus providing a uniform state in the f rame region .
The display apparatus shown in Figure 28 has an identical structur~ to the one show in Figure 18 except for the display unit 101 ~137723 Figure 30 is a drive time chart for the display apparatus shown in Figure 28 and for displaying 8 gradations by using three sub-frames.
The drive scheme shown in Figure 30 includes a 5 waveform shown at W to be applied to the frame scanning electrodes ~or sf ~nnins addresses) and i8 otherwise identical to the one described with reference to Figure 26.
First, a frame initiation signal FC is 10 generated to rewrite data in the memories M1 - M3.
Then, in synchronism with the ~c~nn1 n~ clock signal Hsync, the content of selection by the multiple~er (MPX) and scanning address are changed in an order as shown in Table 11 below. The content of MPX is 15 changed cyclically in the order of Ml, M2, M3, M1, M2, M3, ... for each Hsync, and interlaced scanning is performed in each sub-frame. For example, in a 1st sub-frame, the seLection is performed in the order of B1, B3, E15, ..., BlI9, B2, B4, ..., B200. Then, if the count reaches 200, 400 or 600, the counting is stopped, and the frame scanning addresses are selected. In case where the frame freq~ency is Z0 -40 Hz, the frame s~ nnin~ frequency amounts to 60 -120 Hz so that flicker due to the frame scanning can 2~ be obviated. In this embodiment, the frame scanning is performed at the time of 200 counts each, but the number of 200 counts need not be observed. Further, . ~ 2137723 the frame sr~nn;ng need not be performed on a count basis but can also be made at a f ixed time interval of, e.g., 10 msec.

Table ll Scanning a~ress C~urt Ml M2 M3 Bl48 S S

Bl S S One 200 . ~ B77 frame W

S S
B1l~

B11~

400 ~ B68 W
401 ~ B12 . ,:
S -B19~ =

~200 Bl~ =
=~ - ` B30 .. ~ - W . y W: f rame scan -49- 2137~23 Figure 31 briefly illu~ aLes a relationship between the scanning address and the display timing.
In view of Figure 31 in comparison with Figure 27, it would be understood that the frame scanning is S performed immediately performed after the counts 200, 400 and 600, respectively .
Figure 32 shows a set of drive signal waveforms used in this ' ~~ff . t. Figure 33 is a time chart identical to the one shown ir Figure 30 10 except for the use of a f rame scanning signal of a dif ferent waveform incluaed in a set of drive signals shown in Figure 34.
Next, an ~ orl1- t of displaying four gradations by using the display apparatus shown in lS Figure 18. In this embodiment two frame memories M1 and M2 are used so as to constitute one frame (400 counts) with two sub-frames . MPX and 8~Annf ng addresses are selected in the order of Table 12 below to provide a ratio of 1: 2 between the display periods 20 of the respective sub-frames. On the other hand, a ratio of 1:3 can be obtained- if the selection order is taken as shown in Table 13.
Figures 35 and 36 respectively show a relationship between the scanning address and the ~5 display timing when the selection order ls taken as shown in Table 12 and Table 13, respectively.

~ 213772~

Table 12 Sca~ning a~dress ~unt MPX M 1 M2 Ml Bl 3 Ml B2 7 Ml B4 -133 Ml B67 134 M2 Bl 135 M1 B68 One 136 M2 B2 fra~r~

139 Ml B70 267 Ml B134 269 Ml B13~
-- . , 39:, Ml Bl98 396 M2 B 1~2 398 M2 _ B 1 33 400 M2 B 1 34 ; = V

2137~23 Ta~le 13 Scann~ng address Count MPX Ml M2 Ml Bl 2 Ml B2 5 3 Ml B3 4 Ml B~
S Ml BS
6 Ml B8 7 Ml B7 10 93 M1 B9~3 199 M1 B9g 100 Ml B100 One fr~r.e 19g M2 B99 2~0 M2 B1~0 201 Ml B101 .
20 ~ 5 298 Ml Bl98 299 ML Bl99 300 Ml B200 302 M2 8102 ~-303 M2 B103 . . - .
~5 ~ ~ :

2399 M2 B 199 _;
400 M2 ~ 8200 ~ V

If the frame modulation scheme show in Figure 36 (and Table 13) i8 adopted, the weight of each sub-frame becomes identical for the pixels on all the scanning lines even when a partial rewrite scheme i8 u&ed in combination as has been de&crlbed in detail with reference to Figure 14.
On the other hand, in case where the f rame modulation scheme shown in Figure 35 (and Table 12) is adopted, if a partial rewrite period is added thereto, the welght8 of the sub-frames can be different nfling on the gcanning lineg or)nf PrnP-l, In this way, the frame modulation scheme shown in Figure 36 allows a combination with a partial rewrite scheme and provides a display with a good responsiveness, Then, another embodiment of display apparatus driven by combination of whole picture ~:r~nnin~ and partial rewrite scanning will be described with reference to Figure 37.
Figure 37 is a scanning chart showing a relationship between the scanning address and the scanning signal application timing. A display device u~ied in this embodiment has 540 Y 400 pixels (640 data lines and 400 scanning lines) and is driven to display four gradations in both the whole picture scanning and the partial rewrite scanning. In the whole picture scanning, interlaced scanning is performed.

213772~

In Figure 37, the y-axis represents scanning electrode addresses and the t-axis represents time with one horizontal scanning period ( 1 El) as a unit.
In this '~ofli t, one frame includes 1200 H for 1200 tlmes of ~r~nn~n~ selection, of which 800 times ~800 El) are used for the whole picture 8canning and 400 times (400 H) are used for the partial rewrite scanning. One frame is divided into 12 blocks including 1st, 2nd, 4th, 5th, 7th, 8th, 10th and 11th blocks as the whole picture scanning period, and 3rd, 6th, 9th and 12th blocks as the partial rewrite scanning period. The whole picture scanning period is used for scanning all of the 400 scanning addresses two times each in one frame regardless of whether the display content is changed or not, thereby displaying a halftone. On the other hand, the partial rewrite scanning period is used for selecting arbitrary scanning addresses including a change in display content and is set to allow four sets of scanning selectlon each including 100 times of scanning sel ection .
In the whole picture scanning, the whole scanning addresses are assumed to be composed of an upper 1 unit including scanning addresses of 0 - 99, an upper 2 unit including scanning addresses of 100 -199, a lower 1 unit including scanning addresses of 200 - 299, and a lower 2 unit including scanning 2~3772~

addresses of 300 - 399. Then, interlaced scanning is performed so as to effect 1st scanning of upper 1 even-numbered addresses and lower 1 odd-numbered addresses in the 1st block; 1st sr~nn~n~ of upper 2 5 odd-numbered addresses and lower 2 even-numbered addresses in the 2nd block; 1st scanning of upper 1 odd- ~ ~~ ' addresses and lower 1 even- ' ~ ed addresses in the 4th block; 2nd scanning of upper 1 even-numbered addresses and lower 1 odd-numbered 10 addresse8 in the 5th block; 1st scanning of upper 2 even-numbered addresses and lower 2 odd- -rPtl addresses in the 7th block; 2nd scanning of upper 1 odd-numbered addre8ses and lower 1 even-numbered addresses in the 8th block; 2nd scanning of upper Z
15 oad-numbered addresses and lower 2 even-numbered addresses in the 10th block; and 2nd scanning of upper 2 even-numbered addres8es and lower 2 odd-numbered addresses in the 11th block. As a result of the scanning selection according to the above-mentioned 20 schedule (timing), all the scanning addresses are provided with a ratio between the display periods K
and L of 1: 2 . ~n Figure 37, the scanning of even-numbered addresses is represented by a bolid line, and the scanning of odd-numbered addresses is represented 25 by a dashed line. 'rhe ratio of a reset period and a period between one scanning selection to a subsequent scanning selection is 1:400 or 1:800, so that the ~ 213772~

reset period can be ignored. In the partial rewrite scanning periods of the 3rd, 6th, 9th and 12th blocks, the control is performed in a similar manner as in the embodiment of Figure 14. As a result, also ln this S embodiment, four gradations can be displayed and similar effects can be attained.
Incidentally, in case where the display content is not charged, the partial rewrite operation is not required essentially, but it is preferred that the partial rewrite period is not shortened so as to retain the gradation. Further, in order to re~ain the contrast, it is preferred to contlnually apply waveforms identical to the data signals. It is possible to use the above-mentioned liquid crystal IS display device together with a color filter of three colors so as to efiect a multi-color display with three pixels as a unit.
Some experiment were performed by us in order to confirm the effects of the present invention and will be described below.
(Experimental Example 1 ) A liquid crystal display device of 320 x 200 pixels was constituted by using a chiral smectic liquid crystal showlng the following properties:
Ps = 6.1 nC/cm2 (30 C) Tilt angIe = 14.6 deg. (30 C) ,~= -0.2 (30 C) ~ 2~3~23 Phase transition series (C):
91.5 85.0 66.7 -16.7 Iso. ~ ` Ch. ~ ` SmA ~ ` SmC* ~ ` Cryst.
91.9 85.7 -12.5 The liquid crystal device was driven by the 5 drive scheme described with reference to Figure 14 by using a set of drive signals shown in Figure 12 with the following parameters.
Vl = 20 volts V2 = -14 volts V3 = 6 . 6 volts V4 = 6 volts V5 = -6 volts ~T = 25 usec lH = 50 usec As a result, a good halftone display was performed at a frame frequency of ca. 33 Hz, and the partial rewrite was made possible at a f requency of ca. 67 lIz with no flicker and good mouse response.
( Experimental Example 2 ) ~ liquid crystal display device of 640 x 400 pixels was similarly constituted and driven by the drive scheme described with reference to Figure 37 by using a set of drive signal shown in Figure 12 with the following parameters.
Vl = 25 volts V2 = -17 volts V3 = 7 7 volts ~57~ 2137~23 V4 = 7 volts V5 = -7 volts a.T = 20 ,usec lH = 40 llsec S As a result, a good halftone display was performed at a frame frequency of ca. 20 Hz, and the partial rewrite was made possible at a f requency of ca. 80 H~ with no flicker and gooa mouse response.
Figure 38 is a scanning chart for illustrating another frame modulation scheme, wherein one f rame is constltuted by three sub-~rames giving ratios of display periods of 1:2:3. One frame i8 divided into 6 consecutive blocks to which an equal selection time is allotted.
Each block is allotted with a selection time for a group of ad~acent 100 scanning lines, and the 100 scanning lines in the group are successively selected, within the block. For example, in the 1st block, the scanning lines Bl - B100 are selected one 20 by one. The selection may be performe(5 either sequentially in the order of addresses, such as B1, B2, B3, ... B100, or may be in a random order of, e.g., Bl, B100, B2, B99, .. B50. In the case of such a random order, the selected random order should be 25 observed also in a subsequent sub-frame.
In this scanning scheme, different order of weights of sub-frames are set to different groups of 2~37723 --~8--scannlng lines, e.g., the order of weights of sub-frames for the first group including scanning lines Bl - B100 is 1, 3, 2, 1, 3, Z, ... and 1, 2, 3, 1, 2, 3, ... for the group of scanning lines B101 - B200 as 5 shown in Figure 38.
In order to combine the above-mentioned f rame modulation scheme, a partial rewrite period may be inserted at places of arrow XA and/or a place of arrow XB. In thls case, the division ratios of sub-frames 10 can be different so that the number of scanning lines selected in the respective blocks may be appropriately set 80 as to provide a aesired sub-frame division ratio .
As described above, in the present invention, 15 one frame is divided into a whole picture ~c~nnfn~
period ana a partial rewriting period so that, in the partial rewritlng period, only certain scanning electrodes required for changing a dlsplay state are scanned, thereby allowing a partial rewrite in a 20 shorter cycle than the frame cycle. As a result, the lowering in image quality can be suppressed to allow a better quality of hal~tone display compared with the case where a partial rewrite is performed by interrupting a whole picture scanning when a change in 25 display content occurs. Further, it becomes possible to provide an enhanced responsiveness to a change in display content.

2~ 3772~
,~ ~

Further, if an almost identical gradational display is performed both in the whole picture scanning period and in the partial rewrite period, an operator can easily recognize what level of gradation 5 is displayed, and it becomes possible to prevent the occurrence of flicker due to a difference in gradat ion .

Claims

1. A display apparatus comprising:
a display device comprising a pair of oppositely disposed substrates having thereon scanning electrodes and data electrodes, respectively, and an optical modulation substance disposed between the substrates so as to form a number of pixels each at an intersection of the scanning electrodes and the data electrodes, and drive means capable of setting one frame period to be divided into different periods of sub-frames, said drive means further including means for setting a whole picture scanning period for scanning all the scanning electrodes and a partial rewrite period for scanning only scanning electrodes for effecting a required display change so as to allow a partial rewrite in a shorter cycle than a frame cycle.

2. A display apparatus according to Claim 1, wherein said frame cycle corresponds to a frequency of at least 20 Hz.

3. A display apparatus according to Claim 1, wherein said shorter cycle for the partial rewrite corresponds to a frequency of at least 60 Hz.

4. A display apparatus according to Claim 1, wherein said one frame period is divided to include a plurality of sub-frames having durations suitable for displaying 2n gradations in the whole picture scanning period, wherein n denotes a positive integer.

5. A display apparatus according to Claim 1, wherein said one frame period is divided to include a plurality of sub-frames having durations suitable for displaying 2n gradations in the partial rewrite period, wherein n denotes a positive integer.

6. A display apparatus according to Claim 1, wherein almost equal gradations are displayed in the whole picture scanning period and in the partial rewrite period.

7. A display apparatus according to Claim 1, wherein interlaced scanning is performed in the whole picture scanning period.

8. A display apparatus according to Claim 1, wherein said optical modulation substance comprises a ferroelectric liquid crystal

9. A data transmission apparatus, including:
a graphic controller for outputting data signals and a scanning scheme signal, a scanning signal control circuit for outputting scanning line address data and a scanning scheme signal, a data signal control circuit for outputting display data and a scanning scheme signal, and a display apparatus according to any one of Claims 1 - 8.

10. A display apparatus for gradational display according to a frame modulation scheme, comprising:
a display device comprising a plurality of scanning lines and a plurality of data lines so as to form a matrix of pixels each at an intersection of the scanning lines and the data lines, and drive means for:
(i) setting one frame including a plurality of sub-frame having different display periods, (ii) dividing said one frame into a plurality of equal blocks which are time-serially consecutive, (iii) dividing the scanning electrodes into a plurality of groups each including a plurality of adjacent scanning lines, and (iv) consecutively selecting scanning electrodes from each group of the adjacent scanning lines.