CA2146335A1 - Architecture and apparatus for image generation - Google Patents

Architecture and apparatus for image generation

Info

Publication number
CA2146335A1
CA2146335A1 CA2146335A CA2146335A CA2146335A1 CA 2146335 A1 CA2146335 A1 CA 2146335A1 CA 2146335 A CA2146335 A CA 2146335A CA 2146335 A CA2146335 A CA 2146335A CA 2146335 A1 CA2146335 A1 CA 2146335A1
Authority
CA
Canada
Prior art keywords
rasterizer
pixel values
screen
image generation
operate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2146335A
Other languages
French (fr)
Other versions
CA2146335C (en
Inventor
John Wood Poulton
Steven Edward Molnar
John Gordon Eyles
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of North Carolina at Chapel Hill
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2146335A1 publication Critical patent/CA2146335A1/en
Application granted granted Critical
Publication of CA2146335C publication Critical patent/CA2146335C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures

Abstract

A system for image generation comprising a plurality of renderers (10), each having a geometry processor (100) and a rasterizer (120) that operate in parallel to compute pixel values for a set of primitive objects that comprise the image to be rendered. The geometry processor transforms graphics primitive objects from their native object coordinates to screen coordinates. The rasterizer consists of an array of enhanced memory devices (150) having a processor (151) and memory (152) for each pixel in a region of a screen. The processors (151) and their associated memories (152) operate in SIMD fashion on screen space primitive descriptions to compute and store pixel values for an entire such region. The enhanced memory devices further comprise compositors (154) for combining their pixel values, for example, based on a visibility test, with those from a corresponding memory device of another rasterizer.
CA002146335A 1992-11-13 1993-11-08 Architecture and apparatus for image generation Expired - Fee Related CA2146335C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/975,821 US5388206A (en) 1992-11-13 1992-11-13 Architecture and apparatus for image generation
US975,821 1992-11-13
PCT/US1993/010785 WO1994011807A1 (en) 1992-11-13 1993-11-08 Architecture and apparatus for image generation

Publications (2)

Publication Number Publication Date
CA2146335A1 true CA2146335A1 (en) 1994-05-26
CA2146335C CA2146335C (en) 2000-05-30

Family

ID=25523442

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002146335A Expired - Fee Related CA2146335C (en) 1992-11-13 1993-11-08 Architecture and apparatus for image generation

Country Status (6)

Country Link
US (2) US5388206A (en)
EP (1) EP0672275A4 (en)
JP (1) JP3009732B2 (en)
AU (1) AU677027B2 (en)
CA (1) CA2146335C (en)
WO (1) WO1994011807A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109196550A (en) * 2016-06-28 2019-01-11 英特尔公司 For being interleaved the framework of rasterisation and pixel shader for virtual reality and multi-view system
CN114036015A (en) * 2021-10-07 2022-02-11 中国航空工业集团公司洛阳电光设备研究所 High security figure generation device based on FPGA

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CN109196550A (en) * 2016-06-28 2019-01-11 英特尔公司 For being interleaved the framework of rasterisation and pixel shader for virtual reality and multi-view system
CN109196550B (en) * 2016-06-28 2024-03-15 英特尔公司 Architecture for interleaved rasterization and pixel shading for virtual reality and multi-view systems
CN114036015A (en) * 2021-10-07 2022-02-11 中国航空工业集团公司洛阳电光设备研究所 High security figure generation device based on FPGA
CN114036015B (en) * 2021-10-07 2024-04-19 中国航空工业集团公司洛阳电光设备研究所 High security figure generating device based on FPGA

Also Published As

Publication number Publication date
EP0672275A4 (en) 1997-11-12
EP0672275A1 (en) 1995-09-20
JP3009732B2 (en) 2000-02-14
AU5596894A (en) 1994-06-08
CA2146335C (en) 2000-05-30
US5481669A (en) 1996-01-02
WO1994011807A1 (en) 1994-05-26
AU677027B2 (en) 1997-04-10
JPH08503563A (en) 1996-04-16
US5388206A (en) 1995-02-07

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MKLA Lapsed
MKLA Lapsed

Effective date: 20021108