CA2158959C - Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom - Google Patents

Abstract

The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material (36) which defines the single cell memory element, a pair of spacedly disposed contacts (32, 34, 38, 40) for supply electrical input signals to set the memory material to a selected resistance value within a dynamic range, a filamentary portion controlling means disposed between the volume of memory material and at least one of the spacedly disposed contacts.
The controlling means defining the size and the position of the filamentary portion during electrical formation of the memory element and limiting the size and confining the location of the filamentary portion during use of the memory element, thereby proving for a high current density within the filamentary portion of the single cell memory element upon input of a very low total current electrical signal to the spacedly disposed contacts.

Description

215~9 WO 94124707 ~ PCT/US94/03953 ELECTRICALLY ERASABLE, DIRECTLY OVERWRITABLE, MULTIBIT SINGLE

FIELD O~ THE INVENTION
The present invention relates generally to a unique new class of semicon-iuctor materials characterized by a high conrpntration of mo(l~ t~ble free charge carriers. The meçh~nicm of 10 operation of devices fabricated from this new class of semiconductor materials is different from the operation of previous semicon~1uçtor devices and can be tailored to provide new device configurations eYhihiting unusual new properties. More particularly, it relates to a new class of narrow band gap, microcrystalline semicon~luctor materials, per se; to these m~teri~lC as sFeçifir~lly deciEnPd for solid state, electrically and optically operated, directly o~e.wlildble, low 15 energy, very fast ~wilcllillg, non-volatile, analogue and multilevel single-cell O~là~illg memory ~lr.,.~"l~, and to high density electrical memory arrays f~hriç~tPd from these m~tPri~lc BACKGROUND AND PRIOR ART
The Ovonic EEPROM is a novel, ~,t-u~ulicldly, high perfon~n~nr,e, non-volatile, thin fllm 20 electronic memory device. In this device, information can be stored in either analog or binary form (one bit per cell) or in multi-state form (multiple bits per memory cell). The advantages of the Ovonic EEPROM include non-volatile storage of data, potential for high bit density and concequently low cost as a result of its small root~,.ill~ and simple two-terminal device cc nfi~-ration, long r~ .ug~ ing cycle life, low plu~ lallllllillg energies and high speed. The 25 Ovonic EEPROM is capable of Wnary and multistate operation. Ther are small dirr~.G.~ces in the Sl1U~;IUIG and the m~tPri~lc c "ployGd to enhance either the binary or multi-state performance chal-~ lr.l;ctics thereof. For~ul~oses of the instant invention, the terms "memory ~lPmPntc~ and "control elPm-PntC" will be employed ~,yllullylllously.
The operation of most sPmicon-luçtor devices is guve~led by the control of mobile charge 30 carrier c,~"r~"l,dtions dirr,.,.GI~ from that gt~lleldlGd at thermal equilibrium. P'rior to the present invention, only four general methods were known by which to control and modulate the cullçr,.l,alion of excess or free (these two terms are used interch~ng~P~hly throughout this rii.cCIlc~ )n) charge carriers in solid state ~,~miconriuctt)r devices. These four known metho~c will be described h,~ lbelow following a general tiiccuccion of those fi-n-1~mçnt~1 meçh~nicmc of 35 operation of sçmicon,~uctor devices which are npcesc~ry in order to appreciate the advantages of the instant invention.

2 ~ 5 ~ 9 S 9 PCT~S94/03953 By way of e~rpl~n~tion, in a perfcct semicr,n(1uctor lattice with no impurities or lattice defects -- an intrinsic semiconductor -- no charge carriers are present at zero Kelvin since the valence band is filled with electrons and the con~ ction band is empty. At higher ~ XIaLul~S, however, electron-hole pairs generated as valence band electrons are excited thermally across the 5 band gap to t,he con~ ion band. These thermally generated electron-hole pairs are the only charge carriers present in an intrinsic semiconductor m~trn~l Of course, since the electrons and holes are created in pairs, the condllction band electron conrçntration (electrons per cubic cPntimeter) is equal to the conrPnt-ation of holes in the valence band (holes per cubic cçntimeter).
It is well known, but worth t.llph ~ g~ that if a steady state carrier cc,l~ ~Lion is to be 10 m~int~linçd, there must be recombination of the charge carriers at the same rate that they are g~ d E2e~,,..h;..~lion occurs when an electron in the con~urtion band makes a tran~ition to an empty state (hole) in the valence band, either directly or indirectly through the agency of a mid-gap recomhin~tion center, thus ~nnihil~ting the pair.
In addi~ion to thermally generated charge carriers, it is possible to create carriers in 15 sPmicon~ rtclr m~teri~l~ by pu,~osely introducing certain impurities into the crystal lattice. This process is called doping and ~ Li a cc...~ method of varying the con~luctivity of s~mir~n~ Clr~l~. By doping, a s~mir~n~luctor material can be altered so that it has a u,-,d~
of either ele~,L,vns or holes, i.e., it is either n-type or p-type. When a crystal lattice is doped such that the eq~ilibril~m carrier col~rc-~l ~, l ir,n~ are dirr~ from the intrinsic carrier c~ r~ ations, 20 the s~mir~ material is said to be "extrinsic". When imp ~ritirs or lattice defects are introduced into an otherwise perfect lattice crystal, ~ldriition~l levels are created in the energy band structure, usually within the band gap. For in~t~nr~, the introduction of p l~.s~ vus in silicon or ~e~n~ni~ , ge~ 5 an energy level very near the con(il~rtion band. This new energy level is filled with electrons at zero Kelvin, and very little thermal energy is required to excite these clec~runs to the con~v~ion band. Thus, at about 50-100 Kelvin, virtually all of the ele~ uns i the illl~UI;~y level are donated to the contiuctinn band. Semic~ clu, material doped with donor impurities can have a considerable cunr~.l.dlion of electrons in the con~uctir,n band, even when the t~ ,u.~ is too low for the intrinsic charge carrier cunct:"l,alion to be appreciable.
Now that the reader can appreciate the ~ignifir~nc~ of the p,.,i,t;"ce of excess charge carriers for çlçctlic.~l con~lnrtivity~ it must be noted that these carriers can also be created by optical eYcit~tion or they can be injected across a forward biased p-n junction or a Schottky barrier. Simply stated and regardless of the manner in which the excess carriers are ~lle~aled, they can rlc~min~tP the rlPCtric~l con-luction processes in a semicon~uctor m~eri~l It has 215~959 previously been stated that there are four known methnrlc of mod~ ting the cull~;llLlation of free charge. Those four mPthorlc are described below:
(1) In 1948, Bardeen, Brattain, and Schor~ley ushered in the modern era of srmirQnductor electronics when they dPmon~tr~ted the operation of a solid state amplifier by sllccPcSfi~lly 5 modlll~ting the flow of injected minority charge carriers in bipolar junction llal~iSlOl~. The bipolar junction transistor is a three terminal device in which the flow of current through two trrmin~lc. can be controlled by small changes in the current at the third termin~l This control feature provides for the ~mplifir~tiQn of small signals or for the ~wiLI,hillg of the device from an "on" state to an "off" state. In other words, the bipolar trancistor is employed to m~ te the 10 injection and collection of minority charge carriers across a semiconrltlctrlr junction. More particularly, and ccncidPring, for in~t~nr~, in a ~n-p bipolar ~LIu ;Lul~ (the opPration of an n-p-n bipolar structure is simply the reverse of the oper~tion of the p-n-p ~LIu-,Lule), the negative side of the forward biased junction is the same as the negative side of the reverse biased junction.
With this confi~-ration, the injection of holes from the p-n junction into the center n region 1~ s~ppli~ps the lllillolily carriers, holes, to participate in the reverse flow of current through the n-p jlmrtion As should now be evident, the d~P~ tion of this device as "bipolar" relates to the critical illl~lL~Ice of the action of both clc~,l-uns and holes.
In o~.~:l;o~-, the reverse saturation current through the p-n junction of the device depends upon the rate at which lllinoli~y carriers are ~,. ", "~t d in the nPighhorh--od of the j~netirln It is 20 possible to increase the reverse current thr~ugh the junction by in~ asillg the rate of electron-hole pair generation. This can be ~cco...pli~l.rd with light (as dic~l`~d below with respect to photnd~PtPctors). Fl~ctric~lly, a convenient hole i. j~;l;o~- device is a forward biased p-n junction in which the current is due primarily to holes injected from the p region into the n m: ~1 If the n side of the forward biased junction is the same as the n side of the reverse biased jl-nrtion, the resultant p-n-p structure o~,ales when the injPction of holes from the p-n junction into the center n region supplies minority carrier holes to participate in the reverse current flow through the n-p junction of the tr~n~ictnr. Of course, the n-region is na,luwed so that the injected holes do not rec~mhinP in the n region (the base of this p-n-p bipolar tr~n~iCt~lr) before they can diffuse to the depletion layer of the reverse-biased junction.
Finally, when used as a switch, this type of L-dnsi~lor is usually controlled in two con~ ction states, referred to as the "on" state and the -offi' state. While l~ o.~ do not filnrtion as a short circuit when tumed on and as an open circuit when tumed off, they are able to a~lu~hllate these actions. In llal~ or ~wi~l""g, the emitter junction is forward biased and the collector is reverse biased,with a l~on~l-le amount of current flowing out of the base. If the WO 94/24707 2~$~ PCT/US94/03953 base current is switched to zero, the collector current will be negligible. This is the "off" state.
However, if the base current is positive and sl~ffciently large, the devic~ is driven to the s~tur~tion regime and the transistor is in its "on" state. Therefore, in the typical ~wilullil.g operation, the base current swings from positive to negative, thereby driving the device from saturation to cutoff and vice versa.
(2) The second c~"v~ ional method of controlling the conr~ntration of free charge carriers is imF'~rntPd by metal-oxide-semir,onductrr field effect transistor (MOSFET) devices. By way of background, one of the most widely employed electronic devices, particularly in digital e~ d circuits, is the metal-in~ tnr-sPmicon~nctr,r (MIS) transistor. In an MIS transistor, the col~rr.llldlion of charge carriers in the c~nduction channel is controlled by a voltage applied at a gate electrode isolated from the channel by an insulator. The resulting device may be referred to genPIiç~lly as an in~ t~d-gate field effect L dnsisL~r (IG~k-l ). However, since most IGFk-l s are made using a metal (typically ~ mimlm) for the gate electrode, silicon-dioxide as the inc~ tor, and silicon as the st~micond~lctr~r m~trri~l, the term MOS field effect transistor or MOSFET is commonly used.
In O~.dliOII of a MOS~k-l, cu,~ider an n-type channel formed on a ~type silicon ~ub~LId~e. The n-type source and drain regions are formed by dirr~ e or ;~ e dopant atoms into a lightly doped p-type s~,b;,~ P A thin oxide layer sepa-~s the metal gate from the silicon surface. No current flows from the drain to the source unless there is a cou~ illg n-channel between them, since the drain-~u~L aLe-source comhin~tion includes opl)osiLely directed p-n jlmrtion~ flicrosed in series. When a positive voltage is applied to the gate relative to the sub~L aLe (the source in this t~ mple)~ positive charge carriers are depo~ited on the gate metal.
As a result of this deposition, negative charge carriers are induced in the underlying silicon by the fi~rm~tion of a depletion region. In aA~ition~ a thin surface region c~ lg mobile electrons is formed. The induced electrons form the channel of the FET and allow current to flow from the drain to the source. The effect of the gate voltage is to vary the co~ re of the induced charmel for low drain-to-source voltage. The MOS field effect ~ isLor is particularly useful in digital circuits, in which it is switched from the "off" state (no con~ cting channel) to the "on"
state. Both n-channel and p-channel MOS IJa-~;S101~ are in very cr~mmon usage.
The MOS structure can be thought of as a c~r~ritor in which one plate is a srmiconrluctor.
If a negalive voltage is applied between the metal and the s~mir,on~uctor, a negative charge is err~ ively deposiled on the metal. In .~onse thereto, an equal net positive charge is ~cumul~t~d at the surface of the semir~miuctQr. In the case of a p-type ~ub~.ale, this occurs by hole ar,cllmlll~tinn at the sçmirr,n~llctr,r-oxide interface. Since the applied negative voltage dep.~ es 21~8959 .

the ele~L.usLa~ic potential of the metal relative to the semicon~ ctnr, the electron energies are raised in the metal relative to the semicon~1nct~m The energy bands of the sçmicon~llctor bend near the interface to ~cc~mmodate the ~ccum~ tion of holes. Rec~ P no current passes through the MOS structure, there is no variation in the Fermi level position within the bulk of the S sçmicQnrl~lctrr. The result is a bending of the sçmiconrluctor bands near the interface so that the Fermi level is closer to the valence band adjacent the intPrf~re. thereby in~lic~ting a larger hole cu-lr~ a~ion than that arising from the doping of the p-type sçmiconrlllctor m~teri~l When a positive voltage is applied from the metal to the spmiron~lllct~r~ the potPnti~l of the metal increases, thereby lowering the metal Fermi level relative to its e~ librium position 10 As a result, the oxide cond~lction band is again tilted. The positive voltage deposits positive charge on the metal and effectively calls for a co~ g net negative charge at the surface of the spmicon~iuctrr. Such a negative charge in p-type m~teri~l arises from deplction of holes from the region near the surface which leaves behind ~ ...p~ ed ionized acccplo-~. In the del-lPtPd region, the hole cot~ l .,, ion dec-~ases, bending the bands down near the spmiron~luctor 15 surface. If the positive charge c~ P~s to increase, the bands at the s~ r,o~ lu- surface bend down still further. In fact, a sllffiripntly large voltage can cause a large electron co~lre~ on in the con-1uction band. The region near the semicon-luctor in this case has con~1uction properties typical of n-type m~ri~l This n-type surface layer is formed not by doping, but by "i--~ ;o-."
of what was origin~lly p-type semicr~lldll( l~r material due to the applied voltage. This inverted 20 layer, separated from the underlying p-type m~tPri~l by a depletion region, is the key to MOS
transistor operation.

(3) The third known method of controlling the c4l~r~- .l . ~l ion of free charge carriers is by the photogeneration of free charge carriers of both polarities. This phnlugel~ lion of free charge caniers takes place in such state-of-the-art devices as photovoltaic cells, I,holur~istors, 25 phnt~detectnrs and cle~L uplloLugraphic drums.
In general, when excess cle~L.u,.s or holes are created in a s~..;co..~J~ clr m~t~ri~l, there is a co~ g h,~;.case in the ele~L,ical con~uctivity of the material. In the event that the excess charge carriers are gc--~ldled from optical rYcit~tion, the resulting illclcas in con~lllctivity is called '~phr~tocon~uctivityll. When photons are directed to impinge upon a semison~ ctor 30 m~trri~l, those photons having energies greater than the band gap energy are absorbed and electron hole pairs ~n~.ated. The electron and hole created by this absorption process are excess carriers;
since they are out of balance with their envi-u,l--.e..L and exist in their c;~ecLi~/e bands, they contribute to the electric~l con~lctivity of the m~trri~l (4) The fourLh known method of modulating the free charge carrier conr~ntration in semicrJn~ ctor materials is by controlling the physical sL u.;Lu,c of ch~lcogçnide phase change materials as they undergo reversible amorphous to crystalline phase Llcu~r("."~lion.c A detailed ,~pl~n~tirJn of this phPnomPn~ was reported in the early work on optical and electrical Ovonic 5 phase change materials pioneered by S.R. Ovshinsky at Energy Conversion Devices, Inc. These m~tPri~lc and t~hn-logy are diccl~csed in detail below.
Since the present invention has cignific~nt sriPntifiC applirahility to and immPrii~tP
commercial impact on many different segmPntc of the electronic and semir~nfillctor in~lctriçs~ said invention is flicc~lcsed he.~,;l.below in three different, but related sub-secti- nc More particularly, 10 the relevance of the instant invention is discussed with respect to: (A) s~micon-lu- tor devices per se; (B) optically operable, fast, non-volatile phase change memoriPc; and (C) elPctnc~lly erasable, directly ove-w-iLable, multilevel single-cell mPmori~Pc EARLY ELECTRICAL PHASE CHANGE MEMORY
The general concept of lltili7ing el~Pctrir~lly writable and erasable phase change m~tPri~lc 15 (i.e., materials which can be elPctn~lly switched between generally amorphous and generally crystalline states) for electronic memory ~lir~tionc is well known in the art and as is licclos~i, for elc~mrlP, in U.S. Patent No. 3,271,591 to Ov~hil~y, issued Sept-pmhpr 6, 1966 and in U.S.
Patent No. 3,530,441 to Ov~llills},y, issued Sept-mhp~r 22, 1970, both of which are ~ccignP~ to the same acsignPe as the present i~lvenLion, and both flicf~losllres of which are inco-~-~led herein by 20 .ef~.c--ce ~e.~,;narL~. the "Ov~h~ y patents").
As l;c~lose~ in the Ovshinsky patents, such phase change materials can be electrically ~wit~;lled between Sllu~;lulal states of generally amorphous and generally crystalline local order or between dirr.,.~ hle states of local order across the entire ~;llulll between c4~.plct~ly alllOI~ ous and . rlet~Ply crystalline siates. That is, the Ov~l~il~ky patents describe that the 25 elPctri~ wilelling of such m~teri~lc is n~t required to take place between co~ e~ely ~llol~llous and compl~tPly crystalline states but rather can be in hl.,l~,.lle.l~l steps reflecting changes of local order to provide a "gray scale" Ic~ se.lled by a m~ ir;ly of ~J~ C of local order cpAnning the spectrum between the co~rletcly amorphous and the ~ ly crystalline states. The early m~tPri~lc decc-ribed by the Ovshinsky patents could also be switched between only two structural states of generally amorphous and generally crystalline local order to accu.. r~AtP the storage and retrieval of single bits of Pnrode~ binary i,lr.,-~ tion The e1ectrir~lly erasable phase change mPmoriPc clescrihed in the Ov~hil~y patents were utili_ed in a number of culll-,-e-~;ially signific~nt applir~tion~ However, due to the lack of funding .-Pc~cc~.y for c~"""~"";Ali7~tion~ bse~lu~ d~clol,lllc-l~ in other fields of solid state clecl-unic 2~5~9~9 WO 94/24707 ~ PCT/US94/03953 mPmories eventually ~ispl~red these early electrically erasable phase change technology in the m~rkptrl~ce and prevented these memories from being used in electrical devices such as, for in~t~nee, personal co~
In the typical personal c~...l~ rr there often are four tiers of lllenlol.y. Archival S inform~tion is stored in i.~ /e, slow, high storage capacity, non-volatile devices such as ma~ptic tape and floppy disks. This informadon is ~ r~ltd, as needed, to faster and more expensive, but still non-volatile, hard disk memories. Information from the hard disks is sr~ d, in turn, to the still more expensive, faster, volatile system memory which uses sPmicon~1uGtor dynamic RAM (DRAM) devices. Very fast co...l.ut~ ~ even transfer forth and back 10 small portions of the information stored in DRAM to even faster and even more expensive volatilc static RAM (SRAM) devices so that the mic-u~lucessûr will not be slowed down by the time le.lui,t;d to fetch data from the relatively slower DRAM. Tlansfer of inform~tion among the tiers of the memory hie.alclly occupi~s some of the COI--l~u~l'S power and this need for "overhead"
reduces performance and results in ~ iitinn~l Comrl^yity in the co~ ul~, 's ar,~ ue. The 15 current use of the hie.a,~;hal ~L~u~;lun~, ho~ ,-, is dictated by the price and performance of available memory devices and the need to o~ i,f, co.~l,ute- perform~nre while minimi7ing cost.
The elr~.l,;c~lly er~ '- phase change ~ u~;cs desrrihed in the Ovshinsky patents, as well as s~lbsequPnt electri~l solid state memory, had a number of limit~tion~ that p~e~ d their widespread use as a direct and ulli~,e.~dl repl~rf ~ for present c~ J.It~,~ memory ~plir~tion~, 20 such as tape, floppy disks, m~Tnptic or optical hard disk drives, solid state disk flash, DRAM, SRAM, and socket flash memory. Specific~lly~ the following ~ "l the most ~ig,nific~nt Of these limit~tionc- (i) a relatively slow (by present standards) ~le~;l, ;C~l swi~l,i"g speed, parLicularly when switched in the direction of greater local order (in the direction of i"~"~i"g cryst~lli7~Tion); (ii) a relatively high input energy requirement nPc~ss~ry to initiate a detec.t~ e 25 change in local order; and (iii) a relatively high cost per megabyte of stored information (particularly in c~ ol- to present hard disk drive media).
The most signific~nt of these limit~tit~n~ iS the relatively high energy input required to obtain ~i~t~ le changes in the ~h~mic~l and/or electronic bon~ing c~nfi~lrations of the ch~lr~gPn;~iP- m~tlo.ri~l in order to initiate a li~Pt~PCt~ change in local order. Also ~ignific~Tlt wene 30 the ~wilclling times of the elPctric~l memory materials dPc-~ribed in the Ov~hil~ky patents. These materials typically required times in the range of a few milli~ec,on(l~ for the set time (the time required to switch the material from the amorphous to the crystalline state); and ~IJ~u~h~ately a mi-;lusecond for the reset time (the time required to switch the material from the crystalline bac ' r ~ l ' ' WO 94l24707 PCT/US94/03953 21589~9 8 to the amorphous state). The PlPCtriC~I energy required to switch these m~teri~lc typically measured in the range of about a microjoule.
It should be noted that this amount of energy must be delivered to each of the memory P.l~ mentC in the solid state matrix of rows and columns of memory cells. Such high energy levels 5 translate into high current carrying .~ui-e"-e,l~ for the address lines and for the cell icol~tion/address device ~ccoci~n~d with each discrete memory rlPmPnt Taking into consideration these energy requirements, the choices of memory cell icol~tion elemPntc for one skilled in the art would be limited to very large single crystal diode or transistor icol~tirln devices, which would make the use of micron scale lithog,a~-,y and hence a high packing density of memory elPmPntc 10 impossible. Thus, the low bit dPncities of matrix arrays made from this material would result in a high cost per megabyte of stored infonn~tion By effectively ndlluwing the flictinrtirJn in price and perform^nre between archival, non-volatile mass memory and fast, volatile system ".e."o,~, the memory ehPmPntc of the present invention have the car~l-ility of allowing for the creation of a novel, non-l~ic.a.-,llal "universal 15 memory system". Fcspntially al~ of the memory in the system ean be low eost. arehival and fast.
As ct~ dl~d to original Ov~l"l~y-type phase ehange rl~Petrie~l memoriec, the memory m~trri~.lc desn~ihPd herein provide over six orders of ma~nih-~P faster l)lu2;~ in~ time ~ess than 30 oseco,--ic) and use e~ctremely low pro~ -.i--g energy (lless than 0.l to 2 l,a,lojoules) with clPmu..~l~dLed long term stability and cyclability (in exeess of 1 billion eyeles). Also, eYrçrimpnt~l 20 results indieate that Ml~ition~ uctinnc in element si~ ean increase swi~llillg speeds and cycle life.
In general, develc pmPnt and optimi7~tiQn of the elass of ehz~lel~gçni~1e memory m~trri~lc has not proceeded at the same rate as other types of solid state e~ c~l memories that now have ~ b~ lly faster ~,wi~l;l hlg times and sub~.lh ~ ly lower set and reset energies. These other 2~ forms of mrmorie-c typieally employ several solid state mieroeleetronie eireuit rl-,---l ..1~; for eaeh memory bit (as many as three or four ~ ul~ per bit) in some me.llol~ aprlic^~ionc~ The primary "non-volatile" memory cll ",~"l~ in such solid state ",c.,-("ies, such as EEPROM, are typieally floating gate field effeet transistor deviees whieh have limited re-ylu~ ility and which hold a eharge on the gate of a field effeet transistor to store eaeh memory bit. Sinee this 30 eharge ean leak off with the passage of time, the storage of information is not truly non-volatile as it is in the phase ehange media of the prior art where information is stored through ehanges in the aetual atomie config~lration or eleet~nie ~ u-;luie of the chaleogenide material from whieh the e~emPntc are f~brie~tr~1 These other forms of memories now enjoy some limited ~r~e~l nre in the m~rketrl~ce 2158~S9 In contrast to DRAM and SRAM volatile memory devices and unlike other "flash"
devices, such as floating gate structures, no field effect tl.~ lor devices are required in the electnçAl memory devices of the present invention. In fact the electrically erasable, directly overwritable memory PlemPntc of the present invention I~ St;nL the simr'cst electricAl memory S device to f~hric,~tç, cclll~ tillg only two elçctrisAl contacts to a monnlithic body of thin film chalcogenide material and a sPmiconA~lctor diode for isolation. As a result, very little chip "real estate" is required to store a bit of inform~tion~ thereby providing for inhel~llLly high density memory chips. Further, and as ~escribe~ below, ~lAitionA~ cl~aSes in infonn~tinn density can be ~co...plich~P,d through the use of multibit storage in each discrete memory cell.
The solid state, electronic memories presently in use are relatively expensive to mPnl~factllre~ the cost being typically about twenty times the cost per bit of storage capacity in relation to magnptic disk storage. On the other hand, these solid state, electronic m-Pmorics provide certain advantages over magnetic disk memories in that they have no moving parts, Iequire less electrirAl energy to operate, are easy to lla~ and store, and are more versatile and 15 a~Art~ le for use with portable co~ ut~ -~ and other portable electronic devices. As a matter of fact, hard drive m~nllfActnrers are Ç~.,~a~li.lg rapid growth in the use of ever smaller hard drives and eventually solid state memory storage in the portable c~ ,ul~l field. In a(lAitiQn~ these solid state mpmories are usually true random access systems as opposed to disk types which require physical Illo-,elllenl of the disk head to the proper data track for a~c~ the desired memory 20 loçAtirn However, in spite of such advantages, the higher cost of solid state ele~ ically erasable memories have p,-,ie..led them from ~".jo~i..g a S~ ;A1 share of the market now ~1C"";"~I d by magnPtic .,-e.--o-y systems. .Althn~lgh solid state PlpctricAlly erasable memories could potPntiAlly be m~mlf~ctnred at reduced cost, the overall performAnr~ p .~ t ,~ of these materials are i~AAe-luA~ for them to fully replace mAgnPtic disk systems.
We previously mPntinn~Pd that there were only four known types of s~PmiconA~ctor devices which could be employed to mocllllAte the col~r~ linn of free charge. Each of those devices were then l;c~ ed in some detail. A fifth sçmiconAIlctor device which can he set to a plurality of different ~ e values by relatively low energy pulses and which is capable of relatively fast ~.~viLCl~illg .;hdlauL~Iistics will now be tliccllcced in detail. After carefully perusing the following paragraphs l-Psrribing the perfnrmAnre characteristics and the physics behind the operation of the device, the reader will understand why it was not categoriæd as a fifth type of - charge coi-r~.. l.a~ion modlll~ting sçmic~n~l~lctor device.
A l~;c~ ly developed memory device is the metal-amorphous silicon-metal (MSM) elçctriçAl memory switch. See Rose, et al, "Amorphous Silicon Analogue Memory Devices", WO 94/24707 ~ S~ 9~9 PCT/US94/03953 Journal of Non-Crvstalline Solids, 115(1989), pp.168-70 and Hajto, et al, "Qu~nti7P,d Electron T~a~ in Amorphous -Silicon Memory Structures", Phvsical Review Letters, Vol.66, No. 14, April 8, 1991, pp. 1918-21. This MSM switch is f~l~ric~t~d by the dçposition of cpeçific~lly selected metallic contacts on either side of a p-type amorphous silicon (a-Si) thin film. The 5 h..~.L~IcG of the srlectirJn of the metallic contact m~tPri~l~ will be ~ cced later. MSM
memory ~wiL~;l-es are rli~rlnsed as PYhibiting relatively fast (10-100 ns) analogue awiLcllillg behavior for voltage pulses of from 1-5 volts, thereby providing a range of re~ r~c of from about 103 to about 106 ohms to which they can be set in a non-volatile manner. As should be readily ~par~.lL to skilled pr~çtitiQnp~; in the art, the MSM memory ~wi~hGs of Rose, et al and 10 Hajto, et al, ~ltho~lgh eYhibiting electrical switching ~I.a.acLG-istics (i k ,timçs, energics and resultant device rpciq~nre) similar to the ÇlPct-ic~l swiLI,llillg char~rt~orictics of the memory elemrntc of the instant invention, there are actually si~, .i r.c~ .1 operational dirr~ ..,es t~ ,lJG~,I.
The most cignific~nt elrctlic~1 swiL~;lul-g dirf.,.G.~cc resides in the inability of the MSM
15 memory ~wiLcl.es to be directly o~,e-wliLIGll. That is, the MSM :,wiL~;l-es cannot be modlll~t~od directly bidirection~lly fTom any one .es~ r~ in the ~n~ln~l~ range of ~ re~ to any other rç~;~t~nr,e in that range without first being erased (set to a specific starting .~ re or "starting state"). More cpeçifir~lly, the MSM swiech must first be set to the high rP,sict~nre state (erased) before said switch can be set to another le~ re value within the ~n~lrJgllP range. In contrast 20 thereto, the memory el~mt~ntc of the instant invention do not require erasure before being set to another reci~t~nre in the range; i.e., they are directly UVGI ~,vliL~l)le.
Another signific~nt difference in the electrir~l switching c~ a~ ;ctics which exists between the MSM memory switches of Rose, et al and Hajto, et al and the electric~l memory el~ ."~"l~; of the present h~vell~ioll is the bipolar behavior of the said ~wil~l~es. As is ~ c~osed by 2~ Rose, et al, the MSM ~wiLcl-es must be erased using çlectrir~l pulses of reverse polarity from those pulses used to write. Signifir~ntly~ this reversal of polarity of the applied pulse is not required by the memory elemçntc of the present invention, whether the instant memory el~mPntc are used for digital or ~n~logl~e ~wi~hillg.
These dirr~.~nces in electric~l switching ch~r~cterictics between the MSM ~wil~hes and 30 the memory cl~-..k~ ; of the present invention are ~ttrib~t~l hP to more than just a mere difference in m~t~ri~l from which the elemrntc are col~ ;led. These dirrG-GncGs are indicative of the fnn~mPnt~l dirf~,.ences in switching Illk~ which ~,hala~ G the physics of operation of the two devices. As alluded to above and as licrlosed in the aforçmentir,n~d articles, the electrical swilcllillg chalaclGli~lics of the MSM memory switches are critically depP-ndPnt upon the particular 2~ 5~.~59 metal(s) from which the contacts are f~hrir~t~tl This is because these MSM switches require a very highly energetic "forming" process in which metal from at least one of the contacts is L al~ ed into and formed as an integral portion of the switch body. In this process, a plurality (at least 15 from Fig. 1 of the Rose, et al paper) of progressively incl~ g 300 n~nnsecon~l 5-15 5 volt pulses are employed to form the switch. Rose, et al state: "...X-ray microanalysis studies of the devices have been carried out, and the top electrode material has been found embeA(le~ in a fil~ment~ry region of the a-Si. This suggests that the top metal becomes disLflbuled in the fil~ment, and may play a role in the mtorh~nicm of switching...." Rose, et al also crecific~lly find that the dynamic range of the available recict~n~es is determin~d by the metal from which the 10 upper electrode contact is fabricated. As is stated by Rose, et al: ...it is found that its value is entierly (sic) de~ on the top contact, and c~.~.plc~ly in-l.o.~..~l~.-1 of the bottom met~llic~tion (sic), i.e. Cr top electrode devices are always digital and V top electrode devices are always analogue hlt;~;Live of the bottom electrode...."
It is within this metallic fil~ment~ry region where the electncal swil.,hillg occurs; and 15 without this mass migration of metal into the a-Si, there would be no ~wi~hlllg, see the Hajto, et al paper. In c~ le:~ cont-a~lictinrtinn thereto, the memory ~lc",~ ; of the preænt invention do not require migration of the contact m~teri~l into the thin-film IllC-llOl,y element to achieve high speed, low energy, ~ n~logue~ direct overwrite, memory ~wiL~ g. As a matter of fact, in the f~ric~ti~m of the Illt;lllol~ elementc of the instant invention, great care is taken to prevent the 20 diffusion of the metal from either of the electrodes into the active chalcogenide m~teri~l In one embodiment of the device described in the instant invention, the electrodes are each f~ric~ted as a bilayered structure in which, for inct~nce~ carbon fomms a thin film barrier to prevent migratin~
or tliffi)cinn of, for inct~nc~, molyWt;llulll into the chalcogenide swiL~;hing m~t.ori~l From the foregoing analysis of Rose, et al and Hajto, et al, it should be clear that MSM
25 memory swiLclles do not, by any stretch of the imagin~tion qualify as a mod~ tnr of free charge ~or~.,l.. ~inn Rather, MSM memory :iwi~;hes simply rely upon the creation of a fil~ y metallic paLhwày through the amorphous silicon material in order to obtain a range of Iksi~LiviLies in much the same way as a mod--l~tt d switch is used to control the flow of electrical current. A
percolation pathway is est~l~lichpd the fli~mlqter of which can be illclciased or de~ as~d to change 30 the resistivity thereof. No movement of Fermi level position is involved in the swi~cl ing process.
No change in activation of the semicon~-ctnr material need be invoked to explain the operation.
No atomic scale movement of lone pairs of non-bonding electrons is present. Crystallite size and surface to volume ratio thereof is not illl~lL~Il. But most illlpOILalllly, it is impossible for Rose, et al and Hajto, et al to directly o~,. wfl~e information stored in the cells of their memory m~teri~l Wo 94/~4707 2 15 ~ 9 5 9 l2 PCT/US94/03953 The MSM switch requires stored information to be erased before new informadon can be written.
It is not ~ul~ulisillg that Rose, et al have asserted that their MSM switch is limited to one million cycles while the memory rlomrntc of the instant invention were cycled over 1 billion cycles without failure prior to ending the test.
Simply stated, no solid state .-.~I-.u~ y system developed prior to the present invention, regardless of the m~frri~lC from which it was f~hric~tr-l, has been ;~ ive; easily m~nl~f~ctl~rable; non-volatile; electrically writable and directly erasable (uvt;-w-ilable) using low input energies; capable of multibit storage in a single cell (had a gray scale); and capable of very high packing density. The --~;---o.~ system descri~-pd he~c;iu~below, because it addresses all of the dçfiriçnries of known memory systems, will find immrdi~tç widespread use as a universal rerl~rPmrnt for virtually all types of cc l~u~r memory currently in the m~ptr1~re- Further, because the memories of the present invention can be f~hric~trd in an all thin-film format, three-~imPnci~n~l arrays are possible for high speed, high density neural network, and artificial intrlligPnre arplic~tionc The memory system of the present invention is therefore uniquely applicable to neural .~wu-~s and artificial intrlligPnr~ systerns because its multi-layer, three-rlimrncinn~l arrays provide massive ~.. l~ of inform~ti( n storage that is rapidly addressable, thus pc....;~iug learning from stored inform~tion It is clear from the (lic,;~ n.. above that the ~lv~ fi~e changes in ~Wi~l..l.g speed and energy e.lui.~;...c..L~ of the memories of the present invention, as ~---ual~;d to the phase change 20 mçmoriçc of the prior art, ~rmon~rate that those meml~ries define an entirely new class of modlll~t~'^ sçmicQn~ ct( r m~trri~l. In arirlition~ the prior art has no analog to the direct O~.wliLC, wide dynamic range and multibit storage c~r~hilities of the instant memory elpmrntc As should be ~blln~ntly clear to ordinarily skilled artisans, in order to address the flash EEPROM market and be seriously concidçred as a u- i~- ,al memory, it is eScpnti~1 that memory 25 c~ be truly non-volatile. This is even more signifir~nt if the IllhllOl~ element is claimed to possess multibit storage cap^' ilitiss If a set r~Ci~t~nr~ value is lost or even found to ~i~..;r.C"..~ly drift over time, the inform~tir,n stored therein is desl-oyed, users lose confi~nr~e in the archival car^t ilitirs of the memory and the trrhnnlc gy loses all credibility. In addition to set .se stability, another highly hll~lL~ factor which would be required of a u-li~el~al 30 memory is low ~wiL~;h--lg current. This is extremely ~ignific~nt when the EEPROMs are used for large scale archival storage. Used in this manner, the EEPROMs would replace the mPrh~nir~l hard drives (such as magnrtic or optical hard drives) of present c~ .vler systems. One of the main reasons for this repl~rpmrnt of conventional ~rc~ c~l hard drives with EEPROM "hard drives" would be to reduce the colllpal~lively large power conmmrtion of the merh~nir~l systems.

215895~

In the case of lap-top co~ -u~e-s~ this is of particular interest because the merh~rlir~l hard disk drive is one of the largest power con~umers therein. Therefore, it would be espec~ y adv~nt~geou~ to reduce this power load, thereby ~Ubs~ lly increasing the usage time of the co~ ul~ ~ per charge of the power cells. However, if the EEPROM repl~r~."~ .~l for me~ ";C~l 5 hard drives has high switching current ~ ui~ ents (and therefore high power r~uil~ ), the - power savings may be inronsequenti~l or at best ull~ubs~ l Therefore, any EEPROM which is to be considered a universal memory requires low ~wi~;lfulg current.
Yet another requirement of a EEPROM uluve-~al memory is high thermal stability of the information stored therein. Today's cc,.,.r~ s, especi~lly person~l co,..l~ut~"s, are routinely 10 subjected to high L~ elaLulc:s. These high ~e",pe,aLu,t;s can be caused by intemally created heat such as from power sources or other heat producing internal CO~upOI ellLs. These high 1~ es may also be caused by environment~l factors, such as use of the co..".u~r in a hot climate or storage of the co,..l~u~e~ in an environment which is directly or il~h~lly heated to higher than normal tt;lll~;la~u~;S. Whatever the cause of the elevated ~Illpeldtmt;s, present co",~ e, memory 15 systems, ecperi~lly "hard" or archival ".~...o-y, must be th.onn~lly stable even at relatively high t~lll~c;la~ul~s. Without this thermal stability data loss may occur leading to the afor~m~ntionP,d loss of credibility.
Still another ~ ui,~",e.,l of a EEPROM universal memory is long write/erase cycle life.
For EEPROMS, as is the case with all archival memory, cyde life plays an i",~.~,l role in 20 con~mer confi(ienr~ and ~rcc~ P If the cycle life of a ll.e.lloly device is too short, the cnn~l~mer will be adverse to using this device for fear of losing valuable data. If the EEPROM
is to be used as a repl~rpmpnt for c4"~l~u~r,~ main memory or display memory, that is, as a repl~r~ "~"l for DRAM or SRAM, the ,~ui,~",c"l of long cycle life is even more critical. The main and display lllc;lllOIy are a co~ lP- 's most often written to/erased data storage area. Every 2~ time a new co",l~u~e~ plu~lalll is loaded, a portion of the co",l.ul~ 's main memory is erased and Ic;wlilLen. During the eYecution of a co",~ JIU~ ll, a por~ion of the c4,~ t~ r's main memory is c~ lly being cycled. Every time the ~u".l~ ~t. r monitor's display is c~ grd, portions of the display memory are cycled. If the EEPROMs used to replace the co~..l.ul~ . 's main and display memory do not have a relatively long write/erase cycle life, these m~morjes would need to be 30 replaced excessively. This would lead to excessive costs to the co~mmer and therefore loss of con~ m~r confiden~

Wo 94l24707 2 i5 ~ 9 5 9 PCT~S91/03953 SUMMARY OF THE INVENTION
There is ~licclosed herein fundi^mçnt~lly new solid state, directly overwritable, electronic, non-volatile, high density, low cost, readily m,^nllf,^rtllr^rhle, single cell memory elemPntc having reduced switching current c~luhc~ents and greater thermal stability data stored therein. These 5 memory PlPmPntC utilize a unique class of chalcogenide ".e."o-y materials which exhibit orders Of m~gnihldP higher switching speeds at r~m^-~,^hly reduced energy levels. The novel memory materials, of which the memory elPm~Pntc and arrays of the instant invention are formed, are ch~ac~ d, inter alia, by stable and truly non-volatile cletPct^~hle configurations of local atomic and/or electronic order which can be selectively and repeatably est~hlichPd by el~PGtric~^l input l0 signals of varying pulse voltage, current and duration. The memory devices of the instant invention are ~ ,ero,c switchable between atomic and\or electronic configurations of different local order so as to provide at least two stable settings. The orders of mA~gnihld~p of improvement in swi~llillg speeds and in switching energies made possible by the memory PlPmPntc dicclc-sed herein is not merely ill~lGlllc;n~l in nature, but rather l~plcscllL~ a fun-i~ nPnt^l improvement 15 beyond what was previously thought pos~ le While theories on the memory materials described herein are presently being investig~ted, no theory as yet proposed eYrl,^inc all of the eYtraG~i"&,~ Plect~c^l swi~;l u-g behavior obse.~
Spe~^ifi.^^lly, the subject sPmico...~ ~r m Alc can be swil~l,ed between nu,.le.v~ls e1Pçtric;^lly ~P~ct^~hl^ conditions in nAnose~Aon~ time periods with the input of picojoules of energy. The 20 subject memory m~t~ ii^lc are truly non-volatile and can be cycled (written and ~vlil~n) almost in-~efinitely while m~;.~l;.;..;.~g the integrity of the inforr.^.^ticn stored by the memory cell without the need for periodic refresh signals. The subject memory material is direc,tly c,~ v-i~ble so that infonn~tinn stored in other memory el~pmpntc need not be erased (as is required with ferroelectric and other flash storage systems) in order to change infoTm^~ticn stored in a given set of memory One emholimpnt of the present invention CO~ GS an el~ctrirA~lly operated, directly ove,.v.i~ble, ml~ltihit~ single-cell memory elPmPnt The memory element inrllldes a volume of memory material which defines the single cell memory elempnt The memory material is chal~lc.;7ed by: (l) a large dynamic range of elPctric~l r~cict~nre values; and (2) the ability to 30 he set at one of a plurality of rP,sict~nce values within said dynamic range in ~ u--se to selected elPctrie~l input signals so as to provide said single cell with multibit storage c~p~hiliti~Ps The memory element also inrhldPc a pair of spacedly rlicpos~p~ contacts for supplying the electrical input signal to set the memory material to a selected recict~nre value within the dynamic range.
At least a fil~lllrl~ y portion of the single cell memory element being setable, by the selectcd ~15895~
WO 94/24707 ~ PCTIUS94/03953 elPctrir,~l signal to any resict~nr~ value in said dynamic range, regardless of the previous resi~t~nre value of said m~teri~l The memory element further inrl~ldes a filamentary portion controlling means disposed between the volume of memory material and at least one of the spacedly disposed cont~ct~. The controlling means defining the size and position of the fil~ment~ry portion during S el~pctric~l formation of the memory element and limiting the size and confining the location of the fil~mPnt~ry portion during use of the memory elPmçnt, thereby providing for a high current density within the fil~mPnt~ry portion of the single cell memory element upon input of a very low total current ~Pl~Pctric~l signal to the spacedly disposed cont~tc Preferably, the fil~mPnt~ry portion controlling means comrri.~es a thin film layer of 10 between l0 and 100 Angstroms thick disposed between one of the spacedly disposed contacts and the volume of memory m~tP,ri~l More ~l~fe-ably, the fil~mt~nt~ry portion controlling means co~ ,lises a t,hin film layer of highly resistive material CQ~ at least one low re~ e l~d1,hWd~ C~IUSS, through which input electrical signals pass between the spacedly tli~rosed contact and the volume of memory 15 material. In one emho~im-Pnt, the highly resistive material p~Gftlably is formed of C, F, O, Si and H and is most preferably fonned of a m~tPri~l having a coml)o~ition of, in atomic percent, between about 60-70% carbon, 20-30% fluorine, and 3-10% oxygen, 0.5-2% Si and the rem~in~ler H and other ;...l,u~ s Other em~o~;...P~ and features of the present invention as well as other advantages and 20 objects thereof will be set forth and become a~ alGIlL from the detailed dei.~ ion of the invention which follows hereinafter, e~eç~ y when taken in comhin~tion with the ~rc4...~ yillg dlawi BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a r.~.~.. 1~. y cross-section~l view illustrating a portion of an integrated circuit, 25 said circuit ~ ting an elpctriç~lly erasable and directly ov~,wlilable multilevel memory confi~ation of a first "lGrt-~;d tombo limPnt of the present i~ve~Li~ll;
Fig. 2 is a r..~g...~ .y cross-section~l view illu~LIaLiJlg a portion of an integrated circuit, said circuit depicting an elPctric~lly erasable and directly ovc~ wfiLdble multilevel memory confignration of a second preferred emhodiment of the present invention;
Fig. 3 is a top plan view srh-pm~tir~lly illustrating a portion of the integrated circuit csnfi~,..aLiolls of Figs. 1 and 2;
Fig. 4 is a sçhPm~tic circuit diagram illu~LIaLhlg a por~ion of the X-Y matrix array of isolation el~Pm-Pnt~ in csmbin~tion with the memory PlPmrPnt~ of the integrated circuit confi~-rations of Figs. 1 and 2;

WO 94/24707 ~, ~ 5 ~ 9 $ 9 - . PCT/US94/03953 Fig. 5 is a srh~om~tic ~ cst;llLation illllctr~ting a single crystal semicon(lllGtor svbsl~
with the integrated memory matrix of the instant invention as depicted in Figs. l and 2 placed in el~ctric~l co""".~.;r~tion with an integrated circuit chip on which the address/driverstdecoders are operatively affixed;
S Fig. 6 is a temar,v phase diagram of the Ge:Sb:Te alloy system from which the memory çlementc of the instant invention are fabricated, said phase diagram ~llowi"g the multiple phases into which various mixtures of these elementc segregate upon rapid soli~lific~tion;
Fig. 7 depicts the atomic :~Llul;lulal layering of three temary alloys of the Ge-Sb-Te system of Fig. 6 as well as the atomic structure of binary Ge-Te so as to illustrate the anisotropic ~LIuCLul~;
of the systems;
l:ig. 8 is a g~aphiCal depiction of data i~ ct~ting cycling clla~ ;ctics of a first memory element without the fil~ment crnfining layer of the present invention;
fig. 9 is a gr~rhic~l der :'on of data illustrating mllltist~te car~ iti~c (i.e. ability of the memory element to be set to mlllfipl,e resict~nc~ levels within the dynamic range of ~,;cl~ ~s) of a first memory element without the fil~m~nt con~ g layer of the present invention;
Fig. 10 is a graphical depiGtion of data illu~LlaLillg cycling chàla~t~ l;rg of a second memory element without the fil~mPnt co..l;..;~.g layer of the present il.~,..Lioll, Fig. 11 is a graphical d- pj~tjon of data illu~LldLillg m~lti~t~te car~)ilititoS (i.e. ability of the memory element to be set to multiple recict~nr~ levels within the dynamic range of recist~n~s) 20 of a second .-le,-.oly element without the fil~mPnt c~nfining layer of the present invention;
Fig. 12 is a ~,lal~hiCal depiction of data illu~dlillg cycling ~,l~te.istics of a memory element with the fil~ment cv--li--; g layer of the present invention;
Fig. 13 is a graphical ~lepi~ion of data illust,rating mnltict~t.~ c~r~hilities (i.e. ability of the --~,.--o-y element to be set to multiple recict~nce levels within the dynamic range of ~;C;~ es) 25 of a memory element with the fil~m~nt colll;u;l~g layer of the present invention;
~ ig. 14 is a graphical depi(tion of the derivative mode Auger Electron S~ lu~copy analysis of the as-deposited carbon layer in the electrodes of the memory el~ -"~"lC of the present invention;
Fig. 15 is a graphical depiction of the derivative mode Auger Electron Spe~;l,vsco~y 30 analysis of a dry-etched carbon layer in the electrodes of the memory elem~ntc of the present invention; and Fig. 16 is a graphical depiction of the derivative mode Auger E~lectron Speut~uscopy analysis of a wet-etched carbon layer in the electrvdes of the memory el~mentC of the present invention.

WO 94/24707 ~, 1 3 8 9 5 9 PCTIU594l03953 DETAII ED DESCRIPTION OF THE INVENTION
Erasable electrical memories f~ric~tP,d from the broad class of chalcogenide m~tPri~lc have employed structural changes that were ~cGommo~i~tP~d by movement of certain atomic species within the material to permit change of phase as the m~tPri~l switched from the amorphous state 5 to the crystalline state. For PY~mrle in the ease of electrically switchable chalcogenide alloys formed of t~lh-rium and germanium, such as those esmrricing about 80% to 85% tellurium and about 15% gPnn~nil~m along with certain other elPmPntc in small qll~ntitiPs of about one to two percent each, such as sulfur and arsenic, the more ordered or crystalline state was typically e~ d by the form~tion of a highly elPctrie~lly csn-h~tive crystalline Te fil:~ nPnt within 10 the switchable pore of the memory material. A typical c(""posilio,~ of such a prior art material would be, for eY~mrl~, Te8,Gel5S2As2 or Te8lGelsS2Sb2. Reeal~cP Te is so highly cond~lctive in its crystalline state, a very low reCict~nce con~lition wæ e~st~hlichpd through the Te fil~mPnt in the more ordered or crystalline state; this rp. cict~n~e being a number of orders of magnit~l~P lower than the resict~nce of the pore in the less ordered or amorphous state.
However, the fonn~tio~ of the eon~ ctive Te fil~mPnt in the crystalline state required migration of the Te atoms from their atomic confi~lr~ti~nn in the alllGIlJhuus state to the new locally co~ d atomic c(~nfi~ration in the crystalline Te fil^ nPnt state. Similarly, when the ch~lc~g~Pn;~e fil~mPnt~ry m~tPri~l was switched back to the amorphous state, the Te which had preçirit~t~d out into the crystalline fil~mPnt was l~ui~t;d to migrate within the m~tPri~l from its 20 locally eO.~t~P~.I.aled form in the fil~mPnt back to its atomic ~nfi~lration in the ~..o-~ ous state.
This atomic migration, diffusion or Icall~ Pnt ~Iween the alllOl~huu~ and crystalline states required in each case a holding or dwell time of suffil~ient length to acesmmQ~tP the migration, thereby making the requisite swi~l.il-g time and energy relatively high.
The subject illV~ Ol~i have discuie-~d a rPm~k~hle reduction in both the required 2~ switching time and the energy input for a fimrl~ment~lly different type of electri~lly erasable, directly ove,wli~ble memory based up on a new class of chaleogenide sPmic~-ndl Gt~r materials.
Moreover, the chalcogenide materials are based on fim(l~TnPnt~lly new physics, the operation of which, ~lth~lugh not fully nnrlPnctoocl~ provides for ~wi~cl i-lg either within a wide dynamic range of stable states with rPm~*~hly low energy inputs at rem~*~hly fast speeds so that this newly 30 discovt;r~d class of m~teri~lc can be uæd to f~h-ic~t~p improved electrical memory el~omPntc Sperifir~lly, the memory material can be swi~hed between elpctric~lly detPct~hlecon-litirnc of varying reCict~nce in l-~osecol-(~ time periods (the ...;l~ wil~;llillg speed and ...i.-i...-~.. energy l~ui~ ents have not as yet been asce.~i..ed, howt;ver, e,~ l data as of the filing of this ~pplic~tion have shown that the electric~l memory can be mc-d~ tPd (even WO 94/24707 2 ~5 ~ ~ S 9 PCT/US94/03953 ~
- . 18 though not o~i---i,ed) with as short as I n~.,nsec~."fl programming pulses) with the input of picojoules of energy. This memory mateAal is non-volatile and will m~intAin the h~t~ y of the inform~tion stored by the memory cell (within a selected margin of error) without the need for periodic refresh signals. In contrast to many other sPmiconfl~lctor m~tPri~lc and systems heretofore 5 specified for memory applif~tionc, the semirul~ OI memory mateAal and systems of the present invention are directly overwritable so that the discrete memory elPmPntC need not be erased (set to a spe~ified starting point) in order to change information stored there. The rem~*~llly fast and low energy s~ilcl.i..g to any of the different values of r~ e can be ~ttnbutPd to the fact that said swi~l---,g occurc without the need for gross atomic G~.~ ,~e"~ of the swilcllillg material.
The memory material is formed from a plurality of col,~ ,ll atomic elPmPntC. each of which is present throughout the entire volume of memory material. The plurality of col.~
atomic e1~. P.ll~i plerG.ably includes at least one chalcogen element and may include at least one transition metal elPm~Pnt The term "tr~ncition metal" as used herein inrlndes elPmentc 21 to 30, 39 to 48, 57 and 72 tO 80. More preferably, the plurality of co~ ,l atomic pl~ I-f -ll`i which 15 form the volume of memory material inf~-lnfies elemPntc selected from the group cou~ of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof. More preferably the transition metal inf~ f1Ps Cr, Fe, M and Il~ Wt;S of alloys thereof and the f~h~lcogPn element inr~lvdps Te and Se. Most Inef~;.ably the transition metal is Ni. Specific el~ r'-S of such multi-element systems are set forth he.~inar~r with respect to the Te:Ge:Sb system with or without Ni 20 and/or Se.
As is well known to those skilled in the art, f~h~lf,f genidP semico..du.;~Dr m~teri~lc, like other sP.mieonflvotors, are char~cteri7Pd by a forbidden energy zone or band gap sepa,atil-g their confluction and valence bands (see the "Cohen, F~ le~ Ovshinsky model" desc~rihing the mobility gap of chalcogenide spmi~onflllctf~r m~tPri~lc). The Fermi level position, i.e., the energy 25 at which the probability of oc~lJal~y of an energy level is 50%, det~PrminPs, in part, the cle~;llical cQn~1vctivity of the sPmirQndvctnr material and, as it is moved to s..~ lly dir~.rll~ positions in the band gap, a large dynamic range of elPctnc~l cnn~ tivities become ~ ' '^. However, previously l.y~ ;,~ theories can neither explain the very low energy re4ui~ .el~ needed to change the position of the Fermi level and thereby set the memory elPmPntc at a given ,~ ul~e 30 value nor can they explain the types of results presented graphically below, particularly the rPm~ le ability to move to intPmm~P~ t~P values of rPcict~nce in both directions (from values of lesser rç~ict~n~-p to values of greater rPcic~neP upon the input of a given elPctric~l signal as well as visa versa) without rPtllming to the aforPmentinnPd initial "starting state" which requires operation only in a single direction of movement (from values of higher recict~nc_ to values of lower reci~t~nr~). That is why we state that the s~omicon-iuctor material of the instant invention is truly directly overwritable. Regardless of the e~ on of the manner in which this is ?rcompli~h~d, the present invention provides a comhin~tion of valuable electri~l switching char~rtP~i~tic~ never before available in a single memory element.
S A fi-n-i~mlont~l rule ~ iugl~i~hing noncrystalline solids from their crystalline COUI~
is that the con~tihlent atoms of the non-crystalline phases have bonding options. This is the sine aua non of nonc-y~lalline solids. It results from the fact that crystalline symmetry prescribes the lattice which, in tum, restricts chtomic~l bonding choices. All of the properties ~o~ Pd by an amorphous solid; its cohesive energy, its IGS;~ C~ to cryst~lli7~tion~ its optical band gap, its mobility gap, its density of electronic states, etc., depend upon three factors; its short range bonding r~l~ti- n~hip5, its varied topological configura*ons, and its total a~,live Gllvil~llm~
An amorphous m~tPri~l, however, can be a nt)n~toirhirlmptric alloy in a n- nPrl-lillibrinrn confiFIlration, conci~*ng of many dirrGIGll~ types of atoms, providing a variety of local order and environmPnt~. The crystallites from which a large volume fraction of the s~micQnA~lctr r material of the instant invention is collll,osed, are very small, on the order of (by way of es~rnrl~) 500 Angstroms in major ~limPn~ion These crystallites are surrounded by a skin or surface region of structurally disordered m~tPri~l which may only be a few atomic monolayers thick. Therefore, an ~I,o,~hous model or at least a model cll~.~ P,d by only short range local order, can best be employed to attempt to predict the molecular and atomic intPr~tir~n~ in the surface region.
Without wishing to be bound thereby, such a des~;pl;ve model will be (lescrihed in the following palaglal,hs.
The specific semicc-n~uctor alloys employed in f~hric~ting the memory devices include ch~lr,ogPnide elPmPnt~ which are particularly noted for the pl~ ce of "lone pair" el~ulls. It is ~ .ero,G l~c~ to discuss the effect of those lone pair ele~llolls in available chPmiç~l bonding c~nfigllrations. Simply stated, a lone pair is a pair of elecLK)ns in the valence shell of an atom that is typically not eng?.~d in bon-lir~ Such lone pair ele~;Uu, s are ""~,~,1 both u~;lulally and çhPmic~lly. They infl~l~n~ the shape of molecnlPs and crystalline lattice ~UU~;IU1~S by exerLing strong repulsive forces on nei~l,bo",.g electron pairs which are ~ng~ed in bonding confi~lrations and as well as on other lone pairs. Since lone pair eleclluns are not tied down into a bonding region by a second nnçleu~) they are able to inflllçn~e and contribute to low energy electronic tr~n~ifion~ As first pointed out by Ovshinsky, the lone pairs can have 1 and 3 center bon-1ing; and as ~ie.,.u~ d by Kastner, Adler and Fritsche, they have valance ~ltern~tion pairs.

WO 94/24707 21~ 8 9 5 9 PCT/US94/03953 Specific~lly, the tellurium alloys described herein have a valence band made up of lone pair states. Since four (4) p shell electrons are present in Te, and the Te atom is chemir~lly bonded by two of these bonding electrons in the p shell, the other two outer elecL uns (the lone pair) are not utilized for bonding purposes and hence do not sllhst~nti~lly change the atomic S energy of the system. In this regard, note that the highest filled molec~ r orbital is the orbital which cnnt~in~ the lone pair ele~,L-~"ls. This is ~i~nific~nt because, in a perfect stni~hiomçtric crystal of tellurium and germ~ m atoms, upon the arplic~tion of some intemal strain in the lattice from which the crystallite is formed, the valence band can broaden and move upward toward the posidon of the then existing Fermi level. However, TeGe crystals are naturally "self-10 co~ d", that is, the crystal desires to ~,lcfclc,-lially assume a Te rich (52 percent Te and 48 percent Ge) c~,..pos:~ion The stnirhir-mptric crystal is a face centered cube; however, with the addition of a minim~l amount of energy, the crystal can assurne a rhnmbohPAr~l lattice structure by h.l;.c~i.lg the number of its Ge and/or Sb va~ ;es It is this creation of var~nriP~ in the crystalline lattice ~LIu~;Lulc, which can reduce lattice strain in TeGe alloys, is respnnsihl~P for 15 lowering the energy state of the material and moves the Fermi level toward the valence band.
It is nccept~b'-. if not ec~pnti~l to s.~ ;...pose an amorphous model of local order on top of a short range local order model for the purpose of Ob~ai. ing a cl~ ;pl;~e, if not perfectly predictive eYrl~n~tion of atomic behavior. When cnn~;~lPring the amorphous nature of the m~tPri~l, note that the density of defect states in the band tails is greatest ~ rPnt the band edges, while the depth of the recomhin~tinn centers for captured charge carriers are deeper farther away from the band edges. The ~lcscnce of these deep traps and tail states would provide a possible eYpl~n~ion for; . .l--- . . e- ~ le stable ,~ l ;., re values between the Fermi level position and the band edge. Regardless of theory, when fully crystalline, the sPnlirnn-3uct(r m~tPri~l of the instant invention is a degenc-aLe sPmiru.~ Lol which exhibits metallic-like contiuctinn It is further believed that the size of the crystallites which exist in the buLk of the semir~ ,clor and memory material is relatively small, ~lerelably less than about 2000 A, more preferably bcLwcc.. about 50 and 500 A, and most p~crclably on the order of about 200 to about 400 A. Further, these crystallites are believed to be ~u~ ullded by an amorphous skin which may conLlilJuLe to the rapid formation of the many Fermi level positions of the m~tPri~l, det~ct~l~'c as 30 dirrclcllL Ic~ rÇS (cnn~1uctivities)~ as well as to the lower energy le.luilclllellL~ for the tr~n~ition~
between these det~Pct~hle rç~ict~nre values to which the material can be reliably and repeatably set.
In accordance with still another aspect of the present invention, it has been found that modulation of the ~wiLellillg ~:haracLcli~Lics of two or three termin~l semiconductor devices f~hnc~tpd from the microcrystalline materials of the present invention may be controlled such that WO 94/24707 21~ 8 9 5 9 PCT/U594/03953 reE~e~t~hle and detect~hle recict~nr~ values can be effected. It has been found that, in order for the m~t~ri~lc of the present invention to be quickly set by low energy input signals to a desired con~iurtivity (rieterminpd by the Felmi level position), it is only n~c~ that said m~tt ri~lc are capable of stable (or long lived met~ct~le) e~ictçnre with a at least two dirr.,.~ Fenni level 5 pocitionc, which Ferni level pocitionc are chala~ d by ~..h~ lly C~ band gaps but different e4ctric~1 co~ ctivities. As noted above, it is also believed that the relatively small crystallite size may contrihlltr~ to the rapid transition between dctect~hle values of rçcict~rlre Onechar~ctericticofthes~rnicon~ ctormaterialsofthepresentinventionistheirtendency toward the formation of more and smaller crystallites per unit volume. Crystallite sizes of the 10 widest preferential range of e~-c;senlaLive materials embodying the present invention have been found to be far less than about 2000 A, and generally less than the range of about 2,000 to 5,000 A which was char~rt- rictic of prior art m~tr ri~lc Crystallite size is defined herein as the rli~meter of the cryst~llites, or of their l'Ch~a~,L~;IiSLiC rlimr n~ n~ which is equivalent to the di~rneter where the crystallites are not crhrrir~lly shaped.
It has been del~.. ";l--d that co"~io~ in the highly resistive state of the class of TeGeSb m~tr ri~lc which meet the criteria of the present invention are generally r~ t~ i~cd by ~b~ lly reduced c4l~t~ a~i~,ns of Te relative to that present in prior art eU~trically ~
memory m~teri~lc In one c4."po~ that provides ~v~ ly i~ vved ele~;LIicdl ~ lg performance cl-d a~-le-;~ics~ the average conr~,l,a~ion of Te in the as deposit~-d m~tr ri~lc was well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. G.l-~ ,l ,alions of Ge were above about 5% and ranged from a low of about 8% to about 40% average in the material, rem~inir~ generally below 50%. The rem ~in-i- r of the principal c~ e~ ~l rl . l lrl ll~ in this co~ )o~; l ;on was Sb. The ~ ~s given are atomic ~,~t~"l~c which total 100% of the atoms of the conctih~ente1 ."~ ;. Thus,thisco~ ~;I;onmaybecharacterized asTe"GebSb,OO~.tb)- ThesetemaryTe-Ge-Sb alloys are useful starting m~tr ri~lc for the development of ad~iihnn~l memory materials having even better el~ctric~l clldla~;Lelistics.
A ternary diagram of the Te:Ge:Sb system is shown in Fig. 6. Melts were prepared from various mixtures of Te, Ge and Sb, the melts segregated into mnltirle phases upon rapid solidific~ti- n. Analysis of these rapidly solidified melts in~iir~ted the l.r._se,lce of ten dirf~"~nL
phases (not all present in any one rapidly soli-lified melt). These phases are: el~m~nt~l Ge, Te and Sb, the binary co...~ c GeTe, and Sb2Te3 and five dirrGIGllL temary phases. The ~lemPnt~l ColllposiLions of all of the temary phases lie on the pseu~ohin~ry GeTe-Sb2Te3 line and are intlic~ted by the rerGIG ce letters A, B, C, D and E on the temary diagram shown in Fig. 6. The Wo 94/24707 215 8 9 S 9 22 PCT/U594/03953 atomic ratios of the ~l~.mt7nt~ in theses five temary phases are set forth in Table l. A more detailed d~rriptinn of Fig. 6 is ~ ;se.~ed ht;.~ ~low.

Table I
5Observed TernarY CrYstalline Phases of the TeGeSb SYstem Desiqnation At % Ge At ~ Sb At % Te The novel memory e1c....e..l!; of the present invention include a volume of memory m~t~ri~1, said memory m~t~.ri~1 preferably i~ at least one chalcogen and can include one 15 or more tr~n.~ition metals. The memory m~teri~1c which include tran~itinn metals are e1em~nt~11y modified forms of our memory materials in the Te-Ge-Sb temary system. That is, the ~em~nt~11y m~ifi~d memory m~ori~1~ c~ mo-~ifiPd fomms of the Te-Ge-Sb memory alloys. This el ....~ mo~lifi~ ~tinn is a ~h.e~ed by the L~co,~o~ on of Ll~ilioll metals into the basic Te-Ge-Sb temary system, with or without an ~rlitinn~1 chalcogen el~mpnt~ such as Se. Generally the 20 e1- "..~ ny mo~lified memory m~ttori~1~ fall into two c~ .-;e~
First is a memory material which inrllldes Te, Ge, Sb and a transition metal, in the ratio ~Te~GebSb10O (~b~)cTMlO0-c where the ~vl sc~ are in atomic ~..;~ e~ which total 100% of the co~ ..l e1e.mentc, wherein TM is one or more tran~iti(-n metals, a and b are as set forth herein above for the basic Te-Ge-Sb temary system and c is between about 90 and about 99.5 %. The 25 tran.~ition metal can preferably include Cr, Fe, Ni and ~ Lult;S of alloys thereof. Specific ~mplcs of memory m~teri~ ed by this system would include (Tes6Ge22Sb22)95Ms, (Tes6Ge22sb22)soNilo~ (Tes6Ge22sb22)95cr5~ (Te56Ge22Sb22)90Cr10. (Te56Ge22Sb22)95Fe5.
(T*6Ge22Sb22)90Fe10, (Te56Ge22Sb22)90Ni5Cr5, (Te56Ge22Sb22)90Ni5Fe5, (Te56Ge22Sb22)90Cr5Fe5, etc.
Second is a memory m~t-ori~1 which in~ des Te, Ge, Sb, Se and a t~ansition metal, in the 30 ratio (Te.GebSblOo~.+b~)cTMdseloo-~c+d) where the ~bs~;J;~; are in atomic ~...I;.~s which total 100% of the coll~ ll ç1P.mtontc, TM is one or more tr~n.~ition metals, a and b are as set forth helt;hlabove for the basic Te-Ge-Sb temary system, c is between about 80 and 99% and d is between about 0.5 and 10%. The tran.~ition metal can preferably include Cr, Fe, Ni and mixtures of alloys thereof. Specific e~mpl~s of memory materials ~ ...r.~ed by this system would include (Te56Ge22Sb22)90Ni5Se5. (Te56Ge22Sb22)80NilOSe10, (Tes6Ge22sb22)9ocrsses~

21~8959 WO 94/24707 PCT/US94/039~3 (Te56Ge~Sb22)80Cr~OSelO. (Tes6Ge22sb22),~oFesse5~ (Te56Ge Sb22)80F~e,OSe~O, (Te56Ge22Sb22)85Ni5Cr5Se5, ~Te56Ge~Sb22)80Ni5Fe5Se10, (Te56Ge22Sb22)85Cr5Fe5Se5, etc.
The memory pl~mentc of the instant patent applir~tion possess subst~nti~lly non-volatile set recict~nre values. However, if the recict~nre value of the instant memory elements does, under 5 some circum~nres, drift from its original set value, "co...l)o~:~ion~l mollifir~ion", described hereinafter, may be used to elimin~tr for this drift. As used herein, the term "non-volatile" wiU
refer to the conrlition in which the set ",~:cl~ .re value remains s~ ly c~l.cl~ for archival time periods. Of course, software (inclufling the fiçe~h~r~ system dic~ ed hereinafter) can be employed to insure that ahsoll~trly no "drift" occurs outside of a selected margin of error. Because 10 drift of the recict~nre value of the memory el~mrntc can, if left unimpeded, hinder gray scale storage of inform~tion, it is desi, ''e to ~ drift.
"C~....pos;lion~l modifir~tion" is defined herein to include any means of co~ )oli;lion~lly modifying the volume of memory m~t.ori~l to yield s~lh~nti~lly stable values of r~Cict~nce, inr~ ing the a~1~1ition of band gap widening el~m~ntc to increase the hlhC~ e~ ce of the 15 material. One r~;..llple of colllposilion~l mo~lifir~tion is to include graded co~.ros:~ion~l inhnmng~nritiPc with respect to thir~necc For i..~ nes, the volume of memory m~t.ori~l may be graded from a first Te-Ge-Sb alloy to a second Te-Ge-Sb alloy of dirf~,li--g ~u---posi~iol~ The co...l ocilinn~l grading may take any form which reduces set .~ e value drift. For ~ , le, the co~..l o~ on~l grading need not be limited to a first and second alloy of the same alloy system.
20 Also, the grading can be ~cc~...l~lich~ with more than two aUoys. The grading can be uniform and CO..Ii~ ou~ or it can also be non-uniform or non-c~ ouc A specific ~ lle of comrosition~l grading which results in reduced r~ re value drift innlude-c a uniform and cr...li..~o~c grading of Ge,4Sb29Te5, at one surface to Ge22Sb22Te56 at the opposile surface.
Another manner of t;lllployhlg c~ o~ilion~l motlifir~tinn to reduce reCict~nee drift is by 25 layering the volume of memory m~trri~l That is, the volume of ",e",o, y material may be formed of a plurality of discrete, relatively thin layers of differing composition. For ey~mr'~ the volume of memory m~tPri~l may include one or more pairs of layers, each one of which is formed of a dirre~"L Te-Ge-Sb aUoy. Again, as was the case with graded co...p osilionc, any cnmbin~tinn of layers which results in ~ lly reduced ~s;~ e value drift can be employed. The layers 30 may be of similar thi~ness or they may be of differing thie~n~ss Any number of layers may be used and mllltiple layers of the same aUoy may be present in the volume of memory material, either cnntigllous or remote from one another. Also, layers of any number of dirr~.i"g aUoy composition may be used. A specific r~ Jl~ of composition~l layering is a volume of memory material which inrludP$ ~ltrm~ting layer pairs of Ge,4Sb29Te5, and Ge22Sb22Te56.

WO 94/24707 PCT~S94/03953 Yet anothe~ forhl of cc~ po~ilion~l inhomogeneity to reduce recict~nr~ dAft is arc~,...l)lichPd by comhining compocitinn~l grading and co...l osiliQn~l layeAng. More particularly, the aforPmPntinnPcl compQciti-nn~l grading may be combinPd with any of the above dPccribed compositicn~l layeAng to form a stable volume of memory mateAal. FYemrlary volumes of memory m~tPri~l which employ this cnmbinrAtion are: (1) a volume of llle.llol~ mateAal which u(l~Ps a discrete layer of Ge Sbl2Tes6 followed by a graded culllpo~iliol~ of Ge,4Sb29Tes7 and Ge22Sb22Tes6 and (2) a volume of memory mateAal which inrludçs a discrete layer of Gel~Sb29Tes7 and a graded culllposi~ n of Ge,4Sb29Tes7 and Ge22Sb22Tes6-RPfPrring now to Fig. 1, there is shown a eross-sçctinn~l view of a portion of the structure of an el~Pctric~lly erasable memory of the present invention formed on a single erystal silieon sçmir~n~ ctor wafer 10 whieh is p-doped and whieh forms a p-~u~ AI~ for the depoQ,itinn of the rçm~ining Pl~mPntc of the eonfi~lration jllustrated. Formed in the p-substrate 10 are n+ çl.~."~çlc 12, which may be diffusion doped in a manner well known in the art. These n+ rhA.,~flc extend across the ehip in a direetion perpçnr1ir,~ r to the plane of the illllctration and form one set of eleetrodes, in this case the y set, of an x-y electrode gAd for addressing the individual memory el.om~.ntc A top of this n+ gAd ~llu~;lw~ is formed an n-doped crystalline epit~ l layer 14 about s,ooo A thick~ Using known m~QI~in~ and doping tprhniqu~pc~ p-doped icQl~tiQn eh~nnPlc 16 are then formed in the n-epit~ l layer 14~ These p-doped icol~ticm rh~nnPlc 16 extend all the way down to the p substrate 10 as shown in Fig. 1 and also extend comr'~: 'y around and isolate and define islands 18 of the n-epit~xiAl layer 14. The islands 18 are shown more elearly in the top view of Fig. 2 wherein the p icol~tinn eh~nnplc are shown as forming an icnl~tion gAd d~Pfining and icol~ting the islands 18 of n epitaxial matPri~l Instead of the p-doped i~l -tinn çh~nnPlc, SiO2 ic~ inl~ L~ne,l.es may be used for icnl~tiQn of the islands 18. The tçchn;que of formation of such SiO2 icnl~tiQn l,~,ncl,~,s is well known to those skilled in the art. A layer 20 of thermally grown SiO2 is then formed on the strueture just decçrihed and etched to form ~lu~t;S 22 over the islands 18. Diffusion regions 24 of p+ mateAal are then formed within the areas defined by the ~ IUIGS 22 as shown in Fig. 1. The spmiron~ çt(lr jlmrtinnc of the p+ regions and the n eph~lxi~l layer define p-n junetion diodes 26 in seAes with eaeh of the regions of the n epitaxial layer exposed through the a~,lu,es 22 of the SiO2 layer 20.
The memory elpm~pntc 30 are then deposited over the p+ regions 24 in individual ohmic eleetric~l seAes eontact with the diodes 26. The memory PlPmPntc 30 co~ e bottom thin Pl~octriç~l contact layers of high corrosion r~sict~nr~ metal (such as, for example, molybdenum) 32. Previously, in the Ovonic EEPROM, single layers of elpctrir~lly ennd~l~tive ~"("~hous WO 94t24707 PCT/I~S94/03953 carbon were used as (liffucion barrier layers 34 and 38; however, in the structurally mo(lified memory PlPmPntC of the instant invention these a-carbon layers have been mo~ified or replaced.
This mo~lified structure inrl~lde,c either a single ~ o,~hous silicon layer in place of the am~.l,hous carbon layer or a thin silicon layer disposed between the ~--o-l,l-ous carbon layer and the layer 5 of memory m~tPri~l 36. The upper thin PlPctric~l contact layer of corrosion resict~nr_ m~tPri~l 40 is f~hrir.~tPd of molyl,denul.. and the electrically eQ~u~ ;ve ~iffi-cion barrier layer 38 is f~hric~tPd of a-carbon, a-silicon or a dual a-carbon/a-silicon structure. The contact layers 32, 34, 38 and 40 form e~rrÇllpnt ~PlPr,trir~l contacts with the layers of memory m~tPrj ~l 36 and layers 34 and 38 also form ~iiffilcion barriers which inhibit ~iiffi~ n of the molyW~..ul.. metal and/or an 10 optional extemal contact grid material contact into the volume of chalcogenide memory materlal 36. The a-silicon of layers 34 and 38, when used in combin~tinn with a-carbon are relatively thin, typically in the range of 50 to 600 A and more particularly 100 to 400 A. When used alone as layers 34 and 38, the a-silicon layers are between about 400 and 2000 A ~e~~ on the elPct-ir~l resistivity thereof. The molybdenum layers 32 and 40 are relatively thick, in the range of about 1,000 to 2,000 A.
The layer of memory m~teri~l 36 is formed of a multi-element Se'niCOI~ 101 materi~l, such as the chalcogenide m~t~ri~lc riicrlr~sed herein. The layer 36 may be d~po~ilPd by mPthn lc such as s~ , c;v ~ ion or by r.hemir~l vapor d~pocitirJn (CVD), which may be c~h~ d by plasma techni~lues such as RF glow dis~ e. The rh~lrog~n;~e memory m-~Pri~lc of tl~
20 instant invention are most preferably made by RF !l~u~ g and t,~a~,aLion. Typical ~epoCitirJn parameters for RF ~pull~.;..g and evapolaLion of the chalcogenide layer 36 are set forth below in Tables 2 and 3, l~cclively.
Table 2 RF Sputterinq Deposition Parameters Parameter TYpical Ranqe Base pressure 8x10-7 - lx10-6 Torr Sputtering gas 4 - 8 m Torr (Ar) pressure Sputtering power 40 - 60 watts Frequency 13 - 14 MHz Deposition Rate 0.5 - 10 A/second Deposition Time 2 - 25 minutes Film Thickness 250 - 1500 A
Substrate Temp. Ambient - 300C

W094/~707 2158 9~ ~ PCT~S94/03953 Table 3 EvaPoration DePosition Parameters Parameter TvPical Ranqe Base pressure lx10-6 - 5x10-6 Torr Evaporation Temp. 450 - 600 C
Deposition Rate 2 - 4 A/second Deposition Time 2 - 20 minutes Film Thickness 250 - 1500 A
Substrate Temp. Ambient - 300C
It is important ~o nolc that evaporaLed films deposited on a heatcd substrate exhibi~
a...soL.ul~ic gr~wth rh~r~rtprictics (see the "ec~ irJn of Fig. 7) in which ori~P-ntPd layers of the ch~lr,ogPni-le rl ...t~ are successively depo~itP~ Whether this proves to be ~ignifir~nt for çl~ctric~l ~lir~tirnc has yet to be proven; however, this type of film holds promise for 15 th~ormoPl~pctricily (due to the high thermopower already -lca~u-~d for these co.~ onc, i.e., a factor of four greater than that measured for bismuth systems) or for specific semicon~-lctor and ~U~I~ll~lllctivity ~rplir~tionc The layer of ~ ,.--û-~ m~tPri~l 36 is preferably deposited to a thir~nPcc of about 200 A to 5,000 A, more ~.cr~.a~ly of about 400 A to 2,500 A and most preferably of about 250 A to 1,250 20 A in thir~nPcc The lateral ~limencion or di~mpt~pr of the pore of sPmicon~uctc r material 36 is less than about one to two micrometers or so, ~lthr~ugh there is no practical limit on t-he lateral ~imPn~ir,n It has been detPrminPd that the ~ mPtor of the actual c4~d~ e path of the high conductivity m~tPri~l is 5ignifir~rltly less than a micrometer. The pore ~ ,r can thus be as small as lithography resnlution limits will permit and, in fact1 the smaller the pore, the lower the 2s energy ~t;4uhelllents for elPctrir~l ~wil~hillg.
In a preferred embotlimPnt of the present invention, the pore ~ e~ is selected such that it t~nformc ~-b~ lly with the ~ metPr of the low re~ict~nre path which is formed when the m~tPri~l is swiL~;hed to the low re~ict~nrP state. The .li~ of the pore of memory m~tPri~l 36 is Lll~.Grol~i preferably less than about one micrometer so that the volume of the memory material 30 36 is limited, to the extent lithographically possible, to the volume of the m~tPri~l 36 which is actually switched between the various states of rP~ict~nre This further reduces the switching time and the electrical energy required to initiate the ~PtPct~ble change in rP~i~t~nrP The term "pore mP,ter" as used herein shall mean the lateral cross-sectirJn~l dimension of the layer of memory material 36 which extends under the contact regions formed with the memory layer 36 and with 35 the lower p+ layer and the upper con~uctors 42 as shown in the embodiment of Fig. 1. It is WO 94/24707 ~? I 5 8 9 ~ ~ PCT/US94/03953 further p,~;re ,cd that the pore regions of the memory PlPmPnt~ 30 be thPrm~lly isolated and/or controlled except for such electrical contact with the upper and lower electrodes as is nPcp~c~ry for proper operation of the memory Pl~mPnt~ This fur~her confinPs, limits and controls the heat transfer from the ~wilclled volume of the pore and the ~Plectric~l energy required for Lhe resi~t~nre 5 tran~ition~ This is ~ccomrli~hPd in the embodiment of Fig. 1 by the oxide layers 20 and 39 which surround the lateral pe,iphe,y of t-h-e memory çlPmPnt~ 30. Accordingly, in order to minimi7P set energy/ current/ voltage, small pore ~ mptprs of as low as 250 A may be employed.
The layers 32, 34, 36, 38 and 40 are etched and an oxide layer 39 is formed l}~ u~e, and etched to leave openings above the "le,llo,~ ÇlPmPnt~ 30 as shown. Al~.~t;vely, the memory 1 0 el~ i may be formed in a two step etch process with layers 32 and 34 being first de~siled and then etched over the top of which the rem~ining layers 36, 38 and 40 are depos;lP,d and then sep~r~t~ly etched to the selected ~limpn~icn Depo~iLd on top of the entire sLIu~;lule formed by layers 32, 34, 36, 38, and 40 is the second electrode grid structure fonned of ~ mimlm co...l.~ u,~
42, which extend perpP,nrlirul~r in direction to the co~ 12 and c~m~l~t~ the x-y grid 15 co.-n~u~icm to the individual memory Plp~ment~. Overlaying the c~rnrlçtç i.l~g-~t~d structure is a top ~nr~rslll~tin~ layer 44 of a suitable enr~r~ nt such as Si3N~ or a plastic m~tPri~l such as polyamide, which seals the ~llu~;lult against ",oislure and other extemal el~-"~ which could cause deterioration and d~gl~alion of pPrform~nr~ The Si3N~ enrarslll~nt can be dProsi~l, for example, using a low le~nl~"~ t; plasma ~lepo~ition process. The polyamide material can be spin 20 clepo~il~ and baked after deposition in accordance with known l~rl~ s to forrn the çnr~rslll~nt layer 44.
It is i,-,po,~" to note that conventional CMOS technology cannot be used to produce this type of three ~imPn~inn~l memory a ray since CMOS tpchnnlogy builds the requiredsemir~nr1uctor devices into the bulk of single crystal sçmicon~uctrlr wafers and, ll,e ~fu,e, can only 25 be used to fabricate a single layer of devices. r~ O~ ) CMOS cannot produce a small enough rooll.,h~l (actual element dimension) to cost effectively produce large arrays and (2) CMOS
devices, because they exist in a single plane, cannot be il.t~.c~ d along the Z direction.
The.~r(J,e, CMOS devices cannot be r~b ~ with the co--F~- . three-dimpnc;on~
illt~ ..neclivity required for a.lva.~ced parallel l"uc~ g co~ The three~
30 thin-film memory array ~LIu~;~ul~S of the instant invention, on the other hand are capable of both collvelllional serial inform~tion l"uce~ g as well as parallel infonn~tion proce~ing Parallel ~,uces~ing and therefore mlllfirlimencion~l memory array structures are required for rapid perfQrmance of compleY tasks such as pattern recognition, cl~c~sific~tion or ~cc~ori~tive learning etc. Further uses for and descrirtion of parallel p,uce~i,.g are p,~st;"led in U.S. Patent WO 94l24707 PCTIUS94/03953 21S8~ 28 No. 5,159,661 which- is ~ccignpd to the ~ccignPe of the instant arplie~tion and the ~icçlt~sllre of which is hereby inco-~-ated by r~Ç~,,cnce. With the integrated structure as shown in the emho~imPnt of Fig. 1; however, a comrl ~y vertically i~ lPd structure of the memory element and its ico1~ting diode is formed, thus minimi7ing the area oeeupiçd on the substrate by 5 each of the eombin~tionc of memory Plc"" ..l~ and diodes. This means that the density of the memory ~l~mPntC in the chip is limited eccçnti~lly only by the rPsoh-tion e~r~hilitiec of the lithography.
The Pmho~1;...l .~1 of Fig. 2 is the same as Fig. 1 except that a diode 27 is formed as a Schottky barrier o~.alively ~ osPd between the n layer 14 and a metal layer 29 which may be, 10 for eY~mplç pl~timlm silicide. In other respeets, the structural emho~limçnt of memory eelVicc-l~tion element depieted in Fig. 2 is formed in the same manner as that of Fig. 1 and like elPmPntC are labeled with like ~fc.~l-ee nllm~ralc The integrated structure thus form_d is an x-y lllclllul ~ matrix co....~ Pd as shown in Fig.
3 in which each Illelllol.y element 30 is cu,...Peled in series with a diode 26 between a hn,;~J.~
x-line 42 and a vertieal y-line 12. The diodes 26 serve to elpctr~ y isolate eaeh of the memory elPmPntC 30. Other eireuit eonfi~lratiQnc for the ele~,llic~lly erasable memory of the present invention are, of course, possible and feasible to F~ nent One partieularly useful eQnfig~ ion is a three J;--~ l, multilevel array in whieh a plurality of planes of ~ .llul,y or control çl~Pm~Pntc and their l~ e icol^tion devices are stacked upon one another. Each plane of memory ~lC~ 'l-; iS allat gcd as a plulality of rows and eolllmnc of lllC.IlOly cl .. l~, thereby allowing for X-Y addl~illg. This ~ts~lrj~ Of planes, in arl~1ition to hl~,~illg Ille.l,o.~ storage density, allows for an ~l(lition~l Z dim~n~ion of illk,~ ion This arrangement is particularly useful to cimnl~tP a neural networ~ for a 1ruly in~^lligçnt eo~ ut~ ..
Fig. 4 is a stylized, seh-Pm~tie cireuit diagram of a portion of the memory eell25 em~ho~imPntc of Fig. 1. The eireuit co"~lises an x-y grid with eaeh of the memory ~lt ...r.ll!i 30 being elPetrie~lly il~ ;u-~-e~ in series with an icol~ti- n diode 26 at the eross points of the x address lines 42 and the y address lines 12 as shown. The address lines 12 and 42 are ~JIlllP~
to extemal addressing cil.;uill~ in a manner well known to those skilled in the art. The purpose of the x-y matrix of memory ~1~ ".~ ; in cr,mh;n~tion with icnl~tirJn elPmPntC is to enable each 30 one of the discrete memory PlPmPntc to be read and written without ;..I~, rr~;~.g with inform~tion stored in adjd~ll~ or remote memory el~",- .l~ of the matrix.
In Fig. 5, there is diagr~mm~tir~lly i~ ctr~tpd a portion of a single crystal sPmicon-lvctnr ~u~llde 50 with a memory matrix 51 of the present invention formed thereon. Also formed on the same S~ A 50 is an addressing matrix 52 which is suitably c~ d by illl~ l.od 21S89~9 29 ' , ~;hC~liLIy CO~ Pcl;ollc 53 to the memory matrix 51. The addressing matrix 52 inrlllAes signal g~ elaLillg means which define and control the setting and reading pulses applied to the memory matrix 51. Of eourse, the addressing matrix 52 may be integrated with and formed cimlllt~np~ously with the solid state memory matrix 51.
S In prior art semir~n-hletor memories having the relatively high swi~.;l i.. g speeds and low switching energies deemed nece~ y for most ~pplic~tionc thereof, at least one transistor and a càpaeilur is re~luh~ed for eaeh memory plPmPnt The formation of sueh Ille---o-ies in integrated cireuit form requires at least three c4..~P~ rJnc along with other ~dAitirJn~l complexitips whieh oecupy a eertain minimum substrate area regardless of how the i~ gldled eireuit is laid ouL The 10 integrated circuit configuration of the electrically erasable memory of the present invention requires only two c4~ P~;Iir,nc to each memory element and these ean be made in vertiea rPl~finn~hip to each other. Further, each memory elPmP.nt, ComE!lpt~p with i~ tin~ diode and the pair of contacts for the Plpmpnt~ is itself fully vertieally integrated sueh that a signific~ntly higher bit density is possible. In fact, the ..-e---o-y of the present invention provides for a bit density 15 whieh is greater than that s~ hle even in solid state dynamie random aecess mPmorip~s (DRAMs), which are volatile and Lh.,..,rolt; lack the further advantages that the non-volatility a~lh;..~ e with the present invention provides. The inerease in bit density att~in^~l~ with the present invention t~ ncl~tps into a C4~ g rednction in m nllf:~t~l~ing costs because of the smaller areas of the wafer o. ~ per bit of the i..~.d~d circuit confi~ aLiOn. This allows the 20 memory of the present invention to c4~ e with and surpass other availaWe Ill~ )l;eS for a wider range of ~lic~tionc~ not only in terms of el~etric~l performanee and memory storage Ca~a~;ily, but also in terms of cost. By c~ p~;co~. with prior art sPmieQ~ ulnr memories formed of at least one tr~n~ictnr and a c ~lac ;lor for each bit, the integrated eircuit confi~lrations of the present invention, as shown in Fig. 1, can be formed on a chip with greater bit density co...~,d.~;d to prior 2~ arL config-. aLiollS using the same photo liLl.og~a~l~ic resc lufion In ~dAition to the cost advantages that the higher bit density affords, the rl~ ; are pc-~ifinnPd closer IJg~Lller and lead lengths, c~c;l~-.cçs, and otherrelated p~ are fur~her ...;..;...;~.,A, thereby çl-k~ ;..g performance Through experimPnt~tinn, the inventor has shown that factors such as pore AimPn~inn~
(Ai~metçr~ thi~lrnPcc, and volume), chalcogenide c~ os;lion~ thermal pl~palaLiOII (post deposition 30 anneal),signalpulseduration,i."l~",;l;Pssuchasoxygenpresentinthecol-ll)osilion,crystallitesiæ
and signal pulse waveform shape have an effect on the m~gnitllAe of the dynamic range of rçs, the a~solute end-point reci~t~nr~ of said dynamic range, and the voltages required to set the device at these rP~i~t~nrPs For example, relatively thick chalcogenide films (i.e. about 4000 A) will result in higher set voltage .~ui.t;...~ (and ll.t;.~rolc; higher current dPn~iti=Ps within Wo 94/24707 - ' PCT/US94/03953 2~ 30 the volume of memory material), while relatively thin chalcogenide layers (i.e. about 250 A) will result in lower set voltage (and current density) requirements. Of course, the possible signific~nr~
of crystallite size and, therefore, the ratio of the number of surface atoms relative to the number of buL~c atoms has previously been described.
S The signal pulse duration required to set the memory element to the desired rçcict~nr~
level within the dynamic range of electrical rrcict~nr,Pc will likewise be depçn~lrnt upon all of the Çor~gùillg factors as well as signal voltage. Typically signal pulse durations will be less than about 250 nanostco,~ds and preferably less than about 50 n~-~ .nsecQll~s. It is to be stressed that even the short 25 n~nncec~nrl pulse widths noted are dçpçnrlpnt on the size and shape of the pore as well as the thickness and composition of the semicond-lrtor alloy employed. It is believed that the pulse dl~r~tinns can be cignific~ntly leduced without h~.rt~ g with the operation of the rnemory switch. As a matter of fact, with the input of lesser ~mmlntc of energy, the cycle life of the ç~ can only increase.
A fçe~lb~r~ loop which reads and, when required, adjusts the rç~ re of a given memory element may be i-.cor~.dLed into the Illelllul,~ systems of the instant invention. For rle, a memory element may initially be set at a desired rÇc;ct~nre; ho~._ier, in time the l~ -.rc of the element may drift slightly from the value at which it was originally set. The f~F Ib~cL loop, in this inct~nr~. would ç~lrlll~te and deliver a refresh signal pulse of the r~uil~d voltage and dllr~tion to the memory element to bring it back to a plr~lF~1ed l~c:c,.~."~ value. Also, circllmCt~nrçs may exist where the set pulse deli-v.,,.,d to a Illelllol~ element may not result in setting of the element at the desired l~ - .re value. In this case the rc~back loop would deliver ition~l signal pulses to the element until the desired rç-cict~nr,e level is achieved. The total duration of this series of setladjust cycles is less than about 1,000 1~ .osec~ c and preferably less than about 500 ~ -os~c4l-llc The ability to reversibly move up and down the linear portion of the lc~ rG versus voltage curve cannot be o v ~re~ . .pl-~c; ~eA A signal pulse of a selected voltage will set the memory element to a desired reCict~nce~ reg~t~lr~C-c of the previous set con~itinn thereof. This ability to reversibly move along the curve provides for direct U~,lwli~e. of previously stored data. Such direct UVelWliLt; car~hility iS not possible with the phase change and MSM (a-Si) memory m~trri~lc of the prior art. This ability to reversibly set intrrmçAi~te rçcict~rlce values is rem~rk~hle A 1~ d succeccive S-volt pulses achieves the same l~;s~ e value as an 8-volt pulse followed by a single 5-volt pulse or a 4-volt pulse followed by a single 5-volt pulse.
The dynamic range of rÇcict~nrçs also allows for broad gray scale and multilevel analog memory storage. This multilevel memory storage is ~ccomplichrd by dividing the broad dynamic range into a plurality of sub-ranges or levels. This analog storage ability allows for multirle bits of binary inform~fion to be stored in a single memory cell. This multilevel storage is comr1i~hP-d by mimir~ing mnltirle bits of binary information in analog form and storing this analog information in a single memory cell. Thus, by dividing the dynamic range of reCict~nc~ps 5 into 3 or more analog levels, each memory cell would be provided with the car~hi1ity of storing 1 and l/2 or more bits of binary inft)rm~tion As in~ic~tpd hclc;nabo~/e, Fig. 6 is a ternary diagram of the Ge-Te-Sb sçmicond~1ctor alloy system. In ~ddition to the information previously ~ Cus~P~d of which the binary and ternary phases are infiic~tP~d by squares (--), this diagram gives inform~tion on the segl~,gaLion of other alloys.
10 These other alloys are inrlir~atpd by triangles (-), diamonds ( ) and circles (--) and the phases into which the alloys segl~g~LG, upon rapid so1i~ifi-~fion from the melt, are indi~ ~tPd by the lines (solid or dashed) which extend th~ Grlulll. The starting compo,sifionc of two Te-rich melts are inriicat~pd by circular symbols on the ternary ~ia~m Upon rapid so1i~iifi~fir~n~ these Illh~lulGs phase se~ aLG into elpm~pnt~l Te plus phases B, C and D.
Melts with colllposilions to the right of the pseudobin~u~ line, in~ic~tPd by t~i~monti symbols, solidify into the phases inrlir~ted by the lines on the diagram. Othemllh~lulGs, in~ tPd by triangles in the phase ~lia~m, solidify into e1PmPnt~1 Ge and Sb and into phase A. Phase A
is found in the rapid solitiific~ticm of all melts where the co~ os;l;on of the melt is close to that of phase A, an also in the co~ ;lion~ in~ir~tPd by the triangle symbols on the diagram. A
20 molten mixture of conll)o~ilions id-Pnti~ ~1 to that of phase A forms nearly pure phase A upon rapid s~ ific~tion This phase is the only phase which shows this clldla~ tic An alloy of particular interest for use in the improved memory el~'llr~; of the present invention is Ge22Sb22Te56, also referred to as Ge2Sb2Te5 or 2-2-5. This 2-2-5 alloy, upon rapid scli~ific~tir~n~ phæe s;g-~gat~s into a mixture of two distinct phases of c4...l.0~iliol-C B (Ge26Sbl8Te56) and C (Gel"Sb26Te56) indicated in the phase diagram of Fig. 6. Another alloy of particular in~erest is Gel"Sb29Te57 ( also referred to as GeSb2Te~ or 1-2 4) which is c~..po~ on D on the GeTe-Sb2Te3 pse~dobin~ry line.
The 2-2-5 and 1-2 4 alloys are of interest for forming the volume of memory m ~1 in c~ ic n~lly graded, layered or combin~ graded~ayered form, as d;~ ~d ~.G~-Iabu~re.
Fig. 7 depicts the atomic structure of three temary alloys of the Ge-Sb-Te system as well 30 as the atomic ~LIUCLUIG of the binary alloy Ge-Te. Two of the three ternary alloys are the 1-2-4 (c~...lo.~;l;on D on the ternary diagram of Fig. 6) and the 2-2-5 co~ro~-l;on~ ~escnbe~
helGillabo~/e~ The third temary alloy is Ge8Sb33Te59 which is also referred to as GeSb4Te7 or 14-7.
This 14-7 alloy ~ll~nds to c~ os;l;on E on the temary phase diagram of Fig. 6. In the deriction~ of the atomic structures of these alloys, the hollow circles ~ S~ Ge atoms, the ~o9~ ~ --Wo 94/24707 . PCT/US94/03953 striated circles IG~llG~tll~ Sb atoms and the stippled circles depict Te atoms. As shown by Fig. 7, the atomic confi~lration of each of the alloys, when in the face centered cubic crystalline structure, is formed of ordered, repeated layers of atoms. The fcc configuration form three distinct types of layers which are labeled A, B and C in Fig. 7.
S The 1-4-7, 1-2-4, and 2-2-5 alloys d~Ppict~P~ in Fig. 7 are of interest as base memory materials and for use in the PlPmPnt~lly modifip-d memory materials of the instant invention. The tr~ncition metals, along with Se, when present, are incol~,uldted relatively uniformly throughout the Te-Ge-Sb matrix and enhance the electronic/atomic structure so as to produce reduced ~wik;l~illg current requirements and il,c,~dsed thermal stability of data retPntiQn Current analysis shows that the Se replaces Te in the structure, and while the exact pocitioning of the transition metal is not known, it appears that the transition metal bonds with the chalcogen Plempnt Also, as mPntirJn~Pd hereinabove, when the Ge-Sb-Te alloy m~teri~lc are clepQcit~pd by evaporation onto a heated substrate, the m~tP i~lc are depositPA in anisotropic form. That is, when dep~ Pd in this fashion, the crystallites of the alloy materials are oriented such that the layers of 15 CIJ~ atomic cl~ rl~ are aligned S~ 11Y parallel to the ,.~bs~ surface. This will, of course, result in anisotropic current flow, but offers the long term possibility of arrdnging the atoms of the material so as to employ set and reset pulses in the low ,~ .ce direction and thereby achieve still lower set and reset currents, voltages and/or energies.
Most recently, the instant in~ have ~etermin~pd that memory el~ e~ of the instant invention which employ a fil~mPnt collr~ g means between at least one of the spacedly dicposed electrodes and the volume of memory material provides for memory elpmpntc with better thermal stability, lower setlreset current ,~quirG~ents, longer cycle life, and a larger dynamic range of l;,,.rfc In these el.omPntc"~ wi~l.illg appears to occur in a fi1~m~Pnt~ry portion of the volume of II~.lluly material and the fil ..~ y portion appears to be affected by the fil~mPnt 25 co..r..i.-~ means. Typically the fil~mPnt w..ri..i.,~ means is a thin film layer di~ osf~ between one of the spacedly licrosed contacts and the volume of memory m~teri~l and plGrGlably this thin-film layer is between 10 and 100 Angstroms thick. This thin film layer is formed of highly resistive m~teri~l and has at least one low re~ict~nre ual~ vay ~lelGaCIu~S, through which electrical signals pass between the contact and the volume of memory m~teri:~l The area of the low 30 re~ re palllway in the highly resistive thin film layer may be less than about 2 percent of the area of contact between the thin film layer and the volume of Ill~"lloly m~t~ri~l An eY~mrls~ry thin film layer is formed of a material which inrll-~es carbon, fluorine, oxygen, silicon and llydlugcn. The co...l osilion of this film is p~rGlably, in atomic percent, between about 60-70%
carbon, 20-30% fluorinto, and 3-10% oxygen, 0.5-2% Si and the rem~in~er H and other impuritie~

WO 94/24707 215 8 9 ~ 9 PCT/US94/03953 Fig. 8 is a graphical depiction of data illustrating cycling r~ c~ ;ctirs of a memory element without the fil~ nPnt c~nfining layer of the present invention. In this graph, device rç~ict~nre is plotted on the ordinate and cycle number is plotted on the ahsc;~c~ The data was created by cycling the memory element in binary fashion using 400 nsec, 2 Volt pulses to set the 5 material to a "low" recict~nre and 40 nsec, 6 Volt pulses to set the material to a "high" .~ ce As can be 1etenninpd from this figure, the dynamic range of recict~nre is relatively small, 20k ohms at best falling to lOk ohms near device breakdown. Also, the device has a relatively short cycle life, less than 1 x 104 cycles, and the cycling current is relatively large (i.e. 400 nsec set pulses).
Fig. 9 is a graphical depiction of data illustrating multistate c~l ilitiPs (i.e. ability of the memory element to be set to m-lltiple ,~s;~ ,e levels within the dynamic range of l~s~ .~s) of a memory element without the fil~ment c~nfinin~ layer of the present invention. In this graph, device re~ict~nr~P is plotted on the ordinate and set pulse voltage is plotted on the ~hScic~ The data was created by pulsing the memory element with 200 nsec set pulses of varying voltage from 1 to 10 volts. The memory element was pulsed with 10 pulses at 1 volt and the device GC ~Ih~re was measured. The voltage was il~.~iased to 2 volts and another 10 pulses were applied, again the device .e~ -.re was me~c~lrPA The voltage was in~,.G ~ ~t~ d in this manner up to lO volts.
This test was ~ ~ r~ cd 10 times (i.e. ten sets of ill~;~G~ on from 1 to 10 volts). A pemsal of this figure clearly inAir~tP5 that this memory element which lacks the fil~mpnt cG~r~ g layer does not exhibit ~ l;cl~ l')ilitiPC
Fig. 10 is a ~ hical depictir,n of data illu~ ~hlg cycling .,l~ ;cs of a IllC.
element without the fil~ nPnt c4~r~ layer of the present invention. In this graph, device r.,c;~ ,re is plotted on the ordinate and cycle number is plotted on the ~sei5c~ The data was created by cycling the memory element in binary fashion ucing 200 nsec, 1.8 Volt pulses to set the m~t~ri~l tO a "low"
rP~ict~nre and 100 nsec, 6 Volt pulses to set the m~tPri~l to a "high" l~ .rf. As can be dPtPrmimPd from this figure, the dynamic range of l~ -.ce is t~ .lldy small, 2k ohms at best falling to less than 100 ohms near device breakdown. Also, the device has a relatively short useable cycle life, less than 1 x 10~ cycles.
Fig. 11 is a ~ hical depiction of data illu~Lld~lg m~lltict~te c~r~biliti-ps (i.e. ability of the memory element to be set to mllltiI)le recict~nc~ levels within the dynamic range of l~2:~lh .rf,s) of a memory element without the fil~mPnt c~l~r~ g layer of the present invention. In this graph, device l~:clh.-r~ is plotted on the ordinate and set pulse voltage is plotted on the ~i-scisc~ The data was created by pulsing the memory element with 200 nsec set pulses of varying voltage from ~ ~ r WO 94/24707 ~ ~ f PCT/US94/03953 1 to 6 volts. The IIIGIII(JI,~/ element was pulsed with 10 pulses at 1 volts and the device reCict~nre was measured. The voltage was increased to 1.56 volts and another 10 pulses were applied, again the device recict~nre was measured. The voltage was hl~ ed in this manner up to 6 volts This test was performed 7 times (i.e. seven sets of incrPmçnt~tion from 1 to 6 volts). A perusal S of this figure clearly inriic~tps that this memory element which lacks the fil~mPnt cQnfining layer does not exhibit ml-ltict~tP abilities.
Fig. 12 is a graphical depi(tion of data illustrating cycling ~ha.a. Ir,;cficc of a memory element with the fil~mçnt confining layer of the present invention. In this graph, device reCict~nre is plotted on the ordinate and cycle number is plotted on the al~scic~ The data was created by cycling the memory element in binary fashion using 100 nsec, 1.8 Volt pulses to set the material to a "low" ~ c~ e and 40 nsec, 5 Volt pulses to set the material to a "high" ~ .ce As can be dçtPrmin~-d from this figure, the dynamic range of l~ Ul G for this device is relatively large, in the range of 1.~1.2 megohms. Also, the device has a relatively long cycle life, at leact greater than 1 x 105 cycles (similar devices have been tested to 1 x 107 cycles and more), and the cycling 15 current is relatively small (i.e. 100 nsec set pulses).
Fig. 13 is a gla~l..cal depictinn of data illu:,L~lillg mllltict:-tç C~ iti~s (i.e. ability of the memory element to be set to mlllfipl^ ,e~ e levels within the dynamic range of ~ ~s) of a memory element with the fil~mPnt c4.~ ;ug layer of the present hlvGIllioll. In this graph, device IG~;Cl:'~r-e iS plotted on the ordinate and set pulse voltage is plotted on the ahscicc~ The 20 data was created by pulsing the Ill~llOl~ff element with 200 nsec set pulses of varying voltage from 2.5 to 6.5 volts. The nlGlllOI,~f element wæ pulsed with 10 pulses at 2.5 voltc and the device ,e~ re was ll-ca~unGd. The voltage was ill~lGasGd to 2.83 volts and another 10 pulses were applied, again the device ~ e was ,.-easu,Gd. The voltage was ill~,lr.~ lled in this manner up to 6.5 volts. This test was ~,. ru....Pd 10 times (i.e. ten sets of incremPnt~tiQn from 2.5 to 6.5 25 volts). A perusal of this figure clearly indir~t~o~s that the ",c."o,~ çlçmpnts which have this fil^ n~ont confining layer exhibit clear stable ~nllltict~tP, ~hilitiçs~
The dirf~,~,lcc bGL~ the ",~".o.~ rl~ ...~.,1~; of Figs. 8, 9, 10 and 11 and that of figures 12 and 13 is that the former memory PlPm~ntc lacks the fil~mPnt c~nfining layer of the instant invention. This layer lies belwæn at least one of the elect~des and the volume of memory 30 material. The layer appears to define the size and position of the recict~n~ switching fil~
portion of the volume of memory m~tcri~l during çlçctrir:ll formation of the memory element and to limit the size and to confine the location of the fil~mt~nt~ry portion during use of the memory ehPmPnt, thereby providing for a high current density within said fil~mçnt~ry portion of said single cell memory element upon input of a very low total current electric~l signal to said spacedly disposed contacts.
Electrical formation of the memory element consists of applying high voltage electrical pulses to the newly co~ uuled memory element which "forms" the element for subsPqu~Pnt low 5 voltage elPctric~l cycling. Typically the forming process involves applying elPctric~l pulses of increasing voltage until the memory element switches from its originally very high "virgin"
rPcict~nre value to a low ~c;~l~ .re value. The as-depocitP~d fil~mPnt confining layer is highly resistive. During the form~tion process the fil~mPnt confining layer is subjected to mnltirle high voltage EMF pulses. During one or more of these pulses, the elecL,iCa]ly ~ ' (defect) point 10 in the confining layer is physically ch~ngP~I Thereafter, this point is much more highly conductive than the rPm~inri~Pr of the layer and is the point through which all of the current of any s~lhse~ oly cycling pulses (i.e set and reset pulses) will pass. The.efol~, this rh~rlgPd region created at the defect point within the confining layer defines the size and position of the h-~ce ~wik:hillg fil~mPnt~ry portion of the volume of memory m~teri~l during electric~l 15 fr~nn~tion of the memory PlPmPnt Also, since the defect point in the c~-.ri..;-l~ layer is fixed in size and lnc~tion and does not move or grow in size throughout low current memory s~vilcllil~g, it acts to limit the size and to confine the location of the fil_...~ / portion during use of the e.lloly elPmPnt This ultra small lc;-:~lh-~c s..iLellillg fil~ lh.y portion allows for a high current density within said filhl~ lh~y por~ion of said single cell memory element upon input of 20 a very low total current PlPctrir~l signal to memory element since all of the current is ul.~ d 11llUU~1L
Thecc..l.;l...lion/e~ -reofthefil~mPntc~nfininglayerwasdiscoveredwhiletheinstantillVC;ll~ were invç~tig~fing memory cl~ wh~ich did not contain carbon layers adj~r~Pnt the chalcogenide Ill~llUly m~teri~l It was noted that many of the memory PlPmPnt~ without the 25 carbon ele~llude (but with differing metal electrodes) did not show the de~i,uus cha~ cs of those with the carbon layers (~lthnugh some did). Therefore, the carbon layers themselves were inve~tig?~P(l The investig~tirJn of the carbon layers showed that, alone. the carbon could not have provided the extremely high initial l~ lh-.re of the memory Çl~PmPnt~ This ~,u"lpled the ill~.,nk~l~ to investigate the i. .~P. r~rP~ between the chalcogenide and the carbon. During pro~uctinn, 30 a SiN,~ layer is depositpd onto the lower carbon layer. A pore in this SiN,~ layer is then opened into which the chalcogen memory material is deposited. The pore is typically created by m~ ing the SiN" layer with photo resist and dry etching the SiN,~ with CF4 to form a pore the~e~ uugh.
After the pore ~or via) was opened, Auger Profiling Analysis was preformed on the CF4 carbon layer and on non-etched carbon. The analysis of the non-etched carbon infiir~tes the presence of Wo 94/24707 2~ PCT/US94103953 carbon, oxygen, nitrogen and silicon. See the Auger Electron Spectroscopy analysis of Fig. 14.
The analysis of the CF4 etched carbon layer int1icqtes the same elçmpntc plus fl~lorinP See the Auger Electron Spectroscopy analysis of ~ig. 15. This fluorine "cont~minq-tion" was found to a depth of between 20 and 40 angstroms depending on etch tLm--e. X-ray photoelpctron Spectrum 5 (XPS) analysis was used to d~;e the surface cQ~cçntration in atomic pclce.lLage at the surface of the dry-c~ ed carbon. Carbon was around 67~o and fluorine was about 26%. r To det~ if this fluorine UJ~ ;u;~ layer is the "fil2mPnt col~r~ layer", a wet etch of buffered HF was used to open the pore in the SiN%, all other production process steps were held conctq-nt Auger profiling showed that this wet etched carbon sample contqin-Pd no flurJrinP~ See 10the Auger Electron SpeL;L.usco~ analysis of Fig. 16.
In q~riitiQn to the wet etch e~ l, the normal CF4 dry etch was used to open the pore in the SiN,~, Ll~eafLcr, the carbon was etched with argon plasma, all other yl~J~ process steps were held cc..!~l ,l XPS showed that the wet etched carbon cul~ Pd 84.2 at.% carbon, 8.9%
oxygen, 4.8% fll-s)rinP, 1.7Yo lliLIugell, and 0.4% silicon.
15The elPct-irql .,h~ae~.i~Lics of the wet etched memory el~pm~pntc are presented in Figs. 8 and 9. The elprtrirq-l ClI~ua~;L~ ics of the ..-c---o-y elPmf ntc which were dry etched with CF4 and then argon plasma post etched are ~I~,s~.-ted in Figs. 10 and 11. While the elP~trirql c~ u~ tics of the dry etched memory element are pn,~..~t~,d in Figs. 12 arld 13. It is clear that the high CC~ ;on fluorine cn-~ e layer at the interfvr~p between the chqlrogen:~le memory 20 material and the carbon electrode is the "fil~ f.~ y portion c4~ g layer" and that this layer provides the memory PlPmPntc of the present invention with their superior elf~;LIi~,dl properties.
Through the use of the proprietary materials and device configurations ~1isclns~pd herein, an elPctricqlly erasable, directly u~e~ iL~ble -I~,..-O-~ element has been developed which provides fast read and write speeds, a~-ua~ i--g those of SRAM devices; non-volatility and random access 25 reprogramming carq-hilihes of an EEPROM; and a price per megabyte of storage that a~",-uaclles that of hard disk ...~"-.o. y.
It is possible that the r~qmificqtinnc of the free charge c~ alion mnJdlllq~i~n cqp-qhilitiçs of the mqtPriqlc of the present invention will have econc)mir- impact in the field of spmir~onrlllctor devices. As detailed in the bac~ruu-.d section above, the charge carrier morhllqtion (licclosp-d 30 herein Ic;~lesellL~ a fifth type of charge carrier mod~llqtion, one that ~ s~ lL~i a f mdqmPntql de~.Lu-~; from the prior arL Simply stated, in the mqteriqlc of the present invention, even after removal of the field, the Fermi level position~ the elPctric~l co~-luctivity~ and the co~ .l.alion of free charge remain fixed. Thus, it becom~s possible to build either a new class of semiconductor devices in which three termin~lc or two termin:~ls can be employed and the device is ~89~9 preprogrammed to presPl~octed values of electric~l resistivity. In either event, the programming voltages and/or currents are rem~ hly low and the reaction speeds are r~m~ hly fast. This is because the semic~n~iuctor m~trri~lc of the prsent invention have hlh~ speed and energy car~l-iliti~s resulting from mod~ tion that occurs within one or more different crystalline phases.
S Note that, as should be appa-c.1l from a perusal of the subject speçifir~tion, we are able to see a trend in perfo~nre of the memory elementc that is generally related to pore di~meter.
When we use devices in the binary mode, we see a general increase in the off-to-on reci~t~nce ratio as we test devices across a wafer in which pore ~ meters range system~ r~lly from just over one micron to not open at all. If the pore ~ meter is controlled within the range of, for .oy~mple~
from one micron to less than one half of a micron, there is an Op~1Lu1~iLy to improve the perform~nre of our devices. Since voll-mPtric factors such as current density and energy density are ;~po~ in the progr~mming of our devices, r~llctirJn in device volume, resulting from red~ctinn in pore ~ m~tpr~ should ~esult in an increase in sensitivity and speed.
There is a threshold ~wiL~ g voltage ~csori~ted with the p.u~ g of the Ovonic EEPROM and, Ll~ , one expects that, like threshold swi~lles, the Ovonic EEPROM
p1ug1a.1m~i11g voltage will show a ch~lc-ogen;de alloy film th;r~n~cs d~ .d~.re In fact, in the Ovonic EEPROM, a threshold ~wiL~l.h.g voltage serves to separate read events from p-u~ .g events, Pl;...;..~ read upset and providing good opc~;n~ margin during data reading. Our devices show linear ,~ c~ hala~;L~ LiCS when the applied field is low, followed by a gradual 20 decrease in re~ict~nre with h~c1~asing field, up to a threshold voltage. Once the threshold voltage is exceeded, the device exhibits a negative re~ict~nre ~ ;u.- to a highly con~ ctive~ "dynamic on" state. When the applied field is removed, the device returns to a non-volatile p1ugl~llllled .re state, the value of which depon~ic on the currentlenergy profile the device has e~reriPnced during its "memory eql~ilibr~tion time" while in the dynamic on state. ~lthnugh the 25 threshold voltage depends on the r~ -ce of the device, the device current at the threshold voltage is relatively CQ~ I for all device Ir~ s. A linear app1~Ai---ation to the thiclrnr,sc, threshold voltage rel~ionchir~ shows a proportionality factor of less than one, which contributes to a wide operating margin in devices having the same nnmin~l thirL-necc It is to be nn(ier,stood that the dicclcs~re set forth herein is ~,1.,senled in the form of 30 detailed embo~ desc~ibed for the purpose of making a full and cc l ~f dic( lns~~re of the present invention, and that such details are not to be il1~ 1r~ed as limiting the true scope of this invention as set forth and defined in the arpentied claims.

Claims (20)

We claim:

1. An electrically operated, directly overwritable, multibit, single-cell memory element comprising:
a volume of memory material defining a single cell memory element, said memory material characterized by (1) a large dynamic range of electrical resistance values, and (2) the ability to be set at one of a plurality of resistance values within said dynamic range in response to selected electrical input signals so as to provide said single cell with multibit storage capabilities;
a pair of spacedly disposed contacts for supplying said electrical input signal to set said memory material to a selected resistance value within said dynamic range;
at least a filamentary portion of said single cell memory element being setable, by said selected electrical signal to any resistance value in said dynamic range, regardless of the previous resistance value of said material; and a filamentary portion controlling means disposed between said volume of memory material and at least one of said spacedly disposed contacts, said means defining the size and position of said filamentary portion during electrical formation of the memory element and limiting the size and confining the location of said filamentary portion during use of the memory element, thereby providing for a high current density within said filamentary portion of said single cell memory element upon input of a very low total current electrical signal to said spacedly disposed contacts.

2. The memory element of claim 1, wherein said filamentary portion controlling means comprises a thin film layer disposed between one of the spacedly disposed contacts and the volume of memory material.

3. The memory element of claim 2, wherein said filamentary portion controlling means comprises a thin film layer of between 10 and 100 Angstroms thick.

4. The memory element of claim 2, wherein said filamentary portion controlling means comprises a thin film layer of highly resistive material containing at least one low resistance pathway thereacross, through which input electrical signals pass between said spacedly disposed contact and said volume of memory material.

5. The memory element of claim 3, wherein said filamentary portion controlling means comprises a thin film layer formed of C, F, O, Si and H.

6. The memory element of claim 5, wherein said filamentary portion controlling means comprises a thin film layer formed of, in atomic percent, between about 60-70% carbon, 20-30%
fluorine, and 3-10% oxygen, 0.5-2% Si and the remainder H and other impurities.

7. The memory element of claim 1, wherein the memory material forming said volume of memory material is selected from the group consisting of Se, Te, Ge, Sb and mixtures or alloys thereof.

8. The memory element of claim 7, wherein said memory material includes Te, Ge and Sb in the ratio Te a Ge b Sb 100-(a+b) where the subscripts are in atomic percentages which total 100%
of the constituent elements and 40 ~ a ~ 58 and 8 ~ b ~ 40.

9. The memory element of claim 7, wherein said memory material further includes one or more elements selected from the group consisting of Cr, Fe, Ni, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof.

10. The memory element of claim 7, wherein said volume of memory material includes a varied positional composition within said volume of memory material which substantially stabilizes the resistance of said material at a selected resistance value and said volume of memory material adapted to remain set at said selected resistance value without drift after the input signal has been terminated.

11. The memory element of claim 10, wherein said varied positional composition includes compositional grading of said volume of memory material.

12. The memory element of claim 10, wherein said varied positional composition includes compositional layering of said volume of memory material.

13. The memory element of claim 10, wherein said varied positional composition includes compositional grading and compositional layering of said volume of memory material.

14. The memory element of claim 11, wherein said compositional grading includes a composition of Ge14Sb29Te57 graded to Ge22Sb22Te56.

15. The memory element of claim 12, wherein said compositional layering includesdiscrete layers of Ge14Sb29Te57 and Ge22Sb22Te56.

16. The memory element of claim 13, wherein said combination of compositional layering and compositional grading includes a layer of Ge22Sb22Te56 and a graded composition of Ge14Sb29Te57 and Ge22Sb22Te56.

17. The memory element of claim 13, wherein said combination of compositional layering and compositional grading includes a layer of Ge14Sb29Te57 and a graded composition of Ge14Sb29Te57 and Ge22Sb22Te56.

18. The memory element of claim 1, wherein said volume of memory material and said contacts are formed so as to define a matrix array of thin film material; each memory element in said array being addressably isolated from other memory element in the array by thin film isolation devices.

19. The memory element of claim 18, wherein the combination of thin film memory elements and isolation devices define a three dimensional, multilevel array of discreetly addressable high density memory cells.

20. The memory element of claim 1, wherein said volume of memory material is operatively disposed in a pore of less than about 1 micron.