CA2175133C - Digital phase-locked loop (pll) - Google Patents
Digital phase-locked loop (pll) Download PDFInfo
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- CA2175133C CA2175133C CA002175133A CA2175133A CA2175133C CA 2175133 C CA2175133 C CA 2175133C CA 002175133 A CA002175133 A CA 002175133A CA 2175133 A CA2175133 A CA 2175133A CA 2175133 C CA2175133 C CA 2175133C
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
- H03L7/0993—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
Abstract
Using positive-phase or negative-phase clocks of phase count clock Pf0, a number M of multilevel quantized phase comparators output as values quantized in multiple levels the phase differences of output signals outputted from first and second N-stage frequency dividers wherein input clocks and output clocks, respectively, of a digital PLL have been N-stage frequency divided and moreover, divided into M
groups. An adder adds this phase difference information and outputs advanced pulses or delayed pulses. An N1 counter counts up in response to advanced pulses and both outputs an increment pulse and undergoes setting to initial value N1 upon counting up to 2N1. In response to delayed pulses, the N1 counter counts down, and upon counting down to "0" both outputs a decrement pulse and undergoes setting to initial value N1.
groups. An adder adds this phase difference information and outputs advanced pulses or delayed pulses. An N1 counter counts up in response to advanced pulses and both outputs an increment pulse and undergoes setting to initial value N1 upon counting up to 2N1. In response to delayed pulses, the N1 counter counts down, and upon counting down to "0" both outputs a decrement pulse and undergoes setting to initial value N1.
Description
zt~~f~~
DIGITAL PHASE-LOCKED LOOP (PLL) BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a digital phase s locked loop (PLL) used in a cell decomposition circuit in an ATM or stuffing synchronization device.
DIGITAL PHASE-LOCKED LOOP (PLL) BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a digital phase s locked loop (PLL) used in a cell decomposition circuit in an ATM or stuffing synchronization device.
2. Explanation of the Related Art:
In a digital PLL of the prior art in which two N-stage frequency dividers are added to the first stage of a digital PLL, an input signal is inputted to an input of one N-stage frequency divider and the output signal of .the digital PLL is inputted to an input of the other N-stage frequency divider, and following N-stage frequency division of each of the signals, the signals are inputted to a multilevel quantized phase comparator. .
Fig. 1 is a block diagram of a prior-art digital PLL. A digital PLL input clock Fin and output clock foot are inputted to first and second N-stage frequency dividers 11 and 12, respectively, and subjected to N-stage frequency division. Multilevel quantized phase comparator 13, which is driven by phase comparator clock Pfd, inputs the output clocks of N-stage frequency dividers 11 and 12 and outputs output phase error information (advanced pulses or delayed pulses) ~1~5133 indicating the phase advance/phase delay of both output clocks. N1 counter 14 is a competitive counter which inputs the advanced pulses or delayed pulses, counts up in response to advanced pulses, and upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1. N1 counter 14 counts down in response to delayed pulses, and upon counting down to "0," both outputs a decrement pulse and undergoes setting to initial value N1. Frequency regulator 15 is driven by the standard drive clock Rf0 of the digital PLL, and clears one pulse from the pulse train of standard drive clock Rf0 when one increment pulse is generated from N1 counter 14 and adds one pulse to the pulse train of standard drive clock Rf0 when one decrement pulse is generated from N1 counter 14. R-stage frequency divider 16 effects R-stage frequency division upon the output of frequency regulator 15 and outputs the output clock fout of the digital PLL.
In the above-described prior-art digital PLL, however, because the input to multilevel quantized phase comparators is N-stage frequency divided by N-stage frequency dividers, phase comparison is effected 1/N times that of a case in which N-stage frequency dividers are not employed. In other words, the gain of the switching network is reduced to 1/N, phase error information obtained per second drops to an insufficient level, and unwanted fitter (variations in phase) is generated.
Furthermore, if half-clock control is selected for controlling the frequency regulator of the digital PLL, there is the further drawback that half-clock phase error cannot be detected in the phase comparator because the sampling interval of phase error detection in the phase comparator is 1 clock.
SZTMMARY OF THE INVENTION
The object of the present invention is to provide a digital PLL in which half-clock phase control carried out in the frequency regulator can be detected in the phase comparator, and moreover, which prevents a drop in gain of the switching network and prevents the occurrence of unwanted fitter.
To achieve the above-described object, a digital PLL
according to the present invention includes:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL and generates N
clocks of a first phase, a second phase, ... , and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
A
' 21751 33 first multilevel quantized phase comparison means that inputs an arbitrary output signal of the first group of first N-stage frequency dividing means and an arbitrary output signal of the first group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels;
second multilevel quantized phase comparison means that inputs an arbitrary output signal of the second group of first N-stage frequency dividing means and an arbitrary output signal l0 of the second group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; ...; and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of the Mth group of first N-stage frequency dividing means and an arbitrary output signal of the Mth group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized A
x175133 in multiple levels;
adding means that adds phase difference information outputted from the M multilevel quantized phase comparison means and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay;
N1 counting means that is a competitive counter that inputs the advanced pulses or the delayed pulses, counts up in response to the advanced pulses and, upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1; and that counts down in response to the delayed pulses, and, upon counting down to "0," both outputs a decrement pulse and undergoes setting to initial value N1;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of the standard drive clock when one increment pulse is generated from the N1 counting means, and adds one pulse to the pulse train of the standard drive clock when one decrement pulse is generated from the N1 counting means; and R-stage frequency dividing means that R-stage frequency divides the output of the frequency regulating means and outputs an output clock of the digital PLL;
wherein, of the M multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
An N-order digital PLL of the present invention includes the above-described digital PLL.
Another digital PLL according to the present invention includes:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, and an Nth output clock, respectively, divides these N clocks into M
groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of the first A
group of first N-stage frequency dividing means and an arbitrary output signal of the first group of the second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; second multilevel quantized phase comparison means that inputs an arbitrary output signal of the second group of first N-stage frequency dividing means and an arbitrary output signal of the second group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; ...; and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of the Mth group of first N-stage frequency dividing means and an arbitrary output signal of the Mth group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels;
N1 counting means which are competitive counters provided corresponding to each of the M multilevel quantized phase comparison means and which input advanced pulses indicating phase advance or delayed pulses indicating phase delay outputted by the respective multilevel quantized phase comparison means, count up in response to the advanced pulses and, upon counting up to count value 2N1, both output an increment pulse and undergo setting to initial value N1; and that count down in response to the delayed pulses, and, upon counting down to "0", both output a decrement pulse and undergo setting to initial value N1;
adding means that adds increment pulses or decrement pulses of the M N1 counting means and outputs pulses of advanced phase or delayed phase;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of the standard drive clock when one pulse of advanced phase is generated from the adding means, and adds one pulse to the pulse train of the standard drive clock when one pulse of delayed phase is generated from the adding means; and R-stage frequency dividing means that R-stage frequency divides the output of the frequency regulating means and outputs an output clock of the digital PLL;
wherein, of the M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
An N-order digital PLL of the present invention includes the above-described digital PLL.
By employing multiple multilevel quantized phase comparison means, the phase error information obtained in one second can be increased M-fold and the system again can be increased M-fold.
Moreover, generated phase fitter can be reduced because accurate z~~5~33 phase error information can be obtained.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based with references to the accompanying drawings which illustrate examples of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram of one example of a digital PLL of the prior art;
Fig. 2 is a block diagram of a digital PLL according to the first embodiment of the present invention;
Figs. 3, 3A, 3B and 3C are waveform charts illustrating the operation of the digital PLL according to the first embodiment;
Fig. 4 is a block diagram showing an N-order digital PLL
including a digital PLL according to the first embodiment;
Fig. 5 is a block diagram showing a digital PLL
A.
according to the second embodiment of the present invention; and Fig. 6 is a block diagram showing a N-order digital PLL including a digital PLL of the second embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to Fig. 2, a digital PLL according to the first embodiment of the present invention is composed of a first N-stage frequency divider 1, a second N-stage frequency divider 2, M multilevel quantized phase comparators 3-1 to 3-M, an adder 4, an N1 counter 5, a frequency regulator 6, and an R-stage frequency divider 7.
First N-stage frequency divider 1 N-stage frequency divides input clock fin of the digital PLL, generates first phase, second phase, ..., and Nth phase clocks synchronized with the first input clock, the second input clock, ..., and the Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs the result.
Second N-stage frequency divider 2 N-stage frequency divides output clock foot of the digital PLL, generates first phase, second phase, ..., and Nth phase clocks synchronized with the first output clock, the second output clock, ..., and the Nth output clock, 2»5133 respectively, divides these N clocks into M groups (N>M), and outputs the result.
Multilevel quantized phase comparator 3-1 inputs an arbitrary output signal of the first group of first N-stage frequency divider 1 and an arbitrary output signal of the first group of second N-stage frequency divider 2 and outputs the phase difference between the two output signals as a value quantized in multiple levels. Multilevel quantized phase comparator 3-2 inputs an arbitrary output signal of the second group of first N-stage frequency divider 1 and an arbitrary output signal of the second group of second N-stage frequency divider 2 and outputs the phase difference between the two output signals as a value quantized in multiple levels. Multilevel quantized phase comparator 3-M inputs an arbitrary output signal of the Mth group of first N-stage frequency divider 1 and an arbitrary output signal of the Mth group of second N-stage frequency divider 2 and outputs the phase difference between the two output signals as a value quantized in multiple levels. Here, multilevel quantized phase comparators of odd ordinal numbers count input phase differences at the rising edge of phase comparison (sampling) clock PfO, and multilevel quantized phase comparators of even ordinal numbers count input phase difference at the rising edge of sampling clock Pf0 which is 180° out of phase with the sampling clock PfO.
By using sampling clocks of both positive phase and negative phase in this way, sampling accuracy can be doubled as compared with using only a positive-phase sampling clock, and half-clock phase difference can be detected.
A
Adder 4 adds the phase difference information outputted from the M multilevel quantized phase comparators 3-1 to 3-M and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay. When input is of differing phase (increment and decrement), a value for the difference can be obtained.
N1 counter 5 is a competitive counter that inputs advanced pulses or delayed pulses, counts up in response to advanced pulses, and upon counting up to a count value 2N1 (a positive integer), both outputs an increment pulse and undergoes setting to initial value N1. In response to delayed pulses, N1 counter 5 counts down, and upon counting down to "0", both outputs a decrement pulse and undergoes setting to initial value N1.
Frequency regulator 6 is driven by standard drive clocks Rfp of the digital PLL, eliminates one pulse from the pulse train of standard drive clock Rf~ when one increment pulse is generated from N1 counter 5, and adds one pulse to the pulse train of standard drive clocks Rf~ when one decrement pulse is generated from N1 counter 5.
R-stage frequency divider 7 R-stage frequency divides the output of frequency regulator 6, and outputs an output clock fout of the digital PLL. Here, R is a positive integer, any value being selectable. When the value of R is small, the phase fitter generated by addition and elimination of pulses increases, and when R is set to a large value, fitter can be decreased. In addition, the values of R, N, and N1 are each independent.
A
2175f 33 Figs. 3, 3A, 3B and 3C are waveform charts illustrating the operation of the digital PLL of Fig. 2. Fig. 3A shows the output waveform after dividing the waveform of standard drive clock Rf0 in a case where no control is performed. Fig. 3B shows the addition of 1 pulse to R-stage frequency dividing standard drive clock Rf0 in a case where pulse addition is effected, and the output waveform after R-stage frequency division. By adding pulses in this way, output frequency following R-stage frequency dividing can be set to a high level. Fig. 3C shows the elimin-ation of 1 pulse from R-stage frequency dividing standard drive clock Rf0 in a case where pulse elimination is performed, and the output waveform after R-stage frequency division. By eliminating pulses in A
~1T5133 this way, output frequency following R-stage frequency division can be set to a low level.
As described hereinabove, phase can be pulled in by adding or eliminating pulses in frequency regulator 6. The generation of this addition and elimination of pulses is performed as the automatic control loop of the overall system. In other words, a phase locked loop is formed.
Fig. 4 is a block diagram of an N-order digital PLL including the digital PLL of Fig. 2. This N-order digital PLL is made up of first N-stage frequency divider 1, second N-stage frequency divider 2, multilevel quantized phase comparators 3-1, 3-2, ..., and 3-M, N1 counter 5, N2 counter 10-1, N3 counter 10-2, ..., and NN counter 10-(N-1), frequency regulator 6, R-stage frequency divider 7, Q1 counter 8-1, Q2 counter 8-2, ..., and QN-1 counter 8-(N-1) that store the center frequencies of N2 counter 10-1, N3 counter 10-2, ..., and NN counter 10-(N-1), respectively, and rate multiplier 9-1, rate multiplier 9-2, ..., and rate multiplier 9-(N-1) that generate increment pulses or decrement pulses appropriate to the center frequency of the system.
A complete second-order digital PLL construction is described in Electronic Information Communications Conference Papers (B-I, Vol. J73-B-I No. 8 pp. 650-659.
2~75i33 August 1990) and as the operation of the N-order digital PLL of the present invention can be easily inferred from this publication, further explanation will be omitted here.
Referring to Fig. 5, a digital PLL according to the second embodiment of the present invention is constructed by providing in the embodiment of Fig. 2 N1 counters 5-1, 5-2, ..., and 5-M immediately after multilevel quantized phase comparators 3-1, 3-2, ..., and 3-M, respectively, and providing adder 4' immediately after N1 counter 5-1, 5-2, ..., and 5-M.
N1 counters 5-1, 5-2, ..., and 5-M are competitive counters that input either advanced pulses indicating phase advance or delayed pulses indicating phase delay which are outputted by the corresponding multilevel quantized phase comparators 3-1, 3-2, ..., and 3-M, count up in response to the advanced pulses, and upon counting up to 2N1, both output an increment pulse and undergo setting to initial value N1. In response to the delayed pulses, the N1 counters 5-1, 5-2, ..., and 5-M count down, and upon counting down to "0," both output a decrement pulse and undergo setting to initial value N1. Adder 4 adds the increment pulses or decrement pulses of the M N1 counters 5-1 to 5-M and output pulses of an advanced phase or a delayed phase.
The operation of this embodiment is otherwise similar z1~5~33 to that of Fig. 2.
Fig. 6 is a block diagram showing an N-order digital PLL that includes the digital PLL of Fig. 5.
While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.
In a digital PLL of the prior art in which two N-stage frequency dividers are added to the first stage of a digital PLL, an input signal is inputted to an input of one N-stage frequency divider and the output signal of .the digital PLL is inputted to an input of the other N-stage frequency divider, and following N-stage frequency division of each of the signals, the signals are inputted to a multilevel quantized phase comparator. .
Fig. 1 is a block diagram of a prior-art digital PLL. A digital PLL input clock Fin and output clock foot are inputted to first and second N-stage frequency dividers 11 and 12, respectively, and subjected to N-stage frequency division. Multilevel quantized phase comparator 13, which is driven by phase comparator clock Pfd, inputs the output clocks of N-stage frequency dividers 11 and 12 and outputs output phase error information (advanced pulses or delayed pulses) ~1~5133 indicating the phase advance/phase delay of both output clocks. N1 counter 14 is a competitive counter which inputs the advanced pulses or delayed pulses, counts up in response to advanced pulses, and upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1. N1 counter 14 counts down in response to delayed pulses, and upon counting down to "0," both outputs a decrement pulse and undergoes setting to initial value N1. Frequency regulator 15 is driven by the standard drive clock Rf0 of the digital PLL, and clears one pulse from the pulse train of standard drive clock Rf0 when one increment pulse is generated from N1 counter 14 and adds one pulse to the pulse train of standard drive clock Rf0 when one decrement pulse is generated from N1 counter 14. R-stage frequency divider 16 effects R-stage frequency division upon the output of frequency regulator 15 and outputs the output clock fout of the digital PLL.
In the above-described prior-art digital PLL, however, because the input to multilevel quantized phase comparators is N-stage frequency divided by N-stage frequency dividers, phase comparison is effected 1/N times that of a case in which N-stage frequency dividers are not employed. In other words, the gain of the switching network is reduced to 1/N, phase error information obtained per second drops to an insufficient level, and unwanted fitter (variations in phase) is generated.
Furthermore, if half-clock control is selected for controlling the frequency regulator of the digital PLL, there is the further drawback that half-clock phase error cannot be detected in the phase comparator because the sampling interval of phase error detection in the phase comparator is 1 clock.
SZTMMARY OF THE INVENTION
The object of the present invention is to provide a digital PLL in which half-clock phase control carried out in the frequency regulator can be detected in the phase comparator, and moreover, which prevents a drop in gain of the switching network and prevents the occurrence of unwanted fitter.
To achieve the above-described object, a digital PLL
according to the present invention includes:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL and generates N
clocks of a first phase, a second phase, ... , and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
A
' 21751 33 first multilevel quantized phase comparison means that inputs an arbitrary output signal of the first group of first N-stage frequency dividing means and an arbitrary output signal of the first group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels;
second multilevel quantized phase comparison means that inputs an arbitrary output signal of the second group of first N-stage frequency dividing means and an arbitrary output signal l0 of the second group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; ...; and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of the Mth group of first N-stage frequency dividing means and an arbitrary output signal of the Mth group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized A
x175133 in multiple levels;
adding means that adds phase difference information outputted from the M multilevel quantized phase comparison means and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay;
N1 counting means that is a competitive counter that inputs the advanced pulses or the delayed pulses, counts up in response to the advanced pulses and, upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1; and that counts down in response to the delayed pulses, and, upon counting down to "0," both outputs a decrement pulse and undergoes setting to initial value N1;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of the standard drive clock when one increment pulse is generated from the N1 counting means, and adds one pulse to the pulse train of the standard drive clock when one decrement pulse is generated from the N1 counting means; and R-stage frequency dividing means that R-stage frequency divides the output of the frequency regulating means and outputs an output clock of the digital PLL;
wherein, of the M multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
An N-order digital PLL of the present invention includes the above-described digital PLL.
Another digital PLL according to the present invention includes:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, and an Nth output clock, respectively, divides these N clocks into M
groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of the first A
group of first N-stage frequency dividing means and an arbitrary output signal of the first group of the second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; second multilevel quantized phase comparison means that inputs an arbitrary output signal of the second group of first N-stage frequency dividing means and an arbitrary output signal of the second group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; ...; and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of the Mth group of first N-stage frequency dividing means and an arbitrary output signal of the Mth group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels;
N1 counting means which are competitive counters provided corresponding to each of the M multilevel quantized phase comparison means and which input advanced pulses indicating phase advance or delayed pulses indicating phase delay outputted by the respective multilevel quantized phase comparison means, count up in response to the advanced pulses and, upon counting up to count value 2N1, both output an increment pulse and undergo setting to initial value N1; and that count down in response to the delayed pulses, and, upon counting down to "0", both output a decrement pulse and undergo setting to initial value N1;
adding means that adds increment pulses or decrement pulses of the M N1 counting means and outputs pulses of advanced phase or delayed phase;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of the standard drive clock when one pulse of advanced phase is generated from the adding means, and adds one pulse to the pulse train of the standard drive clock when one pulse of delayed phase is generated from the adding means; and R-stage frequency dividing means that R-stage frequency divides the output of the frequency regulating means and outputs an output clock of the digital PLL;
wherein, of the M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
An N-order digital PLL of the present invention includes the above-described digital PLL.
By employing multiple multilevel quantized phase comparison means, the phase error information obtained in one second can be increased M-fold and the system again can be increased M-fold.
Moreover, generated phase fitter can be reduced because accurate z~~5~33 phase error information can be obtained.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based with references to the accompanying drawings which illustrate examples of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram of one example of a digital PLL of the prior art;
Fig. 2 is a block diagram of a digital PLL according to the first embodiment of the present invention;
Figs. 3, 3A, 3B and 3C are waveform charts illustrating the operation of the digital PLL according to the first embodiment;
Fig. 4 is a block diagram showing an N-order digital PLL
including a digital PLL according to the first embodiment;
Fig. 5 is a block diagram showing a digital PLL
A.
according to the second embodiment of the present invention; and Fig. 6 is a block diagram showing a N-order digital PLL including a digital PLL of the second embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to Fig. 2, a digital PLL according to the first embodiment of the present invention is composed of a first N-stage frequency divider 1, a second N-stage frequency divider 2, M multilevel quantized phase comparators 3-1 to 3-M, an adder 4, an N1 counter 5, a frequency regulator 6, and an R-stage frequency divider 7.
First N-stage frequency divider 1 N-stage frequency divides input clock fin of the digital PLL, generates first phase, second phase, ..., and Nth phase clocks synchronized with the first input clock, the second input clock, ..., and the Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs the result.
Second N-stage frequency divider 2 N-stage frequency divides output clock foot of the digital PLL, generates first phase, second phase, ..., and Nth phase clocks synchronized with the first output clock, the second output clock, ..., and the Nth output clock, 2»5133 respectively, divides these N clocks into M groups (N>M), and outputs the result.
Multilevel quantized phase comparator 3-1 inputs an arbitrary output signal of the first group of first N-stage frequency divider 1 and an arbitrary output signal of the first group of second N-stage frequency divider 2 and outputs the phase difference between the two output signals as a value quantized in multiple levels. Multilevel quantized phase comparator 3-2 inputs an arbitrary output signal of the second group of first N-stage frequency divider 1 and an arbitrary output signal of the second group of second N-stage frequency divider 2 and outputs the phase difference between the two output signals as a value quantized in multiple levels. Multilevel quantized phase comparator 3-M inputs an arbitrary output signal of the Mth group of first N-stage frequency divider 1 and an arbitrary output signal of the Mth group of second N-stage frequency divider 2 and outputs the phase difference between the two output signals as a value quantized in multiple levels. Here, multilevel quantized phase comparators of odd ordinal numbers count input phase differences at the rising edge of phase comparison (sampling) clock PfO, and multilevel quantized phase comparators of even ordinal numbers count input phase difference at the rising edge of sampling clock Pf0 which is 180° out of phase with the sampling clock PfO.
By using sampling clocks of both positive phase and negative phase in this way, sampling accuracy can be doubled as compared with using only a positive-phase sampling clock, and half-clock phase difference can be detected.
A
Adder 4 adds the phase difference information outputted from the M multilevel quantized phase comparators 3-1 to 3-M and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay. When input is of differing phase (increment and decrement), a value for the difference can be obtained.
N1 counter 5 is a competitive counter that inputs advanced pulses or delayed pulses, counts up in response to advanced pulses, and upon counting up to a count value 2N1 (a positive integer), both outputs an increment pulse and undergoes setting to initial value N1. In response to delayed pulses, N1 counter 5 counts down, and upon counting down to "0", both outputs a decrement pulse and undergoes setting to initial value N1.
Frequency regulator 6 is driven by standard drive clocks Rfp of the digital PLL, eliminates one pulse from the pulse train of standard drive clock Rf~ when one increment pulse is generated from N1 counter 5, and adds one pulse to the pulse train of standard drive clocks Rf~ when one decrement pulse is generated from N1 counter 5.
R-stage frequency divider 7 R-stage frequency divides the output of frequency regulator 6, and outputs an output clock fout of the digital PLL. Here, R is a positive integer, any value being selectable. When the value of R is small, the phase fitter generated by addition and elimination of pulses increases, and when R is set to a large value, fitter can be decreased. In addition, the values of R, N, and N1 are each independent.
A
2175f 33 Figs. 3, 3A, 3B and 3C are waveform charts illustrating the operation of the digital PLL of Fig. 2. Fig. 3A shows the output waveform after dividing the waveform of standard drive clock Rf0 in a case where no control is performed. Fig. 3B shows the addition of 1 pulse to R-stage frequency dividing standard drive clock Rf0 in a case where pulse addition is effected, and the output waveform after R-stage frequency division. By adding pulses in this way, output frequency following R-stage frequency dividing can be set to a high level. Fig. 3C shows the elimin-ation of 1 pulse from R-stage frequency dividing standard drive clock Rf0 in a case where pulse elimination is performed, and the output waveform after R-stage frequency division. By eliminating pulses in A
~1T5133 this way, output frequency following R-stage frequency division can be set to a low level.
As described hereinabove, phase can be pulled in by adding or eliminating pulses in frequency regulator 6. The generation of this addition and elimination of pulses is performed as the automatic control loop of the overall system. In other words, a phase locked loop is formed.
Fig. 4 is a block diagram of an N-order digital PLL including the digital PLL of Fig. 2. This N-order digital PLL is made up of first N-stage frequency divider 1, second N-stage frequency divider 2, multilevel quantized phase comparators 3-1, 3-2, ..., and 3-M, N1 counter 5, N2 counter 10-1, N3 counter 10-2, ..., and NN counter 10-(N-1), frequency regulator 6, R-stage frequency divider 7, Q1 counter 8-1, Q2 counter 8-2, ..., and QN-1 counter 8-(N-1) that store the center frequencies of N2 counter 10-1, N3 counter 10-2, ..., and NN counter 10-(N-1), respectively, and rate multiplier 9-1, rate multiplier 9-2, ..., and rate multiplier 9-(N-1) that generate increment pulses or decrement pulses appropriate to the center frequency of the system.
A complete second-order digital PLL construction is described in Electronic Information Communications Conference Papers (B-I, Vol. J73-B-I No. 8 pp. 650-659.
2~75i33 August 1990) and as the operation of the N-order digital PLL of the present invention can be easily inferred from this publication, further explanation will be omitted here.
Referring to Fig. 5, a digital PLL according to the second embodiment of the present invention is constructed by providing in the embodiment of Fig. 2 N1 counters 5-1, 5-2, ..., and 5-M immediately after multilevel quantized phase comparators 3-1, 3-2, ..., and 3-M, respectively, and providing adder 4' immediately after N1 counter 5-1, 5-2, ..., and 5-M.
N1 counters 5-1, 5-2, ..., and 5-M are competitive counters that input either advanced pulses indicating phase advance or delayed pulses indicating phase delay which are outputted by the corresponding multilevel quantized phase comparators 3-1, 3-2, ..., and 3-M, count up in response to the advanced pulses, and upon counting up to 2N1, both output an increment pulse and undergo setting to initial value N1. In response to the delayed pulses, the N1 counters 5-1, 5-2, ..., and 5-M count down, and upon counting down to "0," both output a decrement pulse and undergo setting to initial value N1. Adder 4 adds the increment pulses or decrement pulses of the M N1 counters 5-1 to 5-M and output pulses of an advanced phase or a delayed phase.
The operation of this embodiment is otherwise similar z1~5~33 to that of Fig. 2.
Fig. 6 is a block diagram showing an N-order digital PLL that includes the digital PLL of Fig. 5.
While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.
Claims (4)
1. A digital Phase-Locked Loop (PLL) comprising:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL and generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means and an arbitrary output signal of a first group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels, second multilevel quantized phase comparison means that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means and an arbitrary output signal of a second group of second N-stage frequency dividing means and outputs phase difference between the two signals as value quantized in multiple levels, ..., and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means and an arbitrary output signal of an Mth group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
adding means that adds phase difference information outputted from the M multilevel quantized phase comparison means and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay;
N1 counting means that is a competitive counter that inputs said advanced pulses or said delayed pulses, counts up in response to said advanced pulses and, upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1, and that counts down in response to said delayed pulses, and, upon counting down to "0", both outputs a decrement pulse and undergoes setting to initial value N1;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock when one increment pulse is generated from said N1 counting means, and adds one pulse to the pulse train of said standard drive clock when one decrement pulse is generated from said N1 counting means; and R-stage frequency dividing means that R-stage frequency divides output of said frequency regulating means and outputs an output clock of the digital PLL;
wherein, of said M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL and generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means and an arbitrary output signal of a first group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels, second multilevel quantized phase comparison means that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means and an arbitrary output signal of a second group of second N-stage frequency dividing means and outputs phase difference between the two signals as value quantized in multiple levels, ..., and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means and an arbitrary output signal of an Mth group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
adding means that adds phase difference information outputted from the M multilevel quantized phase comparison means and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay;
N1 counting means that is a competitive counter that inputs said advanced pulses or said delayed pulses, counts up in response to said advanced pulses and, upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1, and that counts down in response to said delayed pulses, and, upon counting down to "0", both outputs a decrement pulse and undergoes setting to initial value N1;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock when one increment pulse is generated from said N1 counting means, and adds one pulse to the pulse train of said standard drive clock when one decrement pulse is generated from said N1 counting means; and R-stage frequency dividing means that R-stage frequency divides output of said frequency regulating means and outputs an output clock of the digital PLL;
wherein, of said M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
2. An N-order digital PLL comprising a digital PLL
comprising:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL and generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means and an arbitrary output signal of a first group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels, second multilevel guantized phase comparison means that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means and an arbitrary output signal of a second group of second N-stage frequency dividing means and outputs phase difference between the two signals as value quantized in multiple levels, ..., and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means and an arbitrary output signal of an Mth group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
adding means that adds phase difference information outputted from the M multilevel quantized phase comparison means and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay;
N1 counting means that is a competitive counter that inputs said advanced pulses or said delayed pulses, counts up in response to said advanced pulses and, upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1, and that counts down in response to said delayed pulses, and, upon counting down to "0", both outputs a decrement pulse and undergoes setting to initial value N1;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock when one increment pulse is generated from said N1 counting means, and adds one pulse to the pulse train of said standard drive clock when one decrement pulse is generated from said N1 counting means; and R-stage frequency dividing means that R-stage frequency divides output of said frequency regulating means and outputs an output clock of the digital PLL;
wherein, of said M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
comprising:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL and generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means and an arbitrary output signal of a first group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels, second multilevel guantized phase comparison means that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means and an arbitrary output signal of a second group of second N-stage frequency dividing means and outputs phase difference between the two signals as value quantized in multiple levels, ..., and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means and an arbitrary output signal of an Mth group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
adding means that adds phase difference information outputted from the M multilevel quantized phase comparison means and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay;
N1 counting means that is a competitive counter that inputs said advanced pulses or said delayed pulses, counts up in response to said advanced pulses and, upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1, and that counts down in response to said delayed pulses, and, upon counting down to "0", both outputs a decrement pulse and undergoes setting to initial value N1;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock when one increment pulse is generated from said N1 counting means, and adds one pulse to the pulse train of said standard drive clock when one decrement pulse is generated from said N1 counting means; and R-stage frequency dividing means that R-stage frequency divides output of said frequency regulating means and outputs an output clock of the digital PLL;
wherein, of said M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
3. A digital PLL comprising:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means and an arbitrary output signal of a first group of the second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
second multilevel quantized phase comparison means that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means and an arbitrary output signal of a second group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels; ..., and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means and an arbitrary output signal of an Mth group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
N1 counting means which are competitive counters provided corresponding to each of said M multilevel quantized phase comparison means and which input advanced pulses indicating phase advance or delayed pulses indicating phase delay outputted by the respective multilevel quantized phase comparison means, count up in response to said advanced pulses and, upon counting up to count value 2N1, both output an increment pulse and undergo setting to initial value N1, and that count down in response to said delayed pulses, and, upon counting down to "0", both output a decrement pulse and undergo setting to initial value N1;
adding means that adds increment pulses or decrement pulses of said M N1 counting means and outputs pulses of advanced phase or delayed phase;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock when one pulse of advanced phase is generated from said adding means, and adds one pulse to the pulse train of said standard drive clock when one pulse of delayed phase is generated from said adding means; and R-stage frequency dividing means that R-stage frequency divides the output of said frequency regulating means and outputs an output clock of the digital PLL;
wherein, of said M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means and an arbitrary output signal of a first group of the second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
second multilevel quantized phase comparison means that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means and an arbitrary output signal of a second group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels; ..., and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means and an arbitrary output signal of an Mth group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
N1 counting means which are competitive counters provided corresponding to each of said M multilevel quantized phase comparison means and which input advanced pulses indicating phase advance or delayed pulses indicating phase delay outputted by the respective multilevel quantized phase comparison means, count up in response to said advanced pulses and, upon counting up to count value 2N1, both output an increment pulse and undergo setting to initial value N1, and that count down in response to said delayed pulses, and, upon counting down to "0", both output a decrement pulse and undergo setting to initial value N1;
adding means that adds increment pulses or decrement pulses of said M N1 counting means and outputs pulses of advanced phase or delayed phase;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock when one pulse of advanced phase is generated from said adding means, and adds one pulse to the pulse train of said standard drive clock when one pulse of delayed phase is generated from said adding means; and R-stage frequency dividing means that R-stage frequency divides the output of said frequency regulating means and outputs an output clock of the digital PLL;
wherein, of said M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
4. An N-order digital PLL comprising a digital PLL
comprising:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means and an arbitrary output signal of a first group of the second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
second multilevel quantized phase comparison means that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means and an arbitrary output signal of a second group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels; ..., and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means and an arbitrary output signal of an Mth group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
N1 counting means which are competitive counters provided corresponding to each of said M multilevel quantized phase comparison means and which input advanced pulses indicating phase advance or delayed pulses indicating phase delay outputted by the respective multilevel quantized phase comparison means, count up in response to said advanced pulses and, upon counting up to count value 2N1, both output an increment pulse and undergo setting to initial value N1, and that count down in response to said delayed pulses, and, upon counting down to "0", both output a decrement pulse and undergo setting to initial value N1;
adding means that adds increment pulses or decrement pulses of said M N1 counting means and outputs pulses of advanced phase or delayed phase;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock when one pulse of advanced phase is generated from said adding means, and adds one pulse to the pulse train of said standard drive clock when one pulse of delayed phase is generated from said adding means; and R-stage frequency dividing means that R-stage frequency divides the output of said frequency regulating means and outputs an output clock of the digital PLL;
wherein, of said M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
comprising:
first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N
clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs M groups of clocks;
first multilevel quantized phase comparison means that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means and an arbitrary output signal of a first group of the second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
second multilevel quantized phase comparison means that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means and an arbitrary output signal of a second group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels; ..., and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means and an arbitrary output signal of an Mth group of second N-stage frequency dividing means and outputs phase difference between the two signals as a value quantized in multiple levels;
N1 counting means which are competitive counters provided corresponding to each of said M multilevel quantized phase comparison means and which input advanced pulses indicating phase advance or delayed pulses indicating phase delay outputted by the respective multilevel quantized phase comparison means, count up in response to said advanced pulses and, upon counting up to count value 2N1, both output an increment pulse and undergo setting to initial value N1, and that count down in response to said delayed pulses, and, upon counting down to "0", both output a decrement pulse and undergo setting to initial value N1;
adding means that adds increment pulses or decrement pulses of said M N1 counting means and outputs pulses of advanced phase or delayed phase;
frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock when one pulse of advanced phase is generated from said adding means, and adds one pulse to the pulse train of said standard drive clock when one pulse of delayed phase is generated from said adding means; and R-stage frequency dividing means that R-stage frequency divides the output of said frequency regulating means and outputs an output clock of the digital PLL;
wherein, of said M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock 180° out of phase with said phase count clock.
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| JP7105933A JP2964912B2 (en) | 1995-04-28 | 1995-04-28 | Digital PLL |
| JP105933/95 | 1995-04-28 |
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| CA2175133A1 CA2175133A1 (en) | 1996-10-29 |
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| CA002175133A Expired - Fee Related CA2175133C (en) | 1995-04-28 | 1996-04-26 | Digital phase-locked loop (pll) |
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| EP (1) | EP0740423B1 (en) |
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| DE112018002643T5 (en) | 2017-05-22 | 2020-05-07 | Invention Mine, Llc | MULTIMODAL DATA DRIVEN CLOCK RECOVERY CIRCUIT |
| CN107911114B (en) * | 2017-11-15 | 2021-03-09 | 中国科学技术大学 | Broadband phase-locked loop with constant loop bandwidth |
| US10554380B2 (en) | 2018-01-26 | 2020-02-04 | Kandou Labs, S.A. | Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation |
| EP4145705A1 (en) | 2018-06-12 | 2023-03-08 | Kandou Labs SA | Low latency combined clock data recovery logic network and charge pump circuit |
| US10958251B2 (en) | 2019-04-08 | 2021-03-23 | Kandou Labs, S.A. | Multiple adjacent slicewise layout of voltage-controlled oscillator |
| US10630272B1 (en) | 2019-04-08 | 2020-04-21 | Kandou Labs, S.A. | Measurement and correction of multiphase clock duty cycle and skew |
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| US11463092B1 (en) | 2021-04-01 | 2022-10-04 | Kanou Labs Sa | Clock and data recovery lock detection circuit for verifying lock condition in presence of imbalanced early to late vote ratios |
| US11563605B2 (en) | 2021-04-07 | 2023-01-24 | Kandou Labs SA | Horizontal centering of sampling point using multiple vertical voltage measurements |
| US11496282B1 (en) | 2021-06-04 | 2022-11-08 | Kandou Labs, S.A. | Horizontal centering of sampling point using vertical vernier |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4808884A (en) * | 1985-12-02 | 1989-02-28 | Western Digital Corporation | High order digital phase-locked loop system |
| JP2993200B2 (en) * | 1991-07-31 | 1999-12-20 | 日本電気株式会社 | Phase locked loop |
| FR2682236B1 (en) * | 1991-10-04 | 1997-01-03 | Cit Alcatel | METHOD AND DEVICE FOR CONTROLLING THE MODE OF OPERATION OF A DIGITAL PHASE LOCKING LOOP |
| JP3232351B2 (en) * | 1993-10-06 | 2001-11-26 | 三菱電機株式会社 | Digital circuit device |
| US5463351A (en) * | 1994-09-29 | 1995-10-31 | Motorola, Inc. | Nested digital phase lock loop |
-
1995
- 1995-04-28 JP JP7105933A patent/JP2964912B2/en not_active Expired - Fee Related
-
1996
- 1996-04-25 US US08/637,608 patent/US5694068A/en not_active Expired - Lifetime
- 1996-04-26 EP EP96302922A patent/EP0740423B1/en not_active Expired - Lifetime
- 1996-04-26 CA CA002175133A patent/CA2175133C/en not_active Expired - Fee Related
- 1996-04-26 DE DE69629147T patent/DE69629147T2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0740423A2 (en) | 1996-10-30 |
| JP2964912B2 (en) | 1999-10-18 |
| US5694068A (en) | 1997-12-02 |
| EP0740423B1 (en) | 2003-07-23 |
| DE69629147D1 (en) | 2003-08-28 |
| CA2175133A1 (en) | 1996-10-29 |
| JPH08307250A (en) | 1996-11-22 |
| EP0740423A3 (en) | 1998-04-08 |
| DE69629147T2 (en) | 2004-02-19 |
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| EEER | Examination request | ||
| MKLA | Lapsed |