CA2191100C - Imaging devices, systems and methods - Google Patents

Abstract

An imaging device comprises a semiconductor substrate (16) including an array of pixel cells. Each pixel cell comprising an individually addressable pixel circuit (18) for accumulating charge resulting from radiation incident on a pixel detector. The pixel circuit and the pixel detector can either be implemented on a single substrate or on two substrates bonded together. The charge storage device can be a transistor, for example one of a pair of FETs connected as a cascade amplification stage. An imaging plane can be made up of one imaging device or a plurality of imaging devices tiled to form a mosaic. The imaging devices may be configured as a slot for certain applications, the slit or slot being scanned over the imaging plane. Control electronics (24) can include addressing logic for addressing individual pixel circuits for reading accumulated charge from the pixel circuits. Imaging optimisation can be achieved by determining maximum and minimum charge values for pixels for display, assigning extreme grey scale or colour values to the maximum and minimum charge values and allocating grey scale or colour values to an individual pixel according to a sliding scale between the extreme values.
Scattered radiation can be detected and discarded by comparing the detected pixel value to a threshold value related to a minimum detected charge value expected for directly incident radiation and discarding detected pixel values less than said threshold value.

Description

-~ W095/33332 2 1 9 1 1 00 ~ /1!.17~
rMA(:T~G DEvJ(~F~. SYSTl;M.r' AN~ MF~r~nnC
The invention relates to imaging devices, systems and methods, and in particular to a s~m1rnnr1~rtor pixel imaging device for use as an 5 image sensor and to imaging systems and methods utilizing the pixel cPmi rnn~ rtnr imaging device .
Two basic types of ~Pmi rnn~l1rtor pixel devices are known in the prior art: 1) Charge Coupled image sensors also known as Charge Coupled Devices (CCD) and 2) Pulse Counting ~mirnn~ rtor Pixel Devices.
CCDs have been used for the past 1~ years or so (see for example S.M Sze "Physics of ,r~omirnnrl~lrtnr Devices" 2nd Edition, 1981) as image sensors. Practically all CCDs available are made using silicon (Si) technology. The principle of operation of a CCD is based on the fact that when an appropriate voltage is applied via an electrode gate. the 15 bulk Si volume becomes depleted of majority carriers (e.g. holes) and a region is created (depletion region) where electrons can be Al lAt~l. This depletion region amounts to a potential well with a depth proportional to the applied voltage. The maximum charge that can then be stored in a CCD pixel depends on the area under the electrode, 20 the voltage applied, the dark or leakage current coming from the bulk Si that rnnt~n-ln--c1y fills the well and the thickness of the oxlde layer between the electrode and the bulk Si. These factors determine the effective CCD charge storing capacity.
When electrons arc A' lAt~tl in the potential well and need to 25 be read out, the potential at the electrode gates is pulsed and an electron package stored under one gate starts to be clocked towards the next gate and so on. The electron package never leaves the Si substrate and in order to read a stored charge at some pixel position the contents of all other pixels ahead of it have first to be read out 30 in a sequential way. During this process no further charge can be Ar 1 Ate~i as it would destroy the information of the charge content pér pixel and consequentlY it would spoil image resolution and contrast. Therefore during readout the image sensor is inactive. The above described process requires at least three electrode gates per 35 pixel.
CCDs can be used either for detecting, Al l Atin~ and reading out charge created from light and/or radiation or can be used just as _ _ _ _ .... . . . .. . _ . ... .... _ _ _ _ _ W0 95/33332 2 1 '3 1 1 0 0 r~

a readout device for reading the charge created in another detecting means (e.g. photodiodes~. When used for detecting incident radiation as well as for readirg the signals, CCDs have an additional limitation of low efficiency.
rn particular at high energies (X-rays above a few KeV) CCDs are used in conjunction with light converting screens that convert X-rays to optical light, to which a CCD is more sensitive. However light diffusion worsens resolution and contrast.
Therefore a CCD operates in the following way:
1) Charge is A( lAtPrl within a depletion region created by an applied voltage. For each pixel the depletion region has a potential vell shape and constrains the electrons under the electrode gate to remain inside the Si bulk volume.

2) Voltages are pulsed to the electrode gates to clock each charge package to the volume ~uLL~_~ulldlng to the next pixel. The charge package remains at all eimes inside the Si substrate and clocks its way through, pixel by pixel, to a common output. During that process additional charge cannot be A~ 1 AtP~, As a result of the above the CCD is a device with two substantial limitations:
1) Compromised dynamic range. Typically a CCD can Al lAtP
100,000-700,000 electrons. The reason for the limited dynamic range is that the potential well fills up due to the dark current within the Si volume, the electrode gate surface under which the charge is ~ lAtP~l is at best 1/3 of the total pixel area (thus not utilizing the total charge storage capacity of the pixel) _nd the oxide layer thickness upon which the storage capacity also depends has to be thick to stand the abrupt voltage pulses needed for the readout (note: the thicker the oxide layer, the less charge can be stored in the potential well ) .
2) Large inactive time. The inactive time needed for the readout is considerable. In many cases this inhibits CCDs from being used for fast dynamic multi-frame image Arr~ lAti Two examples of systems using CCDs are included in patent PrrlirAt1nne GB-A-224943û and GB-A-2262383. Both ArrlirAtinnc are concerned with ways of overcoming the intrinsic CCD limitations.
.r~Pmirn-l~il-rtor pixel detectors comprise a cPmirnT~-~Ilrtnr substrate ~ W095133332 2 1 ~ 1 1 0~ P ~ s6 with electrodes which apply a depletion voltage to each pixel and define a charge collection volume. Simple buffer circuits read out the electric signals when a photon is photo-absorbed or when ionizing radiation crosses the depletion zone of the 5Pmi rnnfll~rtnr substrate.
5 The buffer circuits can either be on the sa_e substrate (compare EP-A-0,287,197) as the charge collection volumes or on a separate substrate (compare EP-A-0,571,135) that is morhAnirAlly bonded to a substrate having the charge collection volumes in accordance with, for example, the well known bump-bonding technique (bl, bu~lding is a technique 10 known for a decade or more). These pixel detectors operate in a pulse mode. A pulse counting mode or simply pulse imaging can be i ~ l l t~or~
by either reading the pixels rnntinllmlcly or by reading pixels 8orlllPntiAlly at a fast enough rate.
In either case, every time a charge is present as a result of a 15 high energy ray or light, the aim is to read it out and process the information. The pixel detectors decrease the readout speed needed because there is a higher CP~mPntAtinn and more parallel readout channels. However, they cannot cope with high intensity /IrrlirAt~nnr because the readout electronics will overflow or counting aoility 20 saturates thus destroying the image contrast. In some of these devices simultaneously incident rays cause ambiguous and 'ghost' hits that cannot be resolved an~ worsen the resolution. Although these devices directly detect the incident radiation, they have limitations due to an operation based on a single pulse counting mode and imaging based on 25 the counting of discrete points.
It will be appreciated from the above that all of the devices presently available have limitations which cannot be resolved. In particular CCDs enable charge from successive hits to be 1 AtP~l, but only to the limited extent possible within a potential well inside 3û the Si substrate. which substantially limits the dynamic range. Also, because of the charge Al 1 Atinn method, charge readout happens in a time sequence mode by clocking the pixel charge content to the neighbouring pixel storing unit (which is always the same Si substrate). Thus, until all pixels are read out as a time train 35 sequence, a CCD cannot A~ 1 Ato a new image frame since additional incoming radiation and/or light would not be recorded in one to one ~UL~ e with a pixel position during the readout process.

3~ 2 t 9 1 1 0 0 Therefore limited dynamic range and large inactive time during imaging are the two major CCD limitations.
On the other hand some semiconductor pixel devices have been proposed that directly read the pixel content every time a hit is 5 detected. These devices operate on the single pulse countlng mode and suffer f'rom saturation problems at high counting rates. Such conventional single hit counting devices have a very small dynamic range .
Accordingly, an object of the invention is to provide an imaging lO device based on a different approach which enables the problems of the prior art to be mitigated and/or solved.
In ~ uLd/~ with an aspect of the invention there is provided an imaging device for ~maging radiation, the imaging device comprising an array of pixel cells including a s~mirrn~l~rtor substrate having an 15 array of pixel detectors which generate charge in response to incident radiation and a ~uLLe:~ulldlng array of pixel circuits, each pixel circuit being A~.coriAtPd with a respective pixel detector for r 1 Atin~ charge resulting from radiation incident on the pixel detectDr, the pixel circuits being individually addressable and 20 comprising circuitry for Al lAtin~ charge from successive radiation hits on the respective pixel detectors.
The invention provides an imaging device which can be described as an Active-pixel .ripmirr~n~lrtor Imaging Device (ASID). r ~ tC of an imaging device in accordance with the invention are suitable, in 25 particular, for high energy radiation imaging such as X-ray, ,~-ray and -ray real time imaging. The invention is also Prrl i rAhl P for imaging other types of radiation, including light for example.
An ASID is able actively to r l ptP charge for individual pixels during irradiation. It directly detects rays incident on a 30 pixel cell detector of the sPm;rrn~rtor substrate and I latPc charge (by l Atin~ the charge directly as charge values or by converting it to a voltage or current and Al 1 rtin~ the resulting voltage or current) in an active circuit ..uL.wlJull~ing to the pixel cell detector. By enabling the active circuit for each pixel to be 35 addressed individually, that is ~n~l~rPn~ ntly of all other pixel circuits, (e.g., in random or C~rll-Pnt~Al order), the stored charge can be read out at any time during or after irradiation.

~ Wo 95/33332 2 1 9 1 1 0 0 1 1 /~1 ~ J/ L~)~
In an embodiment of the invention therefore, charge is Arr~ AtPrl in charge-accumulating circuitry (e.g. the gate of an integrated transistor or an integrated capacitor). There is no need for and no use o f the depletion layer And the potential well as in the 5 case of a CCD. A charge storage device such as the gate of a FET or acapacitor can be optimized to cover substantially all of the pixel circuit area with a minimum thickness oxide layer. These two factors maximize the charge storage capacity which is, for example, two orders of magnitude greater than that of a CCD. Moreover, each pixel does not interfere with its neighbouring pixels. Tn~lPrPn~Pnt access to pixels offers fast dynamic image frame r~ l Ptirn not possible with CCDs.
An embodiment of the invention can also overcome the previous limitations of pulse counting pixel devices at high counting rates in that several hundreds or thousands of pulses can be A~ 1 AtPrl prior to being read out. The number of readout channels is therefore ~iminichP~l without compromising device performance.
The active circuit is preferably located proximate to the pixel detector (either integral to the semiconductor substrate comprising the pixel cell detectors or on a substrate bonded thereto) and has a 20 sufficient dynamic range to accumulate charge '_UL' cyUll~illg to several hundreds or thousands of radiation hits on the ~ul.GD~,ullding pixel detector .
Readout of the active pixel circuits car. be arranged to occur very rapidly and ~nrlPr~.n~Pntly of all other pixel circuits, thus with practically no dead time, so that the active circuit and the ,u~ ng pixel cell detector are ready; ''AtPly to continue Al l Atin~ radiation hits.
Each detecting element and the Accr,r1 AtPrl active circuit corstitutes a randomly Arrrcc;hl P, dynamic active imaging pixel capable of ~ ~Ating charge (either directly as charge or as a voltage or current equivalent) during radiation and capable of being read during or after irradiation. The content of each pixel is not transferred sequentially to the nearby pixel but is read out ;nr7Prr~nrlPntly of all other pixels. The readout speed and the degree of parallel or sequential signal processing for the read out data can be optimised to match the radiation intensity and the time available to ~ l Ate one illage f rame .

W094/33332 21 ~ 1 1 0~ r~l/rl '/O~n46 Accordingly, an imaging devicc in accordance with the invention can ArC~ Ate charge from successive radiation or light hits utilizing the large dynamic range of a transistor and/or a capacitor that is provided in one to one corrPcrnnrlpnrp with a detecting pixel cell.
5 Whereas CCDs make use of a depletion layer inside a Si substrate to store charge in a potential well, an ASID Ar, 1 rtPc charge on the gate of a transistor and/or a capacitor. An ASID rnncPrll.Pntly will have a dynamic range up to two orders of magnitude larger than a CCD.
The same charge accumulating pixel circuit elements also allow readout 10 of each Al lAtP~ charge value in one to one CULI.~..IJ'IIII1~ with the detecting pixel element with practically no dead time during image frame Ar~ lAt;nn, An ASID also reduces the limitations of conventional CPmi rnnri-~rtor pixel devices that operate in a pulse counting mode as imagang is performed in direct proportion to the total 15 A~ l AtPrl charge and not to the number of radiation hits . While conventional pulse counting pixel devices suffer from saturation at high counting rates, an ASID can Al lAtP hundreds or thousands of hits prior to being read out. Long charge Al lAtinn times (from a few microseconds to about 1 second is possible) diminish the effect of 20 resetting the pixel circuits. Thus the total inactive time of each pixel circuit is a very small fraction of the charge r- lAtinn time (or active time).
The invention finds particular ArrlirAtinn for high intensity imaging ArFl irAtir~ne. The problems of unrealistic readout speed, 25 ambiguous and 'ghost' hits of prior pixel detectors and the low efficiency, low dynamic range and high inactive time of CCD devices can all be overcome by embodiments of the present invention. However, it will be appreciated that the invention is not limited to high energy and high intensity ArrlirAtinnc, and that embodiments of the invention 30 can also find ArrlirAtinn to lower energy ArrlirAtinnc (e.g., at ultraviolet, optical or infra red wavelengtns) and low intensity Arrl irAtinnC (in astronomY) -Preferably, each pixel circuit comprises a charge storage devicefor n, lAting charge, for example a capacitor and/or a transistor.
35 In a preferred e mPnt of the invention, charge is I - 1 AtP~l on the gate of a FET, preferably forming one of a pair of FETs connected as a cascode a_Plification stage.

WOgs/33332 21 9 1 1 00 r "ll /a70~6 Preferably also, each pixel circuit comprises circuitry for, selectively resetting the charge storage device, for example after readout of any charge stored thereon. A preferred ~ n~l;m~nt of the invention comprises a first FET switch responsive to an enable signal 5 to connect the charge storage device to an output line for outputting ,r lAt~d charge and a second FET switch responsive to a reset signal to ground the charge storage device to reset the charge storage device.
In some Arr1irAt;nnc, for example gamma cameras and nuclear medicine, the pixel size can be of the order of or less than lmm 10 across, preferably approximately 350um across.
In other ArFlir~tinnc~ the pixel cell size can be approximately 150um across or less, preferably approximately 50um across or less and more preferably approximately lOum across with a substrate between 200um and 3mm thick.
The pixel circuits can be implemented integrally to the substrate and aligned with the ~u..~ u..ding pixel detectors. Alternatively, the pixel circuits can be formed in a further substrate, the further substrate incorporating the pixel circuits being coupled to the substrate incorporating the pixel detectors, with each pixel circuit 20 being aligned with and being coupled to the ~u~ u.~ ng pixel detector .
In particular ~ '-m~ntC of the invention, the array comprises a single row of pixel detectors and Aqcnr;AtP~ pixel circuits forming a slit-shaped imaging device or a plurality of rows of pixel detectors 25 and AccOri~tr~l pixel circuits forming a slot-shaped imaging device. In such an embodiment the pixel circuits for respective pixel detectors can also be arranged laterally adjacent to the cuLL~L,u-lding pixel detectors .
An imaging system for the imaging device comprises control 30 electronics for the imaging device including addressing logic for addressing inaividual pixel circuits for reading A~ 1 AtP~l charge from the pixel circuit and selectively resetting the pixel circuit.
Preferably, the addressing logic comprises means for rnnnmrt;n~ output lines of the pixel circuits to an output of the imaging device, means 35 for supplying read enable signals to read enable inputs of the pixel circuits and means for supplying reset signals to reset inputs of the pixel circuits.

W0~5/33332 2~ 9 ~ 3 r~ o5c The means f-or connecting output lines can comprise a shift register or a counter for sequentially connecting output lines of the pixel circuits for respective columns of pixels to the output of the imaging ùevice. Likewise, the means for supplying read enable signals can comprise a shift register or a counter for sequentially supplying read enable signals to read enable inputs of the pixel circuits for respective rows of pixels and/or ~he means for supplying reset signals can comprise a shift register or a counter for sequentially supplying reset signals to reset inputs of the pixel circuits for respective rows of pixels.
Thus, in a preferred embodiment of the invention, the addressing logic comprises a first shift register for cPrlur-ntiAl ly connecting output lines of the pixels circuits for respective columns of pixels to an output of the imaging device, a second shift register for sequentially supplying read enable signals to read enable inputs of pixel circuits for respective rows of pixels and a third shift register for SPq-lr-ntiAlly supplying reset signals to reset inputs of pixel circuits for respective rows of pixels. In another preferred embodiment the same control signals can be implemented with a counter which produces row and column addresses that are decoded to output select, reset and read enable signals. The control electronics can include an analogue to digital converter (ADC) for converting charge read from a pixel circuit into a digital charge value.
At least part of the control electronics can be integrated into the ~m~rnntl~lrtor substrate on which the pixel circuits are formed.
Prefera~ly the imaging system comprises an image processor connected to the control electronics for processing the digital charge values from respective pixel circuits to form an image for display on a display device.
For optimising the display of captured images, the processor determine6 maximum and minimum charge values for pixels for display, assigns extreme grey scale or colour values to the maximum and minimum charge values and allocates grey scale or colour values to an individual pixel according to a sliding scale between the extreme values in ,1 ~ e upon the charge value for the pixel.
The grey scale or colour values are preferably allocated in ac~uL~lrllu~ with the following formula:

Wo 9513333~ 2 1 9 1 1 0 0 g (icharge-Min charge) Grey scale value of pi~el i = Mingrey - ~(May~rey-Mingrey) ~Ma~charge-Min~harge) n a preferred emoodiment o^ the lnven.lon, an~ imagi?.g system ,- compr~sir.g a plurallty cf magi.~g aevices as defined above :s t'led toger~er .o form a mosa~ ?is enables a large area ima~:~g ce~ice to oe conscructed ~ithout the yleid problems normally experienced with ~ery large surface area ~ ntegrated devices . The mosaic can comprise a plura~ ty of columns of tiled imaging devlces, the ~maging devlces of 10 adjacenc columns being oFrse~ in the column di-ectlon. Preferably, t'r.e il~aging system inc udes means for stepping or moving the imagi?.g aevlce ar.d,'or an ob ject to be lmaged to Al 1l ~rP an image over a comPlete image area.
In one embodimen~. t:~e lmaging sy~Srem com~rises two imaging '~ surfaces, each compris r.g a mosaic of imâging devices, said imaging surfaces being arranged substantially parallel to ooe anocher and spaced f-om one another with an object to be imaged between said surfaces, the mosaics being offset laterally wl~h respecc to one ar.other t~ give substan~lally complete imaging of said object 'Lrhis 20 permits substantially complete imaging in cercain Arr7ir~t1rnC without the need or translatory morh inj for the imaging planes.
Respective image ou~puts of a plurality of tiled imaging devices are prerferably connected to a common multiplexer, the output of which multiplexer is conr.ecced to a common analogue to digital converter.
Z5 Alternatively, a pluraIity of t~Ied imaging devices can first be daisy-chained and then converted to a common ADC. Also, individual pixel circuits can be addressed for reading P~r~ ArPi charge at a rate to optimise the resolution of an analogue to digital convert2r for converting analogue Arc~ 1 A rorl charge v~ues into digital values .
30 Lhese measures provide design flexibility to optimise between cost - (more multiplexing, less ADCs) and image contras~ (less multiplexing, more ADCs ) .
In an imaging system comprising one or =ore slit- or slot-shaped imaging device(s) as defined above, means can be provided for moving ~5 the slit- or slot-shaped imaging device(s) in a direction ~L~.av~Laely to a longitudinal axis of the imaging device~s) for A~r- lAtin~ a SUBSTITUTE SHEET (RULE 26) ~V0 95133332 ~ ) r~ ns~ !

complete image over an imaging area.
In accordance with another aspect of the invention, there is provided a method of operating an imaging system with a slit- or slot, 6haped imaging device as defined above, the method comprising moving 5 the slit or slot shaped imaging device(s) in the l,~ L~e direction and reading accumulated charge from the pixel circuits of the slit- or slot-shaped imaging device(s) at a rate ~uLL~,uul~ding to movement of the imaging device(s) by half or less than half of the pixel size in the direction of motion.
In accordance with another aspect of the invention, there is provided a method of operating an imaging system comprising one or more slit- or slot-shaped imaging devices as defined above, the method comprising minimiq1ng the effect of scattered radiation by optimising the r~lst~rmqhir oetween the following parameters: the distance between 15 a radiation source and an object to be imaged; the distance between the object to be imaged and the slit- or slot-shaped imaging device(s); and the width of the slit- or slot-shaped imaging device(s).
The invention also provides a method for imaging l ~t~
values ~u..G_.u...ling to respective pixel positions within a pixel array 2û such as, for example, charge values I 1 Flt~orl for respective pixel positions of an imaging device as defined above, the method comprising:
- determining maximum and minimum ~ tF.~l values for pixels within an area of the pixel array to be imaged;
- assigning grey scale or colour values at extremes of a grey or 25 colour scale to be imaged to the maximum and minimum 9' 1 ~It~f values; and - assigning grey scale or colour values to the Ml 1 At'Pd values for individual pixels scaled in accordance with the extreme values; and - imaging the assigned grey scale or colour values at respective 30 image pixel positions.
In other words, for each portion of an image captured by an imaging device in ~c.uldG -ce with the invention, the charge density of all pixels to be displayed is compared, the points of highest and lowest charge density being assigned a colour value at the two extremes 35 of the grey or colour scale being used. The remainder of the pixels points are given a value from the grey or colour scale according to the charge, 19tF.tl in the respective pixels.

~ W0 95/33332 2 1 ~ 1 i 0 0 The invention also provides a method of automatically optimising imaging using, for example, an imaging system as defined above for different imaging ~rp~ tinnc where incident radiation leaves a different electrical signal in a pixel detector of a cPmi rnnrll~rtnr 7 substrate dependent on a semiconductor material or compound used and an energy and a type of incident radiation, the method comprising:
- determining an expected best resolution using a centre of gravity technique;
- determining an expected efficiency as a function of radiation type and energy; and - ~PtPrm;nine a pixel size and thicxness as a function of a selected radiation type and energy and a selected sPmirnntl~lrtor material or compound.
This method can also include a step of autn-~t;r~lly selecting an imaging device having the det~rmined pixel size and thicxness.
This method enables automatic optimicAtinn of the image processing for different imaging ~rrlirqtinnc where, dependent on the sPmi~rnn~rtor material or compound used, incident radiation leaves a different electrical signal related to the energy and type of the incident radiation. In accordance with this method, the expected best rPRnl~tinn is identified using a centre of gravity technique whereby each step of the radiation inside the spmirnnrl~rtnr is weighted by the energy loss or equivalently by the charge signal created in the step.
Therefore resolution is determined as an average weighted by charge.
Similarly, an expected efficiency is determined as a function of radiation type and energy . For each ASID CPmi rnnrl~rtor material or compound a database provides values for the various radiation types and energies, thus allowing an immediate and automatic opt;mi71~tinn Of design specifications.
The invention also provides a method for autn-^tir~lly detecting and ~l imin~t;ne detected pixel values representative of radiation incident on a pixel cell of an imaging device, for example an imaging device as defined above, the method comprising:
- comparing the detected pixel value to a threshold value related to a minimu_ detected charge value expected for directly incident radiation and - discarding detected pixel values less than the threshold value.

Wo 95/33332 ~ ~ 91 1 ~ PCTIEP95/020~6 Thus this aspect of the invention enables incident radiation (in particular low intensity radiation~ that has been scattered before entering the imaging device to be eliminated before processing. This is done by discriminating the detected radiation according to the 5 energy deposited in the form of electrical signals. Because scattered radiation has lost some of its energy it will not pass the minimum energy cut-of f .
Another aspect of the invention also provides a method for performing real time imaging of an organic or inorganic ob~ect. the 10 method comprising:
- irradiating the object using a radiation source that produces X-rays . r-rays . ~-rays or Q-rays;
- detecting at a sF~mi rrnr~ tor imaging plane or planes of an imaging device as defined above unabsorbed radiation or radiation that is 15 emitted from selected areas of the ob~ect. whereby charge resulting from incident radiation at respective pixel cells of the imaging device is P~ l PtPd in respective active circuits of the pixel cells;
- addressing the active circuits of the pixel cell individually for reading out ~ 1 PtP~1 charge;
20 - processing the read out charge to provide image pixel data; and - displaying the image pixel data.
Thus, in addition to providing a new imaging device, the invention also provides systems utilizing the imaging device. In a first preferred configuration the imaging pixels are arranging in an M
25 X N matrix where M and N can be several thousands thus providing a full field imaging plane. In another preferred configuration the imaging pixels are arranged in a slit or slot shape with several thousand rows ~nd a few columns per row. The slit or slot is moved at a constant speed over a surface to be imaged and the slit (or slot) frame is read 3O out fast enough so that the distance scanned between ad~acent frames is smaller than half the pixel size along the direction of motion. With this configuration and mode of operation it is possible to achieve a point resolution along the direction of motion which is equal to the pixel size in the same direction. Thus, it is possible to improve by 35 a factor of 2 the position resolution obtained with a full field imaging plane or a conventional slit or slot not operating in the mode described. In another preferred arrangement several of the above slits ~ W095133332 2:1 91 1 00 PCr/EP95~020~6 (or slots) are arranged on the same plane parallel to each other and with a constant distance between the longitudinaI axis of the slits (or slots). Thus, if there are n such slits (or slots) and the total distance to be scanned is X cm then each slit (or slot) only needs to 5 scan X/n cm. This will reduce the need for high speed scanning mechanics, and the same image can be formed for a unit period of time with the X-ray source operating at a lower current (n times lower current that with a single slit/slot).
The invention also provides a method of operating an imaging 10 device or imaging system as defined above comprising readi~g the Ar_ lAtPfl charge from individual pixel circuits at a rate to optimise the rPcnllltinn of an analogue to digital converter for conv~rting analogue accumulated charge values into digital values.
The invention also provides methods to utilize the device and 15 system as described.
Thus, the invention provides active ~ lAtive analogue imaging of directly detected high energy rays as opposed to conventional digital imaging techniques based on the counting of hits. According to the invention, a charge (or current or voltage equivalent) value is 20 ~ 1 AtPli rather than a number of points, the charge value being in direct and linear ~U..P,.~ ,, P with the total energy of the initiol rays. CCDs can only provide direct imaging at very low energies (near the optical spectrum). For high energy ArrlirAtinnC (X-rays above lOkeV) CCDs are operated in con~unction with converting screens that 25 convert high energy rays to optical wavelengths to which CCDs are more sensitive. During that process light generation and diffusion substantially worsen the image contrast and resolution. In addition, CCDs are, for all practical purposes, limited to i .lPmPntfltinn with Si only. It is however known that Si is a relatively low density material 3û with very low efficiency for detecting rays with energy above a few keV .
In a~uLd6-l~e with an aspect of the invention, a metl~od is provided for Arr~ l AtinE charge into an image to provide the highest AttAinAhlP contrast and resolution for a given portion of the image.
35 For every portion of the image this can be done by comparing a charge density of all pixels. The point of highest and lowest charge density can be assigned a colour value of the two extremes of the grey or W095/33332 21 9 1 1 0~3 P( l/r~ n~

colour scale that is used. The rest of the points are given a value from the grey or colour scale according to the charge (or current or voltage equivalent) accumulated for those pixels.
The invention also provides a method for m;n;m;~;ne the effect on 5 image resolution of rays that have been scattered before entering the imaging device. Accordingly, when the mode of active, A~ lAtiVe analogue imaging of directly detected rays is effective, the scattered rays will have a much smaller weight in the contrast scale since they will have deposited much less energy in the i~aging device. The 10 deposited energy CULL.~.,UU~Idb to a charge value (or current or voltage equivalent) that, for unscattered rays, is much higher. Thus, when during image proces8ing each pixel is assigned a colour or grey scale value according to the charge value . ~ 1 At~l, the effect of scattered radiation can be minimised.
The invention also provides a method for excluding rays that have been scattered, either coherently or incoherently, before entering the imaging device. A slot technique is used to this effect with a cnl1ir~t~l ray source which is adjusted to emit rays which are aimed at an imaging slot. By optimising the distance separating the ray source from the object under observation, the distance separating the object under observation from the imaging slot and the width of the slot a geometry can be ~terminPd which minimises the detection of scattered rays. This is a result of scattered rays "seeing" a small phase space and having "no reason" to enter the thin imaging slot. This method is particularly powerful as it is a geometric technique and does not require knowledge of the energy of the rays. Scattered rays, whether they have been scattered incoherently and have lost some of their energy (Compton scattering) or coherently and have preserved all their energy (Rayleigh scattering) will most likely not be detected.
3û The invention also provides for excluding from detection radiatiûn which has been scattered before entering the imaging device in low intensity Arr1icAtinnc. Through the use of a threshold to eliminate detected radiation with an energy below a ~ .,..;n~1 value, energy which has been scattered incoherently and has lost some 35 of its initial energy can be ~1 ;m;nAtr~i from detection.
The invention also enables the automatic optimi~-Atinn of a particular configuration for each imaging Arr11rAt1nn A different 2l 91 l 00 Wo 95/33332 ~ PCT/EP9~/020~6 electrical signal will be deposited in d~ d~ upon the s~mi rnnr~l~rtnr material used and the type and energy of the radiation.
An expected best resolution can be found using a centre of gravity method. An expected efficiency as a function of radiation t~pe and energy can also be determined. For every sPmiirnn~lrtor pixel material or compound a data base can provide values for various radiatioll types and energies, thus allowing an immediate and automatic optimi~ ~inn Of the design specification.
An imaging device or an imaging system as defined above can be used for conventional X-rays. for chest X-rays, for X-ray _ ~rl-Y.
~or X-ray ' _ C~lly, for computerized ~ ly, for X-ray bone ~pncil LLY, for y-ray nuclear radiography, for gamma cameras for single photon emission computerised t~ lly (SPECT), for positron emission i ,, cl~l.y (PET), for X-ray dental imaging, for X-ray panoramic dental imaging, for ,6-ray imaging using isotopes for DNA, RNA
and protein S~r~ nrin~, hybridization in situ, hybridization of DNA, P,NA and protein isolated or integrated and generally for ,e-ray imaging and autoradiography using chromatography and polymerars chain reaction, for X-ray and y-ray imaging in product quality control, for non-destructive testing and monitoring in real-time and online, ~nd for security control systems and real-time imaging using radiation, including light.
Exemplary embodiments of the invention are described hereinafter by way of example only with reference to the I , ying drawings in which:
Figure 1 is a schematic block diagram of an imaging system including an embodiment of an imaging device in accordance with the invention;
Figure la is a schematic representation of a FET;
Figure 2 i5 a schematic circuit diagram of one example of a pixel circuit for an imaging device in accordance with the invention;
Figure 3 is a schematic diagram of part of an imaging array and control electronics for an imaging device in accordance with the invention;
Figure 4 is a schematic circuit diagram of part of an imaging array and control electronics for an imaging device with blocks of pixel cells of an imaging device in accu-d~l.~ with the invention;

WO 95/33332 2 ~ ~ ~ 1 0~ PCTIEP95/02056 Figure 5 is a schematic diagram showing a plurality of imaging devices tiled to form a mosaic of imaging devices in accordance with the invention;
Figure 5A is a schematic diagram of part of the control electronics for an embodiment of the invention comprising a plurality of imaging devices tlled to form a mosaic;
Figures 6A-6C are schematic diagra_s of an imaging device in the form of a tile;
Figures 7A-7D illustrate an example in which two imaging planes are located on opposite sides of _n object to be imaged in accordance with one arrl;rAt;nn of the invention;
Figure 8 is a schematic circuit diagra_ of another example of a pixel circuit for an imaging device in accordance with the invention;
Figures 9A and 9B are schematic block diagra_s of parts of an imaging array and control connections, respectively, for the ~ ~ mrnt of Figure 8;
Figure. 10 is a ~Lu~ O_~lon view of part of an cxample of an imaging device in accordance with the invention;
Figure 11 is ~ schematic circuit diagram of another ex~ple of a pixel circuit for an imaging device in accordance with the invention;
Figure 12 illustrates an imaging technir~ue in a~.uLd~ with the invention using a slit- or slot-shaped imaging device;
Figure 13 illustrates the optim;cAtinn of p~L L~.~ for a slit-or slot-shaped imaging device to reduce the effects of srAtt~ring; and Figure 14 is a schematic illustration of the passage of ,~-rays through silicon.
Figure 1 is a schemat~c repr~cPntAr;nn of an exa_ple of an Arpl;rAtinn for an imaging system 1û including an ~mho~7im~nt of an imaging device in accordance with the invention.
This Arrl irAt1nn relates to radiation imaging of an o~ect 12 subjected to radiation 14. The radiation may, for example, be X-ray radiation and the object 12 may, ïor example, be a part of a human body .
The imaging device comprises an Active-pixel SPmi rnn~ rtor Imaging Device (ASID) 16 comprising a plurality of pixel cells 18. The imaging device detects directly high energy incident radiation such as X-rays, y-rays, ,~-rays or a-rays and Ar, lAt~C at each pixel cell, by WO9S133332 2 1 q 1 1 o~ r~ n~6 .

means of a randomly Arr~QQihl~, active. dynamic pixel circuit on or adjacent to a ~u.-~rullding pixel cell detector, values representative - of the radiation inciaent at that pixel cell.
The ASID csn be configured as a single ~Pml rnn~ rtor substrate (e.g., silicon) with each pixel cell comprising a pixel detector 19 and an active pixel circuit 20. Alternatively, the ASID can be configured on two substrates, one with an array of pixel detectors 19 and one with an array of active pixel circuits 20, the substrates being mPrhAnirA1ly connected to each other by, for example, conventional ' , bu~lding technology.
~ach pixel cell 18 is in effect defined on the substrate by electrodes (not shown) which apply a biasing voltage to define a detection zone (i.e., the pixel detector 19) for the pixel cell 18.
Active pixel circuits 20 in the form of electronic structures (e.g., of transistors, capacitors, etc.) can be defined on each pixel cell 18 or at a ~u~ a~ull~ing location on the associated second substrate to ACI lAtP charge created in the pixel detector when, for example, a photon or a charged particle of radiation is incident on the dep].etion zone of the pixel cell 18. An active pixel circuit 20 and the pixel detector 19 can be of the order of a few tens of microns in size ~e.g., 10-50um). Examples of active pixel circuits are described hereinafter with reference to Figures 2, 8 and 11.
As mentioned above the active pixel circuits 20 can be Culla ~L u~ integrally to the sPmi rnnl1llrtor substrate 16 on the pixel cells 18 as part of the cPmi rnn~lrtor processing. Special processing tPrhnir~-lPq can be employed for integrating the pixel circuits on the same wafer with the detecting pixels. Alternatively, the active pixel circuits 20 can be constructed on a second wafer and distributed to ulld to the pixel detectors 19 defined for respective pixel cells 18 on a first wafer. The two elements can then be connected together in a known manner using, for example, bump bonding so that the active pixel circuit 20 for each pixel cell 18 is located ad~acent to (behind) and overlies the ~u~Lea~ull~ing pixel detector 19 for that pixel cell 18.
The pixel detectors 19 are formed with a depletion zone such that, when a photon is photo ~u-bc:.l in the Q~m1rnn~l~rtnr substrate 16 at a pix~l cell 18 creating an electric charge or when a charged .. .. .. .. . . .. .. . , ... _ _ .. .. . . . . . . .. . . . .

WO 95t33332 2 ~ 9 1 1 0 (~ 70r~ ~

radiation ionizes the depletion zone of the semiconductor substrate 16 at a pixel cell 18. an electric pulse flows from the sPmir~nn~l~1rtor substrate depletion 70ne to the active pixel circuit 20 for that pixel cell 18. A value Aqqnri Ato 1 with the electric pulse is then Al 1 AtPd in an active circuit element, either directly as a charge value or as an equiva+ent voltage or current value such that new charge created from subsequent incoming radiation is added rnntin-lrllcly, Examples of possible 1Atine devices are an integrated capacitor or the gate of an integrated transistor. The charge P' 1Atinn process in an active pixel circuit 20 continues until control signals are issued from control electronics 24 to start a process of reaaing out information by addressing each pixel cell, effectively in a random access manner, from each individual Fixel cell. During readout of the Al l Atorl charge values, charge continues to be P~ 1 AtPr~ because the resdout is alweys done individually for detecting pixel cells.
Pixel circuits may selectively be reset after readout to discharge the charge or, llRtinn circuit elements, and only then are pixels inactive for a very short time (practically no dead time as will be shown).
Thus, only during resetting are individual pixels inactive.
Figure la shows the charge A~ lAt~nn principle of one example of a pixel circuit charge Al lAt,inn element in accordance with the present invention. In this example a field effect transistor is formed on a Com~rnn~l~rtor substrate. Specifically, n+ doped regions 4 and 6 are formed for the source and drain, respectively, in a P-type siiicon substrate 1. Electrodes for the source 3 and drain 5 are formed in an oxide layer 2, a gate electrode 7 being formed over the oxide layer 2.
Charge is o~ l Atorl on the gate electrode 7 of a field effect transistor (MOSFET) by virtue of the FET gate capacitance. As charge r lAtPq on the FET gate it decreases the electron concentration in the FET inversion layer 8 ( the layer with minority-electron carriers needed for the FET operation). The maximum charge that can be r 1 At~l depends on the minimum allowable electron density in the inversion layer. The charge A- lAtinn is therefore not affected by any dark current coming from the bulk silicon as in the case of a CCD, because charge is not Ar- 1 otor~ in any depleted volume. Charge r 1 ot~nn capacity is determined only by the total FET gate area (which can be substantially close to the pixel circuit area), the oxide W095l33332 2 ~ q 1 ~ ~ }~~ .a~Ds6 layer thickness (which can be as thin as few nm or tens of nm) and the FET dynamic range ~which determines the maximum gate voltage). It should be noted that this is just an example of a pixel circuit charge Arrl1mlllAtinn element. and according to the invention charge can be 5 Arr~l-.ll AtPd in any suitable charge Arrll-.ll At;ne device implemented in the ~ulLG:.,,ulluing pixel circuit.
The pixel pitch can be as small as lOum which resu] ts in excellent position resolution and consequently excellent image resolution .
Figure 2 illustrates one preferred example of an active pixel circuit 20 for a pixe~ cell in an example of an imaging device in accordance with the invention. This example of the invention uses field effect transistors (FETs) arranged as a cascode connected amplifier. V~IAS 40 is a bias voltage input across the depletion zone forming the pixel detector 19 of the pixel cell. The pixel detector 19 is represented by the diode symbol D11. In the pixel circuit itself, SIGûUT 42 is an analogue signal output and VANA 44 an analogue power supply input. RES-R-1 is a reset input and ENA-R-1 is an enable input for the pixel circuit. Charge is A~ lAtP~l in the gate of a transistor MllA 50 when both the RES-R-1 46 and ENA-R-1 48 inputs are low .
The gate capacitance substantially forms the input node capacitance (total capacitance) thus mAYimi7ine charge storage ability.
It is an aim of the current invention to provide maximum charge Z5 ~ lAtinn ability by m1n;m;7ine the parasitic or unwanted capacitance of all other circuit (and detector) ~ t.c and formin~
substantially all input node capacitance from the charge ~ lAt1nn transistor UllA 50. For a 35um by 35um pixel circuit the MllA 50 capacitance can be 2pF and the FET gate voltage dynamic range ca~ be at least 2Volts. This ~ULLG_~JUIl~ to about 25,000,000 electrons in storage capacity which is more than 100 times the capacity of a CCD of the same pixel size. It should be noted that the 2pF of tlle FET
capacitance in the above example substantially forms all of the input node rArAritAnrP of the pixel cell. In the above example of 35 by 35um pixels the total parasitic capacitance of the detector and the other elements in each pixel circuit and ~u,~ u..dlng pixel detector is in the range of a few fF or tens of fF. The capacitance of the charge W0 95/33332 2 1 9 1 1 0 0 P~ 0~6 $torage device should be maximized and in any case be substantially bigger than the parasitic capacitance in each pixel cell. In the example above the capacitance of the FET acting as a charge Ar l Atinz device in the pixel circuit is more than 90% of the total 5 capacitance of the pixel cell comprising a pixel detector and the ~uL~ Ull~ing pixel circuit. As a result of this, substantially all collected charge will be Arl 1 AtPrl in the charge AI 1 Atine FET
rather than being shared among the detectors, and the rest of the pixel circuit elements.
It will be appreciated that the use of a FET provides an example, only of the invention, in which example charge ~ lAting capacitance is maximised using a pixel charge storage device (such as a FET gate or a capacitor) that accounts for most of the input node capacitance for each pixel. - -To read the pixel cell, ENA-R-1 is taken to a hi~h state, which allows current to flow from the transistor MllA 50 through the tr_nsistor MllB 52 to SIGOUT 42. The pixel circuit is reset by taking RES-R-l to hi6h, whereupon after RES-R-1 has been at high for merely a few mi~Lus~unds, any A/ 1 A~'P~l charge will have been removed from the gate of the transistor MllA 50. T '~AtP~y after RES-R-l 46 goes to a low level, charge can begin to Al 1 AtP at the gate of the transistor MllA 50. If no reset pulse is supplied to the reset input RES-R-1 46. then it is to be noted that a reading operation when the enable input ENA-R-1 goes high does not destroy the charge but instead merely causes a current flow directly proportional to the A~ 1 AtP~
charge. This allows multiple readings without resetting.
Figure 11 illustrates a further example of an active pixel circuit 320 for a pixel cell in an example of an imaging device in a~,~.uL.I~.~ with the invention. This example is similar to the example 3û of Figure 2. The pixel detector is represented at PD 319 of the pixel cell. In the pixel circuit itself, VBIAS 140 is a voltage bias, ûUT
342 is an analogue signal output, RESET 346 is a reset input connected to a reset FET 347 and ENABLE 348 is an enable input connected to an enable FET 352 for the pixel circuit. Charge (electrons) is (are) A~ 1 AtPli in the gate of a charge storage FET 350 when the ENABLE 348 input is low and the RESET 346 input is high. To read the pixel cell, ENABLE 348 is taken to a high state, which allows current tû flow from ~ W095l33332 2 1 q ~ 1 ~0 F~ l/r~ ~ 71~

the FET 350 through the FET 352 to OUT 342. The pixel circuit is reset by taking F~ESET to low, whereupon after RESET 346 has been at ~ow for - merely a few mi.. use~u-~ds, any accumulated charge will have been removed from the gate of the FET 350. r '-AtPly after P,ESET 346 goes to a high level, charge can begin to A~ lAtP at the gate of the FET
350. If no reset pulse is supplied to the reset input PESET 346, then it is to be noted that a reading operation vhen the enable input ENABLE
goes high does not destroy the charge but instead merely causes a current flow directly proportional to the A,l lAtPtl charge. It will therefore be seen that the operation of the circlmit of Figure 11 is similar to that of Figure 2. In addition, the circuit of Figure 11 includes diodes 354 and 356 which act as overload protection circuitry for the pixel circuit. The diodes provide protection both against static electricity which might damage the FETs and against FET
overload. If the FET gate 350 Al 1 AtPq more than a predetermined charge threshold (e.g., ~u--~ ullding to 5 volts, which is the voltage bias) then current will start to flow through the diode 356 towards the ground thus protecting the FET 350. This will protect pixel cells which, for example, receive a full radiation dose outside the perimeter of an object to be imaged. Preferably the two FETs 350 and 352 are i 11 rP~3 as a cascode amplifier stage. In this configuration the two FETs 350 and 352 provide impedance-up conversion without increasing the noise accordingly. Consequently, the noise level from each pixel circuit described in the current embodiment is only about 500 e while the pixel circuit retains very small size (as small as 10-20~m pixel size), very large dynamic range of about 50,000,000 e and individual addressabili ty .
Figure 11 also illustrates an optional bipolar transistor 36û, which may be omitted. The purpose of the bipolar transistor, with its cornection to a voltage source VBASE, will be described later.
Figure 10 is a schematic illustration of one embodiment of an imaging device in a~u-P.~I~ with the invention. The imaging device illustrated in Figure 10 comprises a pixel detector substrate 214 with the active pixel circuits formed on a second~ substrate 212 which is connected to the pixel detector 214 by means of microbumps 222. The active pixel circuits 20 are s ' ti~'Ally represented within the substrate 212 by means of the symbol of a FET.
_ _ _ _ _ _ _ _ _ _ _ _ , . . .. .... .. . ., _ .. _ _, .. _ .. .. . .... , . _ _ _ Wo9SJ33332 2 1 9 1 ~ ~O .~ 0~6 The pix81 detector substrate 214 is provided with a rnntin-lm~c electrodeilO on the site of the substrate which is exposed to incident radiation. In other words, in Figure 10, the incident radiation is assu~ed to arrive in an upwards direction. The body of the pixel detector substrate 112 thus lies behind the continuous electrode 110.
On the rear surface of the layer 112, a plurality of pixel detector electrodes 114 are provided. It is the array of pixel detector electrodes 114 which effectively defines the individual pixel aetector cells 19 within the pixel detector substrate 214. Each of the pixel detector electrodes 114 is electrically and mPrhAn~ ly coupled to a respective pixel circuit 20 by a respective microbump 222. It will be appreciated that the representation in Figure 10 is highly schematic, and not to scale.
In addition to the features alreadY described above, Figure 10 also illustrates optional features which can be used for isolating individual pixel circuits in a manner to be described below.
For different detector pixel cells the .u,, ~_,,ul~ding charge storing FETs 350 may ~ llAtP different amounts of charge as a result of the different radiation or light intensities incident upon the detector pixels. Consequently a potential difference is created between adjacent pixels. IP the pixels are not electrically separated this potential drop may cause signal charge to leak from one pixel circuit through the detector and into the neighbouring pixel circuit.
The longer the A~ lAtinn time, the more severe the problem could be.
In accordance with a preferred asPect of the invention, this effect is ~mlnil;hP~1 or PllminAtP~ by providing means for electrically separating, or equivalently r~Timi7ine the resistance of ad~acent pixel cells. Accordingly, a passivation layer 116, for example of polyamide, is applied between detector pixel cells (i.e. between the electrodes 114 that define the detector pixel cell). This electrically separates adjacent detector pixel cells since such a passivation is non cûnductive. Additionally, electrodes may be applied on the passivation layer and an applied voltage V will create a barrier potential 118 penetrating several micrometres inside the detector volume. Thus charge attempting to escape from the charge Al lAting~ FET in a pixel circuit 20 will encounter the barrier potential and will not be ~1~cclrAtpr~ into the adjacent pixel circuit FET.

~ WO 9~l33332 2 1 9 1 1 3 0 P~lfr~ n~6 FUL LIIVL_~JL~ a third option is to provide an npn transistor (bipolar transistor) at the entrance of each pixel circuit. This is - shown in Figure 11. When the base of the bipolar transistor is set at an appropriate voltage common to all bipolar transistors of the pixel S circuits (about lV) the bipolar transistor will act as a diode allowing charge to flow into the gate of the FET 350 but at the same time prohibiting any escape along the reverse path. In this way, while maintaining different potential drops at the gates of the charge Arrl lAtinf~ FETs 350 (proportional to the different signal charges that have been i lAtPrl), the potential at the entry of the pixel circuits is common to all pixel circuits. Thus. in accordance with this aspect of the current invention, means are provided to PlPrtrirAl1y separate pixel cells in the imaging device so as to retain all or substantially all charge r 1 Ate~i on each pixel circuit.
This preferred aspect of the invention is particularly useful when accumulation times are rather long, for example in the range of tens or hundreds of mi~Lvl,e~vll-la and even more useful when A~ 1 Atinn times are in the range of msec or tens or hundreds of msec.
A pixel circuit 20 can r 1 AtP an electric charge representative of up to 60,000,000 electrons on each pixel while maintaining a pixel size less than 50um by 50um. The pixel thickness or portion of the pixel detector that is fully depleted can be up to 3mm, thus making these detectors very sensitive to X-rays with energies less than 200keV. For charged radiation the sensitivity is practically 100%. The minimum pixel thickness can be of the order of 200um which can give improved resolution when lower energy charged radiation is to be detected. The dead layer of the qPmi rnn~ rtor substrate which is insensitive to radiation can be as thin as 50nm so that a signal from ,~-radiation with energies less than 30keV is not lost.
Figure 3 is a schematic reprPqPntAtinn of one possible configuration of the control electronics 24 of Figure 1 and the rPl Atinnqh1r of the control electronics 24 to an m x n matrix of the active circuits 20 of the pixel cells 18. For ease of iilustration an array of 9 pixel cells is illustrated in Figure 3 and only some of the signal lines which make up the path 22 in Figure 1 are shown. It will be appreciated that an imaging device in accordance with the invention will normally include a significantly larger number of pixel cells than ~ . . .. .. . ....... . ..... , _ .. . , . .. . .. .. . . _ . _ . , ... . _ ... , .. _ Wo 9s/33332 2 1 9 1 1 3 0 PCT/EP~S/02056 are shown in Figure 3. The row select logic 60 cortrols the row readout (ENA 74) and the row reset (RES 76) and the column logic 62 enables (COL-SEL) the readout of Al 1 AtGrl charge values from each pixel circuit ZO in response to a clock signal 79.
The control electronics 24 include row select logic circuits 60, column address logic circuits 62, power supply circuits 70, Analogue to Digital Converter (ADC) 56 and the signal processing circuits 58.
Preferably some, if not all, of the control electronics 24 is implemented on the substrate 16 et the periphery of the image array formed by the array of pixel cells 18.
The power supply circuits 70 provide power for the individual active circuits 20 on the pixel cells 18 via lines 54 (shown ~rh~.mAtirAl ly in Figure 3) and can additionallY be arranged to supply the biasing voltage via lines (not shown) for the electrodes defining the pixel cells.
The row select logic 60 provides signals via row enable and reset lines 64 and 66, respectively (also shown sl~' -t;rAl1y in Figure 3), for selecting columns for the reading and resetting, respectively of the individual active circuits 20 of the pixel cells 18. The row select 64 and row reset 66 lines are connected to the enable input ENA-R-1 48 and the reset input RES-R-1 46, respectively of each of the pixel circuits of the row. Also shown in the row select logic 60 are row enable 74 and row reset 76 signals for scanning successive rows.
It can be seen that the reset pulse 76 follows the row enable pulse 74 to cause resetting of the active circuits after reading.
The column select logic 62 effectively comprises a 3ultiplexer for selecting signals output via the column lines 68 (also shown 6-' tirAlly in Figure 3), each column line being connected to the SIGOUT output 42 of each pixel circuit 20 in that column. The COL-SEL
signal 78 represented in the column select logic 62 thus selects columns for reading the individual active circuits 20 of the pixel cells 18 currently selected by the row enable pulses 74. In the embodiment shown the column select pulse is clocked for successive column positions in response to the clock CLK 79 during one row enable period, so that the r lAted charge value of a respective active pixel circuit on the row currently selected is clocked out at each clock pulse before the row select pulse proceeds to the next row. Each ~ W09513333~ 2 1 9 1 1 0 û PCTÆP95/02056 active pixel circuit of the row ~ust read is then reset simultaneously, by the row reset pulse 76.
The rnnnr~rti nnC shown in Figure 3 are readily realisable using conventional double metAl1icAtir~n technology, Although, as described with reference to Figure 3, the pixels are read out sequentially in a inPrl order, it will be appreciated that the pixels are in effect accessed in a random access manner by means of separate row and column enable signals. It will be appreciated also that the scanning direction could be reversed ( rows to columns ) or indeed individual pixels could be accessed in a totally random order by suitable row and column enable signals. It will also be appreciated that the degree of sequential or parallel processing can easily be modified to match the needs of each ArrlirAtinn. For example all rows can be set simultaneously at an enable high state so that the column select clock will output in parallel all rows, thereby increasing the readout rate.
The resetting of rows need not match the readout rate. After multiple readings each row may be reset at a lower rate than the readout rate.
It will be apprecIated that the rlr~ci~nAtinn of rows and columns is arbitrary and can be reversed.
To cover a very large imaging surface in an effective way, the pixel cells _re preferably grouped in blocks of m x n pixels with the pixels within a block being read out and reset cDql~rntiAlly in rows.
Figure 4 is a schematic diagram showing a block of two rows by four columns of pixel circuits 20. The pixel circuits r lAtr~ charge on the gates of the transistors MijA, where i=1,2 and ~=1,2,3,4. In order to keep the transistors at a low potential, each gate is grounded after reading. Readout is initiated by applying a clock-pulse train to the CLK input 80, and a one clock period high (read bit) to an RB-IN input 82.
During the first clock period the RB-IN input 82 enables the switch sw4, which connects the analogue output line 68 for the fourth column to the analogue output ROUT 88. Thus, when the row enable input ENA-R-1 for the first row is high, which opens the switch transistors Ml~B 52 of the first row, during this first clock period, a signal current representative of any charge stored on the gate of the transistor M14A 50 of the pixel circuit 20(1,4) flows through that tr~nsistor and via the switch sw4 to the analogue output ROUT 90.
. _ _ . .... , , _ WO 9_/33332 2 1 9 7 7 0 ~ r~~ ~.. 6 By the next clock period of the clock CLK. the RB-IN input must be down. The high state, originally at the input of a flip-flop Ul is clocked by the clock train CLK to the input of a flip-flop U2 and switch SW3 which then connects the analogue output line 68 for the 5 third column to the analogue output ROUT 88 so that a signal current representative of any charge stored on the gate of the transistor M13A
50 of the pixel circuit 20(1,3) can flow through that transistor and via the switch SW3 to the analogue output ROUT 90. Because the sw4 is now low (down) the analogue output line 68 for the fourth column is 10 discull.le.L~d. The read bit thus ripples through the switches sw4-swl and flip-flops U1-U4 for successive clock pulses of the clock CLK. The column enable flip flops U1-U4 form a first shift register.
When the read bit is clocked out of the flip-flop u4 it is clocked back to the flip-flop U1. It is also clocked to the clock inputs of row-enable logic U5-U7 and row reset logic U9-U11. Each time these receive a clock input from the output of flip-flop u4 they advance a read bit and a reset bit, respectively, the reset bit moving one step behind the read bit. The row enable logic flip flops U5-U7 form a second shift register and the row reset flip flops U9-U11 a third shift register.
In this way, each time a row is read out, the read bit is moved up one row. Similarly the reset bit is moved up one row, but one row behind the read bit. When the reset bit is read out of the last flip-flop U11, it is supplied to the read bit out ~BO output 84 and a new read cycle can be initiated. The time between successive read operations should be sufficiently short to keep the gates of the transistors MijA with relatively small potential differences, preferably potential differences below 2V from the reset potential (or potential of zero charge A~ lAtirm).
In another preferred embodiment of the invention, the same functions shown in Figure 4 can be implemented with a counter that produces row and column addresses which can be decoded to the same control signals as in Figure 3, COL-SEL 78, RES 76 and ENA 74.
The storage CaPaCitY of the transistors MijA depends upon the capacitance and the voltage on the gate of the transistor. The transistorg Mi~A can withstand up to lOV, but it is desirable to keep the gate voltage well below this at up to about 2V potential difference W0 95~3333~ 2 1 9 1 1 0 0 ~ 7n~
from the reset potential. The gate capacitance can be up to about 5pF
for pixel sizes below 50um by 50um. This means that 6x107 electrons can be stored. This is about 86 times the capacity of a CCD whic~ stores charge within the storage well within the substrate.
To appreciate the advantages offered by an imaging device according to the invention, consider a single imaging device of ncinnc 2cm by 2cm. If the pixel size is 35um by 35um then the imaging plane comprises 571 rows by 571 columns of pixels. Accordingly if the imaging device is an ASID then the total of 326.041 pixels can be read out every 32msec with a multiplexer clock rate of lOMHz. Thus.
in this example with just one readout channel, one frame will be displayed every 32msec offering real time imaging. Since the pixel circuits have a charge storage capacity of tens of millions of electrons. an ASID can indeed cope with the highest foreseeable intensity applications. This is done at the expense of neither image spatial resolution (pixel size in this example is 35um) nor dead and inactive imaging time. Indeed each row of pixels can be reset ~ AtP1y after readout for a$ long as the readout of the next row la$ts (readout cycle wa$ explained in a previous paragraph). This row readout time is lOOnsec times the number of pixels per row, i.e. 57.1 micro seconds. Then, over a 3~mCPrnn~lC image frame acquisition time, the inactive time is just 57mi~use~un~a or 0.17%, which is practically no dead time. Therefore an ASID achieves high spatial resolution. real time imaging with 32msec image frame updates, very high dynamic range, practically no dead time, very low electronic noise and is despite all that in a co$t effective manner by reguiring only one readout channel in this particular example. Also by directly accessing every pixel circuit, it is trivial in an ASID to store a calibration image frame with individual pixel pedestals stored and auLL-~,l.t-l from every ~ l RtP~ image frame. This calibration run can be done in a real time imaging RrrlirRtinn evcry few second$ or more rarely since the pedestals and very low noise level in an ASID remain stable.
Figure 8 is a circuit diagram of a further example of an active circuit 20 for a pixel cell 18 in accordance with an pmho~imPnt of the invention.
The pixel detector 19 is represented by the diode symbol 182 (the detector may alternatively act as a resistor) cornected to the voltage , _ . . . . . . . .

WO9s/33332 2 1 9 ~ 1 0~ PCTIEP95102û56 bias Vbias 180, this being applied via the electrode (not shown) defining the depletion volume or pixel detector 19 of the pixel cell 18 .
Charge created by radiation incident on the depletion volume 19 5 of the pixel cell 18 is input to the base of a first, input transistor 184 (here a field effect transistor (FET) having a l,L~.sLu..Luc~ance of, for example, û.3mS and a drain source current value IDS f lOOuA and a capacitance of 0 . lpF) . The source and drain of the input FET 184 . are connected between a first current source 186 (here a suitably configured FET, although this could be replaced by a resistor) and a ground line GND 174. The current source 186 is in turn connected to a positive supply line V~ 172.
The junction oetween the input FET 184 and the current source 186 is connected to one terminal of a second transistor 188 forming a common base bipolar amplifier ~ontrolled by the bias voltage applied to its base. The base of the second transistor 188 is connected to the bi~s voltage line V" 178. The remaining terminal of the second transistor is connected via a feedback capacitor Cf 190 (e.g., with a capacitance of 0.3pF) to the base of the input FET 184.
The ~unction between the second transistor 188 and the capacitor Cf 190 is also connected to a second current source (here a suitably configured FET, although this could be replaced by a resistor) to a negative supply line V- 176. Charge resulting from radiation incident on the depletion volume of the pixel cell can thus be Ar~ 1 AtPd at the capacitor Cf 190.
X and Y read lines, Xread 160 and Yread 164, are connected to read logic 198 (here a dual base FET) which in turn is cornected between the negative supply line V- 176 and an output switch 196 (here a FET) whereby charge collected on the capacitor Cf 190 can be output via an output line 156 when a signal is supplied on the Xread and Yread lines 160 and 164 simultaneously. The X and Y reset lines, Xreset 162 and Yreset 168, are connected to discharge logic lO0 (here _ dual base FET) which in turn is connected between the negative supply line V- 176 and a discharge switch 192 (here a FET 192) for dischar~ing and thereby resetting the capacitor Cf 190 when a signal is supplied on the Xreset and Yreset lines 162 and 168 simultaneously.

WO 95J3333~ 2 1 9 1 1 0 ~ PCT/EP9S~'02056 The circuit shown in Figure 8 forms a charge sensitive amplifier with charge storage capability in the feedback capacitor Cf 190 and with output and resetting circuitry. Depending on the charge storage time and radiation hardness requirements, the FETs can be im~lPmpntPA
5 by an appropriate technology such as JFET or MOSFET. If the capacitor Cf 190 has a capacitance of 0.3pF, this ~u..G.,,-u--ds to a storage capacity of about 1 8 million electrons. If the capacitor Cf 190 has a capacitance of lpF, this ~U1~ JUIII~ to a storage capacity of about 6 million electrons. The maximum output clock frequency with a reset 10 FET in the output line is 5-lOMHz. This maximum output frequency reduces to about 200kHz without a reset FET in the output line.
The circuitry illustrated in Figure 8 could be implemented on, for example, a pixel cell having a size of approximately 150 x 150um.
In Arrl 1 ratl nnC such as gamma cameras and angiography the pixe~ size 15 does not need to be smaller than about 150um across. In this case the additional space on the pixel circuits allows for other operations besides charge I l Atinn, read out and reset. For example, the Figure 8 ~ .-t amplifies the charge value that has been r lAtPA. Additionally, the Figure 8 ~L~~ _.It could be modified0 to provide charge discrimination of incoming radiation hits pri or to tinn on the pixel circuit. In this way incoming radiation ~u~ "u..ling to lower than expected energy can be excluded before being r 1 AteA on the pixel circuit. Around the outside of the imaging area formed by the array of imaging cells some or all of the control electronics 24 may also be implemented as an integral part of the s~mi nnnA~ tor substrate wafer 16 .
Figure 9A is a schematic representation of the control electronics 24 in more detail and the r~lAtinnchir of the control electronics 24 to active pixel circuits 20 of the type illustrated in Figure 8 on the substrate 16. For ease of illustration an array of 16 pixel cells is illustrated in Figure 9A and only some of the signal lines which make up the path 22 in Figure 1 are shown. It will be appreciated that an imaging device in accordance with the invention will normally include a significantly larger number of pixel cells 18 than are shown in Figure 9A.
The control electronics 24 include X address logic circuits 144, Y address logic circuits 146, power supply circuits 15û and signal Wo 9S/33332 2 ~ 9 1 1 0 0 ~ 46 3o processing circuits 148. Prefersbly some, if not all, of the control electronics 24 is implemented on the substrate on which the pixel circuits are implemented at the periphery of the array of pixel circuits. The power supply circuits 150 provide power for the individual pixel circuits 20 via llnes 170 (shown crhPm~tirAlly on Figure 9A) and can additionally be arranged to supply the biasing voltage via lines (not shown) for the electrodes defining the pixel cell detectors, The X and Y addressing logic 144 and 146 provide signals via row and column lines 152 and 154, respectively, (shown 10 schematically in Figure 9) for controlling the reading and resetting of the individual pixel circuits 20. The signal processing circuitry 148 i9 connected to output lines 156 shown 5rh tirAlly in Figure 9A for the active circuits 20. In the embodiment of Figure 9A, one output line is provided for each row of pixel circuits 20 and is connected via an output amplifier 158 to the signal processing circuitry 148.
However, it will be appreciated that as alternatives separate output lines could be provided for each column, or for groups of rows or columns or for groups of pixel cells/circuits as desired.
Figure 9B illustrates in more detail the signal lines which are provided between the control circuitry 24 and a pixel circuit 20 for a pixel cell 18 in accordance with this embodiment of the invention. The power supply lines 170 comprises a positive supply line V~ 72, a ground line GRD 174, a negative supply line V- 176 and an amplification power line Vq 178. The row lines 152 comprise an Xread line 160 and an Xreset line 162 and the column lines 154 comprise a Yread line 164 and an Yreset line 168. One output line is provided for each row in this embodiment as has already been explained.
The pixel circuits shown in Figures 2, 8 and 11 along with the cnnnF~ct;nnc shown in Figures 3, 4, 9A and 9B can be impl ~,ed integrally on one s~mirnnr1llrtor substrate using conventional integrated circuit manufacturing ~Prhn;rll ~s or on two superimposed Sr-m;rnnrll-rtor substrates with an array of pixel detectors on the first substrate and an array of pixel circuits on a second substrate mrrhAnirAlly attached to the first, for example by ~ . bullding, with a one-to-one uuL~ rr- between pixel detectors and their ~u. L~ ul~dlng pixel circuits .
In an exemplary embodiment of the invention for use in ~ Wo 9SJ33331 2 1 q 1 1 ~

,, C~lly, each block includes 80 x 240 pixels. " _ c~ y is perhaps an Arrl;rAtir~n for the present imaging device with some of the - most stringent requirements with regard to readout speed and storing capacity. For successful ~ pl~y, 104 X-rays at 20keV in one second 5 for each pixel should be recorded. Where each pixel circuit has a storage capacity of 6x107 electrons, this means that more than ten thousand (104) X-rays can be acl latPr; on a pixel before the content of the pixel needs to be read out. It follows therefore that each pixel can for example be read of the order of 10 times per second or 10 less, which equates to a pixel read out rate of lO~z. In a block with 80 rows of Z40 pixels each, the readout time of the whole block is defined by the clock rate divided by 1~200, which is the total number of pixels in the ~lock. For a clock rate of lOMHz, which is a typical clock rate, the whole block can be read at a rate of 520Hz. As only 15 lO~z is needed for ~ a~Jlly, it can be seen that the present ~ mf~nt of the invention is capable of handling intensities of up to fifty times that required for ,, t"~hy. This redundancy offers, as will be explained shortly, the ability to multiplex together the outputs of many blocks (tiles) and minimize the total number of readout 20 channels.
One aspect to the operation of the device is the dead time, which can be defined as the time it takes to reset each row after it has ~een read out. A row of pixels can be reset in lOusec, or less. During this time the pixels are inactive. Since in one second (wllich is 25 typic~l for a mammogram) ten or less readout and reset operations are to be performed, this means that the total dead time is 0.0001 sec, or 0.01% dead t~me compared to the total time for which the imaging device needs to be active. The dead time with the present ` ~ of the invention is insignificAnt therefore, and as good as no dead time. In 30 order to appreciate how small this dead time is it is noted that the number of X-rays lost during this time (assuming 104 X-rays per pixel per second) is 104 X O.0001 (approximately 1 X-ray per pixel). This is very much smaller than the quantum fluctuation limit (100) which is the statistical error for ten thousand X-rays. Accordingly this pmhorl1rnPnt 35 of the invention operates with a performance which matches the maximum possible statistically obtainable performance.
, W0 95/33332 32 r~~ n~6 The example of a pixel circuit illustrated in Fi~ure 2 or Figure 11 can be implemented with major Aimonq;nn.: less than 35um, so that the pixel cells may be 35um square or less. Each block thus has ~im~ncinnc of 4mm x 12mm and imaging surface having an area of, for example, 18cm 5 x 24cm can be formed from a mosaic of a few hundred tiles, where each tile CUL C~.UUlld~ to a block of, for example, 115 x 341 pixel cells.
Using a tiling approach for the generation of large imaging surfaces has the advantage of high manufacturing yield. It also provides the advantage of mQdularity so that if one tile fails, it is 10 possible to replace the tile without having to replace the whole imaging surface. This mekes a large imaging array ~rAnnmirAlly viable.
Surprisingly, it is still possible to ootain good imaging quality using a tiling approach, despite the tiles comprising the blocks of m x n pixels cells and the associated circuitry and control electronics.
15 Each tile will need a minimum of four, possibly five to ten external contacts. Also, on each tile at the edge of the active image area comprising the array of m x n pixel cells, there is some inactive space where the control and logic circuits of the tile are placed. In a preferred embodiment of the invention, the tiles are therefore placed 20 in a mosaic as illustrated in Figure 5.
For use in ~ y, a dctecting plane should be of the order of 30x30cmZ. No dead space is allowed in the detecting plane. To achieve this with the aLL~Ie~ lt shown in Figure 5, the mosaic moves in two steps so that the whole surface to be imaged can be completely 25 covered by ~ 1 Atin~ three image frames. The tile shape can be substantially rectangular. The optimum length o:E the detecting (or active) area of one tile is eoual to two times the total dead space at the long sides. As, however, estimated tile alignment accuracy of 50-lOOum demands some overlapping of the active area of the tiles, the 30 tile ~im~nejnnC may not uuLL~_uulld to the optimum (iim nciAne. An example of the possible mosaic for a O,~ y ArrlirAtiAn can comprises 621 tiles, with each tile having 41760 pixel cells each of 35X35Um2, The movement of the image mosaic can be achieved using 35 conventional m~rhAni rAl arrangements with sufficient accuracy and speed. Figure 5 illuserates that sufficient space has been provided .__ . .. :_ _ _ _ _ _ . . .

-WO 9513333~ 33 1 _I/r~
for the electronics on each tile. The arrangement illustrated in Figure 5 is optimised to allow a full surface image to be produced with the three images being collected, respectively be~ore, between and after two steps of 12mm. However, it will be appreciated that other 5 , mPnts may employ variations from the layout shown in Figure 5 and that the technique dlsclosed here can be used in any PrrlirPtinn for Al- 1Ptinn of loOZ of an image.
Figure 5A illustrates a part of the control electronics for an ~imPnt of the invention comprising a mosaic of tiles, for example as shown in Figure 5.
The basic control electronics for each tile (e.g. T2) ~,UL~e.~,U~lldS
generally to that shown in Figure 3. ~owever, rather than one ADC 56 being provided for each tile (as shown in Figure 3), the outputs from a plurality of tiles (e.g. T1 - T10) are cornected via a master multiplexer MM (e.g., operating at a lOMHz - lOOMHz clock rate) to a common ADC 561 and from there to the signal processing logic, display etc. 58. The master multiplexer MM does not need to be placed on the tiles themselves, but can be located proximate thereto. The ADCs 561 are also not provided on the tiles but are preferably located nearby.
An advantage of the use of a master multiplexer is that the number of ADCs needed can be reduced, thus reducing the overall cost of the imaging system. As an alternative to Figure 5A, tiles can be daisy-chained and read out in using a single, common ADC. The high resolution ADCs form an expensive part of the overall system, so that reducing their number can have a significant effect on the overall cost. In Arrlirstinnc such as ~ ~:,ul~y~ conventional X-rays, chest X-rays, etc. wbich can include a mosaic of several hundred tiles, a minimum of about nine ADCs are needed (i.e., just nine output chaTmels) in order to provide the desired readout performance, even for high intensity qrrlirntinnc. The circuitry in accordance with the invention enables tiles to be read out in a controlled manner such that an image can be Pr lPtPrl by reading out the tiles a plurality of times. This is something that cannot be done with, for example, a CCD device. The multiple reading of the tiles enables a contrast i . u~ t in the following manner. As an example consider that 5000 X-rays are incident on a detector pixel. If the storage capacity of the pixel can handle all 5000 X-rays, it might be decided to set the readout rate to _ = _ _ _ , . .. .. , . . . . .. _ . ... _ WO 95/33332 L_ 1 9 1 1 0 0 r _ I /~A ,!;, ~

ulld to a timing for the receipt of 500û X-reys so that ana1ogue charge values for all 50ûû X-rays can be stored at a pixel and then the total r lAtPrl charge value is read out. If a lû-bit ADC (i.e. 1024 grey scales) is used every 4.88 X-rays (i.e. 500û X-rays/1û24) will then cu.L~arullds to ~ different grey scale quantisation. ~owever, if a faster readout rate i5 used, for example at a timing ~UL~ ing to the reception of 10ûO X-rays and the same ADC is used. then every 100û
X-ray/1024 = 0.97 ~ULL~:7,UUll~a to the grey scale r~lAnt~CRti~n, From this schematic example. it can be seen that the grey scale resolution can be increased by simply reading out at a higher rate.
The tprhn;qllpc described il 'AtPly above and with reference to Figure 5A enable an opt~micAtirn between cost (more multiplexing and less ADCs) and image contrast (less multiplexing and more ADCs).
Figures 6A-6C illustrate in more detail the ~ullaLLu~Lion of one example of a tile having a layered construction including a hybrid suppûrting board 210, a silicon readout chip 212 mounted on the supporting board and a pixel detector layer 214 made of, for example, CdZnTe, CdTe, ~gI2, GaAs, Ge, Si or TlBr and bump bonded to the readout chip. Figure 6A is a plan view of the pixel detector layer 214, which 2û in this example has an active surface area 216 of 19.985mm x 19.985mm.
Around the active surface area of the pixel detector layer is an inactive area including a detector guard ring 218. Figure 6B is a plan view of the detector layer mounted on the readout chip 212 and the supporting board 21û. It will be appreclated that as well as the detector Ouard ring 218, the inactive area surrounding the active detector area also includes the edges of the readout chip 212 and the hybrid supporting layer 21û and space needed between the tiles. Wire bond pads 220 on the supporting layer or board 210 permit the ~lp~tr~r~l connection of the readout chip to circuitry on the board 21û
and from there via a master back plane to image processing circuitry.
Figure 6C is a L.llav~La~ ~Lusa ___Lion of the tile showing the detector layer 214 connected at individual pixel locations to the readout chip by bump bonding 222. The supporting board is provided with an array of pins 224 for positioning and connecting the tile on a master back plane.
Figures 7A-7D illustrate an alternative to the provision of translation of a single detecting plane described with reference to ~ Woss/33332 21 91 1 00 PCr/}EPg5~02~156 Figure 5, for example fQr an Arr1irAtirn in autoradiography where the surface to be imaged emits radiation rather than an external source.
Consider an example of autoradiography where a sample is labelled with isotopes (e.g., C14. P32, P35, 532, I125, H3, etc~. and is positioned 5 as close as possible to an image detector (for example an imaging plane as illustrated in a Figure 7A. Usually the sample rests on a thin mylar layer about 1.5um thick to avoid cont. nAtiAn. If the sample is located on the imaging plane, motion of the imaging plane as described with respect to Figure 5 would not be possible. However, as a result 10 of the inactive areas around the active areas of the tiles, the active imaging area of a single mosaic layer as in Figure 7A will only provide about 85% coverage of the total area. Figure 7A illustrates some of the rli nnc for one example of a tile mosaic.
A solution to this problem as illustrated Y ' tirAlly in 15 Figures 7B and 7C is to provide a sandwich of two imaging planes DP1 and DP2, above and below, respectively, the sample OS. The second imaging plane is brought as close as possible to the first imaging plane with the sample in between, with the imaging planes para~lel to one another and slightly displaced with respect to one another. The 20 po6itional accuracy can be as good as 1-2pm. Figure 7D represents tbe dead or inactive space between the active imaging areas in the t shown in Figures 7B and 7C. The white spots represent the inactive areas with the cross hatched areas showing where the active areas overlap and the remaining hatched areas showing where only one 25 active area overlies an area of the sample. In the particular example shown, and as identified in Figure 7D, only 1.2X of the total area is inactive, 68.9% is imaged by both imaging planes (thus increasing efficiency as radiation is detected on both sides of the sample) and 29.9% imaged by only one plane. The 1.2% of inactive area can still 30 be covered by orrAC~nnAlly lifting the upper plane and rlicr1Ar1n~ it slightly along the diagonal, for example.
Ideally, in autoradiography, image surfaces as large as 42cm x 39cm are needed. With tile ~ironc~nnc as mentioned above, and 35um x 35um pixels, 98.8% of the total area can be covered with 578 tiles.
35 Only 40 ADCs or less would be needed if the tiles are multiplexed together as described elsewhere herein . Using these t~rhni q~ C a new total image could be generated and displayed every 3 seconds. This W095/3333~ 21 ~ r~ 6 ~

application of t~le invention can give practically 4 n coverage of a sample increasing overall efficiency, real time imaging, a spatial resolution of 35~um and a dynamic range of 6 orders of magnitude.
Thus this alternative ~ ,U~ t, which is suitable for use in 5 applications where the object to be imaged includes a source of radiation, is to provide first and second detecting planes arranged substantially parallel to one another and spaced from one another with an object source to be imaged between the detecting planes. By arranging for the tiles of the respective imaging planes to be offset 10 laterally with respect to one another, it is possible to obtain substantially complete imaging of an ob~ect where the radiation from the ob~ect is substantially the same towards both planes.
Other configurations of imaging devices can be used in different Arrl~r~tinnc. For example, for computerized ~ y ~rr1irAtinnq, 15 the imaging devlces aFe arranged substantially ~An~nti~lly around the periphery of a ring or part-ring to encircle or partially encircle a slice of an ob~ect to be imaged. The imaging devices could also be arranged substantially tangentially around the periphery of a plurality of rings or part-rings displaced from one another in the direction 20 forming a common axis of said rings or part-rings in order to image a plurality of slices of the object. In other :Irrlir~tinnc such as non-destructive testing and real time monitoring the imaging deYices could be tiled together to form a mosaic matching the area and shape of an object to be imaged and/or to form a mosaic surrounding part or all of 25 an object to be imaged.
Rather than arranging pixel cells in a largely rectangular array, in other embodi~ents of the invention, the imaging device could be configured as a slit with pixel cells arranged in a single column or a slot with pixel cells being arranged in a number of columns side by 30 side. A slit or slot can be used in many Arrli~innc such as radiographic body scanning, dental panoramic imaging, security scanning, etc. The use of a slot can also be used as an alternative to full field scanning with the advantage of lower cost because of the lower imaging surface. In the case of a slit or a slot having one or 35 two rows of pixels the pixel circuits could be located to the side of the cuLL~_,L,u~ ng pixel detectors on the same s~mirnn~ rtor substrate rather than behind the pixel detectors on the same or a different ~ W09sl3333~ 219', 1 OG ~ m~6 SPmirnnrlllrtor substrate. A very long uninterrupted slit (or slot) could be formed by placing a number of slit (or slot) tiles end to end.
The tiles of adjacent columns can be displaced in the column direction so that during scanning there will be no inactive area cu.L.::,,uullding to 5 the inactive space between tiles. This is shown in Figure 5. By locating the control electronics to the side of the pixel cells formed by the pixel detectors and the pixel circuits, the pixel cells can extend substantially right to the end of the individual slit (or slot) tiles. In this way a very long uninterrupted slit (or slot) can be 10 menuFactured in a very cost effective manner.
Returning to Figure 1, the control eLectronics Z4 include the processing and control circuitry described with reference to Figures 3 and 4, which is connecsed to the pixel cells 18 on the srmi rnn~ rtor substrate as represented schematically by the two-way arrow Z2. The 15 control electronics 24 enable the active circuits 20 AccnriAt~.~l with individual pixel cells 18 to be addressed (e.g., scanned) for reading out charge A~ 1 Atorl in the active circuits 20 at the individual pixel cells 18. The charge read out is supplied tû AnaLogue to DigitaL
Converters (ADCs) for digitisation and Data Reduction PLUU~SSUL:. (DRPs) 20 for processing the binary signal.
The processing which is performed by the DRPs can involve iRrriminAt~nE~ signals which do not satisfy certain conditions such as a minimum energy level. This is particularly useful when each readout signal CULLG,~UII~ to a single incident radiation event. If the energy 25 cu,~ u..dLng to the measured signal is less than that to be expected for the radiation used, it can be concluded that the reduced charge vaLue stored results from scattering effects. In such a case the can be discarded with a resuLting i, v~. - in image resolution. Alternatively for pixels larger than lOOum acros6, the 30 discrimination can be carried out on each pixel circuit as mentioned earlier. In this case low energy hits are excluded while the rest are 1 At~ on the pixel circuits .
The control electronics Z4 is further interfaced via a path represented ~ ' rAl1y by the arrow 26 to an image processor 28.
35 The image pL~u~ssuL 28 includes data storage in which it stores the digital value representative of the charge read from each pixel cell aLong with the position of the pixel cell 18 concerned. For each pixel W0 95l33332 2 1 9 1 1 ~ 0 ~ 7 010~6 cell 18, each charge value read from the pixel cell is added to the charge value already stored for that pixel cell so that a charge value is accumulated. As a result, each image can be stored as a representation of a tWo-~limrncinnAl array of pixel values which can be stored, for example, in a database.
The image processor 28 can access the stored image data in the database to select a given image (all the array) or a part of the image (a sub-sample of the image array). The image processor 28 reads the values stored for the selected pixel positions and causes a representation of the data to be displayed on a display 32 via a path represented schematically by the arrow 30. The data can of course be printed rather than, or in addition to being displayed and can be subjected to further processing operations. Background and noise can be subtracted as a constant from each pixel charge value. This pedestal and/or background subtraction is possible if prior to image tsking an "empty" image is acquired. For each pixel a ba~h~;,u---d value is deduced and can be subtracted accordingly.
The ûperation of the image processor 28 will be described in more detail below.
Figure lZ illustrates an imaging technique in accordance with the invention using an imaging device in accordance with the invention with a slit or slot of random ArrPccihlr, active dynamic pixel cells. In accordance with this technique, the slit or slot is moved sideways at a constant speed v and is read out every t1 - to time units.
In the example shown in Figure 12, a slit with 6 pixels, each pixel having the rlimr-n~2innq (x,y). The constant movement is in the direction of the dimension x. If readout occurs at time to~ then in ac~u.d~l.~ with this aspect of the invention, the slit should be allowed to move until a time tl and then be read out again. The distance moved, or scanned, during the period t1 - to is dx and should not be larger than half the pixel size in the direction of movement (i.e. dx <= x/2). This technique improves the resolution along the axis of movement by a factor of two compared to full field imaging or conventional slit (slot) ~Prhniql,~c. The reason for the improvement lies in the multiple samPling mode that is used and according to which if the slit (slot) frame is A- lAtr~l in short enough intervals Wo 95133332 2 1 9 1 1 Q O PCTIEP95/0~056 (distance scanned =ust be shorter than half the pixel size), the underlying structure is 'sensed' with a resolution eqUAl to the pixel size rather than twice the pixel size. Twice the pixel size is the effective resolution for a full field imaging plane or a slit (slot) 5 that does not operate in the manner in accordance with this aSpect of the invention. The above described technigue can be used for example in dental panoramic imaging. The scan speed is typically 4cm/sec and the slot has a width of 4mm and a length of 8cm. This translates to 80 x 1600 pixels with a 50um square pixel size. The whole image 0 A- lAt;nn should last about 10 seconds. According to the current embodiment of the invention, the slot should be read out at leas~ every 25um which means a slot readout rate of 1.6kHz. If blocks of pixels of 80 columns by 20 rows of pixels and a clock frequency of 5MHz are used, the block readout speed is 5 x 106/(20 x 80) = 3.1kHz: much Gore than 15 the lkHz needed.
When the slit (slot) technique is used the X-ray source should be set at a higher operating current or if possible the X-rays should be condensed from a full field area to the ~limPncinnc of the slit (slot).
This is needed to keep the image Al lAtinn time constant. In many 20 cases this can be t~rhn~nAlly difficult and costly. An alternative to the single slit (slot) technique is a multi-slit (-slot) technique. In a.,cuLd~l~ with this variant multiple slits (slots) are positioned on a plane parallel to each other and with some constant distance between the longitudinal axis of the slits (slots). In this manner, if there 25 are n slits (slots) and the total distance to be scanned is X cm, then each slit (slot) need only scan X/n cm. This makes less demands on the ~ Anl~c, but more importantly the X-ray source intensity needs to increase by only X/(n x slit (slot) width).
Various methods of operation of the imaging devices and systems 30 in accordance with the invention will now be described. As mentioned above the devices and systems of the invention are aimed to provide imaging of high intensity radiation which is intended to be incident directly on the imaging devices. In embodiments of the invention, charge is - lAtPd (by storing charge values directly or voltage or 35 current equivalents ) in response to radiation hits with the charge value being directly and linearly related to the total energy of the incident radiation, rather than by counting numbers of points or events . , . .. ... .. _ ... _ ... _ . , .. _ _ _ _ _ _ _ . . ..

W095,33332 ~ ~ 9~ ~ 00 r~

or pulses. Thus an ASID Ar~ l A~tr-q charge on the gates of transistors and/or capacitors ~or other charge Ar_ lAting devices Implemented on the pixel circuit) that account for mo6t of the input node capacitance for each pixel circuit and each pixel detector, and an ASID has direct 5 one to one access to all pixel cells. These two main features have a dramatic impact on performance . An ASID can ~ l PtP about two orders of magnitude more charge than a CCD. An ASID also provides n~lc imaging with ~ess than a fraction of a percent inactive time. The electronic noise level is just about few hundred electrons.
Compared to conventional pulse counting sPmirnnrlllrtor pixel detectors an ASID has no limitation on the intensity of the radiation (and/or light). Long image frame A~ lAtinn times ~up to 1 second if needed) and very high dynamic range allow high intensity real time imaging without saturation.
As mentioned above with reference to Figure 1, after the ADCs, there is an image processor 28 which stores the digital value representative of the charge read fro3 each pixel cell along with the position of the pixel cell 18 rnnrrrnrrl. For each pixel cell 18, each charge value read from the pixel cell is added to the charge value already stored for that pixel cell so that a charge value is r lAtr~l~ A6 a regult, each image can be stored as a reprrcPntAtinn of _ two~ mr~nc~nnpl array of pixel values.
The image data can be stored, for example, in a database a6 a two-~limr-nrinnPl array for the image:
Image ~1: Npixels ~ 1 3 ) where the first index includes NpiXels items representing a pixel number on the imaging plane which runs linearly from one to a maximum pixel number NpiXels and the second index includes three values, for the x and y coordinates and the charge value r 1Ptl'Cl for each pixel, respectively. For each image a b~_k~;-uulid/pedestal array can be vL~ L~d. The b~k~vu-~d/pedestal pixel values can be ~ lAtr-~l for example just before image Prl lptinn as a calibration image.
This way calibration is provided for each pixel individually and not as a global constant for all pixels.
The image processor 28 access the stored image data in the database to select a given image ~all the array) or a part of the image SUBSrlTv~E SHEET (RU~E 261 ~ W0 95133332 2 1 9 1 1 0 0 F~ l/r.l ,~ .c.,~6 (a sub-sample of the lmage array) and causes a representation of the data to be dlsplayed, printed, or ?rocessed fur~her.
Preferabiy, before displaying, 2rincing or further processlng the image data, the image processor 28 finds the two extreme pixel charge ~ values stored for the p:xels selected and assigns ~hese values to tne two extremes of the grey or colour scale which can be used for displayin3, print~'ng o- ~ further processing of ~he ima~e, as appropri~e. rne remaining charge values for the ~ixel positions can then be assig ed an intermediate grey scale o- colour value between 10 these extreme values according to the charge deposited on the pixel.
For example the grey scale vaIue can be assigned to the charge values for individual plxels in accordar.ce wirh the following equation:
(icharge-Mir~ charge) ~ Grey scale value of pixel i = Mirlgrey + x(Maxgrey-Mingrey) (Maxcharge-Mincharge) The selection of a portion of the image to be zoomed can be achieved by means of conventional user input devices 36 via a data path represen~ed schematically by the arrow 34, possibly interacting with the display 32 as represented schematically by the double arrow 38.
20 The user input devices 36 can include, for example a keyboard, a mouse, etc .
The invention brings a number cf advantages as a result of Al lAtiTlF charg in an active circuit for each pixel cell.
The ability to accumulate the charge in the active circui~s on 25 the pixel cells and then selectively to read ou~ the stored charge from individually addressable active circuits in one to one .u..-~
with the pixel cells completely resolves any ambiguities regarding thepoint of incidence of concurrently incident radiation.
As the charge can be built up over a period on individual active 30 circuits, the readout speed need not be excessively high, with the - result that, for example, software-based generation and processing of the image in real time is possible and indeed can be implemented inexpensively on readily available computer hardware.
For each portion of the captured image the contrast and 35 resolution can be adjusted automatlcally and displayed on a full screen. Wherever there is a charge density variation between tne pixel SUBSTITUTE SHEET ~RULE 26) W0 95/33332 2 1 9 1 1 0 0 ~llrl 5 ~0s6 ~2 cells of an area of the image captured by the imaging device, features of the image can be resolved when that part of the captured image is displayed .
The dynamic range is effectively unlimited assuming that the 5 charge from the charge storage device of the pixel cell active circuits is read and the charge storage device is reset repeatedly before the storage capacity of the charge storage device is exhausted. It is merely necessary to select the "refresh rate" of the active circuits, that is the frequency of reading out and resetting those circuits, to 10 suit the storage capacity of the charge storage devices and the anticipated maximum radiation densi~y. Thus, as more radiation creates more charge, this is stored in the active circuits of the pixel cells, then read out at appropriate intervals and digitized by the control electronics. After digitization, the charge has a known value that can 15 be r 1 Atrrl with existing digitized charge values of the same pixel.
The only practical limitation is the maximum digital value which can be stored by the processing circuitry. However, even then the processing circuity could be arranged to detect a value approaching the maximum possible value which can be stored and then to apply a scaling factor 20 to the stored values of all pixel cells.
The invention enables real-time imaging. Once an image array has been created, even before irradiation starts, the image array can be updated rnntinllm-~ly with new digitized charge vaiues from the imaging device, which charge values are then added to the existing charge 25 values of the respective pixel of the array and the Ar. 1AtP~ charge values are displayed in real time.
Where a continuously updated image array is employed, this provides an efficient use of computer storage as detected radiation will not yield more image points, as is the case with some prior 30 t~rhnirlv~or~, out instead yields higher charge values for the pixel cell positions concerned. In other words, the present invention enables the r lAtinn of radiation counts rather then generation of an ever increasing number of radiation hit points. An ASID can also be used for providing real time imaging where for every predefined time 35 interval a new image frame is displayed. The inactive time between image frames is practically zero thus real time imaging is provided with maximum efficiency and at no expense of additional complexity in ~ W095/33332 21 91 1 ~0 r~ r~nc6 either the number of readout channels or the pixel circuits.
The present invention offers a way to minimise the ef~ect of radiation scattered before entering the imaging device. When an imaging device is used in the maoner described above, scattered rays 5 will lead to a lower charge value being Arrl 1 AtPrl than would be the case if that radiation were directly incident. This is because the scattered rays will deposit less energy in the depletion zone of the pixel detector. Thus, when processing the Al lAtF'~ charge, scattered radiation will have a much lower effect on the overall 0 Al l~tPrl charge than direct radiation. By assigning an appropriate grey scale or colour value to lower values when displaying an Al 1 AtPr image, it is possible to minimise the effect of the scattered radiation.
For Arrl;r~tinnc with radiation intensities requiring less than the maximum achievable readout speed per pixel (kHz range), the present invention offers a way of excluding the effect of radiation scattered before entering the imaging device, which, if not excluded, will degrade the image resolution. The way that this can be done w11 now be PYrl~inP,l. The charge created from each and every photon or charged radiation particle is first stored in the active circuits of the pixel cells and then read out. The control electronics digitises the charge and the DRP can compare the digitized value to a threshold reference value. The refcrence value ~uL~e~ u~ to the charge to be expected from incident radiation of the type in question, that is for example an X-ray of a given wavelength or from a charged radiation of a given energy. The digitised charge value is then excluded from further consideration if it is less than the reference value. This ~Cr~r1minAtinn operation enables scattered rays to be Plim1nAted from consideration. When inelastic scattering effects occur before the imaging plane while, for example, the radiation traverses an object under observation, the scattered radiation loses some of its energy before the imaging plene so that less ch_rge is created in the depletion region of a pixel cell. Such effects are Compton scattering for photons and ionization scattering for charged particles.
3rj On the other hand scattered rays can be excluded at any incoming intensities if this is done on the pixel circuits prior to charge r lAt~nn~ ~rrlir~tinnq such as gamma cameras and real-time _ _ _ _ _ . . . .. . . . _ . _ W0 95/33332 2 1 9 1 1 ~ i~?~cfi ~

angiography imaging need pixels of lOOum or more across and there is adequate space on the pixel circuit for implementing the threshold cut-off .
An example of a method which enables a way of excluding the effect of radiation scattered, either coherently or incoherently, before entering the imaging device using a slot technique and a t~nl 1 imslt~l radiation source such that it is adjusted to emit rays that are aimed at the imaging slot. The distance between the ray source and the object under observation, the distance between the object and the imaging slot and the width of the slot are optimised. These parameters can be used to define the geometry that minimises detectlon of scattered rays. This is because the scattered rays 'see' a small phase space and have no reason to enter the thin imaFing slot. This method is particularly powerful because it i5 based on geometry and does not require knowledge of the energy of the rays. If the rays have been scattered they will most likely miss detection whether they have been scattered ipcoherently and have lost some of their energy (Compton scattering) or coherently and have preserved all of their energy (Rayleigh scattering).
Figure 13 illustrates, by way of example, the ratio of u..ace~LL~ d radiation that reaches the slit (slot) as a function of the slit (slot) width for four different photon energies and four different d~stances between the slit (slot) and the object under observation.
For this example, water is assumed to be the object which causes 25 scattering over lOcm thickness The c~-i nnn~rtor is assumed to be silicon. It is seen from the four curves that practically all srAtt~rin~ is excluded (loOZ vertical axis) at slot widths between lmm and 4mm. This result is almost irrelevant to the distance between the slot and object (~ in the Figure). If the slot width starts to be 30 larger than 1 - 4mm, then the results starts depending on ,B as well.
Thus, for a given energy and obiect under consideration, the optimal slot width and the distance 3 between the slot and the object is determined such that the scattered rays will almost totally be excluded, thus d~ ti~-Plly improving the image resolution and 35 contrast. This method enables the exclusion of coherently scattered rays, which could not otherwise be excluded as they have the same energy as the unscattered rays.

-~ Wo 95l33332 2 1 9 1 1 0 0 , ~I/r~ . A7n~6 Imaging device design opt;micAtiAn in accordance with the invention can be carried out in an predetermined automated manner.
Each material or compound chosen for the cpm;rnnAllrtor substrate has a different response to incident radiation which depends on the physical properties of the material or compound, the radlation type and the radiation energy. A centre of gravity method is applied to the deposited electric signal at every step as incident radiation traverses the Spm;rnn~llrtor substrate. This enables the best attainable resolution to be determined as a function of the above parameters.
Thus the pixel size is determined. By correctly choosing the pixel size the signal to noise ratio can be maximised (because most of the signal is contained in one pixel) while the cost and device complexity is min;m;7e~ These results along with the expected sensitivity can be stored in a database and can be used to define the design p~- of the imaging plane of the imaging device, namely the pixel size and substrate thickness. Alternatively, a series of imaging planes t;hl~ with a common set of control electronics and an imag_ ~-'UI,~:5~Ul' can be provided. An end user can then, before carrying out imaging, input a desired sensitivity to the image processor to cause 2û this autn"l~t;rAl ly to select an imaging plane with the correct Crerifjr~,~f;nn Consider, as an example, the use of silicon as the s~m;~nn-i--rfrr substrate material. In biotechnology Arrl;rAt;nnc, isotopes such es 3H, 35S, 32P, 33P, 14C and 125I are used. Tbese isotopes emit ,B
radiation. Consider 35S, for example, which emits 170keV charged radiation. Figure 14 shows the passage of many such ~-rays through silicon. Ie the centre of gravity method is applied, it is found that the resolution cannot be better than 32um. The pixel size can then be chosen to be greater than 32um in order to contain most of the ol~rfrirAl signal. The ,~ radiation isotopes mentioned above are used in most biotechnology 9rrl;CAtinrc, In ~ y, ~ y, nuclear medicine, dental imaging, security systems and product quality control X-rays are used with energies between lOkeV-180keV, and Cd~nTe, CdTe and HgI2 are suitable choices of s~m;~ ,u.~.
There are many biology ArrlirAt;nnc that perform imaging ~rith ,6 radiation. Most often one of the following isotopes is used:
3H(18keV), 14C(155keV),35Sl170keV), 33P250keV), 32P(1700keV).

W095l33332 21 91 1 00 P~ l7s~lr~s6 ~

The precision reguirements for these ArrlirAtinn~ could be summarized as follows:
- hybridization in situ requires ideally lOum;
- hybridization on DNA, RNA and protein isolated or integrated requires ideally better than 300um;
- Ser~uences of DNA require ideally lOOum.
An imaging device in accordance with the invention can meet the above requirements. In addition the excellent efficiency ~practically 100%) of imaging devices in accordance with the invention can reduce the time for obtaining the results from days or months to hours. Since the imaging is done in real time a biologist can see the results while they are being 1 AteCl . Software and statistical methods of analysis can be used for interpreting these results.
In ~ y the X-rays used have typically energy from lOkeV
to 30keV. The X-ray source is placed behind the object under observation which absorbs part of the X-rays and lets the rest through.
The X-rays that arrive at the imaging plane are consequently photo-absorbed and create an electrical signal from which the point of incidence is determined. The charge density distribution effectively defines the image, which, with on-line conventional processing can be coloured, zoomed and analyzed with maximum image contrast and resolution. With O.5-lmm thick active CdZnTe, CdTe or HgI2 pixels the efficiency is almost 100% and the dose needed can be reduced drastically. The resolution for ,, .lrhY can be better than 30um and organic ~I,LuC~u-ea of that size are revealed.
In nuclear medical diagnosis an isotope emitting X-rays at the range of 150keV (such as, for example, Tc99 with 6 hours half life) i8 injected to the human body and concentrates to certain areas that are imaged. The radiation is emitted isotropically and around the human body collimators filter away unwanted directions thus making projections of a point to different planes. According to an example of the current invention the ASID,- made for example of Cd~nTe, CdTe, }~gI2, InSb, Ge, GaAs or Si, can be placed in front of and around the human brain replacing existing imaging planes.
In dental operations imaging is performed with X-rays at energies of 40keV-lOOkeV and imaging areas around 15 cm2 to 25 cm2 are needed.

~ W<1~5~3333~ 2 1 9 1 1 ~ 0 r~
L~7 Dental panoramic imaging using the slit/slot technique described above thus forms a preferred application of the invention. Suitable iami~ L::~ are as described above.
Yet another possible ArrlirAtinn of the invention is non-5 destructive industrial evaluation and product quality control.Depending on the inorganic object that is observed a different X-ray energy is chosen so as to optimize resolution with high contrast and efficiency. X-ray energies in the range 20keV-180keV may be used. The image of a p~oduct or a structure is Alltn-~t~l~Ally compared to an ideal 10 image of the same product or structure and various levels of severity may trigger different actions that give feedback to the production line .
An ASID and the methods described above car. find Arrl;rAtinn in a wide range of Arrli~Atinn~, including conventional X-rays, for chest5 X-rays, for X-ray _ cylly, for X-ray i _ o~ily, for computerized _ O~ I.y, for spiral computerized ' _ ,.ylly, for X-ray bone .Ly, for y-ray nuclear radiography, for gamma cameras for single photon emission computerlsed i _ oylly (SPECT), for positron emission i ,, at~lly (PET~, for X-ray dental imaging, for X-ray 20 panoramic dental imaging, for ,B-ray imaging using isotopes for DNA, PNA
and protein saqllanrini~ hybridization in situ, hybridization of DNA, i-iNA and protein isolated or integrated and generally for ,~-ray imaging Amd autoradiography using ~.llL~O~OGLtlylly and polymerars chain reaction, for X-ray and y-ray imaging in product quality control, for non-25 destructive testing and monitoring in real-time and online, for security control systems and for real-time (motion) imaging using radiation.
It will be appreciated that the size of the pixel cells and the number of pixel cells which can be ~ ,1 amant~l on a single 30 cami rnnrl~ tnr detector will depend on the particular semiconductor integration technology used. Thus, although particular examples of sizes and component values have been given, the invention is not limited thereto and is intended to include changes in those rl;manqinnq and values as are possible with current such tarhnnl ngy and will be 35 possible with future technology. Also, it will be appreciated thôt the actual circuits shown, for example the pixel circuit 20 shown in Figures 2, 8 and 11 the ronnact~nn lines and control circ~ltry _ _ _ _ _ _ , . , .. . _ _ . ... _ . . _ . _ _ . ... .

WOgs/33332 21 91 1 00 r "~. ; s- ~

illustrated in Figures 3, 4 and 9, are merely ex~mples of possible circuits and that many mnrlifir~innc and additions are possible within the scope of the invention.

Claims (147)

1. An imaging device for imaging high energy radiation, said imaging device comprising an array of pixel cells having a semiconductor substrate including an array of pixel detectors which generate charge in response to incident radiation and a corresponding array of pixel circuits, each pixel circuit being associated with a respective pixel detector for accumulating charge resulting from radiation incident on said pixel detector, being individually addressable and comprising charge accumulation circuitry for accumulating charge from radiation incident on the respective pixel detectors, wherein said charge accumulation circuitry in a pixel circuit is configured to provide a charge storage capacity sufficient to store at least 1.8 million electrons for accumulating charge from a plurality of successive high energy radiation hits on the respective pixel detector.

2. An imaging device according to claim 1, wherein a charge accumulation circuitry capacitance of each pixel circuit is in excess of 0.1pf, preferably in excess of 0.3pf.

3. An imaging device according to claim 2, wherein each pixel circuit comprises a charge storage device for accumulating charge, the capacitance of said charge storage device forming substantially said input node capacitance of said pixel circuit and of said pixel cell.

4. An imaging device according to claim 2, wherein each pixel circuit comprises at least two transistors, a first transistor acting as said charge storage device and a second transistor acting as a readout switch, being responsive to an enable signal to connect said first transistor to an output line for outputting any accumulated charge.

5. An imaging device according to claim 2, wherein each pixel circuit comprises at least two transistors in a cascode amplifier stage.

6. An imaging device according to claim 4, wherein said transistors are field effect transistors.

7. An imaging device according to claim 6, wherein the FET capacitance of the first transistor substantially forms said input node capacitance of the pixel circuit and of said pixel cell.

8. An imaging device according to claim 4, wherein each pixel circuit comprises a further field effect transistor responsive to a reset signal to reset said charge storage device.

9. An imaging device according to claim 1, wherein the pixel circuit comprises overload protection circuitry, preferably diodes, for over and under voltage protection.

10. An imaging device according to claim 1, comprising electrical resistance means for electrically separating pixel cells.

11. An imaging device according to claim 10, wherein said electrical resistance means comprises a non-conductive passivation layer between adjacent pixel detectors.

12. An imaging device according to claim 11, wherein a potential is applied to said passivation layer to create a potential barrier within said semiconductor substrate under said passivation layer for further electrically separating pixel cells.

13. An imaging device according to claim 10, wherein said electrical resistance means comprises a diode formed as part of said pixel circuit.

14. An imaging device according to claim 10, wherein said electrical resistance means comprises a bipolar transistor formed as part of said pixel circuit.

15. An imaging device according to claim 14, wherein a base of said bipolar transistor for each pixel circuit is set to a common potential.

16. An imaging device according to claim 1, wherein the charge value accumulated in a pixel circuit is output from a pixel circuit as a current value, said pixel circuit preferably being switched/multiplexed at a rate of the order of hundreds of kHz or more.

17. An imaging device according to claim 1, wherein said pixel cell size is of the order of or less than 1mm across, preferably approximately 350µm across.

18. An imaging device according to claim 1, wherein said pixel cell size is approximately 150µm across or less, preferably approximately 50µm across or less and more preferably approximately 10µm across.

19. An imaging device according to claim 1, wherein said substrate is between 200µm and 3mm thick.

20. An imaging device according to claim 1, wherein said pixel circuits are integral to said substrate and aligned with the corresponding pixel detectors.

21. An imaging device according to claim 1, wherein said pixel circuits are formed in a further substrate, said further substrate incorporating said pixel circuits being coupled to said substrate incorporating said pixel detectors, with each pixel circuit being aligned with and being coupled to the corresponding pixel detector.

22. An imaging device according to claim 1, wherein said array comprises a single row of pixel detectors and associated pixel circuits forming a slit-shaped imaging device or a plurality of rows of pixel detectors and associated pixel circuits forming a slot-shaped imaging device.

23. An imaging device according to claim 22, wherein said pixel circuits for respective pixel detectors are laterally adjacent to the corresponding pixel detectors.

24. An imaging device according to claim 1, wherein charge can be accumulated on each pixel circuit for a period of up to the order of a millisecond or tens or hundreds of milliseconds or more before readout.

25. An imaging device according to claim 1, in combination with control electronics including addressing logic for addressing individual pixel circuits for reading accumulated charge values from said pixel circuits and selectively resetting said pixel circuits.

26. An imaging device according to claim 25, wherein said addressing logic comprises means for connecting output lines of said pixel circuits to an output of said imaging device, means for supplying read enable signals to read enable inputs of said pixel circuits and means for supplying reset signals to reset inputs of said pixel circuits.

27. An imaging device according to claim 26, wherein said means for connecting output lines comprises a shift register or counter for sequentially connecting output lines of said pixel circuits for respective columns of pixels to said output of said imaging device.

28. An imaging device according to claim 26, wherein said means for supplying read enable signals comprises a shift register or counter for sequentially supplying read enable signals to read enable inputs of said pixel circuits for respective rows of pixels.

29. An imaging device according to claim 25, wherein said means for supplying reset signals comprises a shift register or counter for sequentially supplying reset signals to reset inputs of said pixel circuits for respective rows of pixels.

30. An imaging device according to claim 25, wherein said control electronics includes an analogue to digital converter for converting an analogue charge value from a said pixel circuit into a digital charge value.

31. An imaging device according to claim 25, wherein at least part of said control electronics is integrated into a semiconductor substrate on which said pixel circuits are integrated.

32. An imaging device according to claim 1, wherein said pixel circuit is configured to provide charge storage means having a capacitance and dynamic range sufficient to store 6 million electrons, preferably 25 million, more preferably 50 million and yet more preferably 60 million electrons prior to being read out or reset.

33. An imaging device according to claim 1, wherein each pixel circuit comprises means for discarding charge from an incoming radiation hit corresponding to energy less than a predetermined value prior to accumulation in said pixel circuit.

34. An imaging device according to claim 1, wherein the semiconductor substrate is made of a material selected from: CdZnTe, CdTe, HgI2, InSb, GaAs, Ge, TIBr and Si.

35. An imaging system comprising an imaging device according to claim 25, said imaging system comprising an image processor connected to said control electronics for processing said digital charge values from respective pixel circuits to form an image for display on a display device.

36. An imaging system according to claim 35, wherein said processor determines maximum and minimum charge values for pixels for display, assigns extreme grey scale or colour values to said maximum and minimum charge values and allocates grey scale or colour values to an individual pixel according to a sliding scale between said extreme values in dependence upon the charge value for said pixel.

37. An imaging system according to claim 36, wherein said grey scale or colour values are allocated in accordance with the following formula:

Grey scale value of pixel i =

38. An imaging system comprising a plurality of imaging devices according to claim 1 tiled together to form a mosaic.

39. An imaging system according to claim 38, wherein said mosaic comprises a plurality of columns of tiled imaging devices, said imaging devices of adjacent columns being offset in the column direction.

40. An imaging system according to claim 38, comprising means for stepping or moving said imaging device and/or an object to be imaged to accumulate an image over a complete image area.

41. An imaging system according to claim 38, comprising two imaging surfaces, each comprising a mosaic of imaging devices, said imaging surfaces being arranged substantially parallel to one another and spaced from one another with an object to be imaged between said surfaces, the mosaics being offset laterally with respect to one another to give substantially complete imaging of said object.

42. An imaging system comprising a plurality of imaging devices according to claim 1, wherein said imaging devices are arranged substantially tangentially around the periphery of a ring or part-ring to encircle or partially encircle a slice of an object to be imaged by, for example, a computerized tomography technique.

43. An imaging system according to claim 42, wherein said imaging devices are arranged substantially tangentially around the periphery of a plurality of rings or part-rings displaced from one another in the direction forming a common axis of said rings or part-rings.

44. An imaging system comprising a plurality of imaging devices according to claim 1 tiled together to form a mosaic matching the area and shape of an object to be imaged.

45. An imaging system comprising a plurality of imaging devices according to claim 1 tiled together to form a mosaic surrounding part or all of an object to be imaged.

46. An imaging system according to claim 38, wherein respective image outputs of a plurality of tiled imaging devices are connected to a common multiplexer, the output of which multiplexer is connected to a common analogue to digital converter.

47. An imaging system according to claim 38, wherein respective image outputs of a plurality of tiled imaging devices are daisy-chained to a common analogue to digital converter.

48. An imaging system according to claim 46, wherein the output of said multiplexer comprises current values representative of accumulated charge from said pixel circuits.

49. An imaging system according to claim 35, wherein individual pixel circuits are addressed for reading accumulated charge at a rate to optimise the resolution of an analogue to digital converter for converting analogue accumulated charge values into digital values.

50. An imaging system according to claim 35, wherein multiple image frames are accumulated, either at an analogue to digital conversion stage, or subsequently at an image processing stage.

51. An imaging system according to claim 35, arranged to accumulate image frames at said pixel cells, to repeatedly read out a refresh image for display and to reset said pixel circuits at a rate sufficient to avoid saturation of a charge storage device of said pixel circuits.

52. An imaging system comprising one or more slit- or slot-shaped imaging device(s) according to claim 22 and means for relative movement between said slit- or slot-shaped imaging device(s) and an object to be imaged in a direction transversely to a longitudinal axis of said imaging device(s) for accumulating a complete image over an imaging area.

53. Use of an imaging device according to claim 1 in a method for imaging accumulated values corresponding to respective pixel positions within a pixel array such as charge values accumulated for respective pixel positions of said imaging device, said method comprising:
- determining maximum and minimum accumulated values for pixels within an area of said pixel array to be imaged;
- assigning grey scale or colour values at extremes of a grey or colour scale to be imaged to said maximum and minimum accumulated values; and - assigning grey scale or colour values to said accumulated values for individual pixels scaled in accordance with said extreme values; and - imaging said assigned grey scale or colour values at respective image pixel positions.

54. Use of an imaging device according to claim 1 in a method for performing real time imaging of an organic or inorganic object, said method comprising:
- irradiating said object using a radiation source that produces X-rays, .gamma.-rays, .beta.-rays or .alpha.-rays;
- detecting at a semiconductor imaging plane or planes of said imaging device unabsorbed radiation or radiation that is emitted from selected areas of said object, whereby the amount of charge resulting from radiation incident successively on respective pixel detectors of said imaging device is accumulated in respective pixel circuits;
- addressing said pixel circuits individually for reading out accumulated charge;
- processing said read out charge to provide image pixel data; and - displaying said image pixel data.

55. Use of an imaging device according to claim 1 comprising:
reading the accumulated charge from individual pixel circuits at a rate to optimise the resolution of an analogue to digital converter for converting analogue accumulated charge values into digital values.

56. Use of an imaging device according to claim 1 for conventional X-rays, for chest X-rays, for X-ray mammography, for X-ray tomography, for computerized tomography, for spiral computerized tomography, for X-ray bone densiometry, for X-ray dental imaging, for X-ray panoramic dental imaging, for .beta.-ray imaging using isotopes for DNA, RNA and protein sequencing, hybridization in situ, hybridization of DNA, RNA
and protein isolated or integrated and generally for .beta.-ray imaging and autoradiography using chromatography and polymerars chain reaction, for X-ray and .gamma.-ray imaging in product quality control, for non-destructive testing and monitoring in real-time and online, for security control systems, and for motion imaging.

57. Use of an imaging device according to claim 1 for infrared imaging, optical light imaging or ultraviolet light imaging.

58. A semiconductor imaging device having an array of pixel cells for imaging multiple successive high energy radiation hits, said imaging device comprising:
a semiconductor detector substrate including an array of pixel detector cells, wherein each pixel detector cell directly generates charge in response to incident radiation; and a semiconductor readout substrate including an array of individually addressable pixel circuits, wherein:
each pixel circuit is connected to a corresponding pixel detector cell to form a pixel cell;
each pixel circuit includes charge accumulation circuitry for accumulating charge directly resulting from high energy radiation incident on said corresponding pixel detector cell, readout circuitry for outputting a value representative of charge accumulated in said charge accumulation circuitry and reset circuitry for resetting said charge accumulation circuitry; and each pixel circuit, formed from said charge accumulation, readout and reset circuitry, is configured to provide charge accumulation circuitry which has a capacitance forming substantially the total capacitance of a said pixel cell, formed from said pixel circuit and said corresponding pixel detector cell, and has a charge storage capacity sufficient to store at least 1.8 million electrons for accumulating charge from a plurality of successive high energy radiation hits on the respective pixel detector prior to readout or resetting of said charge accumulation circuitry.

59. An imaging device according to claim 58, wherein said value output from a said pixel circuit is a current representative of charge accumulated in said charge accumulation circuitry of said pixel circuit.

60. An imaging device according to claim 59, wherein each pixel circuit comprises at least two transistors, a first transistor acting as said charge storage circuitry and a second transistor acting as said readout circuitry and responsive to an enable signal to connect said first transistor to an output line for outputting a current representative of any accumulated charge.

61. An imaging device according to claim 59, wherein each pixel circuit comprises at least two transistors in a cascode amplifier stage.

62. An imaging device according to claim 60 or claim 61, wherein said transistors are field effect transistors.

63. An imaging device according to claim 62, wherein each pixel circuit comprises a further field effect transistor acting as said reset circuitry and responsive to a reset signal to reset said charge storage device.

64. An imaging device according to any one of claims 59 to 63, said pixel circuits being switched/multiplexed at a rate of the order of hundreds of kHz or more.

65. An imaging device according to any one of claims 58 to 64, comprising electrical resistance means for electrically separating pixel cells.

66. An imaging device according to claim 65, wherein said electrical resistance means comprises a non-conductive passivation layer between adjacent pixel detectors.

67. An imaging device according to claim 66, wherein a potential is applied to said passivation layer to create a potential barrier within said semiconductor substrate under said passivation layer for further electrically separating pixel cells.

68. An imaging device according to claim 65, wherein said electrical resistance means comprises a diode forming part of said pixel circuit.

69. An imaging device according to any one of claims 58 to 68, wherein a said pixel circuit comprises overload protection circuitry, preferably diodes, for over and under voltage protection.

70. An imaging device according to any one of claims 58 to 69, wherein said array comprises a single row of pixel detectors and associated pixel circuits forming a slit-shaped imaging device or a plurality of rows of pixel detectors and associated pixel circuits forming a slot-shaped imaging device.

71. An imaging device according to any one of claims 58 to 70 in combination with control electronics including addressing logic for addressing individual pixel circuits for reading accumulated charge values from said pixel circuits and selectively resetting said pixel circuits.

72. An imaging device according to claim 71, wherein charge can be accumulated on each pixel circuit for a period of up to the order of a second before readout.

73. An imaging device according to claim 71 or claim 72, wherein said addressing logic comprises means for connecting output lines of said pixel circuits to an output of said imaging device, means for supplying read enable signals to read enable inputs of said pixel circuits and means for supply reset signals to reset inputs of said pixel circuits.

74. An imaging device according to claim 73, wherein said means for connecting output lines comprises a shift register or counter for sequentially connecting output lines of said pixel circuits for respective columns of pixels to said output of said imaging device and/or said means for supplying read enable signals comprises a shift register or counter for sequentially supplying read enable signals to read enable inputs of said pixel circuits for respective rows of pixels and/or said means for supplying reset signals comprises a shift register or counter for sequentially supplying reset signals to reset inputs of said pixel circuits for respective rows of pixels.

75. An imaging device according to any one of claims 58 to 74, wherein said pixel circuit is configured to provide charge storage means having a capacitance and dynamic range sufficient to store 6 million electrons, preferably 25 million, more preferably 50 million and yet more preferably 60 million electrons prior to being read out or reset.

76. An imaging device according to any one of claims 58 to 75, wherein each pixel circuit comprises means for discarding charge from an incoming radiation hit corresponding to energy less than a predetermined value prior to accumulation in said pixel circuit.

77. An imaging device according to any one of claims 58 to 76, wherein the semiconductor substrate is made of a material selected from: CdZnTe, CdTe, HgI , InSb, GaAs, Ge, TIBr and Si.

78. An imaging system comprising an imaging device according to any one of claims 71 to 77, said imaging system comprising an image processor connected to said control electronics for processing digital charge values derived from respective pixel circuits to form an image for display on a display device.

79. An imaging system according to claim 78, wherein said processor determines maximum and minimum charge values for pixels for display, assigns extreme grey scale or colour values to said maximum and minimum charge values and allocates grey scale or colour values to an individual pixel according to a sliding scale between said extreme values in dependence upon the charge value for said pixel.

80. An imaging system according to claim 79, wherein said grey scale or colour values are allocated in accordance with the following formula:

Grey scale value of pixel i =

81. An imaging system according to any one of claims 78 to 80, wherein said control electronic includes an analogue to digital converter stage and wherein means are provided for accumulating multiple image frames, either at said analogue to digital conversion stage, or subsequently at an image processing stage.

82. An imaging system comprising a plurality of imaging devices according to any one of claims 58 to 77 tiled together to form a mosaic.

83. An imaging system according to any one of claims 78 to 82, arranged to accumulate image frames at said pixel cells, to repeatedly read out a refresh image for display and to reset said pixel circuits at a rate sufficient to avoid saturation of a charge storage device of said pixel circuits.

84. Use of an imaging device according to any one of claims 58 to 77 in a method for imaging accumulated values corresponding to respective pixel positions within a pixel array such as charge values accumulated for respective pixel positions of said imaging device, said method comprising:
- determining maximum and minimum accumulated values for pixels within an area of said pixel array to be imaged;
- assigning grey scale or colour values at extremes of a grey or colour scale to be imaged to said maximum and minimum accumulated values; and - assigning grey scale or colour values to said accumulated value for individual pixels scaled in accordance with said extreme values; and -imaging said assigned grey scale or colour values at respective image pixel positions.

85. Use of an imaging device according to any one of claims 58 to 77 in a method for performing real time imaging of an organic or inorganic object, said method comprising:
- irradiating said object using a radiation source that produces X-rays, .gamma.-rays, .beta.-rays or .alpha.-rays;
- detecting at a semiconductor imaging plane or planes of said imaging device unabsorbed radiation or radiation that is emitted from selected areas of said object, whereby the amount of charge resulting from radiation incident successively on respective pixel detectors of said imaging device is accumulated in respective pixel circuits;

- addressing said pixel circuits individually for reading out accumulated charge;
- processing said read out charge to provide image pixel data; and - displaying said image pixel data.

86. Use of an imaging device according to any one of claims 58 to 77 or an imaging system according to any one of claims 78 to 83 comprising:
reading the accumulated charge from individual pixel circuits at a rate to optimise the resolution of an analogue to digital converter for converting analogue accumulated charge values into digital values.

87. Use of an imaging device according to any one of claims 58 to 77 or of an imaging system according to any one of claims 78 to 83 conventional X-rays, for chest X-rays, for X-ray mammography, for X-ray tomography, for computerized tomography, for spiral computerized tomography, for X-ray bone densiometry, for X-ray dental imaging, for X-ray panoramic dental imaging, for .beta.-ray imaging using isotopes for DNA, RNA and protein sequencing, hybridization in situ, hybridization of DNA, RNA and protein isolated or integrated and generally for .beta.-ray imaging and autoradiography using chromatography and polymerars chain reaction, for X-ray and Y-ray imaging in product quality control, for non-destructive testing and monitoring in real-time and online, for security control systems, and for motion imaging.

88. Use of an imaging device according to any one of claims 58 to 77 or of an imaging system according to any one of claims 78 to 83 for infrared imaging, optical light imaging or ultraviolet light imaging.

89. An imaging device for imaging radiation, wherein:
said imaging device comprises at least one semiconductor substrate and comprises an array of pixel cells formed from an array of pixel detectors which generate charge in response to incident radiation and a corresponding array of pixel circuits;
and each of said pixel circuits is associated with a respective pixel detector for accumulating charge resulting from radiation incident on said pixel detector, is individually addressable and comprises circuitry for accumulating charge from successive radiation hits on the respective pixel detectors and overload protection circuitry for over and/or under voltage protection.

90. An imaging device according to claim 89, wherein said overload protection circuitry comprises a diode.

91. An imaging device according to claim 90, wherein each said pixel circuit comprises first and second diodes for over and under voltage protection, respectively.

92. An imaging device according to any one of claims 89 to 91, wherein each said pixel circuit comprises readout circuitry for outputting a value representative of charge accumulated in said charge accumulation circuitry and reset circuitry for resetting said charge accumulation circuitry.

93. An imaging device according to claim 92, wherein each said pixel circuit comprises at least two transistors, a first transistor acting as said charge accumulation circuitry and a second transistor acting as said readout circuitry, which second transistor is responsive to an enable signal to connect said first transistor to an output line for outputting a value representative of charge accumulated in said charge accumulation circuitry.

94. An imaging device according to claim 93, wherein said pixel circuit comprises a further transistor acting as said reset circuitry and responsive to a reset signal to reset said charge accumulation circuitry.

95. An imaging device according to any one of claims 89 to 94, wherein each pixel circuit comprises at least two transistors in a cascode amplifier stage.

96. An imaging device according to any one of claims 93 to 95, wherein said transistors are field effect transistors.

97. An imaging device according to any preceding claim, wherein said array of pixel detectors and said corresponding array of pixel circuits are formed in a common semiconductor substrate.

98. An imaging device according to any one of claims 89 to 96, wherein said array of pixel detectors are formed in a first substrate and said corresponding array of pixel circuits are formed in a different substrate, individual pixel detectors being coupled to corresponding pixel circuits.

99. An imaging device according to any one of claims 89 to 98, comprising control electronics including addressing logic for addressing individual pixel circuits for reading values representative of, accumulated charge from said pixel circuits and for selectively resetting said pixel circuits.

100. An imaging device according to claim 99, wherein said addressing logic comprises means for connecting output lines of said pixel circuits to an output of said imaging device, means for supplying read enable signals to read enable inputs of said pixel circuits and means for supplying reset signals to reset inputs of said pixel circuits.

101. An imaging device according to claim 99 or 100, wherein said means for supplying reset signals comprises a shift register or counter for sequentially supplying reset signals to reset inputs of said pixel circuits for respective rows of pixels.

102. An imaging device according to any one of claims 99 to 101, wherein at least part of said control electronics is integrated into a semiconductor substrate in which said pixel circuits are formed.

103. An imaging device according to any one of claims 89 to 102, wherein said semiconductor substrate(s) is or are made of a material selected from: CdZnTe, CdTe, HgI2, InSb, GaAs, Ge, TIBr and Si.

104. An imaging system comprising an imaging device according to any one of claims 89 to 103, said imaging system comprising an image processor connected for processing values representative of accumulated charge and output from said pixel circuits to form an image for display on a display device.

105. An imaging system comprising a plurality of imaging devices according to any one of claims 89 to 103 tiled together to form a mosaic.

106. An imaging system for imaging radiation, said imaging system comprising a plurality of imaging devices, wherein:
each imaging device comprises at least one semiconductor substrate and comprises an array of pixel cells formed from an array of pixel detectors which generate charge in response to incident radiation and a corresponding array of pixel circuits;
each of said pixel circuits is associated with a respective pixel detector for accumulating charge resulting from radiation incident on said pixel detector, is individually addressable and comprises circuitry for accumulating charge from successive radiation hits on the respective pixel detector; and said plurality of imaging devices are tiled together to form a matrix.

107. An imaging system according to claim 106, comprising at least one analogue to digital converter and means connecting outputs from a plurality of imaging devices to a said analogue to digital converter.

108. An imaging system according to claim 107, wherein said connecting means comprises a multiplexes connected to respective outputs of said tiled imaging devices, an output of which multiplexer is connected to a common analogue to digital converter.

109. An imaging system according to claim 107, wherein said connecting means comprises means daisy-chaining respective outputs of said tiled imaging devices to a common analogue to digital converter.

110. An imaging system according to any one of claims 106 to 109, wherein said mosaic comprises a plurality of columns of tiled imaging devices with said imaging devices of adjacent columns being offset in the column direction.

111. An imaging system according to claim 110, comprising means for stepping or moving said imaging device and/or an object to be imaged to accumulate an image over a complete image area.

112. An imaging system according to any one of claims 106 to 111, comprising:
addressing logic for addressing individual pixel circuits for reading accumulated charge values from said pixel circuits and selectively resetting said pixel circuits; and control electronics including one or more analogue to digital converter(s), said control electronics accumulating multiple image frames during processing at or after an analogue to digital conversion stage.

113. An imaging system according to any one of claims 106 to 112, wherein each imaging device comprises a common semiconductor substrate in which said array of pixel detectors and said corresponding array of pixel circuits are formed.

114. An imaging system according to any one of claims 106 to 112, wherein each imaging device comprises a first semiconductor substrate in which said array of pixel detectors is formed and a further semiconductor substrate in which said corresponding array of pixel circuits is formed, individual pixel detectors being coupled to corresponding pixel circuits.

115. A computerized tomography imaging system comprising an imaging system according to any one of claims 106 to 114, wherein said matrix of imaging devices are arranged substantially tangentially around the periphery of a ring or part-ring to encircle or partially encircle a slice of an object to be imaged.

116. Use of a mosaic of imaging devices according to claim 1 for a method for imaging accumulated charge values corresponding to respective pixel positions of an imaging system, said method comprising:
generating a first image portion from charge values accumulated by said plurality of imaging devices while said mosaic is in a first position relative to an object being imaged;
causing relative movement between said mosaic and said object being imaged to a second position and generating a second image portion while said mosaic is in said second position relative to said object being image;
causing relative movement between said mosaic and said object being imaged to a third position and generating a third image portion while said mosaic is in said third position relative to said object being imaged; and combining said first, second and third image portions into a single image for display.

117. Use of an imaging system according to claim 110 or 111 for a method for imaging accumulated charge values corresponding to respective pixel positions of said imaging system, said method comprising:
generating a first image portion from charge values accumulated by said plurality of imaging devices while said mosaic is in a first position relative to an object being imaged;
causing relative movement between said mosaic and said object being imaged to a second position and generating a second image portion while said mosaic is in said second position relative to said object being imaged;
causing relative movement between said mosaic and said object being imaged to a third position and generating a third image portion while said mosaic is in said third position relative to said object being imaged; and combining said first, second and third image portions into a single image for display.

118. Use of a computerized tomography imaging system according to claim 115 for a computer tomography imaging method for performing real time imaging of an organic or inorganic object, said method comprising:
irradiating said object using a radiation source that produces x-rays, .gamma.-rays, .beta.-rays or .alpha.-rays;
detecting at a semiconductor imaging plane or planes of imaging devices of said system according to claim 115 unabsorbed radiation or radiation that is emitted from selected areas of said object, whereby the amount of charge resulting from radiation incident successively on respective pixel detectors of said imaging device is accumulated in respective pixel circuits;
addressing said pixel circuits individually for reading out accumulated charge;
processing said read out charge to provide image pixel data; and displaying said image pixel data.

119. An imaging device for imaging radiation, wherein:
said imaging device comprises at least one semiconductor substrate and comprises an array of pixel cells formed from an array of pixel detectors which generate charge in response to incident radiation and a corresponding array of pixel circuits;
and each of said pixel circuits is associated with a respective pixel detector for accumulating charge resulting from radiation incident on said pixel detector, is individually addressable and comprises discrimination circuitry for discarding charge from a radiation hit on the respective pixel detector corresponding to energy less than a predetermined value and charge accumulation circuitry for accumulating charge from successive radiation hits on said pixel detector corresponding to energy greater than said predetermined value.

120. An imaging device according to claim 119, wherein each said pixel circuit comprises readout circuitry for outputting a value representative of charge accumulated in said charge accumulation circuitry and reset circuitry for resetting said charge accumulation circuitry.

121. An imaging device according to claim 120, wherein said pixel circuit also comprises overload protection circuitry for over and/or under voltage protection.

122. An imaging device according to any one of claims 119 to 121, wherein said array of pixel detectors and said corresponding array of pixel circuits are formed in a common semiconductor substrate.

123. An imaging device according to any one of claims 119 to 121, wherein said array of pixel detectors is formed in a first substrate and said corresponding array of pixel circuits is formed in a different substrate, individual pixel detectors being coupled to corresponding pixel circuits.

124. An imaging device according to any one of claims 119 to 123, comprising control electronics including addressing logic for addressing individual pixel circuits for reading values representative of accumulated charge from said pixel circuits and for selectively resetting said pixel circuits.

125. An imaging device according to claim 124, wherein said addressing logic comprises means for connecting output lines of said pixel circuits to an output of said imaging device, means for supplying read enable signals to read enable inputs of said pixel circuits and means for supplying reset signals to reset inputs of said pixel circuits.

126. An imaging device according to claim 124 or 125, wherein said means for supplying reset signals comprises a shift register or counter for sequentially supplying reset signals to reset inputs of said pixel circuits for respective rows of pixels.

127. An imaging device according to any one of claims 124 to 126, wherein at least part of said control electronics is integrated into a semiconductor substrate in which said pixel circuits are formed.

128. An imaging device according to any one of claims 119 to 127, wherein said semiconductor substrate(s) is or are made of a material selected from: CdZnTe, CdTe, HgI2, InSb, GaAs, Ge, TIBr and Si.

129. An imaging system comprising an imaging device according to any one of claims 119 to 128, said imaging system comprising an image processor connected for processing values representative of accumulated charge and output from said pixel circuits to form an image for display on a display device.

130. An imaging system comprising a plurality of imaging devices according to any one of claims 119 to 128, tiled together to form a mosaic.

131. A method for imaging radiation using a semiconductor imaging device comprising an array of pixel cells formed from an array of pixel detectors which generate charge in response to incident radiation and a corresponding array of individually addressable pixel circuits which include charge accumulation circuitry for accumulating charge from successive radiation hits on a corresponding pixel detector, said method comprising:
i) discarding charge from a radiation hit on a pixel detector corresponding to energy less than a predetermined value; and ii) storing charge in said charge accumulation circuitry from an incoming radiation hit on said pixel detector corresponding to energy greater than said predetermined value.

132. An imaging device for imaging radiation, wherein:
said imaging device comprises at least one semiconductor substrate and comprises an array of pixel cells formed from an array of pixel detectors which generate charge in response to incident radiation and a corresponding array of pixel circuits;
and each of said pixel circuits is associated with a respective pixel detector for accumulating charge resulting from radiation incident on said pixel detector, is individually addressable and comprises charge accumulation circuitry for accumulating charge from successive radiation hits on the respective pixel detector, said pixel circuit being configured to output a current value representative of charge accumulated in said charge accumulation circuitry.

133. An imaging device according to claim 132, wherein each said pixel circuit comprises reset circuitry for resetting said charge accumulation circuitry.

134. An imaging device according to claim 132, wherein each said pixel circuit comprises at least two transistors in a cascode amplifier stage.

135. An imaging device according to claim 132, wherein each said pixel circuit comprises at least two transistors, a first transistor acting as said charge accumulation circuitry and a second transistor acting as readout circuitry, which second transistor is responsive to an enable signal to connect said first transistor to an output line for outputting a current value representative of charge accumulated in said charge accumulation circuitry.

136. An imaging device according to claim 134 or 135, wherein each said pixel circuit comprises a further transistor acting as reset circuitry and responsive to a reset signal to reset said charge accumulation circuitry.

137. An imaging device according to any one of claims 132 to 136, wherein each said pixel circuit comprises overload protection circuitry for over and/or under voltage protection.

138. An imaging device according to any one of claims 132 to 137, wherein said array of pixel detectors and said corresponding array of pixel circuits are formed in a common semiconductor substrate.

139. An imaging device according to any one of claims 132 to 137, wherein said array of pixel detectors are formed in a first substrate and said corresponding array of pixel circuits are formed in a different substrate, individual pixel detectors being coupled to corresponding pixel circuits.

140. An imaging device according to any one of claims 132 to 139, comprising control electronics including addressing logic for addressing individual pixel circuits for reading values representative of accumulated charge from said pixel circuits and for selectively resetting said pixel circuits.

141. An imaging device according to claim 140, wherein said addressing logic comprises means for connecting output lines of said pixel circuits to an output of said imaging device, means for supplying read enable signals to read enable inputs of said pixel circuits and means for supplying reset signals to reset inputs of said pixel circuits.

142. An imaging device according to claim 140 or 141, wherein said means for supplying reset signals comprises a shift register or counter for sequentially supplying reset signals to reset inputs of said pixel circuits for respective rows of pixels.

143. An imaging device according to any one of claims 140 to 142, wherein at least part of said control electronics is integrated into a semiconductor substrate in which said pixel circuits are formed.

144. An imaging device according to any one of claims 132 to 143, wherein said semiconductor substrate(s) is or are made of a material selected from: CdZnTe, CdTe, HgI2, InSb, GaAs, Ge, TIBr and Si.

145. An imaging system comprising an imaging device according to any one of claims 132 to 144, said imaging system comprising an image processor connected for processing current values representative of accumulated charge and output from said pixel circuits to form an image for display on a display device.

146. An imaging system comprising a plurality of imaging devices according to any one of claims 132 to 145 tiled together to form a mosaic.

147. A method for imaging radiation using a semiconductor imaging device comprising an array of pixel cells formed from an array of pixel detectors which generate charge in response to incident radiation and a corresponding array of individually addressable pixel circuits, said method comprising:

i) accumulating charge generated in said pixel detectors in response to successive radiation hits in respective pixel circuits; and ii) outputting current values representative to said accumulated charge from said respective pixel circuits.