CA2195836A1 - Semiconductor memory having main word line and subword lines provided correspondingly to the main word line - Google Patents
Semiconductor memory having main word line and subword lines provided correspondingly to the main word lineInfo
- Publication number
- CA2195836A1 CA2195836A1 CA002195836A CA2195836A CA2195836A1 CA 2195836 A1 CA2195836 A1 CA 2195836A1 CA 002195836 A CA002195836 A CA 002195836A CA 2195836 A CA2195836 A CA 2195836A CA 2195836 A1 CA2195836 A1 CA 2195836A1
- Authority
- CA
- Canada
- Prior art keywords
- word line
- main word
- semiconductor memory
- lines provided
- cross portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
In a memory in which a memory cell array 200 and a subword drive circuit SWD are alternately arranged in a row direction in addition to an SA array 170 and a cross portion (SWC) alternately arranged, there are arranged an interface circuit 100 between a global I/0 line GIOT/B and a local I/O line LIOT/B in a first cross portion SWD1, nMOSs Q2, Q4, and Q5 of an SA control circuit in a second cross portion SWC2, and pMOSs Q1 and Q3 of the SA control circuit in a third cross portion SWC3.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8010527A JP2757849B2 (en) | 1996-01-25 | 1996-01-25 | Semiconductor storage device |
JP10527/96 | 1996-01-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2195836A1 true CA2195836A1 (en) | 1997-07-26 |
CA2195836C CA2195836C (en) | 2001-03-20 |
Family
ID=11752732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002195836A Expired - Fee Related CA2195836C (en) | 1996-01-25 | 1997-01-23 | Semiconductor memory having main word line and subword lines provided correspondingly to the main word line |
Country Status (5)
Country | Link |
---|---|
US (1) | US5793664A (en) |
JP (1) | JP2757849B2 (en) |
KR (1) | KR100242906B1 (en) |
CA (1) | CA2195836C (en) |
TW (1) | TW340942B (en) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3209265B2 (en) * | 1997-08-01 | 2001-09-17 | 日本電気株式会社 | Semiconductor circuit |
JP2000049307A (en) * | 1998-07-29 | 2000-02-18 | Mitsubishi Electric Corp | Semiconductor storage |
KR100480902B1 (en) * | 1998-09-02 | 2005-06-08 | 주식회사 하이닉스반도체 | Layout of Semiconductor Memory Device |
JP4212171B2 (en) | 1999-01-28 | 2009-01-21 | 株式会社ルネサステクノロジ | Memory circuit / logic circuit integrated system |
JP4632107B2 (en) | 2000-06-29 | 2011-02-16 | エルピーダメモリ株式会社 | Semiconductor memory device |
KR100403344B1 (en) * | 2001-09-13 | 2003-11-01 | 주식회사 하이닉스반도체 | Semiconductor memory device |
DE10339894B4 (en) * | 2003-08-29 | 2006-04-06 | Infineon Technologies Ag | Sense amplifier Zuschalt / shutoff circuitry |
JP4149969B2 (en) * | 2004-07-14 | 2008-09-17 | 株式会社東芝 | Semiconductor device |
KR100772700B1 (en) * | 2006-06-29 | 2007-11-02 | 주식회사 하이닉스반도체 | Memory device that have bitline equalizing unit in cell array, and method for locating bitline equalizing unit in cell array |
JP5690464B2 (en) * | 2007-11-20 | 2015-03-25 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Semiconductor memory device |
US7701785B2 (en) * | 2008-06-23 | 2010-04-20 | Freescale Semiconductor, Inc. | Memory with high speed sensing |
JP2014149884A (en) * | 2013-01-31 | 2014-08-21 | Micron Technology Inc | Semiconductor device |
KR20160074907A (en) * | 2014-12-19 | 2016-06-29 | 에스케이하이닉스 주식회사 | Wordline driver for semiconductor memory device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2785655B2 (en) * | 1993-11-01 | 1998-08-13 | 日本電気株式会社 | Semiconductor device |
-
1996
- 1996-01-25 JP JP8010527A patent/JP2757849B2/en not_active Expired - Fee Related
-
1997
- 1997-01-22 US US08/787,237 patent/US5793664A/en not_active Expired - Fee Related
- 1997-01-23 CA CA002195836A patent/CA2195836C/en not_active Expired - Fee Related
- 1997-01-24 TW TW086100765A patent/TW340942B/en not_active IP Right Cessation
- 1997-01-25 KR KR1019970002110A patent/KR100242906B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CA2195836C (en) | 2001-03-20 |
KR100242906B1 (en) | 2000-02-01 |
TW340942B (en) | 1998-09-21 |
KR970060221A (en) | 1997-08-12 |
US5793664A (en) | 1998-08-11 |
JPH09205182A (en) | 1997-08-05 |
JP2757849B2 (en) | 1998-05-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |