CA2196557A1 - Raised tungsten plug antifuse and fabrication process - Google Patents
Raised tungsten plug antifuse and fabrication processInfo
- Publication number
- CA2196557A1 CA2196557A1 CA002196557A CA2196557A CA2196557A1 CA 2196557 A1 CA2196557 A1 CA 2196557A1 CA 002196557 A CA002196557 A CA 002196557A CA 2196557 A CA2196557 A CA 2196557A CA 2196557 A1 CA2196557 A1 CA 2196557A1
- Authority
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- Canada
- Prior art keywords
- layer
- antifuse
- forming
- interlayer dielectric
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A suction stylet (20) has a main body (22) with a central passageway which extends along the length of the main body (22). The central passageway (28) is in fluid communication with a suction source at one end, and in fluid communication with an elongated suction stylet extension (34) at an opposite end. The extension has a free end (38) with a suction port or ports (42). The main body (22) also includes a connector member (32) for releasable attachment with an endotracheal tube (60). A vent arm (44) extends off the main body (22), and includes a vent passageway (46) that opens into the central passageway (28), preferably at an angle of 90 degrees or less. The vent arm (44) extends toward the free end (38) of the extension (34), and features a vent port (54) at its end that opens into the vent passageway (46).
Description
wo s6l3ss6~
~P E CIEI~IIQI![
RAISED TUNGSTEN PLUG ANTIFUSE
AND FABRICATION PROCESS
BACKGROUND OF THE INVENTION
5 1. Field Of The l~ tion The present invention relates to user~ ,, ' ' ~ antifuse devices. More particularly, tbe present invention relates to several; ' ' of a raised tungsten plug antifuse and to metbods for fabricating such antifuses.
~P E CIEI~IIQI![
RAISED TUNGSTEN PLUG ANTIFUSE
AND FABRICATION PROCESS
BACKGROUND OF THE INVENTION
5 1. Field Of The l~ tion The present invention relates to user~ ,, ' ' ~ antifuse devices. More particularly, tbe present invention relates to several; ' ' of a raised tungsten plug antifuse and to metbods for fabricating such antifuses.
2. The Prior Art Various antifuse structures are known in the prior art The prior-art antifuses may be divided into two groups. A first group includes those antifuses in which the lower electrode comprises a conductive region in a ~ substrate and tbe upper electrode comprises a layer above the substrate. A layer of antifuse material disposed between the lower and upper electrodes usually comprises a single dielectric layer or a plurality of dielectric layers. An example 15 of such an antifuse is shown in United States patent No. 4,823,181 to Mohsen et al. and United States patent No. 4,543,594 to Mohsen et al.
A second group of antifuses comprises antifuses in which both electrodes are disposed in layers above the surface of a substrate which may be either a conducting material, a .
material, or an insulating material. The electrodes may comprise materials such as meul layers or 20 polysilicon layers. A layer of antifuse material disposed between the lower and upper electrodes may comprise a single dielectric layer, a plurality of dielectric layers, a layer of a material such as amorphous silicon, or a layer of a material such as amorphous silicon in ~ ' with one or more dielectric layers. The second group of antifuses is more closely associated with the present mvention.
Examples of above-the-substrate antifuses include those disclosed in United Sutes Patent No. 5,070,384 to McCollum et al., United States Patent No. 5,175,715 to Husher et al., United States Patent No. 5,181,096 to Forouhi, United States Patent No. 5,272,101 to Forouhi et al., ~ ~2 1 '9~ ~ 7 wo 96/38861 r~
and United States Patent No. 5,196,724 to Gordon et al.
It is an object of the present invention to provide an improved above-the-substrate antifuse and methods for fabricating such an antifuse.
BRIEF DESCRIPTION OF TEIE INVENTION
An antifuse according to the present invention ~: clùde i a lower electrode formed from a metal layer in a , A mterlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug extending from about 250 to about 1500 angstroms above the upper surface of the interlayer dielectric. The upper edges of tbe plug are rounded An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitlide sandwich or a silicon nitride, amorphous silicon, silicon nitride sandwich covered by a titanium nitride layer, is dispo~d above tbe plug. Oxide spacers may be disposed around the edges of the antifuse layer. An upper electrode, preferably comprising a metal layer including a titanium nitride barrier layer is disposed over the antifuse layer.
The antifuse of the present invention may be fabricated according to another aspect of the present invention. A lower electrode is frst formed from a metal layer disposed over an underlying insulating layer. A interlayer dielectric layer is formed over the lower electrode and is planarized using techniques such as chemical mechanical polishing (CMP). An aperture is formed in the interlayer dielectric layer.
A conductive plug, comprising a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is then etched back, exposing a portion of the plug to create a raised portion of the plug. The upper edges of the plug are then rounded using, for example, a CMP process step which also serves to smooth any rough points from the plug surface.
An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon uitride sandwich or a silicon nitride, amorphous silicon, silicon nitride sandwich covered by a titanium nitride layer, is formed and defined over the plug and at least a portion of the upper surface of the interlayer dielectric layer. In a variation of this process sequence, an additional titanium nitride layer is formed over the plug and the upper surface of the interlayer dielectric layer prior to forming the antifuse layer or layers.
~ WO9613~1861 2 t ~9~7~ ", ~
Oxide spacers are then formed aroumd the edges of the amtifuse layer. An upper electrode, preferably comprising a metal layer, is then formed and defined over the antifuse layer and the oxide spacers.
BRIEF DESCRIPTION OF THE DRAWINGS
S FIG. 1 is a cross-sectional vie,w of an antifuse according to a first ' ' of the present mvention.
FIGS. 2a-2e are cross sectional views of the antifuses of FIG. I shown after completion of selected steps in its fabrication.
FIG. 3 is a cross ~liulldl view of am antifuse according to a second ' ' of the present invention.
FIGS. 4a 4b are cross sectional views of the antifuse of FIG. 3 shown after completion of ~lected steps im its fabrication.
FIG. 5 is a cross-sectional view of an antifuse according to a third ' " of the present invention.
F~G. 6 is a cross sectional view of the antifuse of FIG. S shown after completiûn of selected steps in its fabrication.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in amy way limiting. Other b~ " of the invention will 20 readily suggest themselves to such skilled persons.
Referring first to FIG. 1, a cross sectional view of an antifuse 10 according to a first b~ ' of the present invention is presented. Antifuse 10 is fabricated over a suitable substrate 12. Substrate 12 may be one of numerous things, including, but not limited to, an insulating layer disposed above a ' substrate containing fumctional circuits or other 25 structures. The nature of substrate 12 is not import;mt to the present invention but those of ordinary skill im the art will understand that the usual c.~ of the present invention will be an integrated circuiL
WO 96/38861 ~ 1 9 6 5 5 7 The lower conductive electrode 14 of the antifu~ 10 of the pre~nt invention may compri~
a portion of a metal layer or composite metal layer u~d as ~m layer in the integrated circuit and may thus be fabricated from materials known for such u~. Such metal layers typically have thicknes~s in the range of from about 5,000 angstroms to about 12,000 angstroms, typically 5 about 9,000 angstroms, although the~ tbicknesses are illustrative only and are not limiting.
Persons skilled in the art are familiar vith integrated circuit metal layers and the details of such layers need not be ~t forth herein.
An interlayer dielectric layer 16 is formed ovsr the surface of the lo ver conductive electrode 14. Interlayer dielectric layer 16 may be formed from materials such as deposited silicon 10 dioxide. Typical interlayer dielectric layer thicknesses 16 which may be used in the poe~nt imvention aoe in the range of from about 5,000 angstroms to about 15,000 angstroms, typically about 9,000 amgstroms altbough this thickness range is illustrative only and not limiting.
A conductive plug 18 is formed in an aperture in the interlayer dielectric layer 16 and extends above its upper surface. According to a poesendy poeferoed; ' ~ ' of the invention, the raised portion of the conductive plug 18 extends from about 250 to about 1500 angstroms above the upper surface of the interlayer dielectric layer 16 and is formed from a material such as tungsten or titanium nitride. Tungsten plug technology is well understood in the ~~ ~ ' arts. As presently preferoed, the top edge of the tungsten plug is slightly rounded by a process such as chemical mechanical polishing (CMP) to oeduce the othervi~ overly high field 20 : which would exist at the sharp edge of the upper surface of the conductive plug 18.
The raised tungsten plug 18 allows the antifuse layer boeakdown during l~luO~ O to occur along the rounded corners of the conductive plug 18 due to field . in the~
oegions. This provides the advantage of controlling wheoe the conductive link is formed, keeping the link away from the edge of the antifu~ layer stack wheoe it could abut an oxide material 25 resulting in an, , ' thermal structuoe which could materially affect oeliability of the 1"", ' devlce. The rounding of the expo~d top of the plug controls the amount of field during I ,, g to poevent uncontrolled boealcdown.
According to this first ' ~ ' of the poe~nt invention, an antifu~ material 20 isdispo~d above the upper surface of the interlayer dielectric layer 16. As shown in FIG. 1, the 30 antifu~ material 20 poeferably compri~s a sandwich structuoe including a first layer of silicon nitride 22, a layer of amorphous silicon 24 and a ~cond layer of silicon nitride 26. The thicknes~s of the layers 22,24, and 26 will of course depend on the ~ " voltage desired. According to a pre~ntly preferoed ' ' of the poe~nt invention, a thin layer 28 of silicon dioxide, e.g. about I to 300 angstroms, preferably about 30 angstroms is dispo~d on ~965~7~
the upper surface of either first silicon nitride layer 22 or amorphous silicon layer 24. FIG. I
shows a thin layer 28 of silicon dioxide 28 disposed on the upper surface of first silicon nitride layer 22 although it is to be understood that silicon dioxide layer 28 could also be disposed on the upper surface of amorphous silicon layer 24. Persons of ordinary skill in the art will recogmze 5 that thin silicon dioxide layer 28 may optionally be omitted from antifuse 10.
~ The purpose of oxide layer 28 is to reduce la~age and raise I O , voltage applied in one orientation. If oxide layer 28 is placed on the upper surface of first silicon nitride layer 22, tbe L v ' g voltage will be higher if the positive potenùal is applied to the lower conductive electrode 14~ If oxide layer 28 is placed on the upper surface of amorphous silicon layer 24, the 10 ~ " ., voltage will be higher if the positive potential is applied to the upper electrode~
Antifuse 10 of FIG I includes a layer of titanium nitride 30 having a typical thickness in the range of about 500 to about 3,000, typically about 2,000 angstroms, disposed over the upper surface of second silicon nitride layer 26 The titanium nitride layer 30 serves to create the conductive link and poevent alummum from bemg , ' into the link~ As presendy preferred, after formation of the titanium nitride layer 30, the layers 22, 24, 26, 28 and 30 are defined in a smgle etching step and an oxide spacer 32 is fonned aroumd the periphery of the defined structure to improve step coverage of the overlying layer~
An upper conductive electrode 34 completes the structure of antifuse 10. As wfih Ihe lower conductive electrode 14, the upper conductive electrode 34 may comprise a portion of a 20 metal ' ,~ layer in the integrated circuit containing antifuse 10~ Those of ordinary skill in the art will recognize that other layers and structures, such as passivation layers and contacts, will be fonned m the integrated circuit containing antifuse 10~ These layers and structures are well known and are not shown in the drawing figures to avoid ~. . ' E the disclosure and thus obscuring the disclosure of the invention herein.
The ~1, 0 " of antifuse 10 of FIG. 1 will be understood by those of ordinary skiU in the art from the following example. An exemplary amtifuse may be fabricated according to Ihe present invention, wherein frst and second layers of silicon nitride 22 and 26 are about 65 angstroms thick, amorphous sihcon layer 24 is ahout 450 angstroms thick, and layer oxide 28 is about 30 angstroms thick and is disposed over the frst silicon nitride layer 22~ In such a case. the antifuse 10 should program at a voltage of about 10.5 volts if the positive potential is apphed to the upper conductive electrode 34~ On the other hand, the antifuse 10 should program at a voltage of about 12 volts if the posiùve potenùal is applied to the lower conductive electrode 14~
Referring now to FIGS. 2a-2e, cross-sectional views of the anùfuse 10 of FIG. 1 are n p ~
WO96/38861 2~965~7 PCT/US96/08263 shown after completion of selected steps in the fabrication process. Referring furst to FIG. 2a, lower conductive electrode 14 has been formed on substrate 12 by use of ~u..~ ' materials processing tecbnology. Portions of the layer of which lower conductive electrode 14 is a part (not shown) have been defined using standard I ' ' ' ., . ' and etching techniques. Interlayer 5 dielectric layer 16, preferably comprising a layer of silicon dioxide has been formed over the upper surface of lower conductive electrode 14, preferably using lu.. . deposition techniques and an antifuse aperture 36 bas been formèd therein. A tungsten plug 18 has been formed in antifuse aperture 36 usmg blanl~et CVD deposition techniques and has heen etched back to e~cpose the upper surface of interlayer dielectric layer 16 as is well known in the arL FIG. 2a shows the 10 structure resulting after completion of these process steps.
Referring now to FIG. 2b, the tungsten plug 18 has been raised above the surface of the interlayer dielectric layer 16 by etching back the surface of the mterlayer dielectric layer 16 using techniques such as wet chemical or dry chemical etching.
According to a presendy preferred ' " of the invention, after completion of the etching 15 step, the tungsten plug 18 extends beyond the upper surface of the interlayer dielectric layer 16 by from about 250 to about 1500 angstroms, preferably about 500 angstroms above the upper surface of the interlayer dielectric layer 16. FIG. 2b shows the structure resulting after completion of the raised plug etching step.
Next, as shown in FIG. 2c, a chemical mechanical polishing (CMP) step is performed to 20 slightly round the corners of the top of the tungsten plug 18. This step may be performed using chemical mechanical polishing equipment for about O.S mmutes with mechanical silicon oxide abrasive such as is used in typical p~ ;.... steps. FIG. 2c shows the structure resulting after completion of the CMP step. The CMP step removes the sharp corners of the tungsten plug 18 amd assures that L ly high fields will not exist during application of p., O g 25 voltages and result in uncertain l~o g voltage ~ ' in production.
Referring now to FlG. 2d, antifuse layer 20 is formed. According to a presently preferred ' ~ " of the invention, a first layer of silicon nitride 22 is formed to a thickness of between about 1 angstrom and about 300 angstroms, typically about 65 angstrorns, using CVD techniques.
Next, a thin layer of silicon dioxide 28, having a thickness of between about 1 to 300 angstroms, 30 preferably about 30 angstroms, is formed over the upper surface of silicon nit~ide layer 22, preferably usmg CVD techniques if the preferred; ' ' of the invention is to be practiced.
Next, a layer of amorphous silicon 24 is formed over the silicon dioxide layer 28 to a thickness of between about 100 angstroms and about 1,500 angstroms, typically about 450 angstroms, using CVD techniques. The amorphous silicon layer 24 may be undoped or may be doped to a level of 35 less than about lel8 using l ' . ' arsenic, nitrogen, or oxygen. A second silicon nitride ~ W096/38861 '~ 6~.57 .~ 7i layer 26 having as thickness of between about I angstrom and about 300 angstroms, typically about 65 angstroms, is next formed over the surface of the amorphous silicon layer 24 using CVD
techniques. Despite the showing in FIG. 2d of the positioning of the thin oxide layer 28 over first silicon nitride layer 22, those of ordinary skill in the art will appreciate that the thin oxide layer 28 5 is formed either before the amorphous silicon layer 24 or before the second silicon nitride layer 26.
A layer of titanium nitride 30 having a tluckness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, is next formed over the second layer of silicon nitride 26 using PVD sputtering or CVD techniques. A; ~ layer 38 is applied over titanium nitride layer 30 and the stack comprising the first silicon nitride layer 22, thin oxide layer 28, the amorphous silicon layer 24, the second silicon nitride layer 26, and the titanium nitride layer 30 and is defined using . ~_~L~Ial etching technology. FIG. 2d shows the structure resulting after completion of the stacked structure comprising layers 22, 24, 26, 28 and 30 and the stack definition etching step, but prior to removal of photomask layer 38.
Referring now to FIG. 2e, the masking layer 38 is then removed and an oxide spacer 32 is 15 formed around the edge of the stacked structure. The oxide spacer 32 may be formed by a blanket deposition of silicon dioxide (i.e., about 3,000 angstroms) followed by an plasma etching step as is known in the art. FIG. 2e shows the structure resulting after completion of the spacer etching step.
Next, with reference again to FIG. 1, the upper conductive electrode 34 is formed over the 20 stacked structure, the oxide spacers 32, and the interlayer dielectric layer 16. As will be rr by those of ordinary skill in the art, upper conductive electrode 34 may be formed from a portion of an i..~.. : metal layer in an integrated circuit (including titanium nitride as a barrier layer if aluminum is used as the metal layer) and fabrication of this layer is well known to such skilled persons. Additional w.. ~ . ' back-end steps (not shown) are then used to 25 passivate and otherwise complete the integrated circuit structure.
Referring now to FIG. 3, an antifuse 40 according to a second, ' - " of the present invention is shown in cross-sectional view. Because the antifuse 40 of FIG. 3 is similar to the antifuse 10 depicted in FIG. 1, structures in the antifuse 40 of FIG. 3 1.~ J to structures in the antifu~ 10 of F~G. I will be designated by the same reference numerals as used in FIG. 1.
30 As would be expected by persons of ordinary skill in the art, the materials and layer thicknesses for the antifuse 40 of F~G. 3 may be the same as or similar to those of the - ~ . ' ,, structures of the antifuse 10 of FIG. 1.
Antifuse 40 is fabricated over a suitable substrate 12. The lower conductive electrode 14 of WO96/38861 ~?~~~557~ PCT/US96/08263 ~
the antifuse 40 of the present invention may comprise a portion of a metal layer or composite metal layer used as an Iayer in the integrated circuit.
An interlayer dielectric layer 16 is formed over the surface of the lower conductive electrode 14. A conductive plug 18 is fonned in att aperture in the interlayer dielectric layer 16 S and extends above its upper surface. As poesen~y preferred, the top edge of the tungsten plug is slightly rounded by a process such as cher~ical mechanical polishing (CMP) to reduoe the otherwise overly high fteld . which would exist at the sharp edge of the upper surface of the conductive plug 18.
According to this second ' ~1" of the present invention, a frst titanium nitride layer 42 having a typical thickness in the range of about 500 angstroms to about 3,000 angstroms, typically about 2,000 angstroms, is disposed over the upper surface of interlayer dielectric layer 16 prior to formation of the composite antifuse material layer 20.
An antifuse material 20 is disposed above the upper surface of the first titanium nitride layer 42. As shown in FIG. 3, the antifuse material 20 of the antifuse 40 also preferably 15 comprises a sandwich structure including a frst layer of silicon nitride 22, a layer of amorphous silicon 24 and a second layer of silicon nitride 26. As in the, ~ " illustrated in FIG. 1, the antifuse material 20 of antifuse 40 preferably, but not necessarily, includes a thin silicon dioxide layer 28, having a thickness of between about I to 300 angstroms, preferably about 30 angstroms, located either between the first silicon nitride layer 22 and the amorphous silicon layer 24, or 20 between the amorphous silicon layer 24 and the second silicon nitride layer 26.
The thicknesses of the layers 22, 24, 26, and 28 will of course depend on the 1,.~ 0 ~ voltage desired. As an example, if first and second layers silicon nitride 22 and 26 are made about 65 angstroms thick, amorphous silicon layer 24 is made about 450 angstroms thick, and thin oxide layer 28 is made about 30 angstroms thick, the antifuse 40 should program at 25 a voltage of about 10.5 volts as poeviously disclosed.
A second titanium nitride layer 30 having a typical thickness in the range of about 500 angstroms to about 3,000 angstroms, typically about 2,000 angstroms, is disposed over the upper surfaoe of second silicon nitride layer 26. The second titanium nitride layer 30 serves to provide material from which the conductive link is formed and to poevent aluminum from being 30 ~ into the link. As poesently poeferoed, after formation of the second titanium nitride layer 30, the layers 42, 22, 24, 26, 28, and 30 aoe defined in a single etching step and an oxide spaoer 32 is formed around the periphery of the defned structuoe to ihnprove step coverage of the overlying layer and to poevent the upper electrode from shorting to the lower electrode.
~ 2 ~ ~ ~515~75 WO 96138861 1 ~_I/U~., -' ''I
An upper conductive electrode 34 complëtes the structure of antifuse 40. As with the lower conductive electrode 14, the upper conductive electrode 34 may comprise a portion of a metal ~ layer in the integrated circuit containing antifuse 40. Those of ordinary sl~ill in the art will recognize that other layers and structures, such as passivation layers and contacts, will S be fonned in the integrated circuit containing antifuse 40. These layers and structures are well known and are not shown in the drawing figures to avoid u . _.. , ' ~ ng the disclosure and thus obscuring the disclosure of the invention herein.
Referring again now to FIGS. 2a-2c and in addition to FIGS. 4a-4b, cross ~Liu ~I views of the antifuse of FIG.3 are shown after completion of selected steps in the fabrication process.
FIGS. 2a-2c depict the formation of lower conductive electrode 14, interlayer dielectric layer 16, antifuse aperture 36, and tungsten plug 18, as well as the process steps for raising the tungsten plug 18 above the upper surface of the interlayer dielectric layer 16 and for rounding its corners.
FIG. 2a shows the structure resulting after fommation of the tungsten plug 18 and I ' of the interlayer dielectric layer 16 and tungsten plug 18. FlG.2b shows the structure resulting after completion of the raised plug etching step, and FIG. 2c shows the structure resulting after completion of the CMP step.
Referring now to FIG. 4a, frrst titanium nitride layer 42 is formed over the tungsten plug 18 and the upper surface of interlayer dielectric layer 16 to a thickness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, using PVD or CVD
techniques. Antifuse material layer 20 is then formed.
As in the ' ~ ' of FIG. 1, it is preferred to use a multilayer structure for antifuse material layer 20. A first layer of silicon nitride 22 iS formed to a thickness of between about I
angstrom and about 300 angstroms, typically about 65 angstroms, using CVD techniques. Next, a layer of amorphous silicon 24 is formed over the silicon nitride layer 22 to a tbickness of between about 100 angstroms and about 1,500 angstroms, typically about 450 angstroms, using CVD techniques. The amorphous silicon layer 24 may be undoped or may be doped to a level of less than about lel8 using 1 ' ~ ' JU:~, arsenic, nitrogen, or oxygen. A second silicon nitride layer 26 having as thickness of between about I angstrom and about 300 angstroms, typically about 65 angstroms, is next formed over the surface of the amorphous silicon layer 24 using CVD
techniques. According to a presently preferred ' ~ ' of the invention, a thin silicon dioxide layer 28, having a thickness of between about I to 300 angstroms, preferably about 30 angstroms, is formed either ~ ' '~, after formation of the first silicon nitride layer 22, or ' '~, after formation of the amorphous silicon layer 24, using CVD techniques.
2'~ 5~7' ~
wo 96138861 A second layer of titanium nitride 30 having a thickness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, is next fonned over tbe second layer of silicon nitride 26 using PVD or CVD ~ephniques. A cu..~. ' I ' ' ' ~ e layer 44 is applied over second titanium nitr,id;e la~er 30 and the stack comprising dle first titanium nitride layer 42, the first silicon nitridè layer 22, the oxide layer 28, the amorphous silicon layer 24, the second silicon nitride layer 26, and the second titanium nitride layer 30 is defined using cull~ ' etching technology. FIG. 4a shows the structure resulting after completion of the stacked structure comprising layers 42, 22,24, 26, 28 and 30 and the stack definition etching step, but prior to temoval of I ' ' ~ e layer 44.
Referring now to FIG. 4b, the masking layer 44 is ~en removed and an oxide spacer 32 is formed around the edge of the stacked structure. The oxide spacer 32 may be formed by a blanket deposition of silicon dioxide (i.e., about 3,000 angstroms) followed by an plasma etching step as is known in the art. FlG.4b shows the structure resulting after completion of the spacer etching step.
Next, with reference again to FIG. 3, the upper conductive electrode 34 is formed over the stacked structure, the o~ide spacers 32, and the interlayer dielectric layer 16. As will be appreciated by those of ordinary skill in the art, upper conductive electrode 34 may be formed from a por~ion of an ~ metal layer in an integrated circuit and fabrication of this layer is weU lcnown to such skiUed persons. Additional cu.,v, ' back-end steps (not shown) are then used to passivate and otherwise complete the integrated circuit structure.
The major difference between the antifuse 10 in FIG. I and the antifuse 40 of FIG. 3 is tbe presence of the titanium nitride 42 layer between the tungsten plug 18 and the first si]icon nitride layer 22 of the antifuse material 20. Because of the presence of this layer in the antifuse 40 of FlG. 3, the ~ . u~ ' antifuse wiU have a higher . ~ than the ~
antifuse 10 of FIG. I whose lower plate comprises only the tungsten plug 18. However, the presence of this additional layer in antifuse 40 of FlG. 3 permits more flexibility in p., " ~ g voltage polarity. Depending on the polarity of the u.", ~ g voltage, the link material for the p " ' antifuse wiU come from either titanium nitride layer 30 (positive polarity on the lower electrode 14) or titanium nitride layer 42 (positive polarity on upper electrode 34).
Referring now to FIG. 5, an antifuse 50 according to a third ~i ' - ' of the present invention is shown in cross-sectional view. Antifuse 50 of FIG. 5 is similar to the antifuse 40 depicted in FIG. 3, and therefore structures in the antifuse 50 of FIG.5 . . ' v to structures in the antifuse 40 of FIG. 3 will be designated by the same reference numerals as used in E~[G. 3. As would be expected by persons of ordinary skill in the art, the materials and layer .\ ' ~ 1~ q, ~ ~.5,7~
W096/38861 L.~ L-thicknessw for the antifuse 50 of FIG. S may be tbe same as or similar to tbose of the E structures of the antifuse 10 of FIG. 1 and the antifuse 40 of FIG.3.
I ~i ~
Antifuse 50 is fabricated over a suihble substrate 12. Like antifuses 10 and 40 of FIGS. I
and 3 ~w~L.~l~, tbe lower conductive electrode 14 of the antifuse 50 of tbe present invention S may comprise a portion of a metal layer or composite metal layer used as an ~ Iayer in the mtegrated circuit.
As in tne previous; ' " of amtifuse accordmg to tbe prwent invention, an interlayer dielectric layer 16 is formed over the surface of the lower conductive electrode 14 amd a conductive plug 18 is formed m an aperture m the mterlayer dielectric layer 16 and extends above its upper surface. As presently preferred, the top edge of the tungsten plug is sligbtly rounded by a procws such as chemical mechanical polishing tCMP) to reduce the otherwise overly high field which would exist at the sharp edge of the upper surface of the tlmgsten plug 18.
As im antifuse 40 of the second ' ~ " of the prwent mvention, antifuse S0 mcludw a first tihnium nitride layer 42 having a typical thicknws m the range of about S00 angstroms to lS about 3,000 angstroms, typically about 2,000 angstroms, and is disposed over the upper surface of interlayer dielectric layer 16 prior to formation of the composite antifuse material layer 20.
An antifuse material 20 is disposed above tbe upper surface of the first tihnium nitride layer 42. As with antifuse 40 of FtG. 3, the antifuse material 20 of the antifuse 50 also preferably comprisw a sandwich structure includmg a first layer of silicon nitride 22, a layer of amorphous silicon 24 and a second layer of silicon nitride 26. As im the; ' " illustrated in FIG. 1, the antifuse material 20 of antifuse 50 preferably, but not necessarily, includes a thin sihcon dioxide layer 28, having a thickness of between about I to 300 angstroms, preferably about 30 angstroms, located either between the frst silicon nitride layer 22 amd the amorphous silicon layer 24, or between the amorphous silicon layer 24 and the second silicon nitride layer 26.
2S The l! L ~ . -- ~ of the layers 22, 24, 26, and 28 will of course depend on the voltage dwired. As an example, if frst and second layers silicon nitride 22 and 26 are made about 65 angstroms thick, amorphous silicon layer 24 is made about 450 angstroms thic_ and thin oxide layer 28 is made about 30 angstroms tluck, the amtifuse 50 should program at a voltage of about 10.5 volts as previously disclosed.
A second titanium nitride layer 30 having a typical thickness in the range of about 500 angstroms to about 3,0110 angstroms, typically about 2,000 angstroms, is disposed over the upper surface of second silicon nitride layer 26. The second tit3nium nitride layer 30 serves to provide 7' WO 96138861 I ~ .A
material from which dle conductive link is formed and to prevent aluminum from being ' into dhe link As presendy prefer ed, after formation of the second titanium nitride layer 30, the layers 42, 22, 24, 26, 28, and 30 a~e defined in a single etching step.
i~ ' The major difference between antifuse 50 of FIG. S and antifuse 40 of FIG. 3 is the absence of the oxide spacer 32 which was formed around the periphery of the defined structure in antifuse 40 of FIG.3 to improve step coverage of the overlying layer and to prevent the upper electrode from shorting to the lower electrode. As shown in FIG. 5, antifuse 50 employs a dielectric layer 52, preferably formed from a material such as silicon dioxide, disposed over the stacked structure of layers 42, 22, 24, 26, 28, and 30. An aperture 54 in dielectric layer 52 allows upper electrode 34 to make contact with second titanium nitride layer 30. As will be appreciated by those of ordinary skill in the art, an additional masking and etching sequence are required to form aperture 54 in dielectric layer 52 of antifuse 50 of FIG. 5.
The upper conductive electrode 34 completes the structure of antifuse 50, mal;ing contact with upper second titanium nitride layer 30 through the aperture 54 in dielectric layer 52. As widh lS dhe lower conductive electrode 14, dhe upper conductive electrode 34 may comprise a portion of a metal ~ ~ Iayer in dhe integrated circuit contaming antifuse S0. Those of ordinary s~ill in the art will recognize that other layers and structures, such as passivation layers and contacts, will be formed in the integrated circuit containing antifuse 50. These layers and structures are well known and are not shown in the drawing figures to avoid u, ~,., , ' ~ g dhe disclosure and thus obscuring dhe disclosure of dle invention herein.
The fabrication of antifuse 50 of FIG. S may be understood with reference ftrst to FIGS.
2A-2c, FIG. 4a, and FIG. 6, cross-sectional views of dhe antifuse of FIG. S shown after completion of selected steps in the fabrication process.
FIGS. 2a-2c depict the formation of lower conductive electrode 14, interlayer dielectric layer 16, antifuse aperture 36, and tungsten plug 18, as well as the process steps for raising the tungsten plug 18 above dle upper surface of the interlayer dielectric layer 16 and for rounding its corners. FIG. 2a shows the structure resulting after formation of the tungsten plug 18 and I ' of dhe interlayer dielectric layer 16 and tlmgsten plug 18. FIG. 2b shows dhe structure resulting after completion of dhe raised plug etching step, and FIG. 2c shows ~e structure resulting after completion of the CMP step.
Referring now to FIG. 4a, frst titanium nitride layer 42 is formed over the tungsten plug 18 and the upper surface of interlayer dielectric layer 16 to a thickness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, using PVD or CVD
~ 1 ~6~57 ~
wog6138861 ~ p techniques. Antifuse material layer 20 is tben formed.
~.
As in the '- ~ " of FIGS. I ,an~d 3, it is preferred to use a multilayer structure for antifuse material layer 20. A first layer of sihcoh nitride 22 is formed to a thickness of between about 1 angstrom and about 300 angstroms, typicaDy about 65 angstroms, using CVD techniques.
5 Depending on the L " ' desired, a thin silicon dioxide layer 28 is next formed over the - upper surface of tbe first silicon nitride layer 22. FIG. 4a illustrates this step. Next, a layer of amorphous silicon 24 is formed over the silicon nitride layer 22 or the thin oxide layer 28 to a tbickness of between about 100 angstroms and about 1,500 angstroms, typically about 450 angstroms, using CVD tecbniques. The amorphous silicon layer 24 may be undoped or may be 10 doped to a level of less than about lel8 using I ' - . ' ~, arsenic, nitrogen, or oxygen. A
second silicon nitride layer 26 having as tbickness of between about 1 angstrom and about 300 angstroms, typically about 65 angstroms, is next formed over the surface of the amorphous silicon layer 24 using CVD techniques. Those of ordinary slcill in the art will appreciate that tbin oxide layer 28 may be formed after formadon of amorphous silicon layer 24 and prior to formadon of 15 second silicon nitride ]ayer 26, rather than after formadon of first silicon nitride layer 22, although this opdon is not illustrated in the figures.
A second layer of dtanium nitride 30 having a thickness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, is next formed over the second layer of silicon nitride 26 using PVD or CVD techniques. A Cul~ g layer 44 is 20 applied over second dtanium nitride layer 30 and tbe stack comprising the first dtanium nitride layer 42, the first silicon nitride layer 22, the amorphous silicon layer 24, the second silicon nitride layer 26, and tbe second tdtanium nitride layer 30 is defned using ~,u~ tiu~d etching technology. FIG. 4a shows the structure resulting after compledon of tbe stacked structure comprising layers 42, 22, 24, 26, 28, and 30 and the stack definition etching step, but prior to 25 removal of I ' ~ g layer 44.
Referring now to FIG. 6, the masking layer 44 is then removed and a dielectric layer 52 is formed over the stacked structure and interlayer dielectric layer 16. The dielectric layer 52 may be formed by a blanl~et deposidon of silicon dioxide (i.e., about 500 to about 3,000 angstroms, typicaDy about 1,000) as is known in the art. A photomaslc 56 is formed over the surface of dielectric layer 52 using ~,u.. ' 1 ' ~, , ' .~ techniques. Aperture 54 is next formed in dielectric layer 52 to expose the upper surface of second titanium nitride layer 30. FIG. 6 shows the structure resuldng after compledon of the aper~ure etching step but prior to removal of photomask 56.
Next, with reference again to FIG. 5, the upper conductdve electrode 34 is formed over the ~ ;3 r~
wo 96/38861 2 1 9 6 5 5 7 i~
stacl~ed structure, the dielectric layer 52, and tbe interlayer dielectric layer 16. As will be p, ' ' by those of ordinary skill in the art, upper conductive elec~rode 34 may be formed from a ponion of an :~ metal layer in an integrated circuit and fabrication of this layer is well known to such s~lcilled persons. Additional w... ' bacX-end steps (not shown) are then S used to passivate and otherwise complete the integ~ted circuit structure.
The major differenoe between the àntifuse 40 in FIG. 3 and the antifuse 50 of FIG. S is the absenoe of the oxide spaoers 32 and the presenoe of tbe dieleclric layer 52. As noted, this ~- requires an additional masking and etching sequence to form the aperlure 54 in dielectric layer 52. The advantage of the bc " of FIG. S over the ' ' of FIG. 3 is 10 that, forming, patterning, and etching dielec~ric layer 52 is more ~ ' than controlling spaoer sidewall height.
While ' ' and _,, I of this invention have been shown and described, it would be apparent to those slcilled in the art that many more "~ than mentioned above are possible without departing from the inventive conoepts herein. The invention. therefore, is not 15 to be restricted exoept in the spirit of the appended claims.
A second group of antifuses comprises antifuses in which both electrodes are disposed in layers above the surface of a substrate which may be either a conducting material, a .
material, or an insulating material. The electrodes may comprise materials such as meul layers or 20 polysilicon layers. A layer of antifuse material disposed between the lower and upper electrodes may comprise a single dielectric layer, a plurality of dielectric layers, a layer of a material such as amorphous silicon, or a layer of a material such as amorphous silicon in ~ ' with one or more dielectric layers. The second group of antifuses is more closely associated with the present mvention.
Examples of above-the-substrate antifuses include those disclosed in United Sutes Patent No. 5,070,384 to McCollum et al., United States Patent No. 5,175,715 to Husher et al., United States Patent No. 5,181,096 to Forouhi, United States Patent No. 5,272,101 to Forouhi et al., ~ ~2 1 '9~ ~ 7 wo 96/38861 r~
and United States Patent No. 5,196,724 to Gordon et al.
It is an object of the present invention to provide an improved above-the-substrate antifuse and methods for fabricating such an antifuse.
BRIEF DESCRIPTION OF TEIE INVENTION
An antifuse according to the present invention ~: clùde i a lower electrode formed from a metal layer in a , A mterlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug extending from about 250 to about 1500 angstroms above the upper surface of the interlayer dielectric. The upper edges of tbe plug are rounded An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitlide sandwich or a silicon nitride, amorphous silicon, silicon nitride sandwich covered by a titanium nitride layer, is dispo~d above tbe plug. Oxide spacers may be disposed around the edges of the antifuse layer. An upper electrode, preferably comprising a metal layer including a titanium nitride barrier layer is disposed over the antifuse layer.
The antifuse of the present invention may be fabricated according to another aspect of the present invention. A lower electrode is frst formed from a metal layer disposed over an underlying insulating layer. A interlayer dielectric layer is formed over the lower electrode and is planarized using techniques such as chemical mechanical polishing (CMP). An aperture is formed in the interlayer dielectric layer.
A conductive plug, comprising a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is then etched back, exposing a portion of the plug to create a raised portion of the plug. The upper edges of the plug are then rounded using, for example, a CMP process step which also serves to smooth any rough points from the plug surface.
An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon uitride sandwich or a silicon nitride, amorphous silicon, silicon nitride sandwich covered by a titanium nitride layer, is formed and defined over the plug and at least a portion of the upper surface of the interlayer dielectric layer. In a variation of this process sequence, an additional titanium nitride layer is formed over the plug and the upper surface of the interlayer dielectric layer prior to forming the antifuse layer or layers.
~ WO9613~1861 2 t ~9~7~ ", ~
Oxide spacers are then formed aroumd the edges of the amtifuse layer. An upper electrode, preferably comprising a metal layer, is then formed and defined over the antifuse layer and the oxide spacers.
BRIEF DESCRIPTION OF THE DRAWINGS
S FIG. 1 is a cross-sectional vie,w of an antifuse according to a first ' ' of the present mvention.
FIGS. 2a-2e are cross sectional views of the antifuses of FIG. I shown after completion of selected steps in its fabrication.
FIG. 3 is a cross ~liulldl view of am antifuse according to a second ' ' of the present invention.
FIGS. 4a 4b are cross sectional views of the antifuse of FIG. 3 shown after completion of ~lected steps im its fabrication.
FIG. 5 is a cross-sectional view of an antifuse according to a third ' " of the present invention.
F~G. 6 is a cross sectional view of the antifuse of FIG. S shown after completiûn of selected steps in its fabrication.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in amy way limiting. Other b~ " of the invention will 20 readily suggest themselves to such skilled persons.
Referring first to FIG. 1, a cross sectional view of an antifuse 10 according to a first b~ ' of the present invention is presented. Antifuse 10 is fabricated over a suitable substrate 12. Substrate 12 may be one of numerous things, including, but not limited to, an insulating layer disposed above a ' substrate containing fumctional circuits or other 25 structures. The nature of substrate 12 is not import;mt to the present invention but those of ordinary skill im the art will understand that the usual c.~ of the present invention will be an integrated circuiL
WO 96/38861 ~ 1 9 6 5 5 7 The lower conductive electrode 14 of the antifu~ 10 of the pre~nt invention may compri~
a portion of a metal layer or composite metal layer u~d as ~m layer in the integrated circuit and may thus be fabricated from materials known for such u~. Such metal layers typically have thicknes~s in the range of from about 5,000 angstroms to about 12,000 angstroms, typically 5 about 9,000 angstroms, although the~ tbicknesses are illustrative only and are not limiting.
Persons skilled in the art are familiar vith integrated circuit metal layers and the details of such layers need not be ~t forth herein.
An interlayer dielectric layer 16 is formed ovsr the surface of the lo ver conductive electrode 14. Interlayer dielectric layer 16 may be formed from materials such as deposited silicon 10 dioxide. Typical interlayer dielectric layer thicknesses 16 which may be used in the poe~nt imvention aoe in the range of from about 5,000 angstroms to about 15,000 angstroms, typically about 9,000 amgstroms altbough this thickness range is illustrative only and not limiting.
A conductive plug 18 is formed in an aperture in the interlayer dielectric layer 16 and extends above its upper surface. According to a poesendy poeferoed; ' ~ ' of the invention, the raised portion of the conductive plug 18 extends from about 250 to about 1500 angstroms above the upper surface of the interlayer dielectric layer 16 and is formed from a material such as tungsten or titanium nitride. Tungsten plug technology is well understood in the ~~ ~ ' arts. As presently preferoed, the top edge of the tungsten plug is slightly rounded by a process such as chemical mechanical polishing (CMP) to oeduce the othervi~ overly high field 20 : which would exist at the sharp edge of the upper surface of the conductive plug 18.
The raised tungsten plug 18 allows the antifuse layer boeakdown during l~luO~ O to occur along the rounded corners of the conductive plug 18 due to field . in the~
oegions. This provides the advantage of controlling wheoe the conductive link is formed, keeping the link away from the edge of the antifu~ layer stack wheoe it could abut an oxide material 25 resulting in an, , ' thermal structuoe which could materially affect oeliability of the 1"", ' devlce. The rounding of the expo~d top of the plug controls the amount of field during I ,, g to poevent uncontrolled boealcdown.
According to this first ' ~ ' of the poe~nt invention, an antifu~ material 20 isdispo~d above the upper surface of the interlayer dielectric layer 16. As shown in FIG. 1, the 30 antifu~ material 20 poeferably compri~s a sandwich structuoe including a first layer of silicon nitride 22, a layer of amorphous silicon 24 and a ~cond layer of silicon nitride 26. The thicknes~s of the layers 22,24, and 26 will of course depend on the ~ " voltage desired. According to a pre~ntly preferoed ' ' of the poe~nt invention, a thin layer 28 of silicon dioxide, e.g. about I to 300 angstroms, preferably about 30 angstroms is dispo~d on ~965~7~
the upper surface of either first silicon nitride layer 22 or amorphous silicon layer 24. FIG. I
shows a thin layer 28 of silicon dioxide 28 disposed on the upper surface of first silicon nitride layer 22 although it is to be understood that silicon dioxide layer 28 could also be disposed on the upper surface of amorphous silicon layer 24. Persons of ordinary skill in the art will recogmze 5 that thin silicon dioxide layer 28 may optionally be omitted from antifuse 10.
~ The purpose of oxide layer 28 is to reduce la~age and raise I O , voltage applied in one orientation. If oxide layer 28 is placed on the upper surface of first silicon nitride layer 22, tbe L v ' g voltage will be higher if the positive potenùal is applied to the lower conductive electrode 14~ If oxide layer 28 is placed on the upper surface of amorphous silicon layer 24, the 10 ~ " ., voltage will be higher if the positive potential is applied to the upper electrode~
Antifuse 10 of FIG I includes a layer of titanium nitride 30 having a typical thickness in the range of about 500 to about 3,000, typically about 2,000 angstroms, disposed over the upper surface of second silicon nitride layer 26 The titanium nitride layer 30 serves to create the conductive link and poevent alummum from bemg , ' into the link~ As presendy preferred, after formation of the titanium nitride layer 30, the layers 22, 24, 26, 28 and 30 are defined in a smgle etching step and an oxide spacer 32 is fonned aroumd the periphery of the defined structure to improve step coverage of the overlying layer~
An upper conductive electrode 34 completes the structure of antifuse 10. As wfih Ihe lower conductive electrode 14, the upper conductive electrode 34 may comprise a portion of a 20 metal ' ,~ layer in the integrated circuit containing antifuse 10~ Those of ordinary skill in the art will recognize that other layers and structures, such as passivation layers and contacts, will be fonned m the integrated circuit containing antifuse 10~ These layers and structures are well known and are not shown in the drawing figures to avoid ~. . ' E the disclosure and thus obscuring the disclosure of the invention herein.
The ~1, 0 " of antifuse 10 of FIG. 1 will be understood by those of ordinary skiU in the art from the following example. An exemplary amtifuse may be fabricated according to Ihe present invention, wherein frst and second layers of silicon nitride 22 and 26 are about 65 angstroms thick, amorphous sihcon layer 24 is ahout 450 angstroms thick, and layer oxide 28 is about 30 angstroms thick and is disposed over the frst silicon nitride layer 22~ In such a case. the antifuse 10 should program at a voltage of about 10.5 volts if the positive potential is apphed to the upper conductive electrode 34~ On the other hand, the antifuse 10 should program at a voltage of about 12 volts if the posiùve potenùal is applied to the lower conductive electrode 14~
Referring now to FIGS. 2a-2e, cross-sectional views of the anùfuse 10 of FIG. 1 are n p ~
WO96/38861 2~965~7 PCT/US96/08263 shown after completion of selected steps in the fabrication process. Referring furst to FIG. 2a, lower conductive electrode 14 has been formed on substrate 12 by use of ~u..~ ' materials processing tecbnology. Portions of the layer of which lower conductive electrode 14 is a part (not shown) have been defined using standard I ' ' ' ., . ' and etching techniques. Interlayer 5 dielectric layer 16, preferably comprising a layer of silicon dioxide has been formed over the upper surface of lower conductive electrode 14, preferably using lu.. . deposition techniques and an antifuse aperture 36 bas been formèd therein. A tungsten plug 18 has been formed in antifuse aperture 36 usmg blanl~et CVD deposition techniques and has heen etched back to e~cpose the upper surface of interlayer dielectric layer 16 as is well known in the arL FIG. 2a shows the 10 structure resulting after completion of these process steps.
Referring now to FIG. 2b, the tungsten plug 18 has been raised above the surface of the interlayer dielectric layer 16 by etching back the surface of the mterlayer dielectric layer 16 using techniques such as wet chemical or dry chemical etching.
According to a presendy preferred ' " of the invention, after completion of the etching 15 step, the tungsten plug 18 extends beyond the upper surface of the interlayer dielectric layer 16 by from about 250 to about 1500 angstroms, preferably about 500 angstroms above the upper surface of the interlayer dielectric layer 16. FIG. 2b shows the structure resulting after completion of the raised plug etching step.
Next, as shown in FIG. 2c, a chemical mechanical polishing (CMP) step is performed to 20 slightly round the corners of the top of the tungsten plug 18. This step may be performed using chemical mechanical polishing equipment for about O.S mmutes with mechanical silicon oxide abrasive such as is used in typical p~ ;.... steps. FIG. 2c shows the structure resulting after completion of the CMP step. The CMP step removes the sharp corners of the tungsten plug 18 amd assures that L ly high fields will not exist during application of p., O g 25 voltages and result in uncertain l~o g voltage ~ ' in production.
Referring now to FlG. 2d, antifuse layer 20 is formed. According to a presently preferred ' ~ " of the invention, a first layer of silicon nitride 22 is formed to a thickness of between about 1 angstrom and about 300 angstroms, typically about 65 angstrorns, using CVD techniques.
Next, a thin layer of silicon dioxide 28, having a thickness of between about 1 to 300 angstroms, 30 preferably about 30 angstroms, is formed over the upper surface of silicon nit~ide layer 22, preferably usmg CVD techniques if the preferred; ' ' of the invention is to be practiced.
Next, a layer of amorphous silicon 24 is formed over the silicon dioxide layer 28 to a thickness of between about 100 angstroms and about 1,500 angstroms, typically about 450 angstroms, using CVD techniques. The amorphous silicon layer 24 may be undoped or may be doped to a level of 35 less than about lel8 using l ' . ' arsenic, nitrogen, or oxygen. A second silicon nitride ~ W096/38861 '~ 6~.57 .~ 7i layer 26 having as thickness of between about I angstrom and about 300 angstroms, typically about 65 angstroms, is next formed over the surface of the amorphous silicon layer 24 using CVD
techniques. Despite the showing in FIG. 2d of the positioning of the thin oxide layer 28 over first silicon nitride layer 22, those of ordinary skill in the art will appreciate that the thin oxide layer 28 5 is formed either before the amorphous silicon layer 24 or before the second silicon nitride layer 26.
A layer of titanium nitride 30 having a tluckness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, is next formed over the second layer of silicon nitride 26 using PVD sputtering or CVD techniques. A; ~ layer 38 is applied over titanium nitride layer 30 and the stack comprising the first silicon nitride layer 22, thin oxide layer 28, the amorphous silicon layer 24, the second silicon nitride layer 26, and the titanium nitride layer 30 and is defined using . ~_~L~Ial etching technology. FIG. 2d shows the structure resulting after completion of the stacked structure comprising layers 22, 24, 26, 28 and 30 and the stack definition etching step, but prior to removal of photomask layer 38.
Referring now to FIG. 2e, the masking layer 38 is then removed and an oxide spacer 32 is 15 formed around the edge of the stacked structure. The oxide spacer 32 may be formed by a blanket deposition of silicon dioxide (i.e., about 3,000 angstroms) followed by an plasma etching step as is known in the art. FIG. 2e shows the structure resulting after completion of the spacer etching step.
Next, with reference again to FIG. 1, the upper conductive electrode 34 is formed over the 20 stacked structure, the oxide spacers 32, and the interlayer dielectric layer 16. As will be rr by those of ordinary skill in the art, upper conductive electrode 34 may be formed from a portion of an i..~.. : metal layer in an integrated circuit (including titanium nitride as a barrier layer if aluminum is used as the metal layer) and fabrication of this layer is well known to such skilled persons. Additional w.. ~ . ' back-end steps (not shown) are then used to 25 passivate and otherwise complete the integrated circuit structure.
Referring now to FIG. 3, an antifuse 40 according to a second, ' - " of the present invention is shown in cross-sectional view. Because the antifuse 40 of FIG. 3 is similar to the antifuse 10 depicted in FIG. 1, structures in the antifuse 40 of FIG. 3 1.~ J to structures in the antifu~ 10 of F~G. I will be designated by the same reference numerals as used in FIG. 1.
30 As would be expected by persons of ordinary skill in the art, the materials and layer thicknesses for the antifuse 40 of F~G. 3 may be the same as or similar to those of the - ~ . ' ,, structures of the antifuse 10 of FIG. 1.
Antifuse 40 is fabricated over a suitable substrate 12. The lower conductive electrode 14 of WO96/38861 ~?~~~557~ PCT/US96/08263 ~
the antifuse 40 of the present invention may comprise a portion of a metal layer or composite metal layer used as an Iayer in the integrated circuit.
An interlayer dielectric layer 16 is formed over the surface of the lower conductive electrode 14. A conductive plug 18 is fonned in att aperture in the interlayer dielectric layer 16 S and extends above its upper surface. As poesen~y preferred, the top edge of the tungsten plug is slightly rounded by a process such as cher~ical mechanical polishing (CMP) to reduoe the otherwise overly high fteld . which would exist at the sharp edge of the upper surface of the conductive plug 18.
According to this second ' ~1" of the present invention, a frst titanium nitride layer 42 having a typical thickness in the range of about 500 angstroms to about 3,000 angstroms, typically about 2,000 angstroms, is disposed over the upper surface of interlayer dielectric layer 16 prior to formation of the composite antifuse material layer 20.
An antifuse material 20 is disposed above the upper surface of the first titanium nitride layer 42. As shown in FIG. 3, the antifuse material 20 of the antifuse 40 also preferably 15 comprises a sandwich structure including a frst layer of silicon nitride 22, a layer of amorphous silicon 24 and a second layer of silicon nitride 26. As in the, ~ " illustrated in FIG. 1, the antifuse material 20 of antifuse 40 preferably, but not necessarily, includes a thin silicon dioxide layer 28, having a thickness of between about I to 300 angstroms, preferably about 30 angstroms, located either between the first silicon nitride layer 22 and the amorphous silicon layer 24, or 20 between the amorphous silicon layer 24 and the second silicon nitride layer 26.
The thicknesses of the layers 22, 24, 26, and 28 will of course depend on the 1,.~ 0 ~ voltage desired. As an example, if first and second layers silicon nitride 22 and 26 are made about 65 angstroms thick, amorphous silicon layer 24 is made about 450 angstroms thick, and thin oxide layer 28 is made about 30 angstroms thick, the antifuse 40 should program at 25 a voltage of about 10.5 volts as poeviously disclosed.
A second titanium nitride layer 30 having a typical thickness in the range of about 500 angstroms to about 3,000 angstroms, typically about 2,000 angstroms, is disposed over the upper surfaoe of second silicon nitride layer 26. The second titanium nitride layer 30 serves to provide material from which the conductive link is formed and to poevent aluminum from being 30 ~ into the link. As poesently poeferoed, after formation of the second titanium nitride layer 30, the layers 42, 22, 24, 26, 28, and 30 aoe defined in a single etching step and an oxide spaoer 32 is formed around the periphery of the defned structuoe to ihnprove step coverage of the overlying layer and to poevent the upper electrode from shorting to the lower electrode.
~ 2 ~ ~ ~515~75 WO 96138861 1 ~_I/U~., -' ''I
An upper conductive electrode 34 complëtes the structure of antifuse 40. As with the lower conductive electrode 14, the upper conductive electrode 34 may comprise a portion of a metal ~ layer in the integrated circuit containing antifuse 40. Those of ordinary sl~ill in the art will recognize that other layers and structures, such as passivation layers and contacts, will S be fonned in the integrated circuit containing antifuse 40. These layers and structures are well known and are not shown in the drawing figures to avoid u . _.. , ' ~ ng the disclosure and thus obscuring the disclosure of the invention herein.
Referring again now to FIGS. 2a-2c and in addition to FIGS. 4a-4b, cross ~Liu ~I views of the antifuse of FIG.3 are shown after completion of selected steps in the fabrication process.
FIGS. 2a-2c depict the formation of lower conductive electrode 14, interlayer dielectric layer 16, antifuse aperture 36, and tungsten plug 18, as well as the process steps for raising the tungsten plug 18 above the upper surface of the interlayer dielectric layer 16 and for rounding its corners.
FIG. 2a shows the structure resulting after fommation of the tungsten plug 18 and I ' of the interlayer dielectric layer 16 and tungsten plug 18. FlG.2b shows the structure resulting after completion of the raised plug etching step, and FIG. 2c shows the structure resulting after completion of the CMP step.
Referring now to FIG. 4a, frrst titanium nitride layer 42 is formed over the tungsten plug 18 and the upper surface of interlayer dielectric layer 16 to a thickness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, using PVD or CVD
techniques. Antifuse material layer 20 is then formed.
As in the ' ~ ' of FIG. 1, it is preferred to use a multilayer structure for antifuse material layer 20. A first layer of silicon nitride 22 iS formed to a thickness of between about I
angstrom and about 300 angstroms, typically about 65 angstroms, using CVD techniques. Next, a layer of amorphous silicon 24 is formed over the silicon nitride layer 22 to a tbickness of between about 100 angstroms and about 1,500 angstroms, typically about 450 angstroms, using CVD techniques. The amorphous silicon layer 24 may be undoped or may be doped to a level of less than about lel8 using 1 ' ~ ' JU:~, arsenic, nitrogen, or oxygen. A second silicon nitride layer 26 having as thickness of between about I angstrom and about 300 angstroms, typically about 65 angstroms, is next formed over the surface of the amorphous silicon layer 24 using CVD
techniques. According to a presently preferred ' ~ ' of the invention, a thin silicon dioxide layer 28, having a thickness of between about I to 300 angstroms, preferably about 30 angstroms, is formed either ~ ' '~, after formation of the first silicon nitride layer 22, or ' '~, after formation of the amorphous silicon layer 24, using CVD techniques.
2'~ 5~7' ~
wo 96138861 A second layer of titanium nitride 30 having a thickness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, is next fonned over tbe second layer of silicon nitride 26 using PVD or CVD ~ephniques. A cu..~. ' I ' ' ' ~ e layer 44 is applied over second titanium nitr,id;e la~er 30 and the stack comprising dle first titanium nitride layer 42, the first silicon nitridè layer 22, the oxide layer 28, the amorphous silicon layer 24, the second silicon nitride layer 26, and the second titanium nitride layer 30 is defined using cull~ ' etching technology. FIG. 4a shows the structure resulting after completion of the stacked structure comprising layers 42, 22,24, 26, 28 and 30 and the stack definition etching step, but prior to temoval of I ' ' ~ e layer 44.
Referring now to FIG. 4b, the masking layer 44 is ~en removed and an oxide spacer 32 is formed around the edge of the stacked structure. The oxide spacer 32 may be formed by a blanket deposition of silicon dioxide (i.e., about 3,000 angstroms) followed by an plasma etching step as is known in the art. FlG.4b shows the structure resulting after completion of the spacer etching step.
Next, with reference again to FIG. 3, the upper conductive electrode 34 is formed over the stacked structure, the o~ide spacers 32, and the interlayer dielectric layer 16. As will be appreciated by those of ordinary skill in the art, upper conductive electrode 34 may be formed from a por~ion of an ~ metal layer in an integrated circuit and fabrication of this layer is weU lcnown to such skiUed persons. Additional cu.,v, ' back-end steps (not shown) are then used to passivate and otherwise complete the integrated circuit structure.
The major difference between the antifuse 10 in FIG. I and the antifuse 40 of FIG. 3 is tbe presence of the titanium nitride 42 layer between the tungsten plug 18 and the first si]icon nitride layer 22 of the antifuse material 20. Because of the presence of this layer in the antifuse 40 of FlG. 3, the ~ . u~ ' antifuse wiU have a higher . ~ than the ~
antifuse 10 of FIG. I whose lower plate comprises only the tungsten plug 18. However, the presence of this additional layer in antifuse 40 of FlG. 3 permits more flexibility in p., " ~ g voltage polarity. Depending on the polarity of the u.", ~ g voltage, the link material for the p " ' antifuse wiU come from either titanium nitride layer 30 (positive polarity on the lower electrode 14) or titanium nitride layer 42 (positive polarity on upper electrode 34).
Referring now to FIG. 5, an antifuse 50 according to a third ~i ' - ' of the present invention is shown in cross-sectional view. Antifuse 50 of FIG. 5 is similar to the antifuse 40 depicted in FIG. 3, and therefore structures in the antifuse 50 of FIG.5 . . ' v to structures in the antifuse 40 of FIG. 3 will be designated by the same reference numerals as used in E~[G. 3. As would be expected by persons of ordinary skill in the art, the materials and layer .\ ' ~ 1~ q, ~ ~.5,7~
W096/38861 L.~ L-thicknessw for the antifuse 50 of FIG. S may be tbe same as or similar to tbose of the E structures of the antifuse 10 of FIG. 1 and the antifuse 40 of FIG.3.
I ~i ~
Antifuse 50 is fabricated over a suihble substrate 12. Like antifuses 10 and 40 of FIGS. I
and 3 ~w~L.~l~, tbe lower conductive electrode 14 of the antifuse 50 of tbe present invention S may comprise a portion of a metal layer or composite metal layer used as an ~ Iayer in the mtegrated circuit.
As in tne previous; ' " of amtifuse accordmg to tbe prwent invention, an interlayer dielectric layer 16 is formed over the surface of the lower conductive electrode 14 amd a conductive plug 18 is formed m an aperture m the mterlayer dielectric layer 16 and extends above its upper surface. As presently preferred, the top edge of the tungsten plug is sligbtly rounded by a procws such as chemical mechanical polishing tCMP) to reduce the otherwise overly high field which would exist at the sharp edge of the upper surface of the tlmgsten plug 18.
As im antifuse 40 of the second ' ~ " of the prwent mvention, antifuse S0 mcludw a first tihnium nitride layer 42 having a typical thicknws m the range of about S00 angstroms to lS about 3,000 angstroms, typically about 2,000 angstroms, and is disposed over the upper surface of interlayer dielectric layer 16 prior to formation of the composite antifuse material layer 20.
An antifuse material 20 is disposed above tbe upper surface of the first tihnium nitride layer 42. As with antifuse 40 of FtG. 3, the antifuse material 20 of the antifuse 50 also preferably comprisw a sandwich structure includmg a first layer of silicon nitride 22, a layer of amorphous silicon 24 and a second layer of silicon nitride 26. As im the; ' " illustrated in FIG. 1, the antifuse material 20 of antifuse 50 preferably, but not necessarily, includes a thin sihcon dioxide layer 28, having a thickness of between about I to 300 angstroms, preferably about 30 angstroms, located either between the frst silicon nitride layer 22 amd the amorphous silicon layer 24, or between the amorphous silicon layer 24 and the second silicon nitride layer 26.
2S The l! L ~ . -- ~ of the layers 22, 24, 26, and 28 will of course depend on the voltage dwired. As an example, if frst and second layers silicon nitride 22 and 26 are made about 65 angstroms thick, amorphous silicon layer 24 is made about 450 angstroms thic_ and thin oxide layer 28 is made about 30 angstroms tluck, the amtifuse 50 should program at a voltage of about 10.5 volts as previously disclosed.
A second titanium nitride layer 30 having a typical thickness in the range of about 500 angstroms to about 3,0110 angstroms, typically about 2,000 angstroms, is disposed over the upper surface of second silicon nitride layer 26. The second tit3nium nitride layer 30 serves to provide 7' WO 96138861 I ~ .A
material from which dle conductive link is formed and to prevent aluminum from being ' into dhe link As presendy prefer ed, after formation of the second titanium nitride layer 30, the layers 42, 22, 24, 26, 28, and 30 a~e defined in a single etching step.
i~ ' The major difference between antifuse 50 of FIG. S and antifuse 40 of FIG. 3 is the absence of the oxide spacer 32 which was formed around the periphery of the defined structure in antifuse 40 of FIG.3 to improve step coverage of the overlying layer and to prevent the upper electrode from shorting to the lower electrode. As shown in FIG. 5, antifuse 50 employs a dielectric layer 52, preferably formed from a material such as silicon dioxide, disposed over the stacked structure of layers 42, 22, 24, 26, 28, and 30. An aperture 54 in dielectric layer 52 allows upper electrode 34 to make contact with second titanium nitride layer 30. As will be appreciated by those of ordinary skill in the art, an additional masking and etching sequence are required to form aperture 54 in dielectric layer 52 of antifuse 50 of FIG. 5.
The upper conductive electrode 34 completes the structure of antifuse 50, mal;ing contact with upper second titanium nitride layer 30 through the aperture 54 in dielectric layer 52. As widh lS dhe lower conductive electrode 14, dhe upper conductive electrode 34 may comprise a portion of a metal ~ ~ Iayer in dhe integrated circuit contaming antifuse S0. Those of ordinary s~ill in the art will recognize that other layers and structures, such as passivation layers and contacts, will be formed in the integrated circuit containing antifuse 50. These layers and structures are well known and are not shown in the drawing figures to avoid u, ~,., , ' ~ g dhe disclosure and thus obscuring dhe disclosure of dle invention herein.
The fabrication of antifuse 50 of FIG. S may be understood with reference ftrst to FIGS.
2A-2c, FIG. 4a, and FIG. 6, cross-sectional views of dhe antifuse of FIG. S shown after completion of selected steps in the fabrication process.
FIGS. 2a-2c depict the formation of lower conductive electrode 14, interlayer dielectric layer 16, antifuse aperture 36, and tungsten plug 18, as well as the process steps for raising the tungsten plug 18 above dle upper surface of the interlayer dielectric layer 16 and for rounding its corners. FIG. 2a shows the structure resulting after formation of the tungsten plug 18 and I ' of dhe interlayer dielectric layer 16 and tlmgsten plug 18. FIG. 2b shows dhe structure resulting after completion of dhe raised plug etching step, and FIG. 2c shows ~e structure resulting after completion of the CMP step.
Referring now to FIG. 4a, frst titanium nitride layer 42 is formed over the tungsten plug 18 and the upper surface of interlayer dielectric layer 16 to a thickness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, using PVD or CVD
~ 1 ~6~57 ~
wog6138861 ~ p techniques. Antifuse material layer 20 is tben formed.
~.
As in the '- ~ " of FIGS. I ,an~d 3, it is preferred to use a multilayer structure for antifuse material layer 20. A first layer of sihcoh nitride 22 is formed to a thickness of between about 1 angstrom and about 300 angstroms, typicaDy about 65 angstroms, using CVD techniques.
5 Depending on the L " ' desired, a thin silicon dioxide layer 28 is next formed over the - upper surface of tbe first silicon nitride layer 22. FIG. 4a illustrates this step. Next, a layer of amorphous silicon 24 is formed over the silicon nitride layer 22 or the thin oxide layer 28 to a tbickness of between about 100 angstroms and about 1,500 angstroms, typically about 450 angstroms, using CVD tecbniques. The amorphous silicon layer 24 may be undoped or may be 10 doped to a level of less than about lel8 using I ' - . ' ~, arsenic, nitrogen, or oxygen. A
second silicon nitride layer 26 having as tbickness of between about 1 angstrom and about 300 angstroms, typically about 65 angstroms, is next formed over the surface of the amorphous silicon layer 24 using CVD techniques. Those of ordinary slcill in the art will appreciate that tbin oxide layer 28 may be formed after formadon of amorphous silicon layer 24 and prior to formadon of 15 second silicon nitride ]ayer 26, rather than after formadon of first silicon nitride layer 22, although this opdon is not illustrated in the figures.
A second layer of dtanium nitride 30 having a thickness of between about 500 angstroms and about 3,000 angstroms, typically about 2,000 angstroms, is next formed over the second layer of silicon nitride 26 using PVD or CVD techniques. A Cul~ g layer 44 is 20 applied over second dtanium nitride layer 30 and tbe stack comprising the first dtanium nitride layer 42, the first silicon nitride layer 22, the amorphous silicon layer 24, the second silicon nitride layer 26, and tbe second tdtanium nitride layer 30 is defned using ~,u~ tiu~d etching technology. FIG. 4a shows the structure resulting after compledon of tbe stacked structure comprising layers 42, 22, 24, 26, 28, and 30 and the stack definition etching step, but prior to 25 removal of I ' ~ g layer 44.
Referring now to FIG. 6, the masking layer 44 is then removed and a dielectric layer 52 is formed over the stacked structure and interlayer dielectric layer 16. The dielectric layer 52 may be formed by a blanl~et deposidon of silicon dioxide (i.e., about 500 to about 3,000 angstroms, typicaDy about 1,000) as is known in the art. A photomaslc 56 is formed over the surface of dielectric layer 52 using ~,u.. ' 1 ' ~, , ' .~ techniques. Aperture 54 is next formed in dielectric layer 52 to expose the upper surface of second titanium nitride layer 30. FIG. 6 shows the structure resuldng after compledon of the aper~ure etching step but prior to removal of photomask 56.
Next, with reference again to FIG. 5, the upper conductdve electrode 34 is formed over the ~ ;3 r~
wo 96/38861 2 1 9 6 5 5 7 i~
stacl~ed structure, the dielectric layer 52, and tbe interlayer dielectric layer 16. As will be p, ' ' by those of ordinary skill in the art, upper conductive elec~rode 34 may be formed from a ponion of an :~ metal layer in an integrated circuit and fabrication of this layer is well known to such s~lcilled persons. Additional w... ' bacX-end steps (not shown) are then S used to passivate and otherwise complete the integ~ted circuit structure.
The major differenoe between the àntifuse 40 in FIG. 3 and the antifuse 50 of FIG. S is the absenoe of the oxide spaoers 32 and the presenoe of tbe dieleclric layer 52. As noted, this ~- requires an additional masking and etching sequence to form the aperlure 54 in dielectric layer 52. The advantage of the bc " of FIG. S over the ' ' of FIG. 3 is 10 that, forming, patterning, and etching dielec~ric layer 52 is more ~ ' than controlling spaoer sidewall height.
While ' ' and _,, I of this invention have been shown and described, it would be apparent to those slcilled in the art that many more "~ than mentioned above are possible without departing from the inventive conoepts herein. The invention. therefore, is not 15 to be restricted exoept in the spirit of the appended claims.
Claims (24)
1. An antifuse comprising:
a lower conductive electrode having an upper surface and disposed over an insulating layer, an interlayer dielectric layer disposed over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface and having an aperture communicating with said lower conductive electrode formed therein;
a conductive plug disposed in said aperture, said conductive plug having an upper surface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
an antifuse layer having an upper surface and disposed over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer; and an upper electrode disposed over said upper surface of said antifuse layer.
a lower conductive electrode having an upper surface and disposed over an insulating layer, an interlayer dielectric layer disposed over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface and having an aperture communicating with said lower conductive electrode formed therein;
a conductive plug disposed in said aperture, said conductive plug having an upper surface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
an antifuse layer having an upper surface and disposed over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer; and an upper electrode disposed over said upper surface of said antifuse layer.
2 . The antifuse of claim 1 wherein said antifuse layer comprises a first layer comprising silicon nitride, a second layer comprising amorphous silicon, and a third layer comprising silicon nitride.
3. The antifuse of claim 2 wherein outer edges of said first layer said second layer and said third layer form a substantial vertical wall and further including an oxide spacer in contact with said vertical wall.
4. The antifuse of claim 2, further including a layer of silicon dioxide disposed between said second layer and one of said first and third layers.
5. An antifuse comprising:
a lower conductive electrode having an upper surface and disposed over an insulating layer, an interlayer dielectric layer disposed over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface and having an aperture with said lower conductive electrode formed therein;
a conductive plug disposed in said aperture, said conductive plug having an upper surface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
an antifuse layer having a lower surface disposed over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer, and an upper surface;
a layer of titanium nitride having an upper surface and a lower surface disposedover said upper surface of said antifuse layer; and an upper electrode disposed over said upper surface of said layer of titanium nitride.
a lower conductive electrode having an upper surface and disposed over an insulating layer, an interlayer dielectric layer disposed over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface and having an aperture with said lower conductive electrode formed therein;
a conductive plug disposed in said aperture, said conductive plug having an upper surface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
an antifuse layer having a lower surface disposed over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer, and an upper surface;
a layer of titanium nitride having an upper surface and a lower surface disposedover said upper surface of said antifuse layer; and an upper electrode disposed over said upper surface of said layer of titanium nitride.
6. The antifuse of claim 5 wherein said antifuse layer comprises a first layer comprising silicon nitride, a second layer comprising amorphous silicon, and a third layer comprising silicon nitride.
7. The antifuse of claim 6 wherein outer edges of said first layer said second layer and said third layer form a substantial vertical wall and further including an oxide spacer in contact with said vertical wall.
8. The antifuse of claim 6, further including a layer of silicon dioxide disposed between said second layer and one of said first and third layers.
9. An antifuse comprising:
a lower conductive electrode having an upper surface and disposed over an insulating layer, an interlayer dielectric layer disposed over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface and having an aperture communicating with said lower conductive electrode formed therein;
a conductive plug disposed in said aperture, said conductive plug having an upper surface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
a first layer of titanium nitride having an upper surface and disposed over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer;
an antifuse layer having a lower surface disposed over all of said upper surface of said first layer of titanium nitride, and an upper surface;
a second layer of titanium nitride having an upper surface and a lower surface disposed over said upper surface of said antifuse layer; and an upper electrode disposed over said upper surface of said second layer of titanium nitride.
a lower conductive electrode having an upper surface and disposed over an insulating layer, an interlayer dielectric layer disposed over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface and having an aperture communicating with said lower conductive electrode formed therein;
a conductive plug disposed in said aperture, said conductive plug having an upper surface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
a first layer of titanium nitride having an upper surface and disposed over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer;
an antifuse layer having a lower surface disposed over all of said upper surface of said first layer of titanium nitride, and an upper surface;
a second layer of titanium nitride having an upper surface and a lower surface disposed over said upper surface of said antifuse layer; and an upper electrode disposed over said upper surface of said second layer of titanium nitride.
10. The antifuse of claim 9 wherein said antifuse layer comprises a first layer comprising silicon nitride, a second layer comprising amorphous silicon, and a third layer comprising silicon nitride, a second layer comprising amorphous silicon, and a third layer comprising silicon nitride.
11. The antifuse of claim 10 wherein outer edges of said first layer said second layer and said third layer form a substantial vertical wall and further including an oxide spacer in contact with said vertical wall.
12. The antifuse of claim 10, further including a layer of silicon dioxide disposed between said second layer and one of said first and third layers.
13. In an antifuse fabrication process formed on an insulating layer, including the steps forming a lower conductive electrode having an upper surface and disposed over the insulating layer;
forming an interlayer dielectric layer over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface;
forming an aperture within said interlayer dielectric layer communicating with said lower conductive electrode formed therein;
forming a conductive plug in said aperture, said conductive plug having an uppersurface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
forming an antifuse layer having an upper surface over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer;
and forming an upper electrode over said upper surface of said antifuse layer.
forming an interlayer dielectric layer over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface;
forming an aperture within said interlayer dielectric layer communicating with said lower conductive electrode formed therein;
forming a conductive plug in said aperture, said conductive plug having an uppersurface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
forming an antifuse layer having an upper surface over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer;
and forming an upper electrode over said upper surface of said antifuse layer.
14. The method of claim 1 wherein the step of forming said antifuse layer further includes the steps of forming a first layer comprising silicon nitride, a second layer comprising amorphous silicon, and a third layer comprising silicon nitride.
15. The method of claim 2 wherein outer edges of said first layer, said second layer and said third layer form a substantial vertical wall and further including the step of forming an oxide spacer in contact with said vertical wall.
16. The method of claim 2, further including the step of forming a layer of silicon dioxide between said second layer and one of said first and third layers.
17. In an antifuse fabrication process formed on an insulating layer, including the steps of:
forming a lower conductive electrode having an upper surface and disposed over the insulating layer;
forming an interlayer dielectric layer over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface;
forming an aperture within said interlayer dielectric layer communicating with said lower conductive electrode formed therein;
forming a conductive plug in said aperture, said conductive plug having an uppersurface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
forming an antifuse layer having an upper surface over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer;
forming a layer of titanium nitride having an upper surface and a lower surface over said upper surface of said antifuse layer; and forming an upper electrode over said upper surface of said layer of titanium nitride.
forming a lower conductive electrode having an upper surface and disposed over the insulating layer;
forming an interlayer dielectric layer over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface;
forming an aperture within said interlayer dielectric layer communicating with said lower conductive electrode formed therein;
forming a conductive plug in said aperture, said conductive plug having an uppersurface raised above said upper surface of said interlayer dielectric layer, an outer edge of said upper surface being rounded;
forming an antifuse layer having an upper surface over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer;
forming a layer of titanium nitride having an upper surface and a lower surface over said upper surface of said antifuse layer; and forming an upper electrode over said upper surface of said layer of titanium nitride.
18. The method of claim 5 wherein the step of forming said antifuse layer further includes the steps of forming a first layer comprising silicon nitride, a second layer comprising amorphous silicon, and a third layer comprising silicon nitride.
19. The method of claim 6 wherein outer edges of said first layer, said second layer and said third layer form a substantial vertical wall and further including the step of forming an oxide spacer in contact with said vertical wall.
20. The method of claim 6, further including the step of forming a layer of silicon dioxide between said second layer and one of said first and third layers.
21. In an antifuse fabrication process formed on an insulating layer, including the steps of:
forming a lower conductive electrode having an upper surface and disposed over the insulating layer;
forming an interlayer dielectric layer over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface;
forming an aperture within said interlayer dielectric layer communicating with said lower conductive electrode formed therein;
forming a conductive plug in said aperture, said conductive plug having an uppersurface raised above said upper surface of said interlayer dielectric layer, an outer edge of said forming a first layer of titanium nitride having an upper surface and over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer;
forming an antifuse layer having a lower surface over all of said upper surface of said first layer of titanium nitride, and an upper surface;
forming a second layer of titanium nitride having an upper surface and a lower surface disposed over said upper surface of said antifuse layer; and forming an upper electrode disposed over said upper surface of said second layer of titanium nitride.
forming a lower conductive electrode having an upper surface and disposed over the insulating layer;
forming an interlayer dielectric layer over said upper surface of said lower conductive electrode, said interlayer dielectric layer having an upper surface;
forming an aperture within said interlayer dielectric layer communicating with said lower conductive electrode formed therein;
forming a conductive plug in said aperture, said conductive plug having an uppersurface raised above said upper surface of said interlayer dielectric layer, an outer edge of said forming a first layer of titanium nitride having an upper surface and over all of said upper surface of said conductive plug and at least a portion of said upper surface of said interlayer dielectric layer;
forming an antifuse layer having a lower surface over all of said upper surface of said first layer of titanium nitride, and an upper surface;
forming a second layer of titanium nitride having an upper surface and a lower surface disposed over said upper surface of said antifuse layer; and forming an upper electrode disposed over said upper surface of said second layer of titanium nitride.
22. The method of claim 9 wherein the step of forming said antifuse layer further includes the steps of forming a first layer comprising silicon nitride, a second layer comprising amorphous silicon, and a third layer comprising silicon nitride.
23. The method of claim 10 wherein outer edges of said first layer, said second layer and said third layer form a substantial vertical wall and further including the step of forming an oxide spacer in contact with said vertical wall.
24. The method of claim 10, further including the step of forming a layer of silicon dioxide between said second layer and one of said first and third layers.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US46041795A | 1995-06-02 | 1995-06-02 | |
| US08/460,417 | 1995-06-02 |
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|---|---|
| CA2196557A1 true CA2196557A1 (en) | 1996-12-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002196557A Abandoned CA2196557A1 (en) | 1995-06-02 | 1996-05-31 | Raised tungsten plug antifuse and fabrication process |
Country Status (6)
| Country | Link |
|---|---|
| US (4) | US5804500A (en) |
| EP (1) | EP0774164A1 (en) |
| JP (1) | JP3027195B2 (en) |
| KR (1) | KR100252447B1 (en) |
| CA (1) | CA2196557A1 (en) |
| WO (1) | WO1996038861A1 (en) |
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-
1996
- 1996-05-31 JP JP8536750A patent/JP3027195B2/en not_active Expired - Fee Related
- 1996-05-31 CA CA002196557A patent/CA2196557A1/en not_active Abandoned
- 1996-05-31 WO PCT/US1996/008263 patent/WO1996038861A1/en not_active Application Discontinuation
- 1996-05-31 EP EP96922380A patent/EP0774164A1/en not_active Ceased
- 1996-05-31 KR KR1019970700695A patent/KR100252447B1/en not_active IP Right Cessation
- 1996-06-04 US US08/657,971 patent/US5804500A/en not_active Expired - Lifetime
- 1996-12-23 US US08/772,241 patent/US5920109A/en not_active Expired - Lifetime
-
1998
- 1998-04-17 US US09/062,298 patent/US6124193A/en not_active Expired - Lifetime
-
2000
- 2000-09-25 US US09/669,035 patent/US6437365B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5920109A (en) | 1999-07-06 |
| KR100252447B1 (en) | 2000-04-15 |
| US6437365B1 (en) | 2002-08-20 |
| JP3027195B2 (en) | 2000-03-27 |
| US6124193A (en) | 2000-09-26 |
| JPH10502774A (en) | 1998-03-10 |
| US5804500A (en) | 1998-09-08 |
| KR970705182A (en) | 1997-09-06 |
| WO1996038861A1 (en) | 1996-12-05 |
| EP0774164A1 (en) | 1997-05-21 |
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