CA2216525A1 - Clock control system and method - Google Patents
Clock control system and method Download PDFInfo
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- CA2216525A1 CA2216525A1 CA002216525A CA2216525A CA2216525A1 CA 2216525 A1 CA2216525 A1 CA 2216525A1 CA 002216525 A CA002216525 A CA 002216525A CA 2216525 A CA2216525 A CA 2216525A CA 2216525 A1 CA2216525 A1 CA 2216525A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1604—Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Abstract
First and second parallel processors operate in one of plural modes including synchronous and stand-alone modes. Each processor includes a clock for selectively providing a first high frequency clock signal to both processors.
Each processor also includes electronic circuitry operating at a second frequency lower than the first frequency which generates a clock selection signal that selects one of the clocks from the first and second processors to clock both processors. The electronic circuitry, in response to mode change signals, generates clock switching control signals at the lower frequency. The lower frequency clock control signals are reclocked so that they are synchronous with the first frequency clock signals before being used to select one of the clocks.
Each processor also includes electronic circuitry operating at a second frequency lower than the first frequency which generates a clock selection signal that selects one of the clocks from the first and second processors to clock both processors. The electronic circuitry, in response to mode change signals, generates clock switching control signals at the lower frequency. The lower frequency clock control signals are reclocked so that they are synchronous with the first frequency clock signals before being used to select one of the clocks.
Description
CLOCK CONTROL SYST13~M AND METHOD
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock control system and method, and more particularly, to the control of high frequency clocking si~ using lower frequency control ~iFn~1.~.
BACEGROUND AND SUMMARY O~ THE INVENTION ~ -A variety of data processing applications use parallel processors which operate together in a synchronous mode of operation. Synchronously operating parallel processors provide system redundancy and therefore high reli~hility. If one processor is faulty, another processor may continue to perform the system control operations in a stand-alone mode of operation. When the faulty processor is repaired, it can be brought back on line to resume parallel synchronous operation. To perform in stand-alone operation, each processor must have its own oscillator or clock. In synchronous operation, only one of ~e processor clocks, however, is used at one time to provide the clocking si~ actually used by the parallel processors. Even if there is some phase delay between the processors, e.g., one of the processors operates N clock signals ahead of the other processor, using the same cloc~ing signal to drive the parallel processors ensures synchronous operation.
In the example of two parallel processors A and B, there are several operational states or modes in which those processors must be able to operat~. First, ~,vith processors A and B operating in parallel =
Wo 96130832 PCT~SE96~00371 and synchronously, processor A operates as an "executive" processor me~nin~ that it operates N cycles ahead of "standby" processor B.
The clock oscillator in executive processor A provides clock siFn~l~
that drive both processor A and processor B. The clock oscillator in 5 processor B is on sta]ldby in the sense ~hat it is not currently used but could be used if needed, i.e., a clock switch occurs. Second, with processors A and B operating in parallel and synchronously, processor B operates as the executive processor meaning that it operates N clock cycles ahead of processor A. ~ccordingly, the lo oscillator in executive processor B provides clock ~i~n~l~ to both processors. Third, both processors A and B must be capable of r~lnnin~ independently of the other processor using their own oscillators in a "stand-alone" mode or state.
Irrespective of operational mode, it is desirable that both processors transition between each of these three states as effectively and as quickly as possible so that the impact on the system being controlled by the processors is minimi~ed. For example, when transitioning between the first and second parallel synchronous 20 states described above, both processors must now switch to rllnning off processor B's clock signal rather than the clock signal from processor A. In addition, processor B, which was previously N cycles behind processor A, must now operate N cycles ahead of processor A.
To minimi7e system impact, the transition should occur without error 2~ and with minim~l delay.
Another problen1 with such state transitions is that the parallel processors operate using a high frequency clock signal that may be much faster than the control sign~ used to control the clock ;,o switching necessary to transition between the various operational :
W 09613~32 PCT/SE96/00371 states of the processors. For example, such state transition control may be generated by a "state m~chine" implemented using discrete logic circuitry or other hardware clocked at a co~siderably lower frequency. The added difficulty then is that of synchroni7.ing 5 the subst~nti~lly lower frequency state control sign~l.s used to effect 'the clock switching transitions with the much higher frequency clocking outputs which drive the parallel processors A and B~ This synchronization process should occur very rapidly (e.g., on the order of several nanoseconds or less if possible), to minimi~e the time 0 required to make the various clock switching transitions.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for 5 controlling clock switching operations between parallel devices ef~lciently and accurately. Moreover, the present invention performs such clock switching operations between high speed clocks using relatively low speed control si~
First and second clock ~ are generated at a first frequency and a clock selection signal is generated at a second, lower frequency. The lower frequency clock selection signal is synchronized with the first frequency clock si~n~l.c and then used to select one of the clock .siFn~l~. Advantageously, the present invention 2~ synchronizes the slower clock selection signal with the faster clock .sign~ls in several nanoseconds or less.
The present invention describes an example method for operating first and second parallel processors in plural modes. Each 30 processor includes its O~YIl i~dependent high speech clock ~~hich may -WO 96/30832 PCT~S~;96/0037 be seIectively connected to supply high speed clocking .ci~n~l.c to both processors. Each processor also includes its own clock switching circuitry for selecting which of the high speed clocking si~n~l.s actually clocks that processor in a particular mode/state. Initially, the first processor may be designated to provide the high speed clocking signal to both the first and second processors using the first processor's clock with the first and second processors operating synchronously. When the mode of operation changes, control ~ lc are provided to the c lock switching circuitry in both processors 10 indicating the need to perforrn a clock switching operation, e.g., the second processor is to provide the high speed clocking signal rather than the first processor. The control ~ign~ are processed in the clock switching circuitry of each processor at a speed substantially slower than the high speed clocking signal. Slower speed clock select 5 .~ are produced which select the high speed clocking signal from the second processor to clock both processors.
Apparatus in accordance with the present invention includes first and second clocks that provide a first frequency clock signal.
20 Electronic circuitry operates at a second frequency lovYer than the first frequency generates a clock selection signal at that second frequency. A synchroni~inF circuit synchronizes the lower frequency clock selection signal with the first frequency clock signal. The synchronized lower frequency clock selection signal selects one of the 25 first and second clocks. The first and second clocks may be resident with respective first and second processors capable of operating in plural modes such as a parallel synchronous mode and an asynchronous stand-alone mode. Each processor also includes electronic circuitry that operates at the second frequency and 30 generates a clock selection signal that selects one of the clocks to wo 96130832 PCI/SE96100371 clock one or both of the processors in response to a change in the operating mode. One of the processors is designated as a clock controlling processor, and the other processor is ~lefiign~ted as a clock following processor operating N clock cycles behind the clock 5 controlling processor. In response to a mode change, the electronic circuitry designates the other processor as the clock controlling processor so that the one processor becomes the clock following processor.
BRIEF D~ESC:EUPTION OF THE DRAWINGS
The novel features believed characteristic of the invention are set forth in the appended cl~im~. Those features as well as other features and advantages thereof will be best understood by reference to the following description of the preferred embodiment when read in conjunction with the accompanying figures, wherein:
r FIGURE 1 is a function block diagram of a data processing system to which the present invention may be applied;
FIGURE 2 is a ~unction block diagram of particular clock switching circuitry which may be used in an example embodiment of the present invention;
2;, FIGURE 3 is a function block diagram of the state logic array shown in Figure 2;
FIGURES 4(a) - 4(c) are tirning diagrams which illustrate an L
exaulple of various clocking and cloc~; switching control ~ ql.s in 30 accordance with various state transitions;
~O 96130832 PCr/SE96/0037 FIGURE 5 is an example state diagram illustrating various states that parallel processors may assume and transitions therebetween; and FIGURE 6 is a table which illustrates for each state shown in the state diagram of Figure 5 corresponding state control .ci~
DETAILED DESCRIPTION OF THE EMBODIMENTS
In the following description, for purposes of ~pl~n~tion and not limitation, specific details are set forth, such as particular circuits, circuit components, interfaces, techniques, etc. in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention 5 may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well known methods, devices, and circuits are omitted so as not to obscure the description of the present invention with unnecessary detail.
Figure 1 illustrates one particular example application of the present invention. A data processing system 10 suitable for controlling, for example, a telephone network includes a central processor 12 that controls several regional processors 20, 22, and 24 which in turn control multiple telephone network operations, e.g., call 2~ set up, routing, etc. The central processor must function at very fast speeds to m~rimi~e the telephone switching capacity but also must function reliably to provide continuous network operation. To ensure reliability, computers 16 and 18, labelled for purposes of description as computer A and colmputer B, operate in parallel and ~,o synchronously. Computers 16 and 18 comm~micate to"ether over a WO 96/30832 PCrJSE96JDl~37 common bus 30 and with regional processors 20-24 through dedicated buses 32 and 34. Both computers include a central processing unit (CPU), memory, and clock circuitry indicated at 26 and 28, respectively~ The clock circuitry at each computer includes an 5 oscillator which operates independently of the other computer's oscillator to generate a high frequency clocking signal, e.g., a 40 MHz clocking signal.
The clocking .si~ A and B are provided to both computers.
10 For example, the oscillator in computer A provides a clocking signal A to the CPU in computer A as well as a clocking signal A to the clock circuitry 28 in computer B. Computer B is simil~rly configured.
A supervisory or maintenance processor (MP) 14 includes its own clock ~5 and may be for example an inexpensive microprocessor 15 operating at a relatively low clock speed, e.g., 16 MHz. Using control .5ign~l1.s from maintenance processor (MP) 14, both sets of clock circuitry 26 and 28 determine in parallel the mode or state of the computers and which clock signal will be selected to operate computers A and B.
In a normal mode of operation, computer A and computer B
operate in parallel synchronous fashion thereby providing redundant and reliable control of regional processors 20-24. Both computer A
and computer B perform the same sequence of operations in parallel.
Although not necessary, in a preferred embodiment, the two computers execute the identical instruction synchronously but slightly offset in time. That is, one computer operates N clock cycles ahead of the other computer, with a suitable value of N being for example four clock cycles. In synchronous operation, both computers ~o use the same clock signal generated by one of the computers. Based , WO 96/308:~2 PCT~SE961ûD371 on control .ciEn~ from the mainten~nce processor 14, the clocking circuitry 26 and 28 in both computers determines which computer's clocking signal will be used to clock both computers. For convenience, the computer whose clock/oscillator is selected to provide 6 clocking si~ to both computers is sometimes referred to as the clock controlling computer or the "executive" computer.
The maintenance processor 14 monitors the operation of computers A and B and generates state control ~ that 10 determine their specific mode/state of operation. If the computers are operating in a parallel synchronous mode, the standby computer buffers the outputs (e.g., operands) generated ~y the executive computer. Outputs from the executive computer are delayed N cycles and compared with the outputs from the standby computer. If there 15 iS a mi~m~tch~ the maintenance processor 14 receives an error signal from the standby computer and may conclude that one of the computers is faulty, send appropriate control signals to the clock circuitry 26 and 28 of both computers to halt the faulty computer, and switch the state of operation of the still functioning computer to 20 a stand-alone state/mode of operation. In that instance, the now independently operating computer necessarily runs on its own clock signal. When the faulty computer is repaired, it is brought back on line with the maintenance processor 14 sending the appropriat control .~ to the clocking circuitry 26 and 28 of both computers 2~ to bring them back into parallel synchronous operation. In order to perform this latter state transition, the currently operating clock in the stand-alone operating computer is stopped for a predetermined delay time, and then the clock in the now executive computer is restarted with the clock sign~l~ being provided to the other computer.
~o Since both computers are clocked at the same time using the same WO 96/30832 Pc rJSE96/0037l t , 9 clock signal, synchronous operation is achieved. Moreover, the executive computer transfers microinstruction addresses and operands via bus 30 to the standby computer which buffers these N
clock cycles and then executes them during an update mode. Ill this 5 way, the computers are brought into synchronous operation with the executive computer N cycles ahead of the standby computer.
With the present invention, these kinds of state transitions are performed in a very short time while still achieving reliable high o speed synchronous operation. The clock circuitry of each computer operates at a second :Frequency lower than the first frequency and generates a clock selection signal that selects one of the clocks from the first and second processors to clock both of the computers. In response to the control .siFn~l.s from maintenance processor 14 15 indicating a mode change, the clock circuitry in each computer generates clock switching control ,sign~ls at that lower frequency.
The lower frequency clock signals are reclocked with extremely short reclocking delay so that they are synchronous with the first frequency clock siFn~l.s. As a result, clock switching operations between high 20 frequency clocks occur with minim~l glitches despite the fact that the clock selection control ~ign~l.s are generated at a lower frequency than the high frequency clocking si~n~l.s.
In another more detailed, example embodiment, Figure 2 26 illustrates an example hardware implementation of the clock circuitry 26 from computer A 16. The clock circuitry B is substantially the same. Of course, other hardware and software implementation could be used. A primary purpose of the clock circuitry is to select one of the high frequency clocks and provide with minimum clock switchillg 30 delay the high frequency clock signal to both computers.
WO 96130832 PCTISE96~00371 The clock circuitry includes an oscillator ~0 for generating a relatively high frequency (fl) clock signal for clocking one or both of the computers at high speed. In one nonlimiting example, fl is 40MHz. A clock divider 52 and a clock selector 72 are connected to 5 the oscillater 50. Clock divider 52 includes an inverting input termin~l 51 which generates a lower frequency (f2) signal that is 180~
out of phase with and an integral multiple of fl, e.g., fl is divided by two to generate f2 at 20MHz. An analogous fl clock signal output from computer B is inverted in inverter 53 and input to the clock 10 selector 72. Clock selector 72 is essentially a high speed multiplexer which selects one of the clock ~ign~ received from both the computers based on state .~ign~ S1-S3. Such a multiplexer may be ~ constructed using three NAND gates 74, 76, and 78, and AND gate 80.
1~ .
A state logic array 56 receives mode detern~inin~ control n~ from the maintenance processor 14 and possibly other control si~nz~ internal to the clock circuitry. Because of the present invention, the state logic array 56 may be constructed using 20 relatively low power and inexpensive integrated logic circuits that run using a much slower clock. For example, array 56 may be constructed using CM[OS circuits which employ well known transistor-transistor logic (TTL) integrated circuits. While CMOS
circuits are quite satisfactory for pulposes of implementing the state 2~ logic array, their switching speed between logic levels is relatively slow, i.e., on the order of 50 nanoseconds. As described in more detail below, when such slow switching speed circuitry generates clock control signals to switch clocks operating at considerably higher frequencies, undesiralble "glitches" may occur.
To be more cornpatible with the high frequency oscillator 50, circuits other than the state logic array 56, like the clock selector 72, operate at higher switching speeds using, for example, ernitter coupled logic (ECL) integrated circuitry. In addition to faster 5 switching speeds, ECL circuits operate at a different set of logic voltage levels than TTL circuits. Therefore, logic conversion buffer 54 buffers the f2 clock signal output from ECL clock divider 52 and converts that signal irlto a corresponding TTL clock signal which clocks the TTL state logic array 66 at frequency f2.
The state logic array 56 may be a programmed logic array (PLA) constructed with discrete, slower switching speed, TTL
integrated circuits in a particular configuration to generate a specific set of state control signals in response to mode deterrnining sign~l~
15 from the maintenance processor 14. While all of the state logic array 56 may operate at frequency f2, there may be circumstances where another third and even lower frequency f3 clocking signal, e.g., 10MHz, drives a portion of the state logic array 56. This third TTL
clocking signal f3 may be generated by dividing the ECL fl clock 20 signal A being sent to operate computer A in a clock divider 82, e.g., a divide by four circuit. The output of the divider 82 is converted by logic level converter 84 into TTL before provided to state logic array 56. Again, a significant advantage of the present invention is that inexpensive relatively slow electronic circuits can be used to control 25 much faster but more expensive clock switching circuitr~ and con~puters.
The TTL state signals Sl-S3 output from state logic array 56 are converted to ECL in a logic level converter 57 including 30 individual conversion buffers 60, 62, and 64 similar to conversio WO 96/30832 ~CTJSE96100371 --buffer 54 described abov.e. The low frequency logic level converter 57 outputs are connected to an ECL synchronizing or reclocking device 58 for reclocking using the lower frPquency clock signal f2 which is 180~ out of phase with and a multiple of the higher frequency clock 5 signal fl. As a result of this reclocking, the relatively slow speed state siEn~l.s S1-S3 are synchronized with the faster computer clock fiiFn~l.s In other word.s, the rising and falling edges of higher frequency clock signal fl align with the rising and falling edges of . .-.
lower frequency f2 state siFn~ls S1-S3. To prevent glitches in clock 1C switching, the reclocker 58 synchronizes S1-S3 with the fl clock signal during the logic 0 half cycle of the fl clock signal. Accordingly, clock divider 52 operates on the negative or falling edge of clock signal fl.
Because the state .si~ S1 -S3 are reclocked using fast switching logic devices such as the three ECL ~;ype D-type flip-flops 66, 68, and 70 in clock selector 72, the time delay required to synchronize the state .c;ign~l.s S1-S3 with the fl clock sign~ is substantially minimi~ed. In this example, using TTL gates to reclock 20 the state siEn~l.s S1-S3 requires a delay on the order of 50 nanoseconds which is a significant "glitch" in any clock switching operation. On the other hand, using ECL gates to reclock the .sign~l.s -, S1-S3 requires a much smaller delay on the order of a nanosecond before the reclocked outputs are provided to clock selector 72 to effect 2~ a clock switching operation. In addition, reclocking the state signals when clock signal fl is low avoids possible glitches which might otherwise occur when i;hose state fiign~l.s change state at the clock r selector 72, as described earlier.
WO 96/3~832 PCTlSE96J0037 Clock selector 72 $elects one of the two clocks to provide high frequency clocking .si~n~l~ to both computers A and B. More specifically, when the mainten~nce ~rocessor 14 comm~n~ a mode or state change which requires a clock switching operation, the state 5 logic array 56, in response to state control .cign~l~ processed using lower frequency clockiLng ~ign~l~ f2 (or f2 and f3), generates corresponding state ~ign~ S1-S3 for executing the clock s-vitch at clock selector 72. To ensure that the clock switch takes place in sync with the high frequency f~ system clocking signal, the state ~ign~l.s 10 S1-S3 are reclocked in reclocker 58. The unavoidable delay encountered in the reclocking operation is truly minimi~ed in the present invention using fast switching ECL transistor circuits with logic level converter 57 being used to convert the TTL logic level of the sign~l~ S1-S3 generated by the slower switching TTL transistor 5 circuits used in the state logic array 56.
Synchronized state signal S1 is input along with the fl clocking signal from computer A oscillator 50 to NAND gate 74 in clock selector 72. Synchronized control signal S2 is input along with 20 the fl clocking signal from computer A oscillator 50 to NAND gate 76. Synchronized stal;e signal S3 is input along with the inverted fl clocking signal from computer B oscillator 50 to NAND gate 78. The outputs of NAND gates 76 and 78 are the inputs to AND gate 80.
The output of NAND gate 74 is the clocking signal provided to 26 computer B (assuming computer A's clock signal is selected), and the output of AND gate 80 is the clocking signal provided to computer A
irrespective of which computer's clock signal is selected.
Referring to Figure 3, a more detailed block diagram of one 30 possible configuration for the state logic array 56 in Figure 2 is W~ 96/3~832 PCTlSE;96/0(1371 illustrated. Control .sign~l.s from the maintenance processor 14 and internal to the clocking circuitrg are decoded in a decoder 90 to produce state control .~ PWOS and SBS State control signal PWOS indicates that both computers A and B are to work in a 5 parallel synchronous mode or state of operation. State control signal SBS indicates if the computer (A or B) is to work in a standby state of operation. Since t:he mainten~nce processor 14 may operate at a frequency different than f2, e.g., 16 MHz, the state control .~ are synchronized in a syrlc block 92 to the f2 clock signal in the clock 10 divider 52. The synchronized state control logic ~ign~l.s PWOS and SBS then are input to a state machine 94 which may include a combination of discrete logic gates connected to implement a specific state table. Those logic gates, based on the combination of input logic states of state control logic sign~ PWOS and SBS, produce 15 state ~ S1-S3. The Iogic circuitry of state machine 94 is also clocked with f2 from clock divider 52.
The timing diagrams in Figures 4(a) - 4(c) illustrate the relationships between the fl, f2, and f3 clock signals, the state control 20 logic .~ign~ PWOS and SBS, the state si~n~l.s S1-S3, and the clock signals to computers A and B, and various example mode changes that require a clock switching operation. The first three waveforms represent the three oscillator ~ fl, f2, and f3. In this example, fl=2f2=4f3. For consistency with Figure 2, the PWOS and SBS state 2:~ control ~ l.s and the S1-S3 state siFn~ are shown next. The final three ~vaveforms include the clock signal from computer B, the clock signal to computer B, and the clock signal to computer A.
Figure 4(a) illustrates a particular example where at time 0 ~o the computers A and B are operatin~, in a parallel synchronous mode - ' CA 02216525 1997-09-26 WO 96/30832 PCTJSE96~a(1371 of operation with executive computer B providing the high speed clocking signal f7 to both computers with computer A currently being the standby (SB) computer. However, at time 1 a mode change occurs as indicated by the shift in the SBS state control signal from a logic high level to a logic low level. This indicates computer A is to now become the executive and the computer B (previously the executive) is to become the standby. Accordingly, computer B stops sending its clock signal as a result of control ~i~n~ generated by its own control clock circuitry 28 at time 4. A predetermined fixed delay 10 period must be waited for the mode/state ch~nging control .~ign~ to be received and processed in the state logic array 56 of the control clock circuitry. At time 5, those control si~n~l~ have been processed, and the state transition ~ S1-S3 which control the clock switch are generated. Thus, at time 5, state signal S2 goes from a logic low level to a logic high level, and state signal S3 goes from a logic high level to a logic low level. Also at time 5, the clock signal generated in computer A (now the executive) begins and commences operation of computer A. The clock signal from computer A to computer B is not transmitted until time 13 (8 clock cycles later) as indicated by the 20 change in lo~c level of state control signal S1. This delay essentially corresponds to a phase shift of two times the N cycle offset between executive computer A and standby computer B. In the example, N=4.
Figure 4~b) shows a timing diagram for an example mode/state 2~ transition where computer A is switched from executive to standby.
State control signal SBS changes logic level at time 2 with the corresponding state transition signals being generated at time 5. At time 5, clock .~ from computer A are no longer delivered to computer A or computer B. From time 5 to 13, computer A prepares 30 to receive clock sign~lc; from comp~ter B. At the same time, control w096130832 PCr/SE961~037 ~;iFn~l.s in the clock c3Lrcuitry of computer B are processed. At time 13 the state transition siLgnal S3 goes from a logic low to logic high level indicating that computer A is ready to receive clock pulses from computer B. Since computer B is now the executive computer, it 5 operates four cycles ahead of computer A. Therefore, there is a phase - shift delay of four cyeles during the time delay before computer A
receives clock ~ign~l~ from clock B at time 14.
Figure 4(c) is a timing diagr~m which shows the timing for 10 computer A operating in a stand-alone, independent mode switched to operate as the executive computer in a parallel synchronous mode with computer B. The state control signal PWOS shifts from a low to high logic level at time 3. State transition (clock switching) signals are generated at time 5, i.e., S2 goes from a high logic level to a low logic level, indicating that computer B is ready to resume parallel synchronous operation with computer A. After the predetermined delay, state transition si, n~ S1 and S2 change logic level at time 6 which starts the clock signal in computer A. At the same time, the clocking signal from clock A is sent to computer B to ensure 20 synchronous operation.
Although not illustrated as specific timing diagrams, clock switching operations are a1sQ required when stand-alone computer A
resumes parallel synchronous operation with computer B but becomes 26 the standby computer rather than the executive computer. Another mode includes the change of a computer operating synchronously beinD converted to stand-alolle operation.
Reference is now made to Figure 5 which illustrates a state ~o diagram of ~7arious possible states of operation for the stat~ logic arrays for computers A and B. Each circle represents a particular mode/state of the cornputers A and B. Each line between circles represents a change of state. Some of the changes of state occur automatically or after a predetermined time period expires. Other 5 state transitions require a particular logic level state control signal.
For example, to change from state SEP1 to state SEP2, the state control signal PWOS must change from a logic zero to a logic one. If PWOS rem~in~ zero~ there is no state change with the state rem~ining at SEP1. In state SEP3, there are two possible state 10 transitions: to state SBS1 if state control signal SBS equals a logic one or to state SEP 4 if state control signal SBS equals a logic zero.
State SEP1 corresponds to both the computers operating in a separate stand-alone state which may occur for example when the 5 other computer is faulty and/or has been taken offline. State EX1 corresponds to the state where the computer whose clock circuitry is implementing the state diagram is the executive providing clock signals to both computers. State SB1 corresponds to the state where this computer is the standby receiving its clocking signal from the zo other computer.
Figure 6 shows in table form for each specific state of operation of the computers a correspol~ding set of state sign~l~ S1, S2, and S3.
For example, state SEP1 corresponds to state ~ S1=0, S2=1, 2~ and S3=0. When state control signal PWOS changes from a zero logic level to a one logic level, these state ~ign~l~ change: S1=0, S2=0, and S3=0. The state signals S1 - S3 do not change due to the fixed delay waiting period between states SEP 2 and SEP 12, between states EX2 EX5, and between states SB1 and SB10.
30 Moreover, the transitions between states SB11 and SB14 are driven CA 022l6525 l997-09-26 - -by internal timers to provide the four cycle offset between the executive computer and the standby computer. -~
Various functions performed by clock control circuitry of each 5 computer A and B may of course be implemPnted using software ;~-~
algorithms executed by a suitably programmed microprocessor, a -digital signal processor, or an application specific integrated circuit '-(A~IC). For example and as is well known in the data processing art, ;~
the functions illustrated in the state diagram in Figure 5 and ~.
10 represented in the state table in Figure 6 may be implemented using m-icrocode~ assembler code, or high level progr~mming languages.
Using programmed or discrete logic that operates at a lower frequency means the state transition sign~l~ controlling clock switching/selection can be generated using readily available and -~
inexpensive electronic cireuitry. Of course, while a specific example :-~
of a state diagram and state signals is provided in Figures 5 and 6 -for purposes of assisting in the description of the invention, other .
state diagrams and tables for implementing other desirable state transitions could also be readily implemented. Moreover, the state 20 logic array can be easily and inexpensively modified to flexibly accommodate changes in l~he state diagran~/table in the sense that a state diagram implemented with an inexpensive progr~mm~hle circuit may be readily reprogrammed, and an inexpensive discrete logic array could simply be easily and cost effectively replaced. ~
2~ r While the invention has been described in connection with '5~
what is presently considered to be the most practical and preferred ~s embodiment, it is to be understood that the invention is not to be -s -limited to the disclosed ernbodiment, but on the contrar~, is intended . .
CA 02216525 1997-09-26 ,.
W 096/30832 PCT/SE96~0371 to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock control system and method, and more particularly, to the control of high frequency clocking si~ using lower frequency control ~iFn~1.~.
BACEGROUND AND SUMMARY O~ THE INVENTION ~ -A variety of data processing applications use parallel processors which operate together in a synchronous mode of operation. Synchronously operating parallel processors provide system redundancy and therefore high reli~hility. If one processor is faulty, another processor may continue to perform the system control operations in a stand-alone mode of operation. When the faulty processor is repaired, it can be brought back on line to resume parallel synchronous operation. To perform in stand-alone operation, each processor must have its own oscillator or clock. In synchronous operation, only one of ~e processor clocks, however, is used at one time to provide the clocking si~ actually used by the parallel processors. Even if there is some phase delay between the processors, e.g., one of the processors operates N clock signals ahead of the other processor, using the same cloc~ing signal to drive the parallel processors ensures synchronous operation.
In the example of two parallel processors A and B, there are several operational states or modes in which those processors must be able to operat~. First, ~,vith processors A and B operating in parallel =
Wo 96130832 PCT~SE96~00371 and synchronously, processor A operates as an "executive" processor me~nin~ that it operates N cycles ahead of "standby" processor B.
The clock oscillator in executive processor A provides clock siFn~l~
that drive both processor A and processor B. The clock oscillator in 5 processor B is on sta]ldby in the sense ~hat it is not currently used but could be used if needed, i.e., a clock switch occurs. Second, with processors A and B operating in parallel and synchronously, processor B operates as the executive processor meaning that it operates N clock cycles ahead of processor A. ~ccordingly, the lo oscillator in executive processor B provides clock ~i~n~l~ to both processors. Third, both processors A and B must be capable of r~lnnin~ independently of the other processor using their own oscillators in a "stand-alone" mode or state.
Irrespective of operational mode, it is desirable that both processors transition between each of these three states as effectively and as quickly as possible so that the impact on the system being controlled by the processors is minimi~ed. For example, when transitioning between the first and second parallel synchronous 20 states described above, both processors must now switch to rllnning off processor B's clock signal rather than the clock signal from processor A. In addition, processor B, which was previously N cycles behind processor A, must now operate N cycles ahead of processor A.
To minimi7e system impact, the transition should occur without error 2~ and with minim~l delay.
Another problen1 with such state transitions is that the parallel processors operate using a high frequency clock signal that may be much faster than the control sign~ used to control the clock ;,o switching necessary to transition between the various operational :
W 09613~32 PCT/SE96/00371 states of the processors. For example, such state transition control may be generated by a "state m~chine" implemented using discrete logic circuitry or other hardware clocked at a co~siderably lower frequency. The added difficulty then is that of synchroni7.ing 5 the subst~nti~lly lower frequency state control sign~l.s used to effect 'the clock switching transitions with the much higher frequency clocking outputs which drive the parallel processors A and B~ This synchronization process should occur very rapidly (e.g., on the order of several nanoseconds or less if possible), to minimi~e the time 0 required to make the various clock switching transitions.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for 5 controlling clock switching operations between parallel devices ef~lciently and accurately. Moreover, the present invention performs such clock switching operations between high speed clocks using relatively low speed control si~
First and second clock ~ are generated at a first frequency and a clock selection signal is generated at a second, lower frequency. The lower frequency clock selection signal is synchronized with the first frequency clock si~n~l.c and then used to select one of the clock .siFn~l~. Advantageously, the present invention 2~ synchronizes the slower clock selection signal with the faster clock .sign~ls in several nanoseconds or less.
The present invention describes an example method for operating first and second parallel processors in plural modes. Each 30 processor includes its O~YIl i~dependent high speech clock ~~hich may -WO 96/30832 PCT~S~;96/0037 be seIectively connected to supply high speed clocking .ci~n~l.c to both processors. Each processor also includes its own clock switching circuitry for selecting which of the high speed clocking si~n~l.s actually clocks that processor in a particular mode/state. Initially, the first processor may be designated to provide the high speed clocking signal to both the first and second processors using the first processor's clock with the first and second processors operating synchronously. When the mode of operation changes, control ~ lc are provided to the c lock switching circuitry in both processors 10 indicating the need to perforrn a clock switching operation, e.g., the second processor is to provide the high speed clocking signal rather than the first processor. The control ~ign~ are processed in the clock switching circuitry of each processor at a speed substantially slower than the high speed clocking signal. Slower speed clock select 5 .~ are produced which select the high speed clocking signal from the second processor to clock both processors.
Apparatus in accordance with the present invention includes first and second clocks that provide a first frequency clock signal.
20 Electronic circuitry operates at a second frequency lovYer than the first frequency generates a clock selection signal at that second frequency. A synchroni~inF circuit synchronizes the lower frequency clock selection signal with the first frequency clock signal. The synchronized lower frequency clock selection signal selects one of the 25 first and second clocks. The first and second clocks may be resident with respective first and second processors capable of operating in plural modes such as a parallel synchronous mode and an asynchronous stand-alone mode. Each processor also includes electronic circuitry that operates at the second frequency and 30 generates a clock selection signal that selects one of the clocks to wo 96130832 PCI/SE96100371 clock one or both of the processors in response to a change in the operating mode. One of the processors is designated as a clock controlling processor, and the other processor is ~lefiign~ted as a clock following processor operating N clock cycles behind the clock 5 controlling processor. In response to a mode change, the electronic circuitry designates the other processor as the clock controlling processor so that the one processor becomes the clock following processor.
BRIEF D~ESC:EUPTION OF THE DRAWINGS
The novel features believed characteristic of the invention are set forth in the appended cl~im~. Those features as well as other features and advantages thereof will be best understood by reference to the following description of the preferred embodiment when read in conjunction with the accompanying figures, wherein:
r FIGURE 1 is a function block diagram of a data processing system to which the present invention may be applied;
FIGURE 2 is a ~unction block diagram of particular clock switching circuitry which may be used in an example embodiment of the present invention;
2;, FIGURE 3 is a function block diagram of the state logic array shown in Figure 2;
FIGURES 4(a) - 4(c) are tirning diagrams which illustrate an L
exaulple of various clocking and cloc~; switching control ~ ql.s in 30 accordance with various state transitions;
~O 96130832 PCr/SE96/0037 FIGURE 5 is an example state diagram illustrating various states that parallel processors may assume and transitions therebetween; and FIGURE 6 is a table which illustrates for each state shown in the state diagram of Figure 5 corresponding state control .ci~
DETAILED DESCRIPTION OF THE EMBODIMENTS
In the following description, for purposes of ~pl~n~tion and not limitation, specific details are set forth, such as particular circuits, circuit components, interfaces, techniques, etc. in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention 5 may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well known methods, devices, and circuits are omitted so as not to obscure the description of the present invention with unnecessary detail.
Figure 1 illustrates one particular example application of the present invention. A data processing system 10 suitable for controlling, for example, a telephone network includes a central processor 12 that controls several regional processors 20, 22, and 24 which in turn control multiple telephone network operations, e.g., call 2~ set up, routing, etc. The central processor must function at very fast speeds to m~rimi~e the telephone switching capacity but also must function reliably to provide continuous network operation. To ensure reliability, computers 16 and 18, labelled for purposes of description as computer A and colmputer B, operate in parallel and ~,o synchronously. Computers 16 and 18 comm~micate to"ether over a WO 96/30832 PCrJSE96JDl~37 common bus 30 and with regional processors 20-24 through dedicated buses 32 and 34. Both computers include a central processing unit (CPU), memory, and clock circuitry indicated at 26 and 28, respectively~ The clock circuitry at each computer includes an 5 oscillator which operates independently of the other computer's oscillator to generate a high frequency clocking signal, e.g., a 40 MHz clocking signal.
The clocking .si~ A and B are provided to both computers.
10 For example, the oscillator in computer A provides a clocking signal A to the CPU in computer A as well as a clocking signal A to the clock circuitry 28 in computer B. Computer B is simil~rly configured.
A supervisory or maintenance processor (MP) 14 includes its own clock ~5 and may be for example an inexpensive microprocessor 15 operating at a relatively low clock speed, e.g., 16 MHz. Using control .5ign~l1.s from maintenance processor (MP) 14, both sets of clock circuitry 26 and 28 determine in parallel the mode or state of the computers and which clock signal will be selected to operate computers A and B.
In a normal mode of operation, computer A and computer B
operate in parallel synchronous fashion thereby providing redundant and reliable control of regional processors 20-24. Both computer A
and computer B perform the same sequence of operations in parallel.
Although not necessary, in a preferred embodiment, the two computers execute the identical instruction synchronously but slightly offset in time. That is, one computer operates N clock cycles ahead of the other computer, with a suitable value of N being for example four clock cycles. In synchronous operation, both computers ~o use the same clock signal generated by one of the computers. Based , WO 96/308:~2 PCT~SE961ûD371 on control .ciEn~ from the mainten~nce processor 14, the clocking circuitry 26 and 28 in both computers determines which computer's clocking signal will be used to clock both computers. For convenience, the computer whose clock/oscillator is selected to provide 6 clocking si~ to both computers is sometimes referred to as the clock controlling computer or the "executive" computer.
The maintenance processor 14 monitors the operation of computers A and B and generates state control ~ that 10 determine their specific mode/state of operation. If the computers are operating in a parallel synchronous mode, the standby computer buffers the outputs (e.g., operands) generated ~y the executive computer. Outputs from the executive computer are delayed N cycles and compared with the outputs from the standby computer. If there 15 iS a mi~m~tch~ the maintenance processor 14 receives an error signal from the standby computer and may conclude that one of the computers is faulty, send appropriate control signals to the clock circuitry 26 and 28 of both computers to halt the faulty computer, and switch the state of operation of the still functioning computer to 20 a stand-alone state/mode of operation. In that instance, the now independently operating computer necessarily runs on its own clock signal. When the faulty computer is repaired, it is brought back on line with the maintenance processor 14 sending the appropriat control .~ to the clocking circuitry 26 and 28 of both computers 2~ to bring them back into parallel synchronous operation. In order to perform this latter state transition, the currently operating clock in the stand-alone operating computer is stopped for a predetermined delay time, and then the clock in the now executive computer is restarted with the clock sign~l~ being provided to the other computer.
~o Since both computers are clocked at the same time using the same WO 96/30832 Pc rJSE96/0037l t , 9 clock signal, synchronous operation is achieved. Moreover, the executive computer transfers microinstruction addresses and operands via bus 30 to the standby computer which buffers these N
clock cycles and then executes them during an update mode. Ill this 5 way, the computers are brought into synchronous operation with the executive computer N cycles ahead of the standby computer.
With the present invention, these kinds of state transitions are performed in a very short time while still achieving reliable high o speed synchronous operation. The clock circuitry of each computer operates at a second :Frequency lower than the first frequency and generates a clock selection signal that selects one of the clocks from the first and second processors to clock both of the computers. In response to the control .siFn~l.s from maintenance processor 14 15 indicating a mode change, the clock circuitry in each computer generates clock switching control ,sign~ls at that lower frequency.
The lower frequency clock signals are reclocked with extremely short reclocking delay so that they are synchronous with the first frequency clock siFn~l.s. As a result, clock switching operations between high 20 frequency clocks occur with minim~l glitches despite the fact that the clock selection control ~ign~l.s are generated at a lower frequency than the high frequency clocking si~n~l.s.
In another more detailed, example embodiment, Figure 2 26 illustrates an example hardware implementation of the clock circuitry 26 from computer A 16. The clock circuitry B is substantially the same. Of course, other hardware and software implementation could be used. A primary purpose of the clock circuitry is to select one of the high frequency clocks and provide with minimum clock switchillg 30 delay the high frequency clock signal to both computers.
WO 96130832 PCTISE96~00371 The clock circuitry includes an oscillator ~0 for generating a relatively high frequency (fl) clock signal for clocking one or both of the computers at high speed. In one nonlimiting example, fl is 40MHz. A clock divider 52 and a clock selector 72 are connected to 5 the oscillater 50. Clock divider 52 includes an inverting input termin~l 51 which generates a lower frequency (f2) signal that is 180~
out of phase with and an integral multiple of fl, e.g., fl is divided by two to generate f2 at 20MHz. An analogous fl clock signal output from computer B is inverted in inverter 53 and input to the clock 10 selector 72. Clock selector 72 is essentially a high speed multiplexer which selects one of the clock ~ign~ received from both the computers based on state .~ign~ S1-S3. Such a multiplexer may be ~ constructed using three NAND gates 74, 76, and 78, and AND gate 80.
1~ .
A state logic array 56 receives mode detern~inin~ control n~ from the maintenance processor 14 and possibly other control si~nz~ internal to the clock circuitry. Because of the present invention, the state logic array 56 may be constructed using 20 relatively low power and inexpensive integrated logic circuits that run using a much slower clock. For example, array 56 may be constructed using CM[OS circuits which employ well known transistor-transistor logic (TTL) integrated circuits. While CMOS
circuits are quite satisfactory for pulposes of implementing the state 2~ logic array, their switching speed between logic levels is relatively slow, i.e., on the order of 50 nanoseconds. As described in more detail below, when such slow switching speed circuitry generates clock control signals to switch clocks operating at considerably higher frequencies, undesiralble "glitches" may occur.
To be more cornpatible with the high frequency oscillator 50, circuits other than the state logic array 56, like the clock selector 72, operate at higher switching speeds using, for example, ernitter coupled logic (ECL) integrated circuitry. In addition to faster 5 switching speeds, ECL circuits operate at a different set of logic voltage levels than TTL circuits. Therefore, logic conversion buffer 54 buffers the f2 clock signal output from ECL clock divider 52 and converts that signal irlto a corresponding TTL clock signal which clocks the TTL state logic array 66 at frequency f2.
The state logic array 56 may be a programmed logic array (PLA) constructed with discrete, slower switching speed, TTL
integrated circuits in a particular configuration to generate a specific set of state control signals in response to mode deterrnining sign~l~
15 from the maintenance processor 14. While all of the state logic array 56 may operate at frequency f2, there may be circumstances where another third and even lower frequency f3 clocking signal, e.g., 10MHz, drives a portion of the state logic array 56. This third TTL
clocking signal f3 may be generated by dividing the ECL fl clock 20 signal A being sent to operate computer A in a clock divider 82, e.g., a divide by four circuit. The output of the divider 82 is converted by logic level converter 84 into TTL before provided to state logic array 56. Again, a significant advantage of the present invention is that inexpensive relatively slow electronic circuits can be used to control 25 much faster but more expensive clock switching circuitr~ and con~puters.
The TTL state signals Sl-S3 output from state logic array 56 are converted to ECL in a logic level converter 57 including 30 individual conversion buffers 60, 62, and 64 similar to conversio WO 96/30832 ~CTJSE96100371 --buffer 54 described abov.e. The low frequency logic level converter 57 outputs are connected to an ECL synchronizing or reclocking device 58 for reclocking using the lower frPquency clock signal f2 which is 180~ out of phase with and a multiple of the higher frequency clock 5 signal fl. As a result of this reclocking, the relatively slow speed state siEn~l.s S1-S3 are synchronized with the faster computer clock fiiFn~l.s In other word.s, the rising and falling edges of higher frequency clock signal fl align with the rising and falling edges of . .-.
lower frequency f2 state siFn~ls S1-S3. To prevent glitches in clock 1C switching, the reclocker 58 synchronizes S1-S3 with the fl clock signal during the logic 0 half cycle of the fl clock signal. Accordingly, clock divider 52 operates on the negative or falling edge of clock signal fl.
Because the state .si~ S1 -S3 are reclocked using fast switching logic devices such as the three ECL ~;ype D-type flip-flops 66, 68, and 70 in clock selector 72, the time delay required to synchronize the state .c;ign~l.s S1-S3 with the fl clock sign~ is substantially minimi~ed. In this example, using TTL gates to reclock 20 the state siEn~l.s S1-S3 requires a delay on the order of 50 nanoseconds which is a significant "glitch" in any clock switching operation. On the other hand, using ECL gates to reclock the .sign~l.s -, S1-S3 requires a much smaller delay on the order of a nanosecond before the reclocked outputs are provided to clock selector 72 to effect 2~ a clock switching operation. In addition, reclocking the state signals when clock signal fl is low avoids possible glitches which might otherwise occur when i;hose state fiign~l.s change state at the clock r selector 72, as described earlier.
WO 96/3~832 PCTlSE96J0037 Clock selector 72 $elects one of the two clocks to provide high frequency clocking .si~n~l~ to both computers A and B. More specifically, when the mainten~nce ~rocessor 14 comm~n~ a mode or state change which requires a clock switching operation, the state 5 logic array 56, in response to state control .cign~l~ processed using lower frequency clockiLng ~ign~l~ f2 (or f2 and f3), generates corresponding state ~ign~ S1-S3 for executing the clock s-vitch at clock selector 72. To ensure that the clock switch takes place in sync with the high frequency f~ system clocking signal, the state ~ign~l.s 10 S1-S3 are reclocked in reclocker 58. The unavoidable delay encountered in the reclocking operation is truly minimi~ed in the present invention using fast switching ECL transistor circuits with logic level converter 57 being used to convert the TTL logic level of the sign~l~ S1-S3 generated by the slower switching TTL transistor 5 circuits used in the state logic array 56.
Synchronized state signal S1 is input along with the fl clocking signal from computer A oscillator 50 to NAND gate 74 in clock selector 72. Synchronized control signal S2 is input along with 20 the fl clocking signal from computer A oscillator 50 to NAND gate 76. Synchronized stal;e signal S3 is input along with the inverted fl clocking signal from computer B oscillator 50 to NAND gate 78. The outputs of NAND gates 76 and 78 are the inputs to AND gate 80.
The output of NAND gate 74 is the clocking signal provided to 26 computer B (assuming computer A's clock signal is selected), and the output of AND gate 80 is the clocking signal provided to computer A
irrespective of which computer's clock signal is selected.
Referring to Figure 3, a more detailed block diagram of one 30 possible configuration for the state logic array 56 in Figure 2 is W~ 96/3~832 PCTlSE;96/0(1371 illustrated. Control .sign~l.s from the maintenance processor 14 and internal to the clocking circuitrg are decoded in a decoder 90 to produce state control .~ PWOS and SBS State control signal PWOS indicates that both computers A and B are to work in a 5 parallel synchronous mode or state of operation. State control signal SBS indicates if the computer (A or B) is to work in a standby state of operation. Since t:he mainten~nce processor 14 may operate at a frequency different than f2, e.g., 16 MHz, the state control .~ are synchronized in a syrlc block 92 to the f2 clock signal in the clock 10 divider 52. The synchronized state control logic ~ign~l.s PWOS and SBS then are input to a state machine 94 which may include a combination of discrete logic gates connected to implement a specific state table. Those logic gates, based on the combination of input logic states of state control logic sign~ PWOS and SBS, produce 15 state ~ S1-S3. The Iogic circuitry of state machine 94 is also clocked with f2 from clock divider 52.
The timing diagrams in Figures 4(a) - 4(c) illustrate the relationships between the fl, f2, and f3 clock signals, the state control 20 logic .~ign~ PWOS and SBS, the state si~n~l.s S1-S3, and the clock signals to computers A and B, and various example mode changes that require a clock switching operation. The first three waveforms represent the three oscillator ~ fl, f2, and f3. In this example, fl=2f2=4f3. For consistency with Figure 2, the PWOS and SBS state 2:~ control ~ l.s and the S1-S3 state siFn~ are shown next. The final three ~vaveforms include the clock signal from computer B, the clock signal to computer B, and the clock signal to computer A.
Figure 4(a) illustrates a particular example where at time 0 ~o the computers A and B are operatin~, in a parallel synchronous mode - ' CA 02216525 1997-09-26 WO 96/30832 PCTJSE96~a(1371 of operation with executive computer B providing the high speed clocking signal f7 to both computers with computer A currently being the standby (SB) computer. However, at time 1 a mode change occurs as indicated by the shift in the SBS state control signal from a logic high level to a logic low level. This indicates computer A is to now become the executive and the computer B (previously the executive) is to become the standby. Accordingly, computer B stops sending its clock signal as a result of control ~i~n~ generated by its own control clock circuitry 28 at time 4. A predetermined fixed delay 10 period must be waited for the mode/state ch~nging control .~ign~ to be received and processed in the state logic array 56 of the control clock circuitry. At time 5, those control si~n~l~ have been processed, and the state transition ~ S1-S3 which control the clock switch are generated. Thus, at time 5, state signal S2 goes from a logic low level to a logic high level, and state signal S3 goes from a logic high level to a logic low level. Also at time 5, the clock signal generated in computer A (now the executive) begins and commences operation of computer A. The clock signal from computer A to computer B is not transmitted until time 13 (8 clock cycles later) as indicated by the 20 change in lo~c level of state control signal S1. This delay essentially corresponds to a phase shift of two times the N cycle offset between executive computer A and standby computer B. In the example, N=4.
Figure 4~b) shows a timing diagram for an example mode/state 2~ transition where computer A is switched from executive to standby.
State control signal SBS changes logic level at time 2 with the corresponding state transition signals being generated at time 5. At time 5, clock .~ from computer A are no longer delivered to computer A or computer B. From time 5 to 13, computer A prepares 30 to receive clock sign~lc; from comp~ter B. At the same time, control w096130832 PCr/SE961~037 ~;iFn~l.s in the clock c3Lrcuitry of computer B are processed. At time 13 the state transition siLgnal S3 goes from a logic low to logic high level indicating that computer A is ready to receive clock pulses from computer B. Since computer B is now the executive computer, it 5 operates four cycles ahead of computer A. Therefore, there is a phase - shift delay of four cyeles during the time delay before computer A
receives clock ~ign~l~ from clock B at time 14.
Figure 4(c) is a timing diagr~m which shows the timing for 10 computer A operating in a stand-alone, independent mode switched to operate as the executive computer in a parallel synchronous mode with computer B. The state control signal PWOS shifts from a low to high logic level at time 3. State transition (clock switching) signals are generated at time 5, i.e., S2 goes from a high logic level to a low logic level, indicating that computer B is ready to resume parallel synchronous operation with computer A. After the predetermined delay, state transition si, n~ S1 and S2 change logic level at time 6 which starts the clock signal in computer A. At the same time, the clocking signal from clock A is sent to computer B to ensure 20 synchronous operation.
Although not illustrated as specific timing diagrams, clock switching operations are a1sQ required when stand-alone computer A
resumes parallel synchronous operation with computer B but becomes 26 the standby computer rather than the executive computer. Another mode includes the change of a computer operating synchronously beinD converted to stand-alolle operation.
Reference is now made to Figure 5 which illustrates a state ~o diagram of ~7arious possible states of operation for the stat~ logic arrays for computers A and B. Each circle represents a particular mode/state of the cornputers A and B. Each line between circles represents a change of state. Some of the changes of state occur automatically or after a predetermined time period expires. Other 5 state transitions require a particular logic level state control signal.
For example, to change from state SEP1 to state SEP2, the state control signal PWOS must change from a logic zero to a logic one. If PWOS rem~in~ zero~ there is no state change with the state rem~ining at SEP1. In state SEP3, there are two possible state 10 transitions: to state SBS1 if state control signal SBS equals a logic one or to state SEP 4 if state control signal SBS equals a logic zero.
State SEP1 corresponds to both the computers operating in a separate stand-alone state which may occur for example when the 5 other computer is faulty and/or has been taken offline. State EX1 corresponds to the state where the computer whose clock circuitry is implementing the state diagram is the executive providing clock signals to both computers. State SB1 corresponds to the state where this computer is the standby receiving its clocking signal from the zo other computer.
Figure 6 shows in table form for each specific state of operation of the computers a correspol~ding set of state sign~l~ S1, S2, and S3.
For example, state SEP1 corresponds to state ~ S1=0, S2=1, 2~ and S3=0. When state control signal PWOS changes from a zero logic level to a one logic level, these state ~ign~l~ change: S1=0, S2=0, and S3=0. The state signals S1 - S3 do not change due to the fixed delay waiting period between states SEP 2 and SEP 12, between states EX2 EX5, and between states SB1 and SB10.
30 Moreover, the transitions between states SB11 and SB14 are driven CA 022l6525 l997-09-26 - -by internal timers to provide the four cycle offset between the executive computer and the standby computer. -~
Various functions performed by clock control circuitry of each 5 computer A and B may of course be implemPnted using software ;~-~
algorithms executed by a suitably programmed microprocessor, a -digital signal processor, or an application specific integrated circuit '-(A~IC). For example and as is well known in the data processing art, ;~
the functions illustrated in the state diagram in Figure 5 and ~.
10 represented in the state table in Figure 6 may be implemented using m-icrocode~ assembler code, or high level progr~mming languages.
Using programmed or discrete logic that operates at a lower frequency means the state transition sign~l~ controlling clock switching/selection can be generated using readily available and -~
inexpensive electronic cireuitry. Of course, while a specific example :-~
of a state diagram and state signals is provided in Figures 5 and 6 -for purposes of assisting in the description of the invention, other .
state diagrams and tables for implementing other desirable state transitions could also be readily implemented. Moreover, the state 20 logic array can be easily and inexpensively modified to flexibly accommodate changes in l~he state diagran~/table in the sense that a state diagram implemented with an inexpensive progr~mm~hle circuit may be readily reprogrammed, and an inexpensive discrete logic array could simply be easily and cost effectively replaced. ~
2~ r While the invention has been described in connection with '5~
what is presently considered to be the most practical and preferred ~s embodiment, it is to be understood that the invention is not to be -s -limited to the disclosed ernbodiment, but on the contrar~, is intended . .
CA 02216525 1997-09-26 ,.
W 096/30832 PCT/SE96~0371 to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (26)
1. An apparatus comprising:
first and second processors capable of operating in plural modes, each processor including:
a clock selectively providing a first frequency clock signal to the first and second processors, and electronic circuitry, operating at a second frequency lower than the first frequency, generating a clock selection signal that selects one of the clocks from the first and second processors to clock one or both of the processors in response to a change in the operating mode of the processors.
first and second processors capable of operating in plural modes, each processor including:
a clock selectively providing a first frequency clock signal to the first and second processors, and electronic circuitry, operating at a second frequency lower than the first frequency, generating a clock selection signal that selects one of the clocks from the first and second processors to clock one or both of the processors in response to a change in the operating mode of the processors.
2. The apparatus in claim 1, wherein the processors are capable of operating in a synchronous mode and an asynchronous stand-alone mode.
3. The apparatus in claim 1, wherein in a synchronous mode of operation, one of the processors is designated as a clock controlling processor and the other processor is designated as a clock following processor, and in response to a mode change, the electronic circuitry changes the other processor to the clock controlling processor and the one processor to the clock following processor.
4. The apparatus in claim 3, wherein the electronic circuitry in the clock controlling processor stops its clock in response to the mode change, and after a predetermined time period, the clock following processor becomes the clock controlling processor and provides clocking signals to both processors.
5. The apparatus in claim 4, wherein the clock controlling processor operates N clock cycles ahead of the clock following processor.
6. The apparatus in claim 1, wherein the electronic circuitry includes:
a clock selector receiving clocking signals from both processors and selecting one of the clocking signals to operate both of the processors, and a clock switching controller operating at the lower frequency clock signal for receiving mode change signals and providing a clock control signal to the clock selector.
a clock selector receiving clocking signals from both processors and selecting one of the clocking signals to operate both of the processors, and a clock switching controller operating at the lower frequency clock signal for receiving mode change signals and providing a clock control signal to the clock selector.
7. The apparatus in claim 6, wherein the clock switching controller includes:
an array of logic devices for generating various clock control state signals at the lower frequency, and a reclocking circuit for reclocking the lower frequency clock control state signals synchronous with the first frequency clocking signals.
an array of logic devices for generating various clock control state signals at the lower frequency, and a reclocking circuit for reclocking the lower frequency clock control state signals synchronous with the first frequency clocking signals.
8. The apparatus in claim 7, wherein the reclocking circuit reclocks the clock control state signals with a delay on the order of 1-2 nanoseconds.
9. The apparatus in claim 7, the clock switching controller further comprising:
a logic level converter for converting the logic level of the clock control state signals to another logic level.
a logic level converter for converting the logic level of the clock control state signals to another logic level.
10. An apparatus comprising:
first and second processors capable of operating in parallel in a synchronous mode and separately in an asynchronous mode, and a supervisor for monitoring the mode of operation of the processors and changing the processors from the synchronous mode to the asynchronous mode when an error in synchronous operation is detected, wherein each processor includes:
a clock, operating at a first frequency, selectively providing a first frequency clock signal to the first and second processors, and means, operating at a second frequency slower than the first frequency, for generating a clock selection signal that selects one of the clocks from the first and second processors to clock one or both of the processors in response to a change in the operating mode of the processors.
first and second processors capable of operating in parallel in a synchronous mode and separately in an asynchronous mode, and a supervisor for monitoring the mode of operation of the processors and changing the processors from the synchronous mode to the asynchronous mode when an error in synchronous operation is detected, wherein each processor includes:
a clock, operating at a first frequency, selectively providing a first frequency clock signal to the first and second processors, and means, operating at a second frequency slower than the first frequency, for generating a clock selection signal that selects one of the clocks from the first and second processors to clock one or both of the processors in response to a change in the operating mode of the processors.
11. The apparatus in claim 10, wherein the supervisor operates at a frequency that is less than or equal to one half of the first frequency.
12. The apparatus in claim 11, wherein the synchronous mode of operation, the clock of one of the first and second processors is selected to clock both of the processors and the supervisor compares the output from the first and second processors and changes the mode of operation from synchronous to asynchronous when the outputs do not match.
13. The apparatus in claim 12, wherein when the supervisor halts one of the processors, the other of the processors operates asynchronously using its own clock signals, and when the one processor is brought back into synchronous operation, the processor clocks are stopped for a predetermined time delay, and thereafter synchronous operation is resumed using one of the processor's clock signals to operate both processors.
14. An apparatus comprising:
first and second clocks providing a first frequency clock signals;
electronic circuitry, operating at a second frequency lower than the first frequency, generating a clock selection signal at the second frequency; and a synchronizing circuit for synchronizing the lower frequency clock selection signal with the first frequency clock signal, wherein the synchronized lower frequency clock selection signal selects one of the first frequency clock signals generated by the first and second clocks.
first and second clocks providing a first frequency clock signals;
electronic circuitry, operating at a second frequency lower than the first frequency, generating a clock selection signal at the second frequency; and a synchronizing circuit for synchronizing the lower frequency clock selection signal with the first frequency clock signal, wherein the synchronized lower frequency clock selection signal selects one of the first frequency clock signals generated by the first and second clocks.
15. The apparatus in claim 14, wherein the synchronizing circuit includes:
a logic array having a first logic type that receives control signals and generates state signals at the lower frequency, and a reclocking circuit for reclocking the state signals at the lower frequency synchronous with the first frequency clock signal.
a logic array having a first logic type that receives control signals and generates state signals at the lower frequency, and a reclocking circuit for reclocking the state signals at the lower frequency synchronous with the first frequency clock signal.
16. The apparatus in claim 15, wherein the synchronizing circuit includes:
a logic converter for converting the first logic type state signals into second logic type signals.
a logic converter for converting the first logic type state signals into second logic type signals.
17. A method comprising the steps of:
generating first and second clock signals at a first frequency;
generating a clock selection signal at a second lower frequency;
synchronizing the clock selection signal with the first frequency clock signals; and selecting one of the clock signals using the clock selection signal.
generating first and second clock signals at a first frequency;
generating a clock selection signal at a second lower frequency;
synchronizing the clock selection signal with the first frequency clock signals; and selecting one of the clock signals using the clock selection signal.
18. The method in claim 17, wherein the second frequency is one half or less the first frequency.
19. The method in claim 17, wherein second frequency is derived from the first frequency, the synchronizing step further comprising:
reclocking the clock selection signal with the second frequency signal.
reclocking the clock selection signal with the second frequency signal.
20. The method in claim 19, wherein the synchronizing step synchronizes the clock selection signal with the clock signals in several nanoseconds or less.
21. A method for operating first and second parallel processors in plural modes, each processor having its own independent high speed clock connected to selectively supply high speed clocking signals to the parallel processors and its own clock switching circuitry for selecting which high speed clocking signal clocks that processor in a particular operational mode, comprising the steps of:
designating the first processor to provide the high speed clocking signal to both the first and second processors from the first processor's clock;
operating the first processor synchronous with the second processor;
providing control signals to the clock switching circuitry in both processors designating the second processor to provide the high speed clocking signal to both the first and second processors; and processing the control signals in the clock switching circuitry at a speed substantially slower than the high speed clocking signal to produce clock select signals that select the high speed clocking signal from the second processor to clock the first and second processors.
designating the first processor to provide the high speed clocking signal to both the first and second processors from the first processor's clock;
operating the first processor synchronous with the second processor;
providing control signals to the clock switching circuitry in both processors designating the second processor to provide the high speed clocking signal to both the first and second processors; and processing the control signals in the clock switching circuitry at a speed substantially slower than the high speed clocking signal to produce clock select signals that select the high speed clocking signal from the second processor to clock the first and second processors.
22. The method in claim 21, wherein when one of the processors is removed from synchronous operation, the method further comprises the steps of:
operating the other of the processors asynchronously using its own high speed clocking signals.
operating the other of the processors asynchronously using its own high speed clocking signals.
23. The method in claim 21, wherein the first processor providing the high speed clocking signal to both the first and second processors is N clock cycles ahead of the second processor.
24. The method in claim 23, further comprising:
generating a signal that changes the processor which provides the high speed clocking signals;
stopping the clocks of both processors for a predetermined delay;
generating the high speed clocking signal at the second processor; and providing the high speed clock signal to the first processor after a 2*N cycles delay.
generating a signal that changes the processor which provides the high speed clocking signals;
stopping the clocks of both processors for a predetermined delay;
generating the high speed clocking signal at the second processor; and providing the high speed clock signal to the first processor after a 2*N cycles delay.
25. The method in claim 21, wherein the processing step further comprises:
reclocking the clock selection signal with a clocking signal at the lower speed to synchronize the clock selection signal with the high speed clocking signal.
reclocking the clock selection signal with a clocking signal at the lower speed to synchronize the clock selection signal with the high speed clocking signal.
26. The method in claim 25, wherein the reclocking step synchronizes the clock selection signal with the high speed clocking signals in several nanoseconds or less.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/413,857 US5758132A (en) | 1995-03-29 | 1995-03-29 | Clock control system and method using circuitry operating at lower clock frequency for selecting and synchronizing the switching of higher frequency clock signals |
| US08/413,857 | 1995-03-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2216525A1 true CA2216525A1 (en) | 1996-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002216525A Abandoned CA2216525A1 (en) | 1995-03-29 | 1996-03-25 | Clock control system and method |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US5758132A (en) |
| EP (1) | EP0817999B1 (en) |
| JP (1) | JPH11502959A (en) |
| KR (1) | KR100301720B1 (en) |
| CN (1) | CN1090779C (en) |
| AU (1) | AU5166496A (en) |
| CA (1) | CA2216525A1 (en) |
| DE (1) | DE69625473T2 (en) |
| WO (1) | WO1996030832A1 (en) |
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-
1996
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- 1996-03-25 AU AU51664/96A patent/AU5166496A/en not_active Abandoned
- 1996-03-25 KR KR1019970706850A patent/KR100301720B1/en not_active IP Right Cessation
- 1996-03-25 CA CA002216525A patent/CA2216525A1/en not_active Abandoned
- 1996-03-25 EP EP96908427A patent/EP0817999B1/en not_active Expired - Lifetime
- 1996-03-25 WO PCT/SE1996/000371 patent/WO1996030832A1/en active IP Right Grant
- 1996-03-25 JP JP8529257A patent/JPH11502959A/en active Pending
- 1996-03-25 DE DE69625473T patent/DE69625473T2/en not_active Expired - Lifetime
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| CN1090779C (en) | 2002-09-11 |
| AU5166496A (en) | 1996-10-16 |
| JPH11502959A (en) | 1999-03-09 |
| DE69625473T2 (en) | 2003-10-02 |
| DE69625473D1 (en) | 2003-01-30 |
| WO1996030832A1 (en) | 1996-10-03 |
| CN1185847A (en) | 1998-06-24 |
| EP0817999B1 (en) | 2002-12-18 |
| KR19980703446A (en) | 1998-11-05 |
| US5758132A (en) | 1998-05-26 |
| EP0817999A1 (en) | 1998-01-14 |
| KR100301720B1 (en) | 2001-10-27 |
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