CA2241446A1

CA2241446A1 - Printed circuit multilayer assembly and method of manufacture therefor

Info

Publication number: CA2241446A1
Application number: CA002241446A
Authority: CA
Inventors: Richard J. Pommer
Original assignee: Individual
Current assignee: Honeywell International Inc
Priority date: 1996-01-05
Filing date: 1997-01-03
Publication date: 1997-07-17
Also published as: CN1212115A; EP0956748A1; US5839188A; TW342580B; MY113149A; CN1096222C; IL125101A0; AU1527697A; KR19990077005A; JP2000515680A; US6246014B1; KR100442215B1; IL125101A; BR9706961A; WO1997025844A1

Abstract

A printed circuit assembly and method of making the same utilize in one embodiment an adhesive layer including a plurality of non-conductive "gauge particles" disposed within a non-conductive adhesive. When the adhesive layer is disposed between opposing printed circuit layers (be they insulating substrates, conductive layers, or other layers), individual gauge particles (44, 174) are interposed or sandwiched at various points between the layers such that the diameters of the particles control the layer separation throughout overlapping areas of thereof, thereby permitting careful control over layer separation. A printed circuit assembly and method of making the same utilize in another embodiment an interlayer interconnecting technology incorporating conductive posts that are deposited on one of a pair of contact pads formed on opposing printed circuit boards and thereafter bonded to the other in the pair of contact pads during lamination. Fusible material may be utilized in the conductive posts (208, 209) to facilitate mechanical bonding to a contact pad, and the posts project through a dielectric layer disposed between the printed circuit boards, thereby forming the electrical connections between the boards at discrete locations.

Description

CA 02241446 1998-06-2~
W O 97/25844 PCTrUS97/00175 PRINTED CIRCUIT MULTILAYER ASSEMBLY AND METHOD OF MANUFACTURE THEREFOR

Field of the Invention The invention relates to printed circuit assemblies and methods of m~mlf~rtllre therefor. More particularly, the invention relates to printed circuit assemblies and methods of m:lmlf~rtllre thereof having controlled separations between conductive layers, and to printed circuit assemblies and methods of m~m-f~rtllre thereof in which multiple overlapping conductive layers are electrically interconnected.

B~3ck~round of the Invention As the complexity and data processing speeds of electronic products continue to increase, the Lllo~el~ies of the interc~ i..g circuitry which connects complex and high speed integrated circuit devices become more pronounced and must be carefully analyzed to ensure reliable circuit perform~nce Often, it is the increases in complexity and data proceccing speeds of integrated circuit devices that dictate performance improvements in the interc~nn~cting c~.~;uiL~y to which the devices are mounted.
For ex~mrl~7 the complexity of integrated circuit devices, and in particular the advent of surface mount technologies, dictate that greater densities of signal traces be packed into smaller packages to reduce costs and illl~ Ve reliability.Signal trace widths and spacing has decreased to accommodate higher densities.
Moreover, greater ~lencities may be obtained with double-sided and multilayer printed wiring boards having multiple conductive layers that are typically electrically connected via conductive through holes.
Signal trace width and spacing, as well as through hole width and spacing, cignific~ntly impact the r~rk~ging density obtainable with interconn~cting cil~;uiLIy, W O 97n5844 PCT~US97/00175 and conseque.ntly, much development efforts are directed to interconnection technologies that decrease these rninimllm flim~.n~ ns to perrnit greater E!~r~gin~
densities without co~ly~ m ising reliability or perform~nre Some of these development efforts are related to the interlayer interconnection of overlapping conductive layers across dielectric layers, where it is desirable to decrease the size of the intercormects across the dielectric layers, while reducing m~nuf~rturing costs and complexities. For example, conductive through holes may be drilled and plated through mllltiple layers to forrn interlayer connections. However, drilled through holes occupy .cignific~nt space on a printed circuit board, both because the through holes are formed through the entire board, regardless of which layers need be interconnectt~ and because most lllecl~ ical drilling processes are typically limited to holes with about; 100 micron minimnmdiameters. Anisotropic adhesives are another al~ alive for forming interlayer connections; however, some anisotropic adhesives do not form pure m.ot~llnrgicaljoints, and thus may suffer from a reliability standpoint. Further, they often require coverlayers to in.~nl~tr. non-connected but overlapping conductive areas, thus increasing overall assembly thickne~.ces.
Tlle~e~ol~, a ~ignifi~nt need c~ntinurs to exist for a reliable interlayer interconnection technology which is compatible with the c<~ g drive to increase packaging clrn~iti~s in interconn~cting ~ y.
As was also noted above, the data processing speeds obtainable with advanced high speed integrated circuit devices also dictate the required char~rte.ri.~tirs of the interconnP.cting c~ ly used to connect such devices.
Currently, int~.gr~tt-.~l circuit devices may operate with a throughput in gigabits per second, r~.~llltin~ in pulse durations of less than a n~nose.cond and rise times in the picosecond range. IJnder these conditions, the conductors connecting these devices become active components in the circuits, both in terrns of affecting propagation delays and impefl~nr.e matching.
Propagation delays are affected by h~telco~ g cill;uilly such as printed circuit boards and assemblies 1" ;"~ lly as a result of the ~lirlectnc constant of the m~tr.ri~l.c used in the ci . ~;uiL~y. In particular, m~t~.ri~l~ having low t1i~.lect~ic c~ are desirable to use for . . ~ g any propagation delays, and thereby increasing the range of obtainable signal speeds within a circuit.

W O 97/25844 PCTrUS97/00175 Impedance is principally the combination of rP,cict~n~-P" capacitance and in~ t:~nc~ which create electric and mz~gnPtic fields in a circuit. The impedance of a eircuit is also called the chaLA~ IP.I ;ctic impedance, as it depends solely on the characteristies of the m~tPri~lc used and their spatial relationship. Faetors such as the dielectric c--nct~ntc of circuitry m~tPri~lc and lengths and widths of conductive ~es ~na~ af~eet the ~d~eristie impedar.e~a~le~ronie~re~.
tching the impe-l~nces of interc(-nnPcting ch~;uilly with other eleetronic devices and conneetors is hll~ol L~lt for ensuring signal integrity in a circuit. This is be~ ce, at high frequeneies, signals may get refleeted when impe~l~n~e micm~tches are present in a circuit. Such micmatches distort signals, increase rise times, and otherwise generate errors in data tr~ncmiccion. Consequently, impedance m~tchin~ is often n~c~,csslry to provide m~3ximllm power lldn~.fel between the connected eleetronic eomponents and systems and to prevent signal reflections from forming along the signal paths.
As noted above, impedance in a printed circuit is directly related to the separation between signal traces separated by an inclll,.ting layer, as well as to the dielectric constant of the mz-tPri~l in the inclll~ting layer. One controlled impedance design is the surface microstrip configuration, where a signal trace opposes a ground plane, with no other overlapping conductive layers. Another is the stripline configuration, where a signal trace is sandwiched between a pair of ground planes.
Controlled impedance requires that both the .~ lcctric constant of the inclll~ting layer, and the separation between the signal traces, to be carefullycontrolled. For many conventional double-sided printed circuit assemblies, this may not be a ~ignific~nt problem because incnl~ting ~.ul~ dl~s such as polymer films and h~oal~ls can usually be m~nllf~l~tnred with earefully eontrolled thiclcnPcces and dielectric c~-nct~nt.c.
However, for many multilayer printed circuit assemblies (i.e., those with three or more conductive layers), impedance control is more dif~lcult, typicallybecause of the adhesives commonly used in the interlayer interconnection technologies that bond individual single- or double-sided boards together when forming such assemblies. A similar problem may also exist for some two layer boards, e.g., those with opposing single sided boards eonneeted through adhesives.

CA 0224l446 l998-06-2~
WO 97~5844 PCT~US97/00175 The problem with such adhesives principally stems from the inability to control the separation between the opposing conductive layers during and after co~ r~,s~ion or l~min~tion of the assembly, as most of the adhesives are ~l~.cign~-1 to flow somewhat during l~min~tion and f~ in gaps between boards. As a result, it becomes difficult to obtain controllable separation throughout a printed circuitassembly. Additional problems may arise from imperfect or uncontrolled deposition of the conductive layers and any intel vt;ni~lg coverlayers, rçsnlting in varying thicknesses in these layers.
Another i~ o,t~lL concern with many multilayer printed circuit assemblies is planarity. In particular, it may be important to m:~int~in controlled thi~kn~.~.c~,~ of layers, even in non-impedance critical applications, so that outer surfaces of an assembly are substantially planar. This may be important, for example, when populating an assembly with integrated circuit and other electronic devices, since connecting pads on the assembly for mounting these devices should have similar elevations to ensure reliable connections therebetween. However, given the more compzlrtible nature of in~nl~ting substrates and adhesives as co~ aL~d to conductive m~tf~,ri~ min~ti~n of such assemblies may induce non-planarity.
Further, the effects are cumulative with the ~ el of layers, and consequently, the effects may be more pronounced in thicker multilayer assemblies.
One type of interlayer inLt;r~olmection technology used to bond together opposing conductive layers is the aforenlc;llLioned anisotropic adhesive, which typically contains conductive parficles disposed in a non-conductive adhesive. An anisotropic adhesive, when layered between opposing conductive layers, is (lecign~fl to conduct only across its thickness and not between dirre ~nt pointswithin the layer. The anisotropic nature of the adhesive permits it to be layered throughout overlapping portions of conductive layers to both bond the layers together and electrically connect any opposing contact pads formed in the conductive layers.
Some anisotropic adhesives utilize conductive particles such as metal-coated polymeric or glass spheres, and some may further include ~A~lifion~l non-conductive particles that prevent excess defollllaLion of the conductive particles during l~min~fi~n Also, some of these particles are int~,nflf .A to be disposed in a single layer such that opposing contact pads connected by the particles are sep~r~
by a fli~f~n~e equal to the Ai:~m~ters of the particles.

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W O 97/25844 PCT~US97/00175 While such particles may control the separation b~;lween the electrically connected contact pads in some applications, they are not suitable for controlling the separation between conductive layers throughout an entire circuit assembly, particularly in areas where overlapping conductive portions in the layers are not ~ electric ~l~y connPcte~l across the adhesive layer. Tn~te.a(l, in areas where overlapping pads or traces of conductive m~tPri~l are not electri-~lly connP-ct~l, a coverlayer is used (which also has the disadvantage of increasing the overall assembly thickn~.s~), or one or both conductive layers in the overlapping areas are somewhat recesse-1, such that the conductive particles are not capable of abutting both conductive layers directly. Otherwise, undesired electrical connections would be formed in those overlapping areas.
Also, since interlayer electrical connections between opposing conductive layers generally take up a relatively small area of a printed circuit assembly, the conductive particles in anisotropic adhesives are not suitable for controlling the separation between conductive layers in most of an assembly. Furtherrnore, when dealing with a signal layer opposing one or more ground planes, as is found in many controlled impedance applications, the el~octric~l connections between the signal layer and the ground planes may be quite sparse and widely separated, further minimi7.ing the ability of such adhesives to effectively control layer separation throughout relatively large areas of the printed circuit assembly.
Therefore, a substantial need has also existed for a manner of bonding printed circuit layers to one another with a highly controllable separation throughout opposing portions thereof. Mo}eover, a ~ub~alllial need has arisen for a manner of bonding printed circuit layers with controlled separation which do not rely solely on the interlayer electrical connection points between opposing layers to control layer separation.

Su~ / of the Invention The invention addresses these and other problems associated with the prior art in providing a printed circuit assembly and method of making the same which in one aspect utilizes an adhesive layer in~ ling a plurality of non-conductive "gauge particles" disposed within a non-conductive adhesive. When the a&esive layer is interposed bt;lw~en opposing printed circuit layers, individual gauge particles are interposed or sandwiched at various points be~weell the printed circuit layers such CA 0224l446 l998-06-25 W O 97~5844 PCT~US97/00175 that the ~ rnPters of the particles control the separation belween the circuit layers throughout the assembly.
By "printed circuit layer", what is meant is any layer within a printed circuit assembly, whether conductive or non-conductive, and irrespective of its manner of deposition or placement on the assembly. Thus, a "printed circuit layer" may include conductive layers formed of metals or conductive polymers, flexible or rigid substrates, coverlayers, films, etc. Preferably, a "printed circuit layer" will be substantially non-deformable, so that any gauge particles abutting the layer will not subst~nti~lly deform the layer, but will instead control its relative position within the assembly.
Moreover, it will be appreciated that using gauge particles to control the separation b~;lwe~ll circuit layers may also de facto control the separation between other circuit layers in the assembly which do not abut the gauge particles, but which are conn~ctP~l in some manner to the circuit layers which do abut the particles.Thus, it will be appreciated that control of this separation may be obtained consistent with the invention not only by interposing the gauge particles between the conductive layers, but also belweell one conductive layer and another layer-to which the other conductive layer is attached (e.g., an insulating ~ub~ldl~), as well as between two such layers to which the conductive layers are attached (e.g., between two inc~ ting ~ul~ al~s). Other combinations may also be used concictent with the invention.
The particles in the adhesive layer are decign~te~l "gauge" particles because they r1~termin~ or control the separation b~lwe~ll opposing printed circuit layers in a m~nllf~etured assembly. Furthermore, the particles are constructed to be non-conductive, such that a particle may be oriented at practically any point between opposing printed circuit layers irrespective of the ms~teri~l.c used in the opposing layers, and irrespective of whether an el(.ctrit~l connection has or is to be formed at this point.
The invention addresses a~1t1itiotl~l problems associated with the prior art in providing a printed circuit assembly and method of making the same which in another aspect h~l~;rco.-llects contact pads on an overlapping pair of conductive layers through conductive posts formed on the contact pads on one layer and bonded to the contact pads on the other layer. Fusible m~t~.ri~l may be inccl~o~dl~d CA 0224l446 l998-06-2~
WO 97/25844 PCTrUS97/00175 into the posts to form fused connections with the opposing contact pads. The posts may project through ~ Lul~;s in a dielectric layer s~a~ g the conductive layers, or alternately, the posts may "pierce" through the dielectric layer during l~min~ti~)n, thereby elimin~ting a separate a~ u~ formation step.
Therefore, in accordance with one aspect of the invention, there is provided a printed circuit assembly, which in~ (les first and second printed circuit boards, each printed circuit board including an in~ll:~ting substrate with a conductive layer disposed thereon, the conductive layer on the first printed circuit board including a first contact pad opposing a second contact pad on the conductive layer on the second printed circuit board, and at least one of the first and second printed circuit boards including a second conductive layer formed on the opposite surface of thein~nlating substrate; a dielectric layer disposed between the first and second printed circuit boards; and a conductive post, formed on the first contact pad, the conductive post ext~n~ling across the dielectric layer and abutting the second contact pad, thereby ~lectric~lly connecting the first and second contact pads.
In accol.lance with another aspect of the invention, there is provided a method of m~mlf~f tnring a printed circuit assembly. The method includes the step of forming a conductive post on a first printed circuit board, the printed circuit board incln-ling an in~nl~ting substrate with a conductive layer disposed thereon, wheleill the conductive post is disposed on a first contact pad disposed in the conductive layer of the first printed circuit board; placing a second printed circuit board over the first printed circuit board with a second contact pad aligned with the conductive post and with a dielectric layer disposed thel~bt;lween, the second printed circuit board including an in~ ting substrate with a conductive layer disposed thereon, wherein the second contact pad is disposed in the conductive layer of the second printed circuit board, and W11~LCi1I at least one of the first and second printed circuit boards includes a second conductive layer forrned on the opposite surface of the in~nl~tinp substrate; and col~ essillg the first and second printed circuit boards together until the conductive post extends across the dielectric ~ layer and abuts the second contact pad, thereby electrically conn~cting the first and second contact pads.
These and other advantages and features, which characterize the invention, are set forth in the claims ~nnt~xpd hereto and forming a further part hereof.
However, for a better underst~ntling of the invention, and of the advantages and WO 97n5844 PCT~US97/00175 objectives attained by its use, reference should be made to the Drawings, and to the a~co,ll~anying ~1PSCI ;p~ e matter, in which there are described preferred embo-lim~rlt~ of the invention.

BrIef Pescription of the Drawings FIGURE 1 is a perspective view of one pLt;felled printed circuit assembly consistent with the principles of the invention.
FIGURE 2 is an exploded cross-sectional view of a preferred printed circuit assembly of Fig. 1.
FIGUE~E 3 is a cross-sectional view of a preferred printed circuit assembly, taken through line 3-3 of Fig. 1.
FIGURE 4 is a cross-sectional view of an ~ltentsl~ ~lc;r~l~ed printed circuit assembly to that of Figs. 1-3, where gauge particles are disposed between an insulating substrate and a conductive layer.
FIGURE 5 is a cross-sectional view of an slltf~ tl~ preferred printed circuit assembly to that of Figs. 1-3, where gauge particles are disposed between a pair of conductive layers.
FIGURE 6 is an exploded cross-section view of another ~ltern~tf~ printed circuit assembly to that of Figs. 1-3, where a conductive plug is formed in the adhesive layer to electrically connect opposing contact pads.
FIGURE 7 is a cross-section view of the ~lt~ te printed circuit assembly of Fig. 6.
FIGURE 8 is an exploded cross-section view of another ~lt~ P printed circuit assembly to that of ~igs. 1-3, where a conductive post projects through the adhesive layer to electrically connect opposing contact pads.
FIGURE 9 is a cross-section view of the ~?ltern~te printed circuit assembly of Fig. 8.

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W O 97/25844 PCT~US97/00175 _~_ F~GURE 10 is a cross-section view of another ~ltern~te, printed circuit assembly to that of Figs. 8-9, whereby an alternate dielectric layer is disposedbetween opposing printed circuit boards.

~et~ l Description of the Preferred Embodiments The invention incol~oldLes two plilllaly aspects. The first deals with controlling the separation between opposing printed circuit layers in a printed circuit assembly. The second deals with forming interlayer interconnections between opposing conductive layers in a printed circuit assembly. While both aspects of the invention are useful when used in conjunction with one another, it should be appreciated that neither aspect should be limited to use only in conjunction with the other.

Co~trolled Separation Turning to the Drawings, wherein like numbers denote like parts throughout the several views, Fig. 1 shows a ~lGfell~,d printed circuit assembly 10 cnn~i~tent with the principles of the present invention. Assembly 10 generally incl~ s a pair of double-sided printed circuit boards 20, 30 joined by an adhesive layer 40.
One principle benefit of the invention is the ability to reliably control circuit layer separations through the use of an adhesive layer having gauge particles dispersed therein. Controlled laye} separation may be ben~,fici:~l for controlling impe-l~nre7 as well as to ensure planarity throughout an assembly.
In general, preferred embo-1im.o,nt~ of the invention operate by interposing controlled diameter gauge particles between opposing or ~v~lla~illg portions of printed circuit layers and compressing the circuit layers such that the particles abut both opposing layers and thereby define the separation therebetween. Moreover, con~ rinp the stability and non-deformability of many printed circuit materials,controlling the separation between printed circuit layers also controls the separation between other layers connecte,-1 thereto. This also has the effect of .ni.~ g any additive planarity distortions in a multiple layer printed circuit assembly.
The gauge particles may be interposed between any two opposing printed circuit layers, which as discussed above may include nuInerous m:~t~ , incl~ ing CA 02241446 1998-06-2~
W O 97~5844 PCT~US97/00175 conductive layers formed of metals or conductive polymers, flexible or rigid substrates, coverlayers, films, etc. These layers are preferably subst~nti~lly non-deformable so that they will abut the particles but will not subst~nti~lly deform or compress at their point of abutment with the particles, to thereby fix their relative separations in the assembly.
For example, one pler~ ,d embodiment of the invention, printed circuit assembly 10 shown in Figs. 1-3, utilizes gauge particles which are sized to abutopposing in~ ting ~,ub~kdles. With conductive layers mounted to the substrates, the separation bt;lweell the conductive layers is also controlled, which may be i~lyolLant for impefl~nf~e control, as well as form m~int~ining planarity throughout the assembly. Assembly 10 generally includes a pair of printed circuit boards 20, 30 joined by an adhesive layer 40. Also shown are a plurality of through holes 12 joining the opposing conductive layers on each circuit board, as well as an integrated circuit chip 14, which is one of i.~ able types of electronic devicesthat may be populated on assembly 10.
As shown in Fig. 2, printed circuit board 20 includes an incnl~ting substrate 22 with opposing conductive layers 24 and 26. Similarly, printed circuit board 30 includes an in~ tinp; substrate 32 with opposing conductive layers 34, 36.
Tn~ ting substrates 22, 32 may be any type of flexible or rigid dielectric material suitable for use as a substrate, including polyimide, polyester, PEN, polyetherimide, epoxy, ceramic, hll~re~llated woven or non-woven glass, among others. Conductive layers 24, 26, 34, 36 are preferably deposited and p~tt~ 1 on substrates 22 and 32 in any manner generally ~nown in the art, inc~l~ltlin~ various additive, semi-additive or subtractive techniques. Deposition of the conductive layers may be performed via adhesiveless ~l~,cesses such as vacuum m~t~lli7.~tion, s~ulLt;lillg, ion plating, chemical vapor deposition, electroplating, electroless plating, etc., as well as through the use of adhesives. The conductive layers may be formed of single metal layers or composite layers formed by different processes, and may include metals such as copper, gold, Ch~ iulll, 5.1l....;,.l.,." pz~ lm,tin, etc., as well as conductive polymers and the like.
In the ~ f~r~d embodiment, ~ub~LIdLes 22, 32 are formed of polyimide, and conductive layers 24, 26, 34, 36 are formed via the NOVACLAD~9 process, which is the subject matter of U.S. Patent Nos. 5,112,462; 5,137,791 and 5,364,707 to Swisher, and zlc~Tgne/1 to Shto~ hl~ Inc. This process generally CA 0224l446 l998-06-2 W O 97/25844 PCT~US97/0017 includes the steps of ( l) treating the substrate with a plasma made up of ionized oxygen produced from a m~tz-llic electrode to form a metal/oxide treated film and (2) forrning mPt~lli7~t1 interconnection layers on the treated film, preferably either by vacuum mt~t~lli7~tion of metal, or by combination of vacuum m.-$~11i7:~tion of metal and an additional step of electroplating metal on top of the vacuum-deposited metal. The first step in the process produces a bonding surface on the film which is capable of sec11ring metal interconnection layers which, unlike adhesive-based substrates, have excellent d.~min~fion resi~t~nl~e, especially when exposed to heat, chemical treatment, mech~nic~1 stress or environmental stress. The board, thus m~t~lli7lo~1, may be etched in a conventional manner to form the desired circuitpatterns in the conductive layers.
Through holes may be formed on printed circuit boards 20, 30 e.g., by drilling vias in the substrate prior to m-ot~lli7~tion such that conductive m~t~ 1 is deposited thereon. In some applications the conductive material deposited on thevia walls may completely fill the vias, such that no a~GllurG remains within thethrough hole. Coverlayers may also be deposited over the p~tt~rn~l conductive layers in some applications. Other variations, e.g., drilling after plating, will be app~Gnl to one of ordinary skill in the art.
As shown in Fig. 2, an adhesive layer 40 is preferably interposed between boards 20, 30. Layer 40 preferably is a dried and cured B-stage layer formed of a plurality of non-conductive gauge particles 44 in~Gl~el~ed in a non-conductive adhesive 42. ~lt~rnsltively, the layer may be deposited on one of the printed circuit boards via screen printing, roll coating or another suitable process.
The adhesive 42 used in layer 40 is ~lGrGlably a non-conductive thermosetting adhesive such as polyimide, epoxy, butyrl ph~no1i~, etc. and combinations thereof. Other adhesives such as pressure sensitive and thermoplastic adhesives may also be used in the ~ltenlzltive. The adhesive used should have suitable adhesive and flow characteristics, and may also be selectedbased upon concerns such as dielectric constant and lGIllpGl~lulG resi~t~n~e. The adhesive used in the ~3lcrGllGd embodiment is a polyimide th~ settinp adhesive, which has a dielectric constant of about 4.4 (measured at 1 Mhz under 4.8.3. l .4.
of Mil-P-13949 Std.), and which is also high temperature r~ci~t~nt W O 97~5844 PCTrUS97/00175 The gauge particles are preferably non-compactible spherical particles formed of solid or hollow non-conductive material such as glass, polymer, silica, ceramic, etc. The m:~t~ri~l used for the particles may also be selected based upon a specific ~liel~ctric strength to tailor the adhesive layer to a controlled dielectric constant. In addition, through the use of low dielectric constant particles, theoverall tli~lectrif~ constant of the adhesive layer may be decreased below that of the adhesive itself. The particles may also have diLL~ llL geometries than spherical. In the preferred embodiment, the particles are hollow glass spheres. Using the ~c;felled size and distribution ranges for the particles, this results in an overall dielectric constant for the adhesive layer of about 1.5 to 3 (measured at 1 Mhz under 4.8.3.1.4. of Mil-P-13949 Std.).
The sizes of the particles are preferably controlled to be sllkst~nti~lly the same throughout the adhesive layer, with preferably at least 30 percent of the particles being between about +/- 10 percent of a mean ~ m(~t~r. Moreover~ the loading or distribution of particles in the adhesive is preferably about 30 to 75 percent by volume, although other particle densities may be required in different applications, particularly where the particles are used to define the separations between other types of printed circuit layers. In addition, the final separationdistances, the layouts of the boards, and other considerations may also impact the sizes and distributions of the particles in the adhesive.
In use, the particles are preferably dispersed uniformly throughout the adhesive, then the adhesive is layered, dried and cured to form a B-stage adhesive layer. The layer is then interposed between the printed circuit boards, and the entire assembly is l~min~tt~d under heat and pressure to COlll~l~SS the boards together, as shown in Fig. 3. Under l~min~tion~ the gauge particles are trapped between the circuit boards to abut the opposing in~ ting layers at areas where there are no conductive layers. In areas where one or more conductive layers arepresent, the particles are typically displaced to areas having no conductive layers (i.e., "exposed areas" of the in~nl~ting substrates). In addition, the adhesive flows into the recesses between the boards, and any excess adhesive is squeezed out ofthe sides of the assembly. The extent to which the boards are co"lL.ressed together during l:~min:~tion is d~ l by the ~ ,"~i of the gauge particles, as these particles abut opposing printed circuit layers to define the final layer sep~r~tions for the ~semhly.

CA 0224l446 l998-06-2~
W O 97/25844 PCT~US97/00175 -~3-As noted above, the mean diameter for the population of particles is preferably selected to provide controlled separation between printed circuit layers.
For example, for the embodiment shown in Figs. 1-3, the ~ m~ter of the particlesd is pl~r~lc.bly selected to control the connected ~ tsm~e x between in~uT~tinp substrates 22 and 32 (best seen in Fig. 3). By virtue of the substantially nondeformable nature of sl-bstr~t~s 22, 32, controlling the ~ t:~n~e between these layers also indirectly controls the rli~t:~n~ey b~;lweell the conductive layers 26, 36.
In many controlled impe~l~n~e appli~ti~)n~, it may be desirable to include relatively constant separations b~lw~ the conductive layers in each layer of a multilayer assembly. For exarnple, for printed circuit assembly 10, it may be desirable to set the ~ t~n~ey between conductive layers across the a&esive layerto equal the distance z between conductive layers across the in~ tin~ substrates.
For a typical assembly, e.g., including S0 micron polyimide substrates patternedwith 15 micron copper layers, the mean diameter of the gauge particles would need to be 80 microns to provide a S0 micron separation between conductive layers across the a&esive layer. It may also be desirable to match the dielectric constant of the adhesive layer with that of the insulating ~ub~lldles.
As stated above, however, the gauge particles are not limited to abutting opposing in~ ting substrates. For example, Fig. 4 illustrates an assembly S0 having an a&esive layer 80 (having gauge particles 84 disposed in an a&esive 82)for bonding together a pair of printed circuit boards 60, 70, with in~ ting substrates 62, 72 and conductive layers 64, 66, 74. In this embodiment, the plurality of gauge particles 84 abut, on printed circuit board 60, the insulating substrate 62; and on printed circuit board 70, the conductive layer 74. Again, the diameters d of the particles are controlled to indirectly set the fli~t~ncey bGlwee the conductive layers 66, 74, as well as the ~ t~n~e x between the in~nl~ting substrates 62, 72. During l~min~ti~n, the particles are displaced from any areashaving two layers of overlapping conductive m:~t~ori~l The configuration shown in Fig. 4 may be useful in applications having ground, power or shield planes whereconductive m~t~ri~l fully covers a surface of at least one printed circuit board.
As another example, Fig. 5 illustrates an assembly 100 having an adhesive layer 130 (having gauge particles 134 disposed in an adhesive 132) for bonding together a pair of printed circuit boards 110, 120, with incnl~ting substrates 112, 122 and conductive layers 114, 116, 124. In this configuration, the ~ ters d of W O 97/25844 PCT~US97tOO175 the particles are controlled to directly set the r1ict~nc~ey between the conductive layers 114, 124, as well as to indirectly set the ~1ict~nrex between the insulating substrates 112, 122. Any particles disposed in areas without any overlapping conductive material tend to "float" within the a&esive and not control layer separation. In addition, due to the non-conductive nature of the particles, they do not conduct across the adhesive layer and cause any potential undesired short circuits in the assembly. Consequently, a ~i~nific:~nt advantage is ~tt~in~l, in that controlled mechanical separation is provided between conductive layers without introducing undesired conductive paths through the adhesive layer. Moreover, coverlayers are often not required, thereby re-lucing m~nl-fArtnring costs and complexities, as well as overall assembly thicknesses.
Other printed circuit layers may abut the gauge particles, inclll-ling any coverlayers formed over the conductive layers on a circuit board. Additional printed circuit boards may also be bonded together using :~Miti~n~l adhesive layers, e.g., to produce multilayer assemblies having five or more conductive layers. Inaddition, a ~ ctric mAt~ri~l may be "filled in" between circuit traces to provide a more planar surface for the printed circuit boards, whereby the gauge particles would abut two types of layers on the same printed circuit board.
Further, it may be desirable to utilize otherwise open areas of the in~ ting substrates ("non-signal ~ x,~ ;"g areas" that is, those areas where conduetive m:lt~ri~l would otherwise not be used) to pattern conductive mz~tt~ris~l which assists in eontrolling separation in these areas. The conductive m~t~ri~l in these non-signal i I .g areas may serve no other purpose than controlling sep~r~ti~ , or it may be used as shielding or other purposes, for example.
Moreover, dirrt;~ particle sizes may be used in different areas of an assembly, e.g., if a ground or shield plane is only provided in one area of an assembly, and the particles and/or adhesive may be used in only some overlappingportions of the circuit boards. In addition, other manners of depositing an adhesive layer and col~ cssillg the assembly may also be used. Other modifications will be t to one skilled in the art.
The plcrcllcd adhesive layers may also include pad interconn~cting means for Pl~tri~lly connecting any contact pads on the printed circuit boards at diserete W O 97~5844 PCTrUS97/00175 locations across t'ne adhesive layers. Any number of manners may be used to formconductive areas through an adhesive layer.
One preferred manner is to form deformable and/or fusible conductive "plugs" in an adnesive layer prior to l~n~in~tion. For example, printed circuit assembly 140 of Figs. 6 and 7 illustrates one marmer of forming pad connections wll~l~y an ape luie 175 is formed in an a&esive layer 170 (having gauge particles 174 in an adhesive 172) and f~ed with conductive m~t~riAl 176. The resllltinp layer is interposed between a pair of printed circuit boards 150, 160 (with ~ub~.Lldl~s 152, 162 and conductive layers 154, 156, 164, 166), with the conductive material 176 in layer 170 aligned with opposing pads 157 (e.g., formed at a through hole 158) and 167. When the assembly is l~min~t~rl (Fig. 7), conductive m~teri~l 176 preferably fuses with pads 157, 167 to form a reliable inLt;l.;olll~ection thc;l~etween concurrent with the pl~f .omt-nt of particles 174 between substrates 152, 162.
Apertures 175 in layer 170 may be formed by (1rilling, punching, ~ y~ g, laser ablation, etc. Conductive m~t~ri~l 176 may be deposited in the apertures by a llulllbel of processes, including electroplating, screen printing, ink jet printing, etc.
The conductive m~tt~ l may be a metal such as copper, or may be a conductive ink(cured or uncured) or a fusible material such as solder particles. Two preferredmanners include screen printin~ a fusible conductive ink, and ink jet printing fine solder particles.
Other manners of forming interlayer interconnections, e.g., dri~ing and plating through holes after l~min~tion, may also be used without departing from the spirit and scope of the invention.
Therefore, it may be seen that the preferred embodiments of the invention realize controlled separation between printed circuit layers, be they in~ ting .ul~LIalt;;S, conductive layers, other layers, or combinations thereof. The controlled separation benef~ts circuit design in controlled impedance applications, since the impecl~nces across the adhesive layers may be reliably ~iet~min~ ~ Moreover, theplanarity of the resulting assemblies is i~ r~v~d, which is particularly ~-ly?OlL~ll as the number of layers in an assembly increases since planarity errors are additive as the llullioer of layers increases. This has the added advantage of . . .~
relatively con~.L~-L elevations of mounting pads on ext~n~l surfaces of an assembly CA 02241446 1998-06-2~
W O 97/25844 PCT~US97/00175 to which electronic devices such as integrated circuits are ~tt~Ch.or1 Other modifications may be made to tnese ~I~;r~ d embodirnents without departing from the spirit and scope of the invention.

,~lternatç Interlayer Iule;~olmection As noted above, a second aspect of the invention is directed to forrning an interlayer interconnection between opposing conductive layers in a printed circuit assembly, in particular by forming conductive "posts" or similar structures on one of the printed circuit boards which are bonded with a pad on the other printed circuit board. This second aspect of the invention is particularly suitable for use in conjunction with providing controlled separation using an adhesive layer in the manner disclosed herein. However, it will be appreciated that this interlayer interconnection process may also be used across other dielectric layers, as will be set forth below.
For example, printed circuit assembly 180 of Figs. 8 and 9 illustrates a manner of forming interlayer pad connections whereby a first printed circuit board 200, with a pair of conductive layers 204,206 formed on an incnl~ting substrate 202, has a conductive post forrned on a contact pad 207. The post is comprised of a copper layer 208 coated by a fusible m~t~ri:ll 209 such as tin. The copper and tin are preferably deposited by electroplating using a serni-additive process, although other processes, including subtractive and additive metal deposition processes, screen printing processes, stencil printing processes (e.g., stenciling conductive ink coupled with subsequent curinglsintering of the ink), etc. may also be used.Other conductive ms~t--,ri~l~ such as any number of binary and tertiary metals, fusible mz-t-o,ri~l.c, and combinations thereof may be used for layer 208.
With one ~ ;d process, a layer of dry film photoresist is applied over a copper foil printed circuit board, then the photoresist is imaged with the desired circuit pattern and developed, and copper is electroplated through the r~s-llting mask to form the desired circuit pattern. Next, a second layer of photoresist isapplied over the first layer and is exposed and developed with the pattern of the conductive posts to be forrned on the printed circuit. The posts are electroplated to thickness with copper, then capped by an electrodeposited layer of tin. The photoresist is stripped off and the excess copper is etched away.

CA 02241446 1998-06-2~
W O 97/25844 PCT~US97/00175 The thicknPs~ to which copper layer 208 on each post is plated is primarily dependent upon the desired connected ~ t~n~e between the opposing contact pads, and when used in conjunction with gauge particle-filled adhesive, is dependent upon the diameters of the particles. For example, it may be desirable to providec--nn~cte~ t:~n~-es between pads in the range of about 1 to 4 mils (50 to 100 microns), with the thickn~.c~ of copper layer 208 preferably being in a similar range. Tin layer 209 is preferably immersion, electroless or electroplated to a thickness selected to provide sufficient m~t~ri~l for forming a fused cormectionbetween copper layer 208 and the opposing contact pad, pl~r~;l~ly in the range of about 8 to 50 microinches.
The posts can also have different profiles, e.g., circular, rectangular, etc.
Moreover, the m;.xi.~ . width or ~ m~tt~r of the posts may be selected dependingupon resistance re~luh~lllellL~ current h:~n~lling capability, and contact pad size, typically in the range of about 50 to 100 rnicrons. The posts, however, typically do not require any additional surface area on a board beyond the contact pads towhich they are mounted, and they are preferably about 1/2 the ~ mPte.r of the contact pads to allow for some mi~lignm~nt Accordingly, in preferred embo-lim~nt~, the posts generally do not signific~ntly impact the overall pitch (i.e., the ...i ..i ..., ., ., combined signal trace spacing and width) of the board.
Printed circuit board 200 is preferably hllelc. ~n~ct~-l via l~min~tinn to a second board 190 (with conductive layers 194, 196 formed on a substrate 192) across an adhesive layer 210 (with gauge particles 214 in an adhesive 212). Prior to l~min~tion, it may be desirable to deposit, e.g., by i.. ~l iion, electroless or electroplating, an a&esion promoting layer 199 over the contact pads, e.g., pad 197. Layer 199 may be, for example, about 8 to 50 microinches in thickness, and formed of gold or a similar m~t~ri~l that promotes adhesion with a fi~sible metal such as tin layer 209. The adhesion promoting layer may also not be nece~s~ry insome applications.
,~ During l~min~tion (Fig. 9), the post formed of layers 208, 209 may "pierce" through layer 210 and contact pad 197 (shown at through hole 198) formed on board 190. Fusible layer 209 preferably reflows and fuses to the gold layer 199 over pad 197 to form a reliable electrical illLel~o~ ect with pad 207. Due to the high unit load of the posts, they will generally displace the adhesive to perrnit the fusible layers to fully contact the opposing pads and form the fused connections CA 02241446 l99X-06-25 W O 97~584~ PCT~US97/00175 --t 8--therebetween. Also due to their high unit load, the posts also displace the gauge particles during the l~min~tion process as shown in Fig. 9. With further compression, the gauge particles in the adhesive layer begin to share a portion of the applied, resultin~ in both controlled separation and reliable interconnects in the finished assembly.
Al~rn~tively, as above with other interlayer i~Lel~o~ ections, a~el~u,cs may be driIled or formed in adhesive layer 210 with the apelLulcs aligned with the posts, as opposed to the posts forming their own apertures.
As was mentioned previously, the post interlayer interconnection technology disclosed herein may also be used to form interconn~ ctiQIlc across other dielectric layers. For example, as shown in the assembly 220 of Fig. 10, a pair of printed circuit boards 230 and 240 may be h.tt;,c~ ected across a dielectric layer 250 with a post having copper layer 244 and fusibIe m~tt-ri~l 246, formed on board 240, and fused to board 230. Dielectric layer 250 preferably includes an aligneda~elL~LIc 256 through which the post may project.
Numerous dielectric layer constructions may be used to bond boards 230 and 240 together. For example, as shown in Fig. 10, dielectric layer 250 may include a base dielectric film 252 coated on both sides with an adhesive 254.
Al~ern~tively, the ~liel~ctric film may be a prepreg composition of woven gIass impregnated with adhesives. Other dielectric layers, such as non-woven glass andfilm tapes, etc., or any other form of ~lieJectric layer suitable for bonding opposing boards to one another may also be used.
It is also possible to utilize a dielectric layer having a base fiIrn or sheet with a preflPtt~rmin~l grid or pattern of a~c;,lulcs at known locations. Through proper circuit design, posts may be located to be aligned with a~ell-ncs, thereby çli " ~ g the need to specially drill a ~lielectric Iayer.
It is believed that the use of i,llelco~ ecting posts in the manner disclosed herein provides reliable interlayer interconnects in a simple, reliable and costeffective manner. Moreover, the posts may be constructed with fine ~lim~n~ions and spacing, thereby increasing the obtainable p~c~ing density for a printed circuit assembly. In addition, the posts are capable of forming int.~ t~llic joints, which are typically much more reliabIe than a&esive joints due to the mtot~ rgicaI

W O 97/25844 PCT~US97/00175 interaction of such joints. The posts also have the benefit of being deposited using standard photolithographic techniques at generally the same resolution of the overall circuit patterns, and they also reduce material costs because discrete conductive hllelco~ ections may be made only at desired locations on the boards.Further, the posts may be made smaller than the contact pads to which they are c~-nn~ctçcl, thereby allowing for some mi~li nm~nt of the pads during l~min~ti~,n.
Other benefits will be appreciated by one skilled in the art.
Other changes and modifications may be made to the pl~felled embodiments without departing from the spirit and scope of the invention.
Therefore, the invention lies in the claims hereinafter appended.

Claims

What is claimed is:

1. A printed circuit assembly, comprising:
(a) first and second printed circuit boards, each printed circuit board including an insulating substrate with a conductive layer disposed thereon, the conductive layer on the first printed circuit board including a first contact pad opposing a second contact pad on the conductive layer on the second printed circuit board, and at least one of the first and second printed circuit boards including a second conductive layer formed on the opposite surface of the insulating substrate;
(b) a dielectric layer disposed between the first and second printed circuit boards; and (c) a conductive post, formed on the first contact pad, the conductive post extending across the dielectric layer and abutting the second contact pad, thereby electrically connecting the first and second contact pads.

2. The printed circuit assembly of claim 1, wherein the dielectric layer comprises an adhesive for bonding the first and second printed circuit boards toone another.

3. The printed circuit assembly of claim 2, wherein the dielectric layer further includes a dielectric film coated on both sides with the adhesive and including an aperture through which extends the conductive post.

4. The printed circuit assembly of claim 2, wherein the dielectric layer further includes a prepreg sheet filled with the adhesive and including an aperture through which extends the conductive post.

5. The printed circuit assembly of claim 2, wherein the dielectric layer includes a grid of apertures, and wherein the conductive post is aligned with one of the apertures in the grid of apertures.

6. The printed circuit assembly of claim 1, wherein the conductive post has a width which is smaller than the widths of the first and second contact pads.

7. The printed circuit assembly of claim 1, wherein the conductive post comprises a first metal layer formed on the first contact pad and a second metal layer formed on the first metal layer, the second metal layer comprising a fusible metal that is fused with the second contact pad.

8. The printed circuit assembly of claim 7, wherein the first metal layer comprises copper and the second metal layer comprises tin.

9. The printed circuit assembly of claim 7, wherein the second contact pad comprises an adhesion promoting layer deposited thereon and fused with the second metal layer on the conductive post.

10. The printed circuit assembly of claim 9, wherein the adhesion promoting layer comprises gold deposited to a thickness in the range of about 8 to 50 microinches.

11. A method of manufacturing a printed circuit assembly, comprising the steps of:
(a) forming a conductive post on a first printed circuit board, the printed circuit board including an insulating substrate with a conductive layer disposed thereon, wherein the conductive post is disposed on a first contact paddisposed in the conductive layer of the first printed circuit board;
(b) placing a second printed circuit board over the first printed circuit board with a second contact pad aligned with the conductive post and with a dielectric layer disposed therebetween, the second printed circuit board including an insulating substrate with a conductive layer disposed thereon, wherein the second contact pad is disposed in the conductive layer of the second printed circuit board, and wherein at least one of the first and second printed circuit boards includes a second conductive layer formed on the opposite surface of the insulating substrate;
and (c) compressing the first and second printed circuit boards together until the conductive post extends across the dielectric layer and abuts the second contact pad, thereby electrically connecting the first and second contactpads.

12. The method of claim 11, wherein the dielectric layer comprises an adhesive, and wherein the compressing step includes the step of mechanically bonding the first and second printed circuit boards to one another with the adhesive.

13. The method of claim 12, wherein the dielectric layer further includes a dielectric film coated on both sides with the adhesive and including an aperture through which extends the conductive post.

14. The method of claim 12, wherein the dielectric layer further includes a prepreg sheet filled with the adhesive and including an aperture through whichextends the conductive post.

15. The method of claim 12, wherein the dielectric layer includes a grid of apertures, and wherein the conductive post is aligned with one of the apertures in the grid of apertures.

16. The method of claim 11, wherein the conductive post has a width which is smaller than the widths of the first and second contact pads.

17. The method of claim 11, wherein the forming step includes the steps of depositing a first metal layer on the first contact pad, and depositing a second, fusible metal layer over the first metal layer, and wherein the compressing stepincludes the step of applying heat to fuse the second metal layer to the second contact pad.

18. The method of claim 17, wherein the forming step includes the step of photoimaging a resist mask, and wherein the first and second metal layers aredeposited via electroplating through the resist mask.

19. The method of claim 17, further comprising the step of depositing an adhesion promoting layer on the second contact pad, and wherein the compressing step fuses the adhesion promoting layer with the second metal layer on the conductive post.

20. The printed circuit assembly of claim 1, wherein the conductive post comprises a first layer formed on the first contact pad and a second layer formed on the first layer, the second layer comprising a fusible material that is fused with the second contact pad.

21. The printed assembly of claim 20, wherein the fusible material comprises a conductive ink.

22. The method of claim 11, wherein the forming step includes the steps of depositing a first layer on the first contact pad, and depositing a second, fusible material over the first layer, and wherein the compressing step includes the step of applying heat to fuse the second layer to the second contact pad.

23. The method of claim 22, wherein in the step of depositing a second, fusible material, the fusible material comprises a conductive ink.