CA2265692A1 - Multiple network protocol encoder/decoder and data processor - Google Patents

Multiple network protocol encoder/decoder and data processor

Info

Publication number
CA2265692A1
CA2265692A1 CA002265692A CA2265692A CA2265692A1 CA 2265692 A1 CA2265692 A1 CA 2265692A1 CA 002265692 A CA002265692 A CA 002265692A CA 2265692 A CA2265692 A CA 2265692A CA 2265692 A1 CA2265692 A1 CA 2265692A1
Authority
CA
Canada
Prior art keywords
data
state machine
network
protocol
network protocol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002265692A
Other languages
French (fr)
Other versions
CA2265692C (en
Inventor
John Shigeto Minami
Ryo Koyama
Michael Ward Johnson
Masaru Shinohara
Thomas C. Poff
Daniel F. Burkes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia Corp
Original Assignee
Iready Corporation
John Shigeto Minami
Ryo Koyama
Michael Ward Johnson
Masaru Shinohara
Thomas C. Poff
Daniel F. Burkes
Nvidia Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iready Corporation, John Shigeto Minami, Ryo Koyama, Michael Ward Johnson, Masaru Shinohara, Thomas C. Poff, Daniel F. Burkes, Nvidia Corporation filed Critical Iready Corporation
Publication of CA2265692A1 publication Critical patent/CA2265692A1/en
Application granted granted Critical
Publication of CA2265692C publication Critical patent/CA2265692C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6225—Fixed service order, e.g. Round Robin
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/623—Weighted service order
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/325—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the network layer [OSI layer 3], e.g. X.25
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level

Abstract

A multiple network protocol encoder/decoder comprising a network protocol layer (101), data handler (102), O.S. State machine (104), and memory manager (103) state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine (101) which decodes network protocols such as TCP, IP, user Data Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler (102) which consists of data state machines (104) that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML). Each data state machine (104) reacts accordingly to the pertinent data, and any data that are required by more than one data state machine (104) is provided to each state machine concurrently, and any data required more than once by a specific data state machine, are placed in a specific memory location (206) with a pointer designating such data; thereby ensuring minimal memory usage.
Resulting display data are immediately passed to a display controller (205).
Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.
CA002265692A 1996-10-31 1997-09-26 Multiple network protocol encoder/decoder and data processor Expired - Fee Related CA2265692C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/742,085 US6034963A (en) 1996-10-31 1996-10-31 Multiple network protocol encoder/decoder and data processor
US08/742,085 1996-10-31
PCT/US1997/017257 WO1998019412A1 (en) 1996-10-31 1997-09-26 Multiple network protocol encoder/decoder and data processor

Publications (2)

Publication Number Publication Date
CA2265692A1 true CA2265692A1 (en) 1998-05-07
CA2265692C CA2265692C (en) 2001-08-07

Family

ID=24983424

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002265692A Expired - Fee Related CA2265692C (en) 1996-10-31 1997-09-26 Multiple network protocol encoder/decoder and data processor

Country Status (8)

Country Link
US (1) US6034963A (en)
EP (1) EP0935855B1 (en)
JP (2) JP3938599B2 (en)
CN (1) CN1154268C (en)
AU (1) AU723724B2 (en)
CA (1) CA2265692C (en)
DE (1) DE69739159D1 (en)
WO (1) WO1998019412A1 (en)

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