CA2265692C - Multiple network protocol encoder/decoder and data processor - Google Patents
Multiple network protocol encoder/decoder and data processor Download PDFInfo
- Publication number
- CA2265692C CA2265692C CA002265692A CA2265692A CA2265692C CA 2265692 C CA2265692 C CA 2265692C CA 002265692 A CA002265692 A CA 002265692A CA 2265692 A CA2265692 A CA 2265692A CA 2265692 C CA2265692 C CA 2265692C
- Authority
- CA
- Canada
- Prior art keywords
- data
- network
- memory
- state machine
- protocol
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012546 transfer Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 37
- 230000008569 process Effects 0.000 claims description 36
- 238000012545 processing Methods 0.000 claims description 23
- 238000004891 communication Methods 0.000 claims description 8
- 230000005540 biological transmission Effects 0.000 claims description 4
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
- 238000012163 sequencing technique Methods 0.000 claims 2
- 230000007246 mechanism Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 101001094649 Homo sapiens Popeye domain-containing protein 3 Proteins 0.000 description 3
- 101000608234 Homo sapiens Pyrin domain-containing protein 5 Proteins 0.000 description 3
- 101000578693 Homo sapiens Target of rapamycin complex subunit LST8 Proteins 0.000 description 3
- 102100027802 Target of rapamycin complex subunit LST8 Human genes 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000000872 buffer Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001485 positron annihilation lifetime spectroscopy Methods 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/12—Protocol engines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/622—Queue service order
- H04L47/6225—Fixed service order, e.g. Round Robin
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/622—Queue service order
- H04L47/623—Weighted service order
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
- H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/325—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the network layer [OSI layer 3], e.g. X.25
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
Abstract
A multiple network protocol encoder/decoder comprising a network protocol layer (101), data handler (102), O.S. State machine (104), and memory manager (103) state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine (101) which decodes network protocols such as TCP, IP, user Data Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler (102) which consists of data state machines (104) that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML). Each data state machine (104) reacts accordingly to the pertinent data, and any data that are required by more than one data state machine (104) is provided to each state machine concurrently, and any data required more than once by a specific data state machine, are placed in a specific memory location (206) with a pointer designating such data; thereby ensuring minimal memory usage.
Resulting display data are immediately passed to a display controller (205).
Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.
Resulting display data are immediately passed to a display controller (205).
Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.
Description
W0 98/ 19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/US97/17257
MULTIPLE NETWORK PROTOCOL ENCODER/DECODER
AND DATA PROCESSOR
BACKGROUND OF THE INVENTION
TECHNICAL FIELD
The invention relates to network protocols and data packets. More particularly, the
invention relates to the decoding of network protocols and processing of packet
data during packet reception without the time-consuming overhead of software or
software/hardware implementations. In addition, the invention allows one pass
parsing of the data, eliminating the buffering of data packets for different stacks,
and thus minimizing the memory usage.
DESCRIPTION OF THE PRIOR ART
Computer networks necessitate the provision of various communication protocols
to transmit and receive data. Typically, a computer network comprises a system of
devices such as computers, printers and other computer peripherals,
communicatively connected together. Data are transferred between each of these
devices through data packets which are communicated through the network using
a communication protocol standard. Many different protocol standards are in
current use today. Examples of popular protocols are Internet Protocol (IP),
lnternetwork Packet Exchange (IPX), Sequenced Packet Exchange (SPX),
Transmission Control Protocol (TCP), and Point to Point Protocol (PPP). Each
network device contains a combination of hardware and software that translates
protocols and process data.
An example is a computer attached to a Local Area Network (LAN) system,
wherein a network device uses hardware to handle the Link Layer protocol, and
software to handle the Network, Transport, and Communication Protocols and
W0 98/19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/US97l17257
information data handling. The network device normally implements the one Link
Layer protocol in hardware, limiting the attached computer to only that particular
LAN protocol. The higher protocols, e.g. Network, Transport, and Communication
protocols, along with the Data handlers, are implemented as software programs
which process the data once they are passed through the network device
hardware into system memory. The advantage to this implementation is that it
allows a general purpose device such as the computer to be used in many
different network setups and support any arbitrary network application that may be
needed. The result of this implementation, however, is that the system requires a
high processor overhead, a large amount of system memory, complicated
configuration setup on the part of the computer user to coordinate the different
software protocol and data handlers communicating to the computer's Operating
System (O.S.) and computer and network hardware.
This high overhead required in processing time is demonstrated in U.S. Pat. No.
5,485,460 issued to Schrier et al on 16 January 1996, which teaches a method of
operating multiple software protocol stacks implementing the same protocol on a
device. This type of implementation is used in Disk Operating System (DOS)
based machines running Microsoft Windows. During normal operation, once the
hardware verifies the transport or link layer protocol, the resulting data packet is
sent to a software layer which determines the packets frame format and strips any
specific frame headers. The packet is then sent to different protocol stacks where
it is evaluated for the specific protocol. However, the packet may be sent to
several protocols stacks before it is accepted or rejected. The time lag created by
software protocol stacks prevent audio and video transmissions to be processed
in real-time; the data must be buffered before playback. It is evident that the
amount of processing overhead required to process a protocol is very high and
extremely cumbersome and lends itself to applications with a powerful Central
Processing Unit (CPU) and a large amount of memory.
Consumer products that do not fit in the traditional models of a network device are
entering the market. A few examples of these products are pagers, cellular
W0 98/19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/US97/1 7257
phones, game machines, smart telephones, and televisions. Most of these
products have small footprints, 8-bit controllers, limited memory or require a very
limited form factor. Consumer products such as these are simplistic and require
low cost and low power consumption. The previously mentioned protocol
implementations require too much hardware and processor power to meet these
requirements. The complexity of such implementations are difficult to incorporate
into consumer products in a cost effective way. If network access can be simplified
such that it may be easily manufactured on a low-cost, low-power, and small
form-factor device, these products can access network services, such as the
Internet.
SUMMARY OF THE INVENTION
The invention provides a low-cost, low-power, easily manufacturable, small
form-factor network access module which has a low memory demand and
provides a highly efficient protocol decode. The invention comprises a
hardware-integrated system that both decodes multiple network protocols in a
byte-streaming manner concurrently and processes packet data in one pass,
thereby reducing system memory and form factor requirements, while also
eliminating software CPU overhead.
The preferred embodiment of the invention comprises a network protocol layer,
data handler, O.S. State Machine, and memory manager state machines
implemented at a hardware gate level. Network packets are received from a
physical transport level mechanism by the network protocol layer state machine.
The protocol state machine decodes network protocols such as TCP, lP, User
Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is
received. Each protocol handler parses, interprets, and strips header information
immediately from the packet, requiring no intermediate memory. The resulting
data are passed to the next protocol layer or data handler for which the latter case
consists of data state machines that decode data formats such as email, graphics,
Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language
W0 98/19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/US97/17257
(HTML). Each data state machine reacts accordingly to the pertinent data, and
any data that are required by more than one data state machine are provided to
each state machine concurrently. Any data that are required more than once by a
specific data state machine, are placed in a specific memory location with a
pointer designating such data (thereby ensuring minimal memory usage).
Resulting display data are immediately passed preformatted to a display
controller. Any outgoing network packets are created by the data state machines
and passed through the network protocol state machine which adds formats to the
packet, and checksums the information header information, and forwards the
resulting network packet via a physical transport level mechanism.
The preferred embodiment does not necessarily require a CPU and software to
process the network packets, thereby greatly reducing system cost. The hardware
gate level implementation provides a modular, embeddable design whereupon
the designer may pick and choose the functionality that the particular application
requires and still retain a low cost, low power, small form factor.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a high-level data flow diagram of the core system according to the
invenï¬on;
Fig. 2 is a high-level block diagram of a system according to the invention;
Fig. 3 is a functional block diagram of a complete system implementation
according to the invention;
Fig. 3A is a functional block diagram of the UMA memory controller according to
the invention;
Fig. 4 is a time comparison chart illustrating data task time requirements for a
traditional architecture and the invention.
W0 98/19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/U S97! 17257
Fig. 5 illustrates the possible progression of applications according to the
invention;
Fig. 6 illustrates the concept of an Internet Tuner according to the invention;
Fig. 7 illustrates two implementations according to the invention;
Fig. 8 illustrates Network PC implementations according to the invention;
Fig. 9 illustrates Handheld Devices implementations according to the invention;
Fig. 10 illustrates Smart Telephone implementations according to the invention;
Fig. 11 illustrates Smart Television, cable-box, Video Cassette Recorder (VCR),
Digital Video Disc (DVD) and game machine implementations according to the
invention; and
Fig. 12 is a timing diagram sharing a received packet according to the invention;
and
Fig. 13 is a block schematic diagram showing signal flow for the packet of claim 12
according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 1, the invention comprises a Network Protocol Layer 101, a Data
Handler 102, a Memory Control module 103, and an Operating System (O.S.)
State Machine module 104, each implemented at the hardware gate level. The
Network Protocol Layer 101 decodes incoming and encodes outgoing network
packets. The Network Protocol Layer 101 comprises a plurality of state machines
representing different network protocol stacks (i.e. PPP, TCP, IP, UDP, and Raw
W0 98/ 19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/U S97/ 17257
The
implementation of the protocol stacks in gate level logic allows the real time
Socket) which simultaneously decode incoming network packets.
decoding of the network packet as the packet is received, thereby requiring no
temporary memory storage. After all of the packet header information is stripped
out and verified by the state machines, the resulting data is passed to the Data
Handler 102. The Data Handler 102 comprises a plurality of state machines, each
of which process a specific data type (i.e. HTTP, email formats (Post Office
Protocol (POP3), Internet Message Access Protocol (IMAP4), Simple Mail Transfer
Protocol (SMTP)), graphics standards (Joint Photographic Experts Group (JPEG),
Graphics Interchange Format (GlF)), Java, and HTML). The gate level
implementation of the data handlers enable the invention to concurrently process
received data in real time and is especially suitable for applications which handle
streams of data as they are received, i.e. Java, HTML, POP3 email, and audio and
video applications. Any data that are required by more than one data state
machine are provided in a concurrent manner. Any data required more than once
by a specific data state machine are placed in a specific memory location with a
pointer designating them. All memory accesses are arbitrated through the
Memory Control module 103. Any resulting display data are also routed through
the Memory Control module 103. The O.S. State Machine 104, acts as an
arbitrator between all of the state machines for resource control, system, and user
interface. Any user input is interpreted by the O.S. State Machine and routed to
the Data Handler 102.
As an example, a data handler that interprets HTML format could decode the
HTML tags using a Cyclic Redundancy Check (CRC) calculation. HTML format
contains character strings known as tags, which control the formatting of a
subsequent block of text when displayed on a video output device. These tags
may be efficiently decoded by generating a CRC number for a given tag and using
said number to enable a formatting instruction. Such a decoding algorithm is
suited for gate level implementation and provides for an HTML encoded document
to be displayed on a video output device much more quickly than is currently
possible.
WO 98/19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/U S97/ 17257
Although the invention is described as being at the hardware gate level, one
skilled in the art can readily appreciate that these functions may be implemented
in many other ways such as Programmable Array Logic (PALS), General Array
Logic (GALs), Read Only Memory (ROMS), and software. Additionally, specific
protocols and data types have been indicated and one skilled in the art can
readily appreciate that the modularity of the invention does not limit it to those
specific protocols or data types.
Turning to FIG. 2, the invention is represented in a highâlevel block diagram. This
diagram describes the operational task of each module in a full implementation of
the invention. The O.S. State Machine 208, contains the system âg|ue" logic, and
the device control interface, and acts as a âtraffic cop" between the state machines
of the other modules. The Network Protocol Layer 207, contains state machines
for TCP/IP, UDP, Raw Socket, and PPP protocols. The Memory Control module
206 contains the logic for the Unified Memory Architecture (UMA) which allows the
system and video display memory to reside in the same memory area. A Display
Controller 205 provides control of a VGA, television standard, or other type of
display. Four data handlers are used in this implementation. An Email data
handler 201 interprets both POP3 and IMAP4 formats.
implemented which decode JPEG and GIF formats (commerce and telephony
standards may also be decoded). A Java Machine 203 is also included which
Interpreters 202 are
interprets the Java language byte codes. The World-Wide Web (WWW) Browser
204, contains an HTML decoder/accelerator, HTTP Data handler and an
integrated email state machine.
As an example, an incoming JPEG image packet is traced through the system,
assuming a MODEM physical transport. The request starts with the user indicating
a desire to download a given JPEG image by typing on keyboard 321. This input
is interpreted by the keyboard interface 316 and passed to the O.S. State machine
315. O.S. State machine 315 processes the input and passes it as a command to
the HTTP client 311. The HTTP client creates a request packet and passes it via
W0 98/ 19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/US97/17257
the Port Decoder 309 to the TCP Layer 308. The TCP Layer prepends the
appropriate TCP header and passes it to the IP Layer 307. The IP layer then
prepends the appropriate IP header and passes the packet to the PPP Layer 306.
The PPP Layer prepends the appropriate header, appends an FCS, and passes
the data to the Physical Transport interface 305. The Physical Transport Interface
serializes the data into a bit stream and sends the packet to the MODEM unit 304.
When the request is accepted by the host sewer, it sends the requested JPEG
image back to the client system. The data are first received by the MODEM 304
which indicates to the Physical Transport Interface 305 that data are present. The
Physical Transport interface then reads the bit serial data from the MODEM,
converts it to a parallel byte data, and indicates to the PPP Layer 306 that data are
present. The PPP Layer reads in the received bytes. When it detects a valid start
byte, it begins to parse the incoming bytes. When the byte stream reaches the
PPP protocol field, the PPP Layer decodes it, and in this example decodes the
embedded packet as being of type IP. in response to this protocol byte, the PPP
Layer enables the IP Layer 307 and indicates to it that IP data are being received.
All further data bytes received are now passed directly to the IP Layer. The IP
Layer then begins to parse the incoming data bytes. When it comes to the IP
In this
example, the IP Layer decodes the protocol field as being of type TCP. At this
point, the IP Layer enables the TCP Layer 308 and indicates to it when TCP data
are being received. When this indicator goes active, all further data bytes in the
header protocol field, it determines which higher protocol to enable.
received packets are sent to both the IP and TCP Layers (IP Layer needs the data
bytes to complete checksum calculations). The TCP Layer then begins to parse
the incoming data bytes. When it comes to the TCP header destination port field, it
In this example, the PORT field
decodes to the HTTP client 311. At this point, the PORT decoder enables the
HTTP client and indicate to it that HTTP requested data are being" received. The
determines which data handler to enable.
HTTP client then begins to parse received data bytes. When the HTTP client
determines that the packet is of type JPEG image, the HTTP client enables the
JPEG decoder 313. At this point, all data bytes are now routed to the JPEG
decoder. The JPEG decoder then receives all further incoming data bytes and
W0 98/19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/US97/1 7257
processes them accordingly. The resulting decoded image is sent to the display
memory via the Memory Controller 312 to be processed by the Display Controller
324 for output to display device 326.
As also noted in Fig. 3, various layers need access to a shared memory resource.
All memory accesses are arbitrated by a single memory controller. This memory
controller determines which layer or handler has access at any given cycle to the
unified memory buffer. This memory controller is needed due to the fact that all
system and display memory buffers are shared within a single memory buffer unit.
The unified memory controller 312 takes read and write requests from the various
layers, arbitrates the requests based on a dynamic rotating arbitration scheme
with fixed priority weighting. This algorithm is depicted in Fig. 3A. If, in the
pictured configuration, device D2 302A and device D3 303A both request memory
access at the same time, then the arbitor 307A awards the cycle to the device that
has not had the most recent memory access. The arbitor 307A then passes its
memory request to the A input arbitor 309A. If the B input on arbitor 309A is idle,
then the request is passed up to the B input of arbitor 310A. If the A input to the
arbitor 310A is idle, then the request is made to the memory unit. All arbitration
determinations are performed using combinatorial logic, thereby eliminating any
wait states to any device if no other memory requests are being made. Priority
In Fig. 3A,
Device DO 300A and Device D1 301A each have 25% priority weighting meaning
weighting is assigned by configuring the arbitration tree structure.
that if all devices requested constant memory usage, they would each win the
arbitration 25% of the time. Devices D2 302A, D3 303A, D4 304A, and D5 305A
each have 12.5% priority weighting. The memory controller design is simplified by
having each of the individual arbitration units having the same logic structure. In
this scheme, the number of requesting devices, and their priority weighting can
easily be configured by adding and arranging arbitor units.
Turning to FlG. 4, the speed advantages that the invention offers are much higher
than the traditional architecture currently in use. The figure represents the time
needed to complete each task. For a series of packets that require an HTML
W0 98/19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/US97ll 7257
download 401, decode of the HTML 402, JPEG download 403, decode of the
JPEG 404, JAVA download 405, decode of the JAVA bytes 406, and streaming
audio 407, the total time required for these tasks is shown for the traditional
architecture 408 and the invention (iReady architecture) 409. The invention 409 is
significantly faster for these tasks than the traditional architecture 408.
Turning to FIG. 5, the progression of applications for this type of network access is
shown. Presently, the traditional model of the network client is being used,
namely the computer 501. The consumer appliance concepts of the Network PC
502, handheld devices 503, smart telephones 504, set-top appliances 505, and
smart televisions 506 are now becoming a reality. The invention provides these
products with a cost-effective, space, speed, and power conscious network
access.
Referring to FIG. 6, the invention operates much like a television 602 or radio tuner
611 - the signals (packets) are processed immediately without delay and sent to a
display or audio output. The term lnternet Tuner 608 is used to describe the
invention as an analogy to such signal processing devices. The Internet Tuner
608 acts as the interface between the Internet signals 609 and application
products such. as smart televisions 604, set-top appliances 605, smart telephones
606, and handheld devices 607. It processes Internet signals 609 in real-time as
do television 602 and radio tuners 611.
FIG. 7 illustrates that a full implementation of the invention using the O.S. State
Machine 701, Network Protocol Layer 702, Memory Control 703, Display
Controller 704, email data handler 708, Interpreters 707, Java Machine 706, and
WWW Browser 705 may be separated into two separate modules. The modularity
of the invention allows functions such as the data handlers 713 (email data
handler 717, Interpreters 716, Java Machine 715, and WWW Browser 714) to be
separated and placed into a high-level ROM code for certain applications.
10
W0 98/19412
âIO
15
20
25
30
CA 02265692 l999-03- l2
PCT/US97/17257
The following application examples further illustrate the versatility of the modular
design of the invention.
FIG. 8 demonstrates the possible configurations of the invention for a Network PC.
One variation includes the O.S. State Machine 801, Network Protocol Layer 802,
Memory Control 803, Display Controller 804, email data handler 808, interpreters
807, Java Machine 806, and the WWW Browser 805. This can be varied by
placing the data handlers for email 817, Interpreters 816, Java Machine 815, and
WWW Browser 814 code into high-level ROM running on a microprocessor 813.
The microprocessor 813 communicates through the O.S. State Machine 809 for
network and display functions. A third variation allows a microprocessor 822
running off of a 3rd Party ROM 823 to interpret the data coming from the Network
Protocol Layer 819 and O.S. State Machine 818. The microprocessor 822
displays data through the Display Controller 821.
Turning to FIG. 9, a handheld device may use only the Network Protocol Layer
901 and interface it to a custom Transport Mechanism 902 and Existing
Microcontroller 904. Email functions may be added by including the email data
handler 905 in the configuration. Further demonstrating the modularity of the
invention, the Network Protocol Layer 911 and Java Machine 910 may be added
to a handheld device, thereby allowing it to process Java applets.
Referring to FIG. 10, smart telephones may add email capabilities by
implementing the O.S. State Machine 1001, Network Protocol Layer 1002,
Memory Control 1003, email data handler 1006, and Display Controller 1004.
The Display Controller 1004 is capable of controlling Light Emitting Diode (LED),
Liquid Crystal Display (LCD) displays, or big-mapped displays. A Physical
Transport Control 1005 may optionally be added, depending on the connectivity
requirements of the smart telephone. The O.S. State Machine 1007, Network
Protocol Layer 1008, and Memory Controller 1009 may be added to smart
telephones with an existing microcontroller 1010. The microcontroller 1010
performs email functions using a 3rd Party email client code 1011.
11
W0 98/ 19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/US97/17257
Turning finally to FIG. 11, smart televisions, cable-boxes, Video Cassette
Recorders (VCRs), Digital Video Disc (DVD) players, and game machines can
take advantage of the network accessibility offered by the invention. The O.S.
State Machine 1102, Network Protocol Layer 1103, Memory Controller 1104,
WWW Browser 1107, Java Machine 1106, and (optionally) the Display Controller
1105 are interfaced to an existing controller 1101. if a controller 1101 is not
present, the Display Controller 1105 is used. Email 1115 functions are easily
added due to the modularity of the invention. As noted previously, the data
handlers for email 1124, Interpreters 1123, Java Machine 1122, and WWW
Browser 1121 code are optionally placed into high level ROM running on a
microprocessor 1120. The microprocessor 1120 communicates through the 0.3
State Machine 1116 for network and display functions.
Example of Packet Reception
Fig. 12 depicts a received network packet. The packet contains the following
items as shown from left to right:
- PPP header
- IP header
- TCP header
- JPEG Data
- PPP FCS (Field Checksum)
The line labeled PPP LAYER ENABLE is activated when a valid start byte is
detected, and is generated within the PPP block in Fig. 13. Once this line goes
high, the rest of the PPP block is activated. Within the PPP header is a field
indicating the type of protocol that the PPP packet is encapsulating. In an
uncompressed PPP header, these are bytes 4 and 5 (counting the start byte
Ox7e). In Fig. 12, these bytes are 0x00 and 0x21 indicating that the encapsulated
data is an IP packet. After decoding this field, the PPP block activates the IP
12
W0 98/ 19412
10
15
20
25
30
CA 02265692 l999-03- l2
PCT/U S97/ 17257
LAYER ENABLE and PPP DATA FIELD signals, which together enable the IP
block in Fig. 13. The IP LAYER ENABLE line is decoded from the PPP protocol
field, and the PPP DATA FIELD line indicates that the incoming data byte stream is
in the data field portion of the network packet. These two lines must be active for
the IP block to be enabled. Once the IP block is enabled, it starts to parse the
incoming data bytes. Referring back to Fig. 12, the data immediately following the
PPP header is the IP header. Within the IP header is a field indicating the type of
data that is encapsulated within the IP packet. In Fig. 12, this field is shown to be
0x06 indicating that the encapsulated data is a TCP packet. The TCP LAYER
ENABLE line is activated in response to the IP block decoding this field. The IP
DATA FIELD line goes active a couple of bytes later, because there are some
bytes that come between the IP header protocol field and the start of the IP data
field. The IP DATA FIELD signal indicates that the incoming data byte stream is in
the data field portion of the network packet. Both the TCP LAYER ENABLE and IP
DATA FIELD lines must be active in order for the TCP block in Fig. 13 to be
enabled. Once the TCP block is enabled, it starts to parse incoming data bytes.
Referring back to Fig. 12, the data immediately following the IP header is the TCP
header. Within the TCP header is a 2 byte field for the destination port. This field
indicates which application or data handler the encapsulated data is meant for. In
Fig. 12, this field decodes to port Ox00O3. In Fig. 13, port 3 is designated as the
HTTP port. After decoding the destination port field within the TCP header, the
HTTP ENABLE line is activated, The TCP DATA FIELD line is activated a couple of
bytes later because there are some intermediate bytes between the destination
port field and the start of the TCP data field. Both the HTTP ENABLE and TCP
DATA FIELD lines must be active for the HTTP/PORT3 block in Fig. 13 to be
enabled. Once the HTTP block is enabled, it starts to parse incoming data bytes.
When it decodes the JPEG header, it enables the JPEG decoder block in Fig. 13.
Once the JPEG decoder is enabled, it starts to process incoming bytes. The JPEG
enable line is the only line needed to enable the JPEG block.
13
CA 02265692 l999-03- 12
W0 98/ 19412 PCT/US97/17257
Although the invention is described herein with reference to the preferred
embodiment, one skilled in the art will readily appreciate that other applications
may be substituted for those set forth herein without departing from the spirit and
scope of the present invention. Accordingly, the invention should only be limited
5 by the Claims included below.
14
Claims (42)
1. An apparatus for decoding and encoding network protocols and data, comprising:
a network protocol layer module for receiving and transmitting network packets and for encoding and decoding network packet bytes which comprise packet data;
a data handler module for exchanging said packet data with said network protocol layer module and for processing a specific data type;
a memory control module in communication with said data handler module for arbitrating memory accesses and for providing display data; and an operating system (o.s.) state machine module that is optimized for a single selected network protocol, said o.s. module in communication with said data handler module and providing resource control and system and user interfaces;
wherein said network protocol layer module, said data handler module, said memory control module, and said operating system (o.s.) state machine module are implemented in hardware gate level circuitry.
a network protocol layer module for receiving and transmitting network packets and for encoding and decoding network packet bytes which comprise packet data;
a data handler module for exchanging said packet data with said network protocol layer module and for processing a specific data type;
a memory control module in communication with said data handler module for arbitrating memory accesses and for providing display data; and an operating system (o.s.) state machine module that is optimized for a single selected network protocol, said o.s. module in communication with said data handler module and providing resource control and system and user interfaces;
wherein said network protocol layer module, said data handler module, said memory control module, and said operating system (o.s.) state machine module are implemented in hardware gate level circuitry.
2. The apparatus of claim 1, wherein said network protocol layer module comprises a plurality of state machines representing different network protocols.
3. The apparatus of claim 2, wherein said network protocol layer module implements one or more of the following network protocols: Point to Point Protocol (PPP), Internetwork Packet (IP), Transmission Control Protocol (TCP), Raw Socket, and/or User Datagram Protocol (UDP).
4. The apparatus of claim 2, wherein said network packet bytes are processed in real time.
5. The apparatus of claim 2, wherein said network packet bytes are processed concurrently.
6. The apparatus of claim 2, wherein said network packet bytes are processed byte-serially.
7. The apparatus of claim 1, wherein any data required more than once by a specific said state machine is placed in a specific memory location with a pointer designating said memory location.
8. The apparatus of claim 1, wherein said data handler module comprises at least one state machine which process a specific data type.
9. The apparatus of claim 8, wherein said data handler module processes one or more of the following protocols: Hypertext Transfer Protocol (HTTP), Hypertext Markup Language (HTML), Post Office Protocol (POP3), Internet Message Access Protocol (IMAP4), Simple Mail Transfer Protocol (SMTP), Joint Photographic Experts Group (JPEG), Graphics Interchange Format (GIF), and/or Java language.
10. The apparatus of claim 8, wherein said data type is processed in real time.
11. The apparatus of claim 8, wherein said data type is processed concurrently.
12. The apparatus in claim 8, wherein said data type is processed byte serially.
13. The apparatus of claim 8, wherein any data shared by said at least one state machine or required more than once by a specific said state machine is placed in a specific memory location with a pointer designating said memory location.
14. The apparatus of claim 8, wherein any data shared by said at least one state machine is provided to said state machine(s) concurrently.
15. The apparatus of claim 1, wherein said memory control module arbitrates all memory accesses.
16. The apparatus of claim 1, wherein said memory control module contains a Unified Memory Architecture (UMA) which allows a system memory and a video memory to reside in a same memory area.
17. The apparatus of claim 1, wherein said memory control module is comprised of one or more arbiter logic blocks where an arbiter block arbitrates according to a dynamic rotating algorithm between two devices.
18. The apparatus of claim 1, wherein said memory control module is comprised of one or more arbiter logic blocks arranged in such a manner as to give a fixed weighted priority to each of a plurality of devices for memory access based on a given arbiter tree structure.
19. The apparatus of claim 1, wherein said o.s. state machine acts as an arbitrator between said network protocol layer module, said data handler module, and said memory control module for resource control, system and user interface.
20. The apparatus of claim 1, further comprising:
a display controller.
a display controller.
21. The apparatus of claim 20, wherein said display controller controls one of the following types of displays: VGA, television, Liquid Crystal Display (LCD), or Light Emitting Diode (LED).
22. The apparatus of claim 1, wherein said apparatus between Internet signals and application products.
23. A process for decoding and encoding network protocols and data, said process comprising the steps of:
providing a network protocol layer module for receiving and transmitting network packets and for encoding and decoding network packet bytes which comprise packet data;
providing a data handler module for exchanging said packet data with said network protocol layer module and for processing a specific data type;
providing a memory control module in communication with said data handler module for arbitrating memory accesses and for providing display data; and providing an operating system (o.s.) state machine module that is implemented in hardware and that is optimized for a single selected network protocol, said o.s.
module in communication with said data handler module and providing resource control and system and user interfaces;
wherein said network protocol layer module, said data handler module, said memory control module, and said operating system (o.s.) state machine module are implemented in hardware gate level circuitry.
providing a network protocol layer module for receiving and transmitting network packets and for encoding and decoding network packet bytes which comprise packet data;
providing a data handler module for exchanging said packet data with said network protocol layer module and for processing a specific data type;
providing a memory control module in communication with said data handler module for arbitrating memory accesses and for providing display data; and providing an operating system (o.s.) state machine module that is implemented in hardware and that is optimized for a single selected network protocol, said o.s.
module in communication with said data handler module and providing resource control and system and user interfaces;
wherein said network protocol layer module, said data handler module, said memory control module, and said operating system (o.s.) state machine module are implemented in hardware gate level circuitry.
24. The process of claim 23, wherein said step of encoding and decoding network packet bytes further comprises the step of:
representing different network protocols using a plurality of state machines.
representing different network protocols using a plurality of state machines.
25. The process of claim 24, wherein said step of encoding and decoding network packet bytes further comprises the step of:
encoding and decoding one or more of the following network protocols: Point to Point Protocol (PPP), Internetwork Packet (IP), Transmission Control Protocol (TCP), Raw Socket, and/or User Datagram Protocol (UDP).
encoding and decoding one or more of the following network protocols: Point to Point Protocol (PPP), Internetwork Packet (IP), Transmission Control Protocol (TCP), Raw Socket, and/or User Datagram Protocol (UDP).
26. The process of claim 23, wherein said step of encoding and decoding network packet bytes further comprises the step of:
processing network packet bytes in real time.
processing network packet bytes in real time.
27. The process of claim 23, wherein said step of encoding and decoding network packet bytes further comprises the step of:
processing network packet bytes concurrently.
processing network packet bytes concurrently.
28. The process of claim 23, wherein said step of encoding and decoding network packet bytes further comprise the step of:
processing network packet bytes in a byte serial fashion.
processing network packet bytes in a byte serial fashion.
29. The process of claim 23, wherein said step of processing packet data bytes further comprises the step of:
processing specific data type(s) using at least one state machine.
processing specific data type(s) using at least one state machine.
30. The process of claim 29, wherein said step of processing packet data bytes further comprises the step of:
use of a CRC algorithm to decode data fields.
use of a CRC algorithm to decode data fields.
31. The process of claim 29, wherein said step of processing packet data bytes further comprises the step of:
processing one or more of the following protocols: Hypertext Transfer Protocol (HTTP), Hypertext Markup Language (HTML), Post Office Protocol (POP3), Internet Message Access Protocol (IMAP4), Simple Mail Transfer Protocol (SMTP), Joint Photographic Experts Group (JPEG), Graphics Interchange Format (GIF), and/or Java language.
processing one or more of the following protocols: Hypertext Transfer Protocol (HTTP), Hypertext Markup Language (HTML), Post Office Protocol (POP3), Internet Message Access Protocol (IMAP4), Simple Mail Transfer Protocol (SMTP), Joint Photographic Experts Group (JPEG), Graphics Interchange Format (GIF), and/or Java language.
32. The process of claim 29, wherein said step of processing packet data bytes further comprises the step of:
processing packet data bytes in real time.
processing packet data bytes in real time.
33. The process of claim 29, wherein said step of processing packet data bytes further comprises the step of:
processing packet data bytes concurrently.
processing packet data bytes concurrently.
34. The process of claim 29, wherein said step of processing packet data bytes further comprises the step of:
processing packet data bytes in a byte serial fashion.
processing packet data bytes in a byte serial fashion.
35. The process of claim 29, wherein said step of processing packet data bytes further comprises the step of:
placing any data more than once by a specific one of said at least one state machine in a specific memory location with a pointer designating said memory location.
placing any data more than once by a specific one of said at least one state machine in a specific memory location with a pointer designating said memory location.
36. The process of claim 23, wherein said step of controlling memory accesses further comprises the step of:
arbitrating all memory accesses.
arbitrating all memory accesses.
37. The process of claim 23, wherein said step of controlling memory accesses further comprises the step of:
allowing a system memory and a video memory to reside in a same memory area using a Unified Memory Architecture (UMA).
allowing a system memory and a video memory to reside in a same memory area using a Unified Memory Architecture (UMA).
38. The process of claim 23, wherein said step of controlling state machine sequencing further comprises the step of:
arbitrating between said step of encoding and decoding network packet bytes, said step of processing packet data bytes, and said step of controlling memory accesses for resource control, system and user interface.
arbitrating between said step of encoding and decoding network packet bytes, said step of processing packet data bytes, and said step of controlling memory accesses for resource control, system and user interface.
39. The process of claim 23, wherein said step of controlling state machine sequencing further comprises the step of:
interpreting system and user input for the purpose of controlling data handler modules and network protocol layer modules.
interpreting system and user input for the purpose of controlling data handler modules and network protocol layer modules.
40. The process of claim 23, further comprising the step of:
displaying output data.
displaying output data.
41. The process of claim 40, wherein said step of displaying output data further comprises the step of:
controlling one of the following types of displays: VGA, television, Liquid Crystal Display (LCD), or Light Emitting Diode (LED).
controlling one of the following types of displays: VGA, television, Liquid Crystal Display (LCD), or Light Emitting Diode (LED).
42. The process of claim 23, wherein said process is used to implement an interface between Internet signals and application products.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/742,085 US6034963A (en) | 1996-10-31 | 1996-10-31 | Multiple network protocol encoder/decoder and data processor |
US08/742,085 | 1996-10-31 | ||
PCT/US1997/017257 WO1998019412A1 (en) | 1996-10-31 | 1997-09-26 | Multiple network protocol encoder/decoder and data processor |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2265692A1 CA2265692A1 (en) | 1998-05-07 |
CA2265692C true CA2265692C (en) | 2001-08-07 |
Family
ID=24983424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002265692A Expired - Fee Related CA2265692C (en) | 1996-10-31 | 1997-09-26 | Multiple network protocol encoder/decoder and data processor |
Country Status (8)
Country | Link |
---|---|
US (1) | US6034963A (en) |
EP (1) | EP0935855B1 (en) |
JP (2) | JP3938599B2 (en) |
CN (1) | CN1154268C (en) |
AU (1) | AU723724B2 (en) |
CA (1) | CA2265692C (en) |
DE (1) | DE69739159D1 (en) |
WO (1) | WO1998019412A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7698413B1 (en) | 2004-04-12 | 2010-04-13 | Nvidia Corporation | Method and apparatus for accessing and maintaining socket control information for high speed network connections |
US7957379B2 (en) | 2004-10-19 | 2011-06-07 | Nvidia Corporation | System and method for processing RX packets in high speed network applications using an RX FIFO buffer |
US8065439B1 (en) | 2003-12-19 | 2011-11-22 | Nvidia Corporation | System and method for using metadata in the context of a transport offload engine |
US8176545B1 (en) | 2003-12-19 | 2012-05-08 | Nvidia Corporation | Integrated policy checking system and method |
US8549170B2 (en) | 2003-12-19 | 2013-10-01 | Nvidia Corporation | Retransmission system and method for a transport offload engine |
US20220377158A1 (en) * | 2021-05-24 | 2022-11-24 | Texas Instruments Incorporated | Priority selection for multiple protocol stacks |
Families Citing this family (213)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9098297B2 (en) * | 1997-05-08 | 2015-08-04 | Nvidia Corporation | Hardware accelerator for an object-oriented programming language |
US6101320A (en) * | 1997-08-01 | 2000-08-08 | Aurora Communications Exchange Ltd. | Electronic mail communication system and method |
US6263344B1 (en) * | 1997-09-18 | 2001-07-17 | Bo Wu | Method and apparatus for processing hypertext objects on optical disc players |
JP3413788B2 (en) * | 1997-09-25 | 2003-06-09 | 日本電信電話株式会社 | Communication method having communication protocol for performing flow control between layers and data communication terminal |
US7133940B2 (en) * | 1997-10-14 | 2006-11-07 | Alacritech, Inc. | Network interface device employing a DMA command queue |
US6687758B2 (en) * | 2001-03-07 | 2004-02-03 | Alacritech, Inc. | Port aggregation for network connections that are offloaded to network interface devices |
US6434620B1 (en) * | 1998-08-27 | 2002-08-13 | Alacritech, Inc. | TCP/IP offload network interface device |
US6807581B1 (en) | 2000-09-29 | 2004-10-19 | Alacritech, Inc. | Intelligent network storage interface system |
US7185266B2 (en) * | 2003-02-12 | 2007-02-27 | Alacritech, Inc. | Network interface device for error detection using partial CRCS of variable length message portions |
US6427171B1 (en) | 1997-10-14 | 2002-07-30 | Alacritech, Inc. | Protocol processing stack for use with intelligent network interface device |
US6389479B1 (en) * | 1997-10-14 | 2002-05-14 | Alacritech, Inc. | Intelligent network interface device and system for accelerated communication |
US7237036B2 (en) * | 1997-10-14 | 2007-06-26 | Alacritech, Inc. | Fast-path apparatus for receiving data corresponding a TCP connection |
US7089326B2 (en) * | 1997-10-14 | 2006-08-08 | Alacritech, Inc. | Fast-path processing for receiving data on TCP connection offload devices |
US7076568B2 (en) * | 1997-10-14 | 2006-07-11 | Alacritech, Inc. | Data communication apparatus for computer intelligent network interface card which transfers data between a network and a storage device according designated uniform datagram protocol socket |
US6470415B1 (en) | 1999-10-13 | 2002-10-22 | Alacritech, Inc. | Queue system involving SRAM head, SRAM tail and DRAM body |
US8539112B2 (en) | 1997-10-14 | 2013-09-17 | Alacritech, Inc. | TCP/IP offload device |
US6757746B2 (en) * | 1997-10-14 | 2004-06-29 | Alacritech, Inc. | Obtaining a destination address so that a network interface device can write network data without headers directly into host memory |
US8782199B2 (en) | 1997-10-14 | 2014-07-15 | A-Tech Llc | Parsing a packet header |
US6591302B2 (en) | 1997-10-14 | 2003-07-08 | Alacritech, Inc. | Fast-path apparatus for receiving data corresponding to a TCP connection |
US7167927B2 (en) * | 1997-10-14 | 2007-01-23 | Alacritech, Inc. | TCP/IP offload device with fast-path TCP ACK generating and transmitting mechanism |
US8621101B1 (en) | 2000-09-29 | 2013-12-31 | Alacritech, Inc. | Intelligent network storage interface device |
US7174393B2 (en) | 2000-12-26 | 2007-02-06 | Alacritech, Inc. | TCP/IP offload network interface device |
US7042898B2 (en) | 1997-10-14 | 2006-05-09 | Alacritech, Inc. | Reducing delays associated with inserting a checksum into a network message |
US6226680B1 (en) * | 1997-10-14 | 2001-05-01 | Alacritech, Inc. | Intelligent network interface system method for protocol processing |
US7284070B2 (en) * | 1997-10-14 | 2007-10-16 | Alacritech, Inc. | TCP offload network interface device |
US6658480B2 (en) | 1997-10-14 | 2003-12-02 | Alacritech, Inc. | Intelligent network interface system and method for accelerated protocol processing |
US6697868B2 (en) * | 2000-02-28 | 2004-02-24 | Alacritech, Inc. | Protocol processing stack for use with intelligent network interface device |
US6427173B1 (en) | 1997-10-14 | 2002-07-30 | Alacritech, Inc. | Intelligent network interfaced device and system for accelerated communication |
US6065120A (en) | 1997-12-09 | 2000-05-16 | Phone.Com, Inc. | Method and system for self-provisioning a rendezvous to ensure secure access to information in a database from multiple devices |
JP3745116B2 (en) * | 1998-04-20 | 2006-02-15 | キヤノン株式会社 | Data processing apparatus, data processing method, and storage medium storing computer-readable program |
US6765901B1 (en) * | 1998-06-11 | 2004-07-20 | Nvidia Corporation | TCP/IP/PPP modem |
JP3225924B2 (en) * | 1998-07-09 | 2001-11-05 | 日本電気株式会社 | Communication quality control device |
US7664883B2 (en) * | 1998-08-28 | 2010-02-16 | Alacritech, Inc. | Network interface device that fast-path processes solicited session layer read commands |
JP2002527002A (en) * | 1998-09-25 | 2002-08-20 | ソマ ネットワークス インコーポレイテッド | Telecommunications operating system |
CA2264407A1 (en) | 1998-09-25 | 2000-03-25 | Wireless System Technologies, Inc. | Method and system for negotiating telecommunication resources |
US6985722B1 (en) | 1998-09-25 | 2006-01-10 | Soma Networks, Inc. | Telecommunication services |
JP2002533998A (en) * | 1998-12-18 | 2002-10-08 | テレフオンアクチーボラゲット エル エム エリクソン(パブル) | Internet Protocol Handler for Telecommunications Platform with Processor Cluster |
US6912590B1 (en) | 1998-12-18 | 2005-06-28 | Telefonaktiebolaget Lm Ericsson (Publ) | Single IP-addressing for a telecommunications platform with a multi-processor cluster using a distributed socket based internet protocol (IP) handler |
WO2000052551A2 (en) * | 1999-03-04 | 2000-09-08 | Gomo Technologies, Inc. | Method and apparatus for communicating graphics data between a source and a recipient over a network |
US6772215B1 (en) * | 1999-04-09 | 2004-08-03 | Telefonaktiebolaget Lm Ericsson (Publ) | Method for minimizing feedback responses in ARQ protocols |
US6542470B1 (en) * | 1999-05-26 | 2003-04-01 | 3Com Corporation | Packet expansion with preservation of original cyclic redundancy code check indication |
US7062574B1 (en) * | 1999-07-01 | 2006-06-13 | Agere Systems Inc. | System and method for selectively detaching point-to-point protocol header information |
US6647409B1 (en) * | 1999-07-13 | 2003-11-11 | Microsoft Corporation | Maintaining a sliding view of server based data on a handheld personal computer |
US7159030B1 (en) * | 1999-07-30 | 2007-01-02 | Intel Corporation | Associating a packet with a flow |
US6418310B1 (en) * | 1999-08-05 | 2002-07-09 | Ericsson Inc. | Wireless subscriber terminal using java control code |
US6961777B1 (en) | 1999-08-06 | 2005-11-01 | Shrikumar Hariharasubrahmanian | Systems and methods for predicting fields in a data packet |
US7009967B1 (en) * | 1999-08-07 | 2006-03-07 | Shrikumar Hariharasubrahmanian | Systems and methods for transmitting data packets |
US7185114B1 (en) | 1999-08-07 | 2007-02-27 | Shrikumar Hariharasubrahmanian | Virtual memory systems and methods |
US8135842B1 (en) * | 1999-08-16 | 2012-03-13 | Nvidia Corporation | Internet jack |
EP1885128A3 (en) * | 1999-09-20 | 2008-03-12 | Tivo, Inc. | Closed caption tagging system |
EP1188294B1 (en) * | 1999-10-14 | 2008-03-26 | Bluearc UK Limited | Apparatus and method for hardware implementation or acceleration of operating system functions |
US6430624B1 (en) * | 1999-10-21 | 2002-08-06 | Air2Web, Inc. | Intelligent harvesting and navigation system and method |
JP3613102B2 (en) | 1999-12-14 | 2005-01-26 | 日本電気株式会社 | Frame configuration method, frame configuration apparatus, and frame configuration transfer system |
US6772413B2 (en) | 1999-12-21 | 2004-08-03 | Datapower Technology, Inc. | Method and apparatus of data exchange using runtime code generator and translator |
US7191240B1 (en) * | 2000-02-14 | 2007-03-13 | International Business Machines Corporation | Generic network protocol layer with supporting data structure |
US6911652B2 (en) * | 2000-03-22 | 2005-06-28 | Jonathan A. Walkenstein | Low light imaging device |
CA2303000A1 (en) | 2000-03-23 | 2001-09-23 | William M. Snelgrove | Establishing and managing communications over telecommunication networks |
AU2001266656A1 (en) * | 2000-06-02 | 2001-12-17 | Zucotto Wireless, Inc. | Data path engine (dpe) |
US20020103942A1 (en) * | 2000-06-02 | 2002-08-01 | Guillaume Comeau | Wireless java device |
US6886004B2 (en) * | 2000-08-24 | 2005-04-26 | Red Hat, Inc. | Method and apparatus for atomic file look-up |
US8019901B2 (en) * | 2000-09-29 | 2011-09-13 | Alacritech, Inc. | Intelligent network storage interface system |
US6720074B2 (en) * | 2000-10-26 | 2004-04-13 | Inframat Corporation | Insulator coated magnetic nanoparticulate composites with reduced core loss and method of manufacture thereof |
US7039717B2 (en) * | 2000-11-10 | 2006-05-02 | Nvidia Corporation | Internet modem streaming socket method |
WO2002059757A1 (en) * | 2001-01-26 | 2002-08-01 | Iready Corporation | Communications processor |
US7379475B2 (en) * | 2002-01-25 | 2008-05-27 | Nvidia Corporation | Communications processor |
US6959007B1 (en) | 2001-03-01 | 2005-10-25 | Lsi Logic Corporation | High speed network protocol stack in silicon |
US20020124095A1 (en) * | 2001-03-02 | 2002-09-05 | Sultan Israel Daniel | Apparatus and method for sending point-to-point protocol over ethernet |
US20020133718A1 (en) * | 2001-03-15 | 2002-09-19 | Turbow Bryan L. | Private enterprise network incorporating digital subscriber lines |
US7814020B2 (en) | 2001-04-12 | 2010-10-12 | Nvidia International, Inc. | System, method and computer program product for the recording and playback of transaction macros |
US6682423B2 (en) | 2001-04-19 | 2004-01-27 | Igt | Open architecture communications in a gaming network |
US8218555B2 (en) | 2001-04-24 | 2012-07-10 | Nvidia Corporation | Gigabit ethernet adapter |
ATE493821T1 (en) * | 2001-04-24 | 2011-01-15 | Nvidia Corp | GIGABIT ETHERNET ADAPTER |
US7203722B2 (en) * | 2001-05-24 | 2007-04-10 | International Business Machines Corporation | Optimistic processing of network frames to reduce latency |
US20020184379A1 (en) * | 2001-06-04 | 2002-12-05 | Geping Chen | Forwarding data packets |
US6483840B1 (en) | 2001-06-25 | 2002-11-19 | Lsi Logic Corporation | High speed TCP/IP stack in silicon |
US6729210B2 (en) * | 2001-06-28 | 2004-05-04 | John L. Morris | Driver for eyebolts and hooks |
US7073070B2 (en) * | 2001-06-29 | 2006-07-04 | Intel Corporation | Method and apparatus to improve the protection of information presented by a computer |
US6912231B2 (en) * | 2001-07-26 | 2005-06-28 | Northrop Grumman Corporation | Multi-broadcast bandwidth control system |
US20030037154A1 (en) * | 2001-08-16 | 2003-02-20 | Poggio Andrew A. | Protocol processor |
US7647561B2 (en) | 2001-08-28 | 2010-01-12 | Nvidia International, Inc. | System, method and computer program product for application development using a visual paradigm to combine existing data and applications |
JP2003076620A (en) * | 2001-09-04 | 2003-03-14 | Fujitsu Ltd | Dynamic protocol exchanging system and its method |
US7620692B2 (en) * | 2001-09-06 | 2009-11-17 | Broadcom Corporation | iSCSI receiver implementation |
US7515587B2 (en) * | 2001-09-20 | 2009-04-07 | Lexmark International, Inc. | Device for processing data packets without use of a microprocessor and a memory |
EP1301008B1 (en) * | 2001-10-04 | 2005-11-16 | Alcatel | Process for transmission of data via a communication network to a terminal and network node |
US7088739B2 (en) | 2001-11-09 | 2006-08-08 | Ericsson Inc. | Method and apparatus for creating a packet using a digital signal processor |
US20030121835A1 (en) * | 2001-12-31 | 2003-07-03 | Peter Quartararo | Apparatus for and method of sieving biocompatible adsorbent beaded polymers |
US7260106B2 (en) * | 2002-01-24 | 2007-08-21 | Intel Corporation | Method and apparatus for managing energy usage of processors while executing protocol state machines |
US20030167347A1 (en) * | 2002-02-11 | 2003-09-04 | Combs James Lee | Home network printer adapter |
US7269661B2 (en) | 2002-02-12 | 2007-09-11 | Bradley Richard Ree | Method using receive and transmit protocol aware logic modules for confirming checksum values stored in network packet |
US7535913B2 (en) * | 2002-03-06 | 2009-05-19 | Nvidia Corporation | Gigabit ethernet adapter supporting the iSCSI and IPSEC protocols |
US7496689B2 (en) * | 2002-04-22 | 2009-02-24 | Alacritech, Inc. | TCP/IP offload device |
US7543087B2 (en) * | 2002-04-22 | 2009-06-02 | Alacritech, Inc. | Freeing transmit memory on a network interface device prior to receiving an acknowledgement that transmit data has been received by a remote device |
US20030212735A1 (en) * | 2002-05-13 | 2003-11-13 | Nvidia Corporation | Method and apparatus for providing an integrated network of processors |
US7079542B2 (en) * | 2002-07-02 | 2006-07-18 | Samsung Electronics Co., Ltd. | Internet protocol address look-up method |
US6823437B2 (en) | 2002-07-11 | 2004-11-23 | International Business Machines Corporation | Lazy deregistration protocol for a split socket stack |
US20040049580A1 (en) * | 2002-09-05 | 2004-03-11 | International Business Machines Corporation | Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms |
US6735647B2 (en) | 2002-09-05 | 2004-05-11 | International Business Machines Corporation | Data reordering mechanism for high performance networks |
US20040049603A1 (en) * | 2002-09-05 | 2004-03-11 | International Business Machines Corporation | iSCSI driver to adapter interface protocol |
US7299266B2 (en) * | 2002-09-05 | 2007-11-20 | International Business Machines Corporation | Memory management offload for RDMA enabled network adapters |
US7519650B2 (en) * | 2002-09-05 | 2009-04-14 | International Business Machines Corporation | Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms |
US7337241B2 (en) * | 2002-09-27 | 2008-02-26 | Alacritech, Inc. | Fast-path apparatus for receiving data corresponding to a TCP connection |
US7191241B2 (en) * | 2002-09-27 | 2007-03-13 | Alacritech, Inc. | Fast-path apparatus for receiving data corresponding to a TCP connection |
US8041735B1 (en) | 2002-11-01 | 2011-10-18 | Bluearc Uk Limited | Distributed file system and method |
US7457822B1 (en) * | 2002-11-01 | 2008-11-25 | Bluearc Uk Limited | Apparatus and method for hardware-based file system |
US20040088262A1 (en) * | 2002-11-06 | 2004-05-06 | Alacritech, Inc. | Enabling an enhanced function of an electronic device |
US7254696B2 (en) * | 2002-12-12 | 2007-08-07 | Alacritech, Inc. | Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests |
US7362772B1 (en) | 2002-12-13 | 2008-04-22 | Nvidia Corporation | Network processing pipeline chipset for routing and host packet processing |
US7324547B1 (en) | 2002-12-13 | 2008-01-29 | Nvidia Corporation | Internet protocol (IP) router residing in a processor chipset |
US7397797B2 (en) * | 2002-12-13 | 2008-07-08 | Nvidia Corporation | Method and apparatus for performing network processing functions |
US20060259508A1 (en) * | 2003-01-24 | 2006-11-16 | Mistletoe Technologies, Inc. | Method and apparatus for detecting semantic elements using a push down automaton |
US7424571B2 (en) * | 2004-07-27 | 2008-09-09 | Gigafin Networks, Inc. | Array machine context data memory |
US7130987B2 (en) * | 2003-01-24 | 2006-10-31 | Mistletoe Technologies, Inc. | Reconfigurable semantic processor |
US7415596B2 (en) * | 2003-01-24 | 2008-08-19 | Gigafin Networks, Inc. | Parser table/production rule table configuration using CAM and SRAM |
US20050281281A1 (en) * | 2003-01-24 | 2005-12-22 | Rajesh Nair | Port input buffer architecture |
US7548512B2 (en) * | 2003-02-06 | 2009-06-16 | General Electric Company | Methods and systems for prioritizing data transferred on a Local Area Network |
US20040167985A1 (en) * | 2003-02-21 | 2004-08-26 | Adescom, Inc. | Internet protocol access controller |
US7286526B2 (en) * | 2003-03-14 | 2007-10-23 | International Business Machines Corporation | Uniform management of mixed network systems |
US7420931B2 (en) * | 2003-06-05 | 2008-09-02 | Nvidia Corporation | Using TCP/IP offload to accelerate packet filtering |
US7609696B2 (en) * | 2003-06-05 | 2009-10-27 | Nvidia Corporation | Storing and accessing TCP connection information |
US7620070B1 (en) | 2003-06-24 | 2009-11-17 | Nvidia Corporation | Packet processing with re-insertion into network interface circuitry |
US7913294B1 (en) | 2003-06-24 | 2011-03-22 | Nvidia Corporation | Network protocol processing for filtering packets |
AU2003903480A0 (en) * | 2003-07-07 | 2003-07-17 | Canon Kabushiki Kaisha | A Low Power Chip Architecture |
US8018928B2 (en) * | 2003-11-21 | 2011-09-13 | Canon Kabushiki Kaisha | Modular approach to the TCP/IPv6 hardware implementation |
US6996070B2 (en) * | 2003-12-05 | 2006-02-07 | Alacritech, Inc. | TCP/IP offload device with reduced sequential processing |
US7899913B2 (en) * | 2003-12-19 | 2011-03-01 | Nvidia Corporation | Connection management system and method for a transport offload engine |
US8572289B1 (en) | 2003-12-19 | 2013-10-29 | Nvidia Corporation | System, method and computer program product for stateless offloading of upper level network protocol operations |
US7260631B1 (en) | 2003-12-19 | 2007-08-21 | Nvidia Corporation | System and method for receiving iSCSI protocol data units |
US7624198B1 (en) | 2003-12-19 | 2009-11-24 | Nvidia Corporation | Sequence tagging system and method for transport offload engine data lists |
US7305476B2 (en) * | 2004-02-01 | 2007-12-04 | Phonex Broadband Corporation | Method and system for network synchronization and isolation |
US7356046B2 (en) * | 2004-02-09 | 2008-04-08 | Metretek, Inc. | Method and apparatus for remotely monitoring and controlling devices |
US7365680B2 (en) * | 2004-02-10 | 2008-04-29 | Sirf Technology, Inc. | Location services system that reduces auto-correlation or cross-correlation in weak signals |
US7249306B2 (en) * | 2004-02-20 | 2007-07-24 | Nvidia Corporation | System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity |
US7206872B2 (en) * | 2004-02-20 | 2007-04-17 | Nvidia Corporation | System and method for insertion of markers into a data stream |
US20050223118A1 (en) * | 2004-04-05 | 2005-10-06 | Ammasso, Inc. | System and method for placement of sharing physical buffer lists in RDMA communication |
US20060067346A1 (en) * | 2004-04-05 | 2006-03-30 | Ammasso, Inc. | System and method for placement of RDMA payload into application memory of a processor system |
US20050220128A1 (en) * | 2004-04-05 | 2005-10-06 | Ammasso, Inc. | System and method for work request queuing for intelligent adapter |
US7251722B2 (en) * | 2004-05-11 | 2007-07-31 | Mistletoe Technologies, Inc. | Semantic processor storage server architecture |
US7398356B2 (en) | 2004-07-22 | 2008-07-08 | Mistletoe Technologies, Inc. | Contextual memory interface for network processor |
US7451268B2 (en) * | 2004-07-27 | 2008-11-11 | Gigafin Networks, Inc. | Arbiter for array machine context data memory |
US20060026377A1 (en) * | 2004-07-27 | 2006-02-02 | Somsubhra Sikdar | Lookup interface for array machine context data memory |
US20060031555A1 (en) * | 2004-08-05 | 2006-02-09 | Somsubhra Sikdar | Data context switching in a semantic processor |
US20070019661A1 (en) * | 2005-07-20 | 2007-01-25 | Mistletoe Technologies, Inc. | Packet output buffer for semantic processor |
US20070043871A1 (en) * | 2005-07-19 | 2007-02-22 | Mistletoe Technologies, Inc. | Debug non-terminal symbol for parser error handling |
US20070027991A1 (en) * | 2005-07-14 | 2007-02-01 | Mistletoe Technologies, Inc. | TCP isolation with semantic processor TCP state machine |
US8248939B1 (en) | 2004-10-08 | 2012-08-21 | Alacritech, Inc. | Transferring control of TCP connections between hierarchy of processing mechanisms |
US7522621B2 (en) * | 2005-01-06 | 2009-04-21 | International Business Machines Corporation | Apparatus and method for efficiently modifying network data frames |
KR100644701B1 (en) * | 2005-06-23 | 2006-11-10 | 삼성전자주식회사 | Method and apparatus of smtp authentication |
US20070016906A1 (en) * | 2005-07-18 | 2007-01-18 | Mistletoe Technologies, Inc. | Efficient hardware allocation of processes to processors |
US20070022225A1 (en) * | 2005-07-21 | 2007-01-25 | Mistletoe Technologies, Inc. | Memory DMA interface with checksum |
US20070022275A1 (en) * | 2005-07-25 | 2007-01-25 | Mistletoe Technologies, Inc. | Processor cluster implementing conditional instruction skip |
US7506080B2 (en) * | 2005-09-16 | 2009-03-17 | Inter Corporation | Parallel processing of frame based data transfers |
US7738500B1 (en) | 2005-12-14 | 2010-06-15 | Alacritech, Inc. | TCP timestamp synchronization for network connections that are offloaded to network interface devices |
US8190698B2 (en) | 2006-06-30 | 2012-05-29 | Microsoft Corporation | Efficiently polling to determine completion of a DMA copy operation |
GB2443005A (en) * | 2006-07-19 | 2008-04-23 | Chronicle Solutions | Analysing network traffic by decoding a wide variety of protocols (or object types) of each packet |
US20080097917A1 (en) * | 2006-10-24 | 2008-04-24 | Kent Dicks | Systems and methods for wireless processing and medical device monitoring via remote command execution |
US20080097550A1 (en) * | 2006-10-24 | 2008-04-24 | Kent Dicks | Systems and methods for remote patient monitoring and command execution |
US8126734B2 (en) * | 2006-10-24 | 2012-02-28 | Medapps, Inc. | Systems and methods for adapter-based communication with a medical device |
US8126735B2 (en) * | 2006-10-24 | 2012-02-28 | Medapps, Inc. | Systems and methods for remote patient monitoring and user interface |
US8126733B2 (en) * | 2006-10-24 | 2012-02-28 | Medapps, Inc. | Systems and methods for medical data interchange using mobile computing devices |
US8126732B2 (en) * | 2006-10-24 | 2012-02-28 | Medapps, Inc. | Systems and methods for processing and transmittal of medical data through multiple interfaces |
US20080097912A1 (en) * | 2006-10-24 | 2008-04-24 | Kent Dicks | Systems and methods for wireless processing and transmittal of medical data through an intermediary device |
US20080097914A1 (en) * | 2006-10-24 | 2008-04-24 | Kent Dicks | Systems and methods for wireless processing and transmittal of medical data through multiple interfaces |
US8126729B2 (en) * | 2006-10-24 | 2012-02-28 | Medapps, Inc. | Systems and methods for processing and transmittal of data from a plurality of medical devices |
US20080097913A1 (en) * | 2006-10-24 | 2008-04-24 | Kent Dicks | Systems and methods for wireless processing and transmittal of data from a plurality of medical devices |
US8126728B2 (en) * | 2006-10-24 | 2012-02-28 | Medapps, Inc. | Systems and methods for processing and transmittal of medical data through an intermediary device |
US8126730B2 (en) * | 2006-10-24 | 2012-02-28 | Medapps, Inc. | Systems and methods for storage and forwarding of medical data |
US8131566B2 (en) * | 2006-10-24 | 2012-03-06 | Medapps, Inc. | System for facility management of medical data and patient interface |
US9543920B2 (en) * | 2006-10-24 | 2017-01-10 | Kent E. Dicks | Methods for voice communication through personal emergency response system |
US8966235B2 (en) * | 2006-10-24 | 2015-02-24 | Kent E. Dicks | System for remote provisioning of electronic devices by overlaying an initial image with an updated image |
US9619621B2 (en) * | 2006-10-24 | 2017-04-11 | Kent Dicks | Systems and methods for medical data interchange via remote command execution |
CN101197681B (en) * | 2006-12-08 | 2010-08-18 | 深圳市同洲电子股份有限公司 | Method for receiving network data by IP set-top box |
US8837294B2 (en) * | 2006-12-19 | 2014-09-16 | Tektronix, Inc. | Schematic display of protocol-specific information |
US8085812B2 (en) * | 2006-12-19 | 2011-12-27 | Tektronix, Inc. | Symbolic representation of protocol-layer information |
US20080144654A1 (en) * | 2006-12-19 | 2008-06-19 | Leo Frishberg | Symbolic representation of protocol-specific information |
JP2008191208A (en) * | 2007-02-01 | 2008-08-21 | Seiko Epson Corp | Encryption processing circuit, arithmetic unit, and electronic equipment |
US8751583B2 (en) * | 2007-02-07 | 2014-06-10 | Acxess Inc. | System and method for providing business continuity through secure e-mail |
JP4320036B2 (en) * | 2007-02-14 | 2009-08-26 | 富士通株式会社 | Communication control method and communication control apparatus |
US8169992B2 (en) | 2007-08-08 | 2012-05-01 | Telefonaktiebolaget Lm Ericsson (Publ) | Uplink scrambling during random access |
US20110090086A1 (en) * | 2007-10-22 | 2011-04-21 | Kent Dicks | Systems for personal emergency intervention |
US8539513B1 (en) | 2008-04-01 | 2013-09-17 | Alacritech, Inc. | Accelerating data transfer in a virtual computer system with tightly coupled TCP connections |
US8341286B1 (en) | 2008-07-31 | 2012-12-25 | Alacritech, Inc. | TCP offload send optimization |
US9306793B1 (en) | 2008-10-22 | 2016-04-05 | Alacritech, Inc. | TCP offload device that batches session layer headers to reduce interrupts as well as CPU copies |
US20100138575A1 (en) | 2008-12-01 | 2010-06-03 | Micron Technology, Inc. | Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices |
US20100174887A1 (en) | 2009-01-07 | 2010-07-08 | Micron Technology Inc. | Buses for Pattern-Recognition Processors |
CN101674308B (en) * | 2009-10-13 | 2015-04-01 | 中兴通讯股份有限公司 | Method and device for transmitting packet-switched domain business data |
US9323994B2 (en) | 2009-12-15 | 2016-04-26 | Micron Technology, Inc. | Multi-level hierarchical routing matrices for pattern-recognition processors |
US8291058B2 (en) * | 2010-02-19 | 2012-10-16 | Intrusion, Inc. | High speed network data extractor |
US20130275709A1 (en) | 2012-04-12 | 2013-10-17 | Micron Technology, Inc. | Methods for reading data from a storage buffer including delaying activation of a column select |
US9524248B2 (en) | 2012-07-18 | 2016-12-20 | Micron Technology, Inc. | Memory management for a hierarchical memory system |
US9235798B2 (en) | 2012-07-18 | 2016-01-12 | Micron Technology, Inc. | Methods and systems for handling data received by a state machine engine |
US9703574B2 (en) | 2013-03-15 | 2017-07-11 | Micron Technology, Inc. | Overflow detection and correction in state machine engines |
US9448965B2 (en) | 2013-03-15 | 2016-09-20 | Micron Technology, Inc. | Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine |
WO2015131929A1 (en) | 2014-03-04 | 2015-09-11 | Huawei Technologies Co., Ltd. | State-dependent data forwarding |
US10430210B2 (en) | 2014-12-30 | 2019-10-01 | Micron Technology, Inc. | Systems and devices for accessing a state machine |
US11366675B2 (en) | 2014-12-30 | 2022-06-21 | Micron Technology, Inc. | Systems and devices for accessing a state machine |
US10769099B2 (en) | 2014-12-30 | 2020-09-08 | Micron Technology, Inc. | Devices for time division multiplexing of state machine engine signals |
US9974492B1 (en) | 2015-06-05 | 2018-05-22 | Life365, Inc. | Health monitoring and communications device |
US10185513B1 (en) | 2015-06-05 | 2019-01-22 | Life365, Inc. | Device configured for dynamic software change |
US11329683B1 (en) | 2015-06-05 | 2022-05-10 | Life365, Inc. | Device configured for functional diagnosis and updates |
US10560135B1 (en) | 2015-06-05 | 2020-02-11 | Life365, Inc. | Health, wellness and activity monitor |
US10388411B1 (en) | 2015-09-02 | 2019-08-20 | Life365, Inc. | Device configured for functional diagnosis and updates |
US10977309B2 (en) | 2015-10-06 | 2021-04-13 | Micron Technology, Inc. | Methods and systems for creating networks |
US10691964B2 (en) | 2015-10-06 | 2020-06-23 | Micron Technology, Inc. | Methods and systems for event reporting |
US10846103B2 (en) | 2015-10-06 | 2020-11-24 | Micron Technology, Inc. | Methods and systems for representing processing resources |
US10079919B2 (en) * | 2016-05-27 | 2018-09-18 | Solarflare Communications, Inc. | Method, apparatus and computer program product for processing data |
US10146555B2 (en) | 2016-07-21 | 2018-12-04 | Micron Technology, Inc. | Adaptive routing to avoid non-repairable memory and logic defects on automata processor |
US10268602B2 (en) | 2016-09-29 | 2019-04-23 | Micron Technology, Inc. | System and method for individual addressing |
US10019311B2 (en) | 2016-09-29 | 2018-07-10 | Micron Technology, Inc. | Validation of a symbol response memory |
US10929764B2 (en) | 2016-10-20 | 2021-02-23 | Micron Technology, Inc. | Boolean satisfiability |
US10592450B2 (en) | 2016-10-20 | 2020-03-17 | Micron Technology, Inc. | Custom compute cores in integrated circuit devices |
JP6988511B2 (en) | 2018-01-24 | 2022-01-05 | 富士通株式会社 | Failure detection method, node device, communication system |
CN112131161B (en) * | 2020-09-14 | 2022-03-29 | 山东产研集成电路产业研究院有限公司 | Hardware analysis method for Binary protocol data stream |
CN112543089B (en) * | 2020-11-12 | 2022-07-26 | 浙江创意声光电科技有限公司 | Operation method and equipment for full-duplex exchange decoding of lighting network |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5012489A (en) * | 1988-11-07 | 1991-04-30 | Hayes Microcomputer Products, Inc. | Method for sending a plurality of data channels over a single communications line |
US5161193A (en) * | 1990-06-29 | 1992-11-03 | Digital Equipment Corporation | Pipelined cryptography processor and method for its use in communication networks |
US5251205A (en) * | 1990-09-04 | 1993-10-05 | Digital Equipment Corporation | Multiple protocol routing |
EP0576546A4 (en) * | 1991-03-18 | 1995-01-25 | Echelon Corp | Networked variables. |
US5307413A (en) * | 1991-07-19 | 1994-04-26 | Process Software Corporation | Method and apparatus for adding data compression and other services in a computer network |
JPH0763161B2 (en) * | 1993-01-05 | 1995-07-05 | 日本電気株式会社 | Multimedia packet communication system |
AU6410994A (en) * | 1993-03-30 | 1994-10-24 | Ast Research, Inc. | Cache address strobe control logic for simulated bus cycle initiation |
US5426694A (en) * | 1993-10-08 | 1995-06-20 | Excel, Inc. | Telecommunication switch having programmable network protocols and communications services |
US5802287A (en) * | 1993-10-20 | 1998-09-01 | Lsi Logic Corporation | Single chip universal protocol multi-function ATM network interface |
US5485455A (en) * | 1994-01-28 | 1996-01-16 | Cabletron Systems, Inc. | Network having secure fast packet switching and guaranteed quality of service |
US5577105A (en) * | 1994-03-11 | 1996-11-19 | U.S. Robotics, Inc. | Telephone call routing and switching techniques for data communications |
US5519704A (en) * | 1994-04-21 | 1996-05-21 | Cisco Systems, Inc. | Reliable transport protocol for internetwork routing |
US5870549A (en) * | 1995-04-28 | 1999-02-09 | Bobo, Ii; Charles R. | Systems and methods for storing, delivering, and managing messages |
US5675507A (en) * | 1995-04-28 | 1997-10-07 | Bobo, Ii; Charles R. | Message storage and delivery system |
US5485460A (en) * | 1994-08-19 | 1996-01-16 | Microsoft Corporation | System and method for running multiple incompatible network protocol stacks |
US5812951A (en) * | 1994-11-23 | 1998-09-22 | Hughes Electronics Corporation | Wireless personal communication system |
US5625678A (en) * | 1995-05-24 | 1997-04-29 | Microsoft Corporation | Method and system for allowing switched voice and data communication among multiple application programs |
US5636371A (en) * | 1995-06-07 | 1997-06-03 | Bull Hn Information Systems Inc. | Virtual network mechanism to access well known port application programs running on a single host system |
US5734865A (en) * | 1995-06-07 | 1998-03-31 | Bull Hn Information Systems Inc. | Virtual local area network well-known port routing mechanism for mult--emulators in an open system environment |
US5754540A (en) * | 1995-07-18 | 1998-05-19 | Macronix International Co., Ltd. | Expandable integrated circuit multiport repeater controller with multiple media independent interfaces and mixed media connections |
US5666362A (en) * | 1995-07-25 | 1997-09-09 | 3Com Corporation | Method and apparatus for asynchronous PPP and synchronous PPP conversion |
US5809235A (en) * | 1996-03-08 | 1998-09-15 | International Business Machines Corporation | Object oriented network event management framework |
US5748905A (en) * | 1996-08-30 | 1998-05-05 | Fujitsu Network Communications, Inc. | Frame classification using classification keys |
US5818935A (en) * | 1997-03-10 | 1998-10-06 | Maa; Chia-Yiu | Internet enhanced video system |
-
1996
- 1996-10-31 US US08/742,085 patent/US6034963A/en not_active Ceased
-
1997
- 1997-09-26 JP JP52046498A patent/JP3938599B2/en not_active Expired - Lifetime
- 1997-09-26 CA CA002265692A patent/CA2265692C/en not_active Expired - Fee Related
- 1997-09-26 EP EP97944464A patent/EP0935855B1/en not_active Expired - Lifetime
- 1997-09-26 AU AU45952/97A patent/AU723724B2/en not_active Ceased
- 1997-09-26 CN CNB97199269XA patent/CN1154268C/en not_active Expired - Lifetime
- 1997-09-26 DE DE69739159T patent/DE69739159D1/en not_active Expired - Lifetime
- 1997-09-26 WO PCT/US1997/017257 patent/WO1998019412A1/en active Application Filing
-
2007
- 2007-01-11 JP JP2007003117A patent/JP2007133902A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8065439B1 (en) | 2003-12-19 | 2011-11-22 | Nvidia Corporation | System and method for using metadata in the context of a transport offload engine |
US8176545B1 (en) | 2003-12-19 | 2012-05-08 | Nvidia Corporation | Integrated policy checking system and method |
US8549170B2 (en) | 2003-12-19 | 2013-10-01 | Nvidia Corporation | Retransmission system and method for a transport offload engine |
US7698413B1 (en) | 2004-04-12 | 2010-04-13 | Nvidia Corporation | Method and apparatus for accessing and maintaining socket control information for high speed network connections |
US7957379B2 (en) | 2004-10-19 | 2011-06-07 | Nvidia Corporation | System and method for processing RX packets in high speed network applications using an RX FIFO buffer |
US20220377158A1 (en) * | 2021-05-24 | 2022-11-24 | Texas Instruments Incorporated | Priority selection for multiple protocol stacks |
Also Published As
Publication number | Publication date |
---|---|
EP0935855A4 (en) | 2000-05-17 |
EP0935855B1 (en) | 2008-12-10 |
CN1237295A (en) | 1999-12-01 |
JP2007133902A (en) | 2007-05-31 |
CA2265692A1 (en) | 1998-05-07 |
WO1998019412A1 (en) | 1998-05-07 |
AU4595297A (en) | 1998-05-22 |
JP2001503577A (en) | 2001-03-13 |
CN1154268C (en) | 2004-06-16 |
EP0935855A1 (en) | 1999-08-18 |
AU723724B2 (en) | 2000-09-07 |
US6034963A (en) | 2000-03-07 |
JP3938599B2 (en) | 2007-06-27 |
DE69739159D1 (en) | 2009-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2265692C (en) | Multiple network protocol encoder/decoder and data processor | |
US7483375B2 (en) | TCP/IP/PPP modem | |
US8359411B2 (en) | Data filtering using central DMA mechanism | |
US6016520A (en) | Method of viewing at a client viewing station a multiple media title stored at a server and containing a plurality of topics utilizing anticipatory caching | |
EP1131930B1 (en) | Partitioning of file for emulating streaming | |
US20060080382A1 (en) | UPnP user interface system and method | |
US20060259582A1 (en) | System and method for storing and processing data for display on a display device | |
US20020073218A1 (en) | Stream device management system for multimedia clients in a broadcast network architecture | |
US8135851B2 (en) | Object request broker for accelerating object-oriented communications and method | |
TW447205B (en) | Multiple network protocol encoder/decoder and date processor | |
US20060224691A1 (en) | Transparent rendering of media to remote client | |
USRE39501E1 (en) | Multiple network protocol encoder/decoder and data processor | |
CN101196934A (en) | Method and device for optimizing user interactive performance of built-in browser | |
US7370078B1 (en) | Determining a remote device name | |
CN111836024A (en) | Hybrid network system design based on video transmission | |
US8176117B2 (en) | Accelerator for object-oriented communications and method | |
KR20000076490A (en) | Tct/ip/ppp modem | |
KR100760025B1 (en) | Method for providing from user information requested via ubiquitous robotics companion and ubiquitous robotics companion of enabling the method | |
JP4025533B2 (en) | Stream video reception control method, stream video distribution system, and stream video reception device | |
JP4064626B2 (en) | Communication protocol | |
CN100425045C (en) | Multifunction remote control device | |
Read | Successful programming for information appliances | |
KR20040089313A (en) | Mobile communication terminal embedded dual cpu and method for managing data using the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |
Effective date: 20130926 |