CA2300255A1 - Power system time synchronization device and method for sequence of event recording - Google Patents

Power system time synchronization device and method for sequence of event recording Download PDF

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Publication number
CA2300255A1
CA2300255A1 CA002300255A CA2300255A CA2300255A1 CA 2300255 A1 CA2300255 A1 CA 2300255A1 CA 002300255 A CA002300255 A CA 002300255A CA 2300255 A CA2300255 A CA 2300255A CA 2300255 A1 CA2300255 A1 CA 2300255A1
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CA
Canada
Prior art keywords
counting error
window
calculated
synchronization device
time synchronization
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Granted
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CA002300255A
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French (fr)
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CA2300255C (en
Inventor
H. Kurtulus Ozcetin
Simon H. Lightbody
Peter M. Van Doorn
Rene T. Jonker
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Power Measurement Ltd
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Power Measurement Ltd
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Application filed by Power Measurement Ltd filed Critical Power Measurement Ltd
Publication of CA2300255A1 publication Critical patent/CA2300255A1/en
Application granted granted Critical
Publication of CA2300255C publication Critical patent/CA2300255C/en
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Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation

Abstract

The invention relates to the field of power distribution systems and more particularly to power monitors within such a system. A time synchronization device and method for synchronizing an internal clock of the power monitor to a periodically stable frequency is provided. Cycles of the periodically stable frequency are counted after each elapse of a predetermined time period. The elapse of the predetermined time period defines a present window and a previous window. A counting error and a change in counting error are calculated, wherein the change in counting error is the difference of a counting error calculated for the present window and a counting error calculated for the previous window. The present method detects when a change in counting error is within a predetermined range. When the counting error is within the predetermined range, the internal clock of the power monitor is adjusted to the line frequency according to the counting error calculated for the present window.
CA002300255A 1999-08-09 2000-03-06 Power system time synchronization device and method for sequence of event recording Expired - Lifetime CA2300255C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/370,863 1999-08-09
US09/370,863 US6611922B2 (en) 1999-08-09 1999-08-09 Power system time synchronization device and method for sequence of event recording

Publications (2)

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CA2300255A1 true CA2300255A1 (en) 2001-02-09
CA2300255C CA2300255C (en) 2003-07-15

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CA002300255A Expired - Lifetime CA2300255C (en) 1999-08-09 2000-03-06 Power system time synchronization device and method for sequence of event recording

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US (1) US6611922B2 (en)
CA (1) CA2300255C (en)

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* Cited by examiner, † Cited by third party
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WO2018166418A1 (en) * 2017-03-17 2018-09-20 杭州海康威视数字技术股份有限公司 Network timing method and device
CN111596253A (en) * 2019-08-24 2020-08-28 青岛鼎信通讯股份有限公司 Method for governing clock error through broadcast time synchronization on 09 standard intelligent meter

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Also Published As

Publication number Publication date
US20030014678A1 (en) 2003-01-16
CA2300255C (en) 2003-07-15
US6611922B2 (en) 2003-08-26

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