CA2305203C - Group iii nitride photonic devices on silicon carbide substrates with conductive buffer interlayer structure - Google Patents
Group iii nitride photonic devices on silicon carbide substrates with conductive buffer interlayer structure Download PDFInfo
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- CA2305203C CA2305203C CA002305203A CA2305203A CA2305203C CA 2305203 C CA2305203 C CA 2305203C CA 002305203 A CA002305203 A CA 002305203A CA 2305203 A CA2305203 A CA 2305203A CA 2305203 C CA2305203 C CA 2305203C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02513—Microstructure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02642—Mask materials other than SiO2 or SiN
Abstract
An optoelectronic device with a Group III nitride active layer is disclosed that comprises a silicon carbide substrate; an optoelectronic diode with a Group III nitride active layer, a buffer structure selected fro m the group consisting of galllium nitride and indium gallium nitride between the silicon carbide substrate and the optoelectronic diode; and a stress-absorbing structure comprising a plurality of predetermined stress-relieving areas within the crystal structure of the buffer structure, so that stress-induced cracking that occurs in the buffer structure occurs at predetermined areas rathen than elsewhere in the buffer structure.
Description
-I-Group III Nitride Photonic Devices on Silicon Carbide Substr aces with Conductive Buffer Interlaver Structure Field of the Invention This invention relates .to photonic devices in wide bar~dgap materials, and in particular relates to photonic devices forned with Group III nitride active layers on silicon carbide substrates.
Background of the Invention The semiconductor materials with wide bar._dgaps such as diamond, silicon IO carbide, and gallium nitride have become of significant interest in recent years because their wide bandgap characteristics provide them with the capability to emit light of higher energy (with correspondingly higher frequency and shorter wavelength) than do other semiconductor materials such as silicon er Qallium arsenide. In particular, silicon carbide, gallium nitride, and certain a they Group III
15 nitrides have bandgaps large enough to produce visible light throughout the visible spectrum,_including the higher-energy blue portion. They thus provide tl~e basis for semiconductor lasers and light emitting diodes (LEDs) with blue and green emissions.
Of these materials, gallium nitride is of pa.~-ticular interest because it is a direct semiconductor, i.e., the transition from the valence band to the conduction band does 20 not require a change in crystal momentum for the electron. As a result. the transition produces light very efficiently. In contrast silicon carbide is an indirect semiconductor; the bandgap transition energy is given off partly as a photon and partly as vibrational energy. Thus, gallium nitrAde offers the advantc.ge that for a given operating voltage and current, it will produce light more efficiently than silicon 25 carbide As with other semiconductor materials, however, the first step in forming a workable photonic devise is to build-up or otherwise obtain a suitable crystal structure with the desired active layer. Because of the differences in the structural characteristics of semiconductor materials, however, particularly their crystal lattice 30 structures, the materials which will workably support Group III nitride active layer devices are somewhat limited.
Presently, commercially available structures for a light emitting diode photonic device are formed of a gailium.nitride or related Group III nitride active layer on.a sapphire substrate. Sapphire (A120,) provides a relatively close lattice match to Group III nitrides, but also suffers certain disadvantages, the most limiting of which is its electrically insulating character. Thus, when Group III
nitride active and buffer layers (i.e., the intermediate layers that provide a crystal structure transition from the substrate to the active layer) are built on sapphire, the sapphire cannot be used as a conductive pathway to the active portions of the device.
This limits the type of devices that can be designed and produced on sapphire, and in particular limits the ability to form "vertical" devices in which the device contacts can be placed on opposite surfaces of the device witrL a direct conductive path through the substrate, buffers, and active layer. and the other contacts on the opposite of the device.
Accordingly, interest, including that of the assignee of the present invention, has focused upon the use of other materials as substrate candi da tes for Group III
nitride photonic devices. Silicon carbide (SiC) is a particularly attractive candidate because it can be made conductive, has a lattice match that car_ be appropriately buffered to a Group III nitride active Iaver, and has excellent th ermai and mechanical stability.
Nevertheless, silicon carbide's crystal lattice structure is such that some of the best candidates for an appropriate Group III buffer layer on a silicon carbide substrate are insulating rather than conductiv e. Thus, although the silicor_ carbide substrate can be made conductive, some of the preferred buffer layers bet'veen silicon carbide substrates and Group III active layer photonic devices rerr~ain insulating, thus minimizing the advantages of th.e ccnductive silicon carbide substrate.
For example, aluminum nitride (Ally provides an excellent buffer between a silicon carbide substrate and a Group III active layer, particularly a gallium nitride active layer. Aluminum nitride is, however, insulating rather than conductive.
Thus, structures with aluminum nitride buffer layers require shorting contacts that bypass the aluminum nitride buffer to electrically link the conductive silicon carbide substrate to the Group III nitride active layer. As noted above sucr: shorting contacts preclude some of the more advantageous device designs.
Alternatively, conductive buffer Iayer materials such as gallium nitride (GaN), aluminum gallium nitride (AIGaN), or combinations of gallium nitride and aluminum ll:;;V E11 : 1_'- lE)-:3:J : l i::11) : 7U~1:3~W:7a5-~ +4:3 f3;3 "~3:3:3~b~l-EW N t3 .~r ( m a m wru~(n m i ~ mu ~ . v~r muv ~ uv - ~ . vvu ium nitride can eliminate the shorting contacts. In turn, eliminating the shorting tact reduces the epitaxial layer thickness, decreases the number of fabrication steps tired to produce devices, reduces the overall chip size, and increases the device ;iency. Accordingly, Group IrI nitride devices can be produced at lower cost with ;her performance, Nevertheless, although these Conductive buffer materials offer these advantages, their crystal lattice match with silicon carbide is less satisfactory than is that of aluminum nitride. Accordingly, when epitaxial buffer layers of gallium nitride, alurt~inum gallium nitride, or combinations thereof are grown on silicon carbide substrates, they tend to produce excessive cracking in subsequent epilayers that are required for phatonic devices such as light-emitting diodes or laser diodes.
Some devices comprising gallium nitride and silicon carbide substrates are known. Far example,1P-A-b 326 416 discusses a compound semiconductor element utilizing a silicon carbide substrate, a gallium nitride buffer layer and an undoped , gallium aluminum indiurz nitride active layer. However, such a device is incapable of fully utilizing the favorable electronic characteristics of gallium nitride and the gallium niuide buffer layer is subject to cracking, Similarly, WO 9612417 discusses a light emitting semiconductor laser comprising a gallium nitride active layer separated from a silicon carbide substrate by a multilayered buffer that may contain gallium ni tride.
Researchers have proposed various solutions to the cracking problem. For example, WO 9/10950 discusses a method for growing a single crystal, solid orate device onto a mismatched substrate by growing a secondary substrate on the primary i substrate. The secondary substrate is obtained by growing an epilaycr divided into mesas onto the ptzmary substrate followed by annealing. This rrtcthod, however, serves primarily to direct cracking into non-critical areas rather than reduce or eliminate cracking.
3Q EP-A-0 352 472 discusses heteroepitaxy of lattice-mismatched semiconductor materials. In EP-A-0 352-472 a protruding grid is placed on a silicon substrate. A
lattice-mismatched semiconductor material, such as GaAs, is then deposited an both !ly 1) L : i:'- l()-:);i : 15::31) : 704~E5E~7a35-. +.;.J t3:3 _~39:3446p' II
;3 111IL11 JUt~l:~l7 fll ll IIrL~ lU't)YUV1VJ I. VV!
exposed silicon and the protruding grid. This method also serves primarily to ct cracking into non-critical areas rather than reduce or eliminate cracking.
Thus, there exists a need far a buffer structure that offers the crystal lattice :h advantages of aluminum nitride and yet which at the same time offers the conductivity advantages of galliurln nitride or aluminum gallium nitndc and that can be used in conjunction with conductive silicon carbide substrates rather than insulating sapphire substrates, Object and Summar_,y of the Invention Therefore, it is an object of the present invention to produce photonic devices and their wafer precursors, with a Group III nitride active layer, a conductive silicon carbide substrate, and a conductive buffer layer, hut that avoids the cracking and other problems that have to date hindered such combinations of materials and layers.
1 ~ The invention meats this object with a photonic device with a Group IIT
nitride active layer which comprises a silicon carbide substrate, an optoelectronic diode with a Group III nitride active layer, and a buffer structure between the silicon carbide substrate and the optoelectronic diode in which the buffer structure is both conductive;
and which provides the appropriate crystalline properties.
Zd In one aspect, the buffer structure is selected from the Group consisting of gallium nitride and indium gallium nitride (InGaN), and incorporates a stress absorbing structure comprising a plurality of predetermined stress relieving areas within the crystal structure of the buffer layer so that stress induced cracking that occurs in the buffer occurs at the predetermined areas rather than elsewhere in the 25 buffer.
In another aspect, the buffer layer includes a plurality of discrete crystal portions selected from the group consisting of gallium nitride and indium gallium nitride on the surface of the silicon carbide substrate for minimizing or eliminating the heterobarrier between silicon carbide and aluminum gallium nitride buffer structure.
Accordingly, in one aspect of the present invention there is provided a wafer precursor for Group III nitride devices comprising:
a silicon carbide substrate wafer comprising a predetermined pattern of grooves in the surface of said silicon carbide substrate;
a buffer layer on said substrate, said buffer layer selected from the group consisting of gallium nitride and indium gallium nitride; and a plurality of stress-absorbing crystal discontinuities grown within said buffer layer in positions that track said predetermined pattern of grooves in said substrate, so that the minimal degree of stress-induced cracking occurs in said buffer layer along said predetermined pattern rather than elsewhere in said buffer structure.
According to another aspect of the present invention there is provided a wafer precursor for vertically conductive Group III nitride devices comprising:
a silicon carbide substrate wafer comprising a predetermined pattern of stress-absorbing mesa structures formed of a material that is resistive to the growth of a buffer material and a conductively doped buffer layer deposited on the exposed surface of said substrate.
According to yet another aspect of the present invention there is provided a method of producing a Group III nitride optoelectronic device on a silicon carbide substrate comprising:
forming a predetermined pattern of grooves on the surface of a silicon carbide substrate that has otherwise been prepared for crystal growth thereon;
forming a buffer layer selected from the group consisting of gallium nitride and indium gallium nitride on the patterned surface of the silicon carbide substrate so that the buffer layer grows stress-absorbing discontinuities in the crystal structure of the buffer layer that track the predetermined pattern in the surface of the silicon carbide substrate; and forming an optoelectronic device with a Group III nitride active layer on the buffer layer.
-4a-According to still yet another aspect of the present invention there is provided method of producing a Group III nitride optoelectronic device on a silicon carbide substrate comprising:
forming a predetermined pattern of mesa structures on the surface of the silicon carbide substrate from a material that is resistive to the growth of a buffer material;
forming a conductively doped buffer layer on the exposed surface of the silicon carbide substrate; and forming an optoelectronic device with a Group III nitride active layer on the buffer layer.
The foregoing, and other objects and advantages of the invention, and the manner of accomplishing the same will become clearer when taken in conjunction with the accompanying detailed description and drawings in which:
Brief Description of the Drawings Figure 1 is across-sectional view of a prior-art diode with a shorting ring contact;
Figure 2 is a cross-sectional view of a vertical diode that can be produced to the present invention;
Figure 3 is an enlarged schematic view of a pixel formed according to the present invention;
Figure 4 is a schematic view of a display that includes a parality of pixels that incorporates structures according to the present invention;
Figure 5 is a schematic view of a silicon carbide wafer that incorporates the stress relieving structure according to the present invention;
Figure 6 is a cross-sectional view of the wafer of Figure 5;
Figure 7 is a cross-sectional view of the wafer of Figure 5 and showing in schematic view a buffer layer grown thereon;
Figure 8 is a cross-sectional view of a wafer incorporating second embodiment of the invention;
Figure 9 is a cross-sectional view identical to Figure 3 but showing additional crystal growth thereon;
-4b-Figure 10 is a l OX magnification photo from a scanning election microscope (SEM) of an epilayer that does not incorporate the present invention;
Figure 11 is an l OX SEM photo showing an epilayer according to the present invention;
Figure 12 is another I OX SEM photo showing an epilayer according to the present invention;
Figure 13 is a SOX SEM photo of an epilayer similar to Figure 12;
Figure 14 is a 100X SEM photo of an epilayer according to the present invention;
Figure 15 is another 100X SEM photo showing another epilayer that does not incorporate the present invention;
Figures 16, is a 15,OOOX SEM photo of a second embodiment of the invention;
and Figure I7 is a 50,OOOX SEM photo of the second embodiment.
Detailed Description Figure 1 is a cross-sectional view of a prior art device that is broadly designated at 20. As illustrated in Figure I, the device 20 includes a silicon carbide substrate 21, a contact 22 to the "back" of the substrate 21, a Group III
nitride active layer 23, a buffer layer 24 which is insulating rather than conductive, shorting contacts 25 for providing electrical contact between the conductive silicon buffer 21 and the active layer 23, and a top contact 26 for completing the circuit and permitting current to flow through the device in operation.
Figure 2 shows the manner in which the present invertior~ prcvides fer a more compact device. In Figure 2 the device is broadly designated at 30, and includes a .
conductive silicon carbide substrate 3I, a back contact 32, ar: active Layer 33 and a conductive buffer structure 34, along with a top contact 35. The invention thus eliminates the shorting contacts (typically shorting ring contacts) 25 of the device of Figure 1. As a result, the device 30 is easier to manufacture. and more efficient in operation: It will be understood that the active layer 33 as discussed herein can represent a device with a single p-n junction, a single or double p-r.
heterojunction or a p-n junction quantum well structure. Such structures are described in a number of prior U.S. patents including Nos. 5,393,993 and 5,592,501, and will not be otherwise discussed in detail herein other than to further illustrate the present invention.
Figure 3 illustrates that the device 30 according to the present invention can be incorporated with similar devices of different emitting wavelengths, in particular a red emitting diode 36 and a green emitting diode 37, as part of a three-color pixel broadly designated at 40 which in turn canoe one of a plurality of such pixels in a display 41.
The vertical 42 and horizontal 43 lines shown schematically in Figure 4 represent the rows and columns of pixels typically used in displays that incorporate light emitting diodes.
In its first aspect, the invention is a photonic device with a Group III
nitride active layer that comprises a silicon carbide substrate 31, a photonic diode with a Group III nitride active layer 33, and a buffer strucW re 34 selected from the group consisting of gallium nitride and indium gallium r_itride between the silicon carbide substrate 31 and the diode 33. In particular, the buffer structure includes a stress absorbing structure that is made up of a plurality of predetermined stress relieving areas within the crystal structure of the buffer structure 34 so that stress induced cracking that occurs in the buffer structure occurs at the predetermined areas rather than elsewhere in the structure.
Figure 5 is a schematic view of a wafer that incorporates a plurality of device precursors and that incorporates the stress absorbing structure of the present invention. Figure 5 illustrates a wafer broadly designated at 44 on which is superimposed a grid pattern of grooves 45. Figure 6 shows the sam a wafer 44 and grooves 45 in a cross-sectional orientation. When the next epitaxial layer 46 (Figure 7) is grown on the wafer 44 with its grooves 45, the surface of the epitaxial layer 46 tends to have a series of discontinuities 47 whose positions reflect the positions of the grooves 45 that form the pattern in the wafer 44. These discontinuities 47 form areas at which stress will relieve itself as t'r~e crystal lattice structure of the buffer layer 46 grows on the silicon carbide wafer 44. As a result, such stress resulting from lattice mismatches (or other factors) occurs at intended rather than random positions, thus permitting devices to be formed in the remaining areas without significant risk of stress cracking.
As noted above and illustrated in Figure S, in one preferred embodiment the predetermined pattern of stress relieving areas comprises a grid and the.grid can preferably be formed in any desired or necessary size that defines individual devices.
For example, where the individual devices will be light emitting diodes, a preferable grid pattern defines squares of about 250 microns per side. Alternatively, for different devices such as laser diodes, the gr~d can define rectangles of about 250 by microns (~.).
Figure 10 is a SEM photograph taken at a lOX magnification (10 times actual size) that shows the extent to which cracking-seen as the somewhat triangular or hexagonal patterns-can mar an epitaxial layer and render it defective or useless for photonic devices.
Figure I 1 is another lOX SEM photograph and illustrates a grid pattern of grooves in the epitaxial layer. In comparison with Figure I0, the surface shown in Figure 1I is relatively free of cracking defects.
Figure 12 is another l OX SEM photograph, and illustrates a smaller grid pattern. As with Figure I l, it is quite free of the cracks illustrated in Figure 10., Figure 13 is a SOX SEM photograph that paL~ticularly illustrates the advantages of the invention. In Figure 13, one of the grid sections cor_tains a largo defect (in a somewhat "X" shape). The defect ends, however, at the grid line and spoils only one device (or device precursor) rather than a mufti-device portion of the wafer.
Figure 14 is a 100X SEM photograph that similarly illustrates one defective 1 S grid portion (in the lower right portion of the photograph) fcr which the defect ends at the grid line rather than propagating further throughout the surface.
Figure 15 is a 100X SEM photograph that again illustrates a surface that does not incorporate any of the embodiments of the present invention. As with Figure 10, the geometric pattern of defects is quite evident.
In another embodiment, the stress absorbing structure can corr~prise a predetermined pattern of small mesa structures that are best illustrated in Figures 8 and 9. In Figures 8 and 9 the silicon carbide substrate is designated at 50 and the small mesa structures at S I. The mesa structures 51 are formed of a material upon which the growth of the selected buffer material is disfavored. For a gallium nitride or indium gallium nitride buffer structure, the preferred materials are selected from the group consisting of silicon dioxide, silicon nitride, and aluminum oxide.
Figure 9 illustrates the same structure as Figure 8, but with the buffer material grown as an epitaxial layer on the silicon carbide substrate 50. The epitaxial layer porEions are illustrated at 52. As Figure 9 illustrates, because growth of the buffer material is disfavored on the mesas 51, the epitaxial layer 52 forms a pattern which again exhibits predetermined stress-relieving discontinuity stractures therebetween.
As in the previous embodiment, the areas between the mesas can be tailored to be _g_ about the same size as the individual device, which, as noted above, is on the order of about 250 microns for LEDs and about 250 x 500, for Iaser diodes. It will be understood, however, that the particular size of the pattern of either the grids or the mesa.structures is illustrative rather than limiting of the present invention.
It will be understood that although the wafer structures according to the invention are particularly advantageous for optoelectronic devices, they are not limited to such, and the superior structural properties are advantageous for other devices formed upon the wafers.
As noted in the background portion, the optoelectroric device formed upon the I O buffer layer, and as typically illustrated at 23 in Figure 1 and 33' in Figure 2, is generally not a single layer, but rather is a multi-layer diode selected from the group consisting of p-n homojunctions, p-n heterojunctions, p-n single and double heterojunctions, and p-n junction quantum well structures.
In preferred embodiments, the silicon carbide substrate has a polytype selected IS from the group consisting of the 3C, 4H, 6H, and 15R polytypes. In the most preferred embodiments, the Group III nitride active layer of the diode comprises gallium nitride or indium gallium r_itrde.
Figures 16 through 18 illustrate another embodiment of the invention. In general, in schematic fashion, the overall structure is again illustrated by Figure 2 and 20 comprises the silicon carbide substrate 3I, the photonic diode 33 ar_d the buffer layer 34. In this embodiment, however. the buffer layer is aluminum ~aliium nitride rather than gallium nitride or indium gallium nitride. This embodiment ir~cluu'es a plurality of discrete crystal portions that appear as the white colored dots ir~ Figure 16-18. The discrete crystal portions are selected from the group of gallium nitride and indium 25 gallium nitride and are on the surface of the silicon carbide substrate for minimizing or eliminating the heterobarrier between the silicon carbide substrate 3I and the aluminum gallium nitride buffer structure 34.
In preferred embodiments, the discrete crystal portions are present in an amount sufficient to minimize or eliminate the heterobarrier but Iess than the amount 30 that would detrimentally affect or destroy the fanction ef any resul ring diode device built on the silicon carbide substrate 31. As illustrated in the photographs of Figures 16-18 the discrete crystal portions are present in an amount ef between about 40 and 60 per square micron.
Additionally, the sizes of the discrete crystal portions are preferably large enough to minimize or eliminate the heterobar~ier, but smaller than a size that would detrimentally affect or destroy the fi_:nction of any resulting diode device built on the silicon carbide substrate 31. In preferred embodiments, the discrete crystal portions are between 0.01 and 0.1 microns in diameter.
As in the previous embodiments, the optoelectronic device 33 formed on the buffer structure can comprise a light emitting diode or Iaser diode, and the resulting light emitting diode can be incorporated into pixels which in t~:rn can be incorporated into displays.
In preferred embodiments, the aluminum gallium nitride buffer layer has an atomic fraction of aluminum of between about 10 and 15%.
In another aspect, the invention comprises the method of producing the Group III nitride optoelectronic device on a silicon carbide substrate with a conductive buffer structure. In its method aspects, the invention comprises forming a structural pattern on the surface of a silicon carbide substrate that has otherwise been prepared for crystal growth thereon; forming a buffer layer selected from the group consisting of gallium nitride and indium. gallium r_itride on the patterned surface of the silicon carbide substrate so that the buffer layer exhibits features that follow the pattern of openings in the surface of the silicon carbide substrate; and thereafter forming a optoelectronic device with a Group III nitride active layer on the buffer layer.
As described with respect to the structural aspects, the step of forming the structural pattern can comprise forming a pattern of openings in the surface of the silicon carbide substrate or forming a pattern of mesa struct~.xes on the surface of the silicon carbide substrate.
When the pattern is formed of openings, the step of forming the openings can comprise techniques such as reactive ion etching or masking and etching steps.
Each of these steps is relatively well understood for silicon carbide and will not be otherwise described except to note, for example, U.S. Patents Nos. 4,865,685 and 4,981,551 describe exemplary dry etching procedures for silicon carbide.
Where the mesa structures are incorporated, they are preferably selected from the group consisting of silicon dioxide, silicon nitride, and aluminum oxide.
As in the structural environments, the optoelectronic device with the Group III active layer is preferably formed of gallium nitride or indium gallium r_itride.
S As in the structural embodiments, the method of the invention can comprise forming a light emitting diode or a Laser diode, and when a Iiaht emitting is formed, the method can further comprise incorporating the LED into a pixel, and the pixel into a display.
In an alternative method aspect, the buffer structure of the invention structure is formed of aluminum gallium nitride on a silicon carbide substrate that has been previously prepared by forming a plurality of discrete crystal portions selected from the group consisting of gallium nitride and indium gallium nitride on the silicon carbide surface. Thereafter, the optoelectronic device with the Group III
nitride active layer is formed on the buffer layer.
As set forth in the structural aspects of the invention, the method comprises forming discrete crystal portions of a size and in an amount that is sufficient to minimize or eliminate the heterobarrier, but less than sizes or amounts that would detrimentally affect or destroy the function of any resulting diode device built on the silicon carbide substrate: In particular the invention provides a robust structure that can withstand normally expected levels of electrostatic discharge.
In the second method aspect, the resulting device can be formed as a Light emitting diode so that the method can further comprise incorporating the LED
pixel and the pixel into a display. The method.can alternatively comprise forning a laser diode rather than an LED.
As in the other aspects of the invention, when the aluminum gallium nitride buffer Layer is used, it is preferably has an atomic fraction of aluminum of between about 10 and 15%.
EXAMPLE
In a current process for producing conductive buffer LEDs and Laser Diodes, GaN dots are first deposited. The purpose of the GaN dots is to decrease the barrier between the SiC substrate and the Si-doped AlGa..N buffer Layer. This is done at considerably lower temperatures than are used for the other epitaxial layers in the structure. The size and density of the dots are shown in Figures 16 and I7: It is important to keep the dots relatively small so the electrostatic discharge will not be adversely affected. The GaN dots are deposited in about 6 seconds, and then "capped" with Si-doped Al,ta Ga.9~N for about i5 seconds. The purpose of this cap is to prevent the dissociation of the GuN dots upon heating. In this material system, adding any Al to GaN, i.e., Ahl_~~Ga~~~N decreases the dissociation rate of the material because AIGaN is more stable than GaN in an NH3/HZ atmosphere. After the capping of the dots; the temperature is then ramped up to the buffer Iayer temperature.
Temperatures are allowed to stabilize for 2 minutes after the ral-np before commencing buffer layer growth.
In a specific run, a SiC wafer is heated in an atmosphere ef NH3 and H2, at I3 SLM and 15 SLM, respectively. These flows remain constant throughout the growth of the GaN dots, the AlGaN cap, and the subsequent buffer layer. The temperature ramps up over the course of 10 minutes until the GaN dot temperat~.sre is reached which is about 960°C. After allowing the temperature in the system to stabilize for approximately 5 minutes, the dots are deposited by flowing 10 -l5cc of trimethyl gallium (TMG; -5°C, 600 torr) for about 6 seconds. In order to ensure that the dots are conducting, SiHa is also added with the TMG flow. The amount of SiH a is determined by growing a bulk GaN Iayer with a carrier concentration of about 1 x 1018 cm 3. Immediately following the deposition of the GaI~T dots, the TMG and SiHc continue to flow, but now with the addition of trimethyl aluminum (TMA, 92cc, 25°C, 600 ton). This leads to a "cap" of about IO-I l% AlGaN. The growth time of the cap is 15 seconds. The flows (TMG, TMA, and SiH4) are then terminated and the temperature is ramped to the buffer temperature which is typically around 1060°C.
The temperature ramp is I minute and is followed by a 2 minute period during which the temperature is allowed to stabilize. The buffer layer is then grown.
Typical conditions are l8cc TMG/1 I OccTMA/ .087cc SiH4. Buffer layers consist of approximately I 1-12% AIGaN and are typically between about 1600 and 2700 t~
thick.
In the drawings and specification, there have been disclosed typical embodiments of the invention, and, although specific terms have been employed, they have been used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set ford: in the following claims.
Background of the Invention The semiconductor materials with wide bar._dgaps such as diamond, silicon IO carbide, and gallium nitride have become of significant interest in recent years because their wide bandgap characteristics provide them with the capability to emit light of higher energy (with correspondingly higher frequency and shorter wavelength) than do other semiconductor materials such as silicon er Qallium arsenide. In particular, silicon carbide, gallium nitride, and certain a they Group III
15 nitrides have bandgaps large enough to produce visible light throughout the visible spectrum,_including the higher-energy blue portion. They thus provide tl~e basis for semiconductor lasers and light emitting diodes (LEDs) with blue and green emissions.
Of these materials, gallium nitride is of pa.~-ticular interest because it is a direct semiconductor, i.e., the transition from the valence band to the conduction band does 20 not require a change in crystal momentum for the electron. As a result. the transition produces light very efficiently. In contrast silicon carbide is an indirect semiconductor; the bandgap transition energy is given off partly as a photon and partly as vibrational energy. Thus, gallium nitrAde offers the advantc.ge that for a given operating voltage and current, it will produce light more efficiently than silicon 25 carbide As with other semiconductor materials, however, the first step in forming a workable photonic devise is to build-up or otherwise obtain a suitable crystal structure with the desired active layer. Because of the differences in the structural characteristics of semiconductor materials, however, particularly their crystal lattice 30 structures, the materials which will workably support Group III nitride active layer devices are somewhat limited.
Presently, commercially available structures for a light emitting diode photonic device are formed of a gailium.nitride or related Group III nitride active layer on.a sapphire substrate. Sapphire (A120,) provides a relatively close lattice match to Group III nitrides, but also suffers certain disadvantages, the most limiting of which is its electrically insulating character. Thus, when Group III
nitride active and buffer layers (i.e., the intermediate layers that provide a crystal structure transition from the substrate to the active layer) are built on sapphire, the sapphire cannot be used as a conductive pathway to the active portions of the device.
This limits the type of devices that can be designed and produced on sapphire, and in particular limits the ability to form "vertical" devices in which the device contacts can be placed on opposite surfaces of the device witrL a direct conductive path through the substrate, buffers, and active layer. and the other contacts on the opposite of the device.
Accordingly, interest, including that of the assignee of the present invention, has focused upon the use of other materials as substrate candi da tes for Group III
nitride photonic devices. Silicon carbide (SiC) is a particularly attractive candidate because it can be made conductive, has a lattice match that car_ be appropriately buffered to a Group III nitride active Iaver, and has excellent th ermai and mechanical stability.
Nevertheless, silicon carbide's crystal lattice structure is such that some of the best candidates for an appropriate Group III buffer layer on a silicon carbide substrate are insulating rather than conductiv e. Thus, although the silicor_ carbide substrate can be made conductive, some of the preferred buffer layers bet'veen silicon carbide substrates and Group III active layer photonic devices rerr~ain insulating, thus minimizing the advantages of th.e ccnductive silicon carbide substrate.
For example, aluminum nitride (Ally provides an excellent buffer between a silicon carbide substrate and a Group III active layer, particularly a gallium nitride active layer. Aluminum nitride is, however, insulating rather than conductive.
Thus, structures with aluminum nitride buffer layers require shorting contacts that bypass the aluminum nitride buffer to electrically link the conductive silicon carbide substrate to the Group III nitride active layer. As noted above sucr: shorting contacts preclude some of the more advantageous device designs.
Alternatively, conductive buffer Iayer materials such as gallium nitride (GaN), aluminum gallium nitride (AIGaN), or combinations of gallium nitride and aluminum ll:;;V E11 : 1_'- lE)-:3:J : l i::11) : 7U~1:3~W:7a5-~ +4:3 f3;3 "~3:3:3~b~l-EW N t3 .~r ( m a m wru~(n m i ~ mu ~ . v~r muv ~ uv - ~ . vvu ium nitride can eliminate the shorting contacts. In turn, eliminating the shorting tact reduces the epitaxial layer thickness, decreases the number of fabrication steps tired to produce devices, reduces the overall chip size, and increases the device ;iency. Accordingly, Group IrI nitride devices can be produced at lower cost with ;her performance, Nevertheless, although these Conductive buffer materials offer these advantages, their crystal lattice match with silicon carbide is less satisfactory than is that of aluminum nitride. Accordingly, when epitaxial buffer layers of gallium nitride, alurt~inum gallium nitride, or combinations thereof are grown on silicon carbide substrates, they tend to produce excessive cracking in subsequent epilayers that are required for phatonic devices such as light-emitting diodes or laser diodes.
Some devices comprising gallium nitride and silicon carbide substrates are known. Far example,1P-A-b 326 416 discusses a compound semiconductor element utilizing a silicon carbide substrate, a gallium nitride buffer layer and an undoped , gallium aluminum indiurz nitride active layer. However, such a device is incapable of fully utilizing the favorable electronic characteristics of gallium nitride and the gallium niuide buffer layer is subject to cracking, Similarly, WO 9612417 discusses a light emitting semiconductor laser comprising a gallium nitride active layer separated from a silicon carbide substrate by a multilayered buffer that may contain gallium ni tride.
Researchers have proposed various solutions to the cracking problem. For example, WO 9/10950 discusses a method for growing a single crystal, solid orate device onto a mismatched substrate by growing a secondary substrate on the primary i substrate. The secondary substrate is obtained by growing an epilaycr divided into mesas onto the ptzmary substrate followed by annealing. This rrtcthod, however, serves primarily to direct cracking into non-critical areas rather than reduce or eliminate cracking.
3Q EP-A-0 352 472 discusses heteroepitaxy of lattice-mismatched semiconductor materials. In EP-A-0 352-472 a protruding grid is placed on a silicon substrate. A
lattice-mismatched semiconductor material, such as GaAs, is then deposited an both !ly 1) L : i:'- l()-:);i : 15::31) : 704~E5E~7a35-. +.;.J t3:3 _~39:3446p' II
;3 111IL11 JUt~l:~l7 fll ll IIrL~ lU't)YUV1VJ I. VV!
exposed silicon and the protruding grid. This method also serves primarily to ct cracking into non-critical areas rather than reduce or eliminate cracking.
Thus, there exists a need far a buffer structure that offers the crystal lattice :h advantages of aluminum nitride and yet which at the same time offers the conductivity advantages of galliurln nitride or aluminum gallium nitndc and that can be used in conjunction with conductive silicon carbide substrates rather than insulating sapphire substrates, Object and Summar_,y of the Invention Therefore, it is an object of the present invention to produce photonic devices and their wafer precursors, with a Group III nitride active layer, a conductive silicon carbide substrate, and a conductive buffer layer, hut that avoids the cracking and other problems that have to date hindered such combinations of materials and layers.
1 ~ The invention meats this object with a photonic device with a Group IIT
nitride active layer which comprises a silicon carbide substrate, an optoelectronic diode with a Group III nitride active layer, and a buffer structure between the silicon carbide substrate and the optoelectronic diode in which the buffer structure is both conductive;
and which provides the appropriate crystalline properties.
Zd In one aspect, the buffer structure is selected from the Group consisting of gallium nitride and indium gallium nitride (InGaN), and incorporates a stress absorbing structure comprising a plurality of predetermined stress relieving areas within the crystal structure of the buffer layer so that stress induced cracking that occurs in the buffer occurs at the predetermined areas rather than elsewhere in the 25 buffer.
In another aspect, the buffer layer includes a plurality of discrete crystal portions selected from the group consisting of gallium nitride and indium gallium nitride on the surface of the silicon carbide substrate for minimizing or eliminating the heterobarrier between silicon carbide and aluminum gallium nitride buffer structure.
Accordingly, in one aspect of the present invention there is provided a wafer precursor for Group III nitride devices comprising:
a silicon carbide substrate wafer comprising a predetermined pattern of grooves in the surface of said silicon carbide substrate;
a buffer layer on said substrate, said buffer layer selected from the group consisting of gallium nitride and indium gallium nitride; and a plurality of stress-absorbing crystal discontinuities grown within said buffer layer in positions that track said predetermined pattern of grooves in said substrate, so that the minimal degree of stress-induced cracking occurs in said buffer layer along said predetermined pattern rather than elsewhere in said buffer structure.
According to another aspect of the present invention there is provided a wafer precursor for vertically conductive Group III nitride devices comprising:
a silicon carbide substrate wafer comprising a predetermined pattern of stress-absorbing mesa structures formed of a material that is resistive to the growth of a buffer material and a conductively doped buffer layer deposited on the exposed surface of said substrate.
According to yet another aspect of the present invention there is provided a method of producing a Group III nitride optoelectronic device on a silicon carbide substrate comprising:
forming a predetermined pattern of grooves on the surface of a silicon carbide substrate that has otherwise been prepared for crystal growth thereon;
forming a buffer layer selected from the group consisting of gallium nitride and indium gallium nitride on the patterned surface of the silicon carbide substrate so that the buffer layer grows stress-absorbing discontinuities in the crystal structure of the buffer layer that track the predetermined pattern in the surface of the silicon carbide substrate; and forming an optoelectronic device with a Group III nitride active layer on the buffer layer.
-4a-According to still yet another aspect of the present invention there is provided method of producing a Group III nitride optoelectronic device on a silicon carbide substrate comprising:
forming a predetermined pattern of mesa structures on the surface of the silicon carbide substrate from a material that is resistive to the growth of a buffer material;
forming a conductively doped buffer layer on the exposed surface of the silicon carbide substrate; and forming an optoelectronic device with a Group III nitride active layer on the buffer layer.
The foregoing, and other objects and advantages of the invention, and the manner of accomplishing the same will become clearer when taken in conjunction with the accompanying detailed description and drawings in which:
Brief Description of the Drawings Figure 1 is across-sectional view of a prior-art diode with a shorting ring contact;
Figure 2 is a cross-sectional view of a vertical diode that can be produced to the present invention;
Figure 3 is an enlarged schematic view of a pixel formed according to the present invention;
Figure 4 is a schematic view of a display that includes a parality of pixels that incorporates structures according to the present invention;
Figure 5 is a schematic view of a silicon carbide wafer that incorporates the stress relieving structure according to the present invention;
Figure 6 is a cross-sectional view of the wafer of Figure 5;
Figure 7 is a cross-sectional view of the wafer of Figure 5 and showing in schematic view a buffer layer grown thereon;
Figure 8 is a cross-sectional view of a wafer incorporating second embodiment of the invention;
Figure 9 is a cross-sectional view identical to Figure 3 but showing additional crystal growth thereon;
-4b-Figure 10 is a l OX magnification photo from a scanning election microscope (SEM) of an epilayer that does not incorporate the present invention;
Figure 11 is an l OX SEM photo showing an epilayer according to the present invention;
Figure 12 is another I OX SEM photo showing an epilayer according to the present invention;
Figure 13 is a SOX SEM photo of an epilayer similar to Figure 12;
Figure 14 is a 100X SEM photo of an epilayer according to the present invention;
Figure 15 is another 100X SEM photo showing another epilayer that does not incorporate the present invention;
Figures 16, is a 15,OOOX SEM photo of a second embodiment of the invention;
and Figure I7 is a 50,OOOX SEM photo of the second embodiment.
Detailed Description Figure 1 is a cross-sectional view of a prior art device that is broadly designated at 20. As illustrated in Figure I, the device 20 includes a silicon carbide substrate 21, a contact 22 to the "back" of the substrate 21, a Group III
nitride active layer 23, a buffer layer 24 which is insulating rather than conductive, shorting contacts 25 for providing electrical contact between the conductive silicon buffer 21 and the active layer 23, and a top contact 26 for completing the circuit and permitting current to flow through the device in operation.
Figure 2 shows the manner in which the present invertior~ prcvides fer a more compact device. In Figure 2 the device is broadly designated at 30, and includes a .
conductive silicon carbide substrate 3I, a back contact 32, ar: active Layer 33 and a conductive buffer structure 34, along with a top contact 35. The invention thus eliminates the shorting contacts (typically shorting ring contacts) 25 of the device of Figure 1. As a result, the device 30 is easier to manufacture. and more efficient in operation: It will be understood that the active layer 33 as discussed herein can represent a device with a single p-n junction, a single or double p-r.
heterojunction or a p-n junction quantum well structure. Such structures are described in a number of prior U.S. patents including Nos. 5,393,993 and 5,592,501, and will not be otherwise discussed in detail herein other than to further illustrate the present invention.
Figure 3 illustrates that the device 30 according to the present invention can be incorporated with similar devices of different emitting wavelengths, in particular a red emitting diode 36 and a green emitting diode 37, as part of a three-color pixel broadly designated at 40 which in turn canoe one of a plurality of such pixels in a display 41.
The vertical 42 and horizontal 43 lines shown schematically in Figure 4 represent the rows and columns of pixels typically used in displays that incorporate light emitting diodes.
In its first aspect, the invention is a photonic device with a Group III
nitride active layer that comprises a silicon carbide substrate 31, a photonic diode with a Group III nitride active layer 33, and a buffer strucW re 34 selected from the group consisting of gallium nitride and indium gallium r_itride between the silicon carbide substrate 31 and the diode 33. In particular, the buffer structure includes a stress absorbing structure that is made up of a plurality of predetermined stress relieving areas within the crystal structure of the buffer structure 34 so that stress induced cracking that occurs in the buffer structure occurs at the predetermined areas rather than elsewhere in the structure.
Figure 5 is a schematic view of a wafer that incorporates a plurality of device precursors and that incorporates the stress absorbing structure of the present invention. Figure 5 illustrates a wafer broadly designated at 44 on which is superimposed a grid pattern of grooves 45. Figure 6 shows the sam a wafer 44 and grooves 45 in a cross-sectional orientation. When the next epitaxial layer 46 (Figure 7) is grown on the wafer 44 with its grooves 45, the surface of the epitaxial layer 46 tends to have a series of discontinuities 47 whose positions reflect the positions of the grooves 45 that form the pattern in the wafer 44. These discontinuities 47 form areas at which stress will relieve itself as t'r~e crystal lattice structure of the buffer layer 46 grows on the silicon carbide wafer 44. As a result, such stress resulting from lattice mismatches (or other factors) occurs at intended rather than random positions, thus permitting devices to be formed in the remaining areas without significant risk of stress cracking.
As noted above and illustrated in Figure S, in one preferred embodiment the predetermined pattern of stress relieving areas comprises a grid and the.grid can preferably be formed in any desired or necessary size that defines individual devices.
For example, where the individual devices will be light emitting diodes, a preferable grid pattern defines squares of about 250 microns per side. Alternatively, for different devices such as laser diodes, the gr~d can define rectangles of about 250 by microns (~.).
Figure 10 is a SEM photograph taken at a lOX magnification (10 times actual size) that shows the extent to which cracking-seen as the somewhat triangular or hexagonal patterns-can mar an epitaxial layer and render it defective or useless for photonic devices.
Figure I 1 is another lOX SEM photograph and illustrates a grid pattern of grooves in the epitaxial layer. In comparison with Figure I0, the surface shown in Figure 1I is relatively free of cracking defects.
Figure 12 is another l OX SEM photograph, and illustrates a smaller grid pattern. As with Figure I l, it is quite free of the cracks illustrated in Figure 10., Figure 13 is a SOX SEM photograph that paL~ticularly illustrates the advantages of the invention. In Figure 13, one of the grid sections cor_tains a largo defect (in a somewhat "X" shape). The defect ends, however, at the grid line and spoils only one device (or device precursor) rather than a mufti-device portion of the wafer.
Figure 14 is a 100X SEM photograph that similarly illustrates one defective 1 S grid portion (in the lower right portion of the photograph) fcr which the defect ends at the grid line rather than propagating further throughout the surface.
Figure 15 is a 100X SEM photograph that again illustrates a surface that does not incorporate any of the embodiments of the present invention. As with Figure 10, the geometric pattern of defects is quite evident.
In another embodiment, the stress absorbing structure can corr~prise a predetermined pattern of small mesa structures that are best illustrated in Figures 8 and 9. In Figures 8 and 9 the silicon carbide substrate is designated at 50 and the small mesa structures at S I. The mesa structures 51 are formed of a material upon which the growth of the selected buffer material is disfavored. For a gallium nitride or indium gallium nitride buffer structure, the preferred materials are selected from the group consisting of silicon dioxide, silicon nitride, and aluminum oxide.
Figure 9 illustrates the same structure as Figure 8, but with the buffer material grown as an epitaxial layer on the silicon carbide substrate 50. The epitaxial layer porEions are illustrated at 52. As Figure 9 illustrates, because growth of the buffer material is disfavored on the mesas 51, the epitaxial layer 52 forms a pattern which again exhibits predetermined stress-relieving discontinuity stractures therebetween.
As in the previous embodiment, the areas between the mesas can be tailored to be _g_ about the same size as the individual device, which, as noted above, is on the order of about 250 microns for LEDs and about 250 x 500, for Iaser diodes. It will be understood, however, that the particular size of the pattern of either the grids or the mesa.structures is illustrative rather than limiting of the present invention.
It will be understood that although the wafer structures according to the invention are particularly advantageous for optoelectronic devices, they are not limited to such, and the superior structural properties are advantageous for other devices formed upon the wafers.
As noted in the background portion, the optoelectroric device formed upon the I O buffer layer, and as typically illustrated at 23 in Figure 1 and 33' in Figure 2, is generally not a single layer, but rather is a multi-layer diode selected from the group consisting of p-n homojunctions, p-n heterojunctions, p-n single and double heterojunctions, and p-n junction quantum well structures.
In preferred embodiments, the silicon carbide substrate has a polytype selected IS from the group consisting of the 3C, 4H, 6H, and 15R polytypes. In the most preferred embodiments, the Group III nitride active layer of the diode comprises gallium nitride or indium gallium r_itrde.
Figures 16 through 18 illustrate another embodiment of the invention. In general, in schematic fashion, the overall structure is again illustrated by Figure 2 and 20 comprises the silicon carbide substrate 3I, the photonic diode 33 ar_d the buffer layer 34. In this embodiment, however. the buffer layer is aluminum ~aliium nitride rather than gallium nitride or indium gallium nitride. This embodiment ir~cluu'es a plurality of discrete crystal portions that appear as the white colored dots ir~ Figure 16-18. The discrete crystal portions are selected from the group of gallium nitride and indium 25 gallium nitride and are on the surface of the silicon carbide substrate for minimizing or eliminating the heterobarrier between the silicon carbide substrate 3I and the aluminum gallium nitride buffer structure 34.
In preferred embodiments, the discrete crystal portions are present in an amount sufficient to minimize or eliminate the heterobarrier but Iess than the amount 30 that would detrimentally affect or destroy the fanction ef any resul ring diode device built on the silicon carbide substrate 31. As illustrated in the photographs of Figures 16-18 the discrete crystal portions are present in an amount ef between about 40 and 60 per square micron.
Additionally, the sizes of the discrete crystal portions are preferably large enough to minimize or eliminate the heterobar~ier, but smaller than a size that would detrimentally affect or destroy the fi_:nction of any resulting diode device built on the silicon carbide substrate 31. In preferred embodiments, the discrete crystal portions are between 0.01 and 0.1 microns in diameter.
As in the previous embodiments, the optoelectronic device 33 formed on the buffer structure can comprise a light emitting diode or Iaser diode, and the resulting light emitting diode can be incorporated into pixels which in t~:rn can be incorporated into displays.
In preferred embodiments, the aluminum gallium nitride buffer layer has an atomic fraction of aluminum of between about 10 and 15%.
In another aspect, the invention comprises the method of producing the Group III nitride optoelectronic device on a silicon carbide substrate with a conductive buffer structure. In its method aspects, the invention comprises forming a structural pattern on the surface of a silicon carbide substrate that has otherwise been prepared for crystal growth thereon; forming a buffer layer selected from the group consisting of gallium nitride and indium. gallium r_itride on the patterned surface of the silicon carbide substrate so that the buffer layer exhibits features that follow the pattern of openings in the surface of the silicon carbide substrate; and thereafter forming a optoelectronic device with a Group III nitride active layer on the buffer layer.
As described with respect to the structural aspects, the step of forming the structural pattern can comprise forming a pattern of openings in the surface of the silicon carbide substrate or forming a pattern of mesa struct~.xes on the surface of the silicon carbide substrate.
When the pattern is formed of openings, the step of forming the openings can comprise techniques such as reactive ion etching or masking and etching steps.
Each of these steps is relatively well understood for silicon carbide and will not be otherwise described except to note, for example, U.S. Patents Nos. 4,865,685 and 4,981,551 describe exemplary dry etching procedures for silicon carbide.
Where the mesa structures are incorporated, they are preferably selected from the group consisting of silicon dioxide, silicon nitride, and aluminum oxide.
As in the structural environments, the optoelectronic device with the Group III active layer is preferably formed of gallium nitride or indium gallium r_itride.
S As in the structural embodiments, the method of the invention can comprise forming a light emitting diode or a Laser diode, and when a Iiaht emitting is formed, the method can further comprise incorporating the LED into a pixel, and the pixel into a display.
In an alternative method aspect, the buffer structure of the invention structure is formed of aluminum gallium nitride on a silicon carbide substrate that has been previously prepared by forming a plurality of discrete crystal portions selected from the group consisting of gallium nitride and indium gallium nitride on the silicon carbide surface. Thereafter, the optoelectronic device with the Group III
nitride active layer is formed on the buffer layer.
As set forth in the structural aspects of the invention, the method comprises forming discrete crystal portions of a size and in an amount that is sufficient to minimize or eliminate the heterobarrier, but less than sizes or amounts that would detrimentally affect or destroy the function of any resulting diode device built on the silicon carbide substrate: In particular the invention provides a robust structure that can withstand normally expected levels of electrostatic discharge.
In the second method aspect, the resulting device can be formed as a Light emitting diode so that the method can further comprise incorporating the LED
pixel and the pixel into a display. The method.can alternatively comprise forning a laser diode rather than an LED.
As in the other aspects of the invention, when the aluminum gallium nitride buffer Layer is used, it is preferably has an atomic fraction of aluminum of between about 10 and 15%.
EXAMPLE
In a current process for producing conductive buffer LEDs and Laser Diodes, GaN dots are first deposited. The purpose of the GaN dots is to decrease the barrier between the SiC substrate and the Si-doped AlGa..N buffer Layer. This is done at considerably lower temperatures than are used for the other epitaxial layers in the structure. The size and density of the dots are shown in Figures 16 and I7: It is important to keep the dots relatively small so the electrostatic discharge will not be adversely affected. The GaN dots are deposited in about 6 seconds, and then "capped" with Si-doped Al,ta Ga.9~N for about i5 seconds. The purpose of this cap is to prevent the dissociation of the GuN dots upon heating. In this material system, adding any Al to GaN, i.e., Ahl_~~Ga~~~N decreases the dissociation rate of the material because AIGaN is more stable than GaN in an NH3/HZ atmosphere. After the capping of the dots; the temperature is then ramped up to the buffer Iayer temperature.
Temperatures are allowed to stabilize for 2 minutes after the ral-np before commencing buffer layer growth.
In a specific run, a SiC wafer is heated in an atmosphere ef NH3 and H2, at I3 SLM and 15 SLM, respectively. These flows remain constant throughout the growth of the GaN dots, the AlGaN cap, and the subsequent buffer layer. The temperature ramps up over the course of 10 minutes until the GaN dot temperat~.sre is reached which is about 960°C. After allowing the temperature in the system to stabilize for approximately 5 minutes, the dots are deposited by flowing 10 -l5cc of trimethyl gallium (TMG; -5°C, 600 torr) for about 6 seconds. In order to ensure that the dots are conducting, SiHa is also added with the TMG flow. The amount of SiH a is determined by growing a bulk GaN Iayer with a carrier concentration of about 1 x 1018 cm 3. Immediately following the deposition of the GaI~T dots, the TMG and SiHc continue to flow, but now with the addition of trimethyl aluminum (TMA, 92cc, 25°C, 600 ton). This leads to a "cap" of about IO-I l% AlGaN. The growth time of the cap is 15 seconds. The flows (TMG, TMA, and SiH4) are then terminated and the temperature is ramped to the buffer temperature which is typically around 1060°C.
The temperature ramp is I minute and is followed by a 2 minute period during which the temperature is allowed to stabilize. The buffer layer is then grown.
Typical conditions are l8cc TMG/1 I OccTMA/ .087cc SiH4. Buffer layers consist of approximately I 1-12% AIGaN and are typically between about 1600 and 2700 t~
thick.
In the drawings and specification, there have been disclosed typical embodiments of the invention, and, although specific terms have been employed, they have been used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set ford: in the following claims.
Claims (22)
1. A wafer precursor for Group III nitride devices comprising:
a silicon carbide substrate wafer comprising a predetermined pattern of grooves in the surface of said silicon carbide substrate;
a buffer layer on said substrate, said buffer layer selected from the group consisting of gallium nitride and indium gallium nitride; and a plurality of stress-absorbing crystal discontinuities grown within said buffer layer in positions that track said predetermined pattern of grooves in said substrate, so that the minimal degree of stress-induced cracking occurs in said buffer layer along said predetermined pattern rather than elsewhere in said buffer structure.
a silicon carbide substrate wafer comprising a predetermined pattern of grooves in the surface of said silicon carbide substrate;
a buffer layer on said substrate, said buffer layer selected from the group consisting of gallium nitride and indium gallium nitride; and a plurality of stress-absorbing crystal discontinuities grown within said buffer layer in positions that track said predetermined pattern of grooves in said substrate, so that the minimal degree of stress-induced cracking occurs in said buffer layer along said predetermined pattern rather than elsewhere in said buffer structure.
2. A wafer precursor according to claim 1 wherein said predetermined pattern is selected from the group consisting of a grid that defines squares of about 250 microns per side; and a grid that defines rectangles of about 250 by 500 microns.
3. An optoelectronic device formed from the wafer precursor of claim 2 comprising an optoelectronic diode with a Group III nitride active layer.
4. An optoelectronic device according to claim 3 wherein said diode is selected from the group consisting of p-n homojunctions, p-n single and double heterojunctions, and p-n quantum junction well structures, and said silicon carbide substrate has a polytype selected from the group consisting of the 3C, 4H, 6H, and 15R polytypes.
5. An optoelectronic device according to claim 3 wherein said Group III
nitride active layer is selected from the group consisting of gallium nitride and indium gallium nitride.
nitride active layer is selected from the group consisting of gallium nitride and indium gallium nitride.
6. A wafer precursor for vertically conductive Group III nitride devices comprising:
a silicon carbide substrate wafer comprising a predetermined pattern of stress-absorbing mesa structures formed of a material that is resistive to the growth of a buffer material and a conductively doped buffer layer deposited on the exposed surface of said substrate.
a silicon carbide substrate wafer comprising a predetermined pattern of stress-absorbing mesa structures formed of a material that is resistive to the growth of a buffer material and a conductively doped buffer layer deposited on the exposed surface of said substrate.
7. A wafer precursor according to claim 6 wherein said material that is resistive to the growth of buffer material is selected from the group consisting of silicon dioxide (SiO2), silicon nitride and aluminum oxide.
8. A wafer precursor according to claim 6 wherein said buffer layer is selected from the group consisting of gallium nitride and indium gallium nitride.
9. An optoelectronic device formed from the wafer precursor of claim 6 and further comprising an optoelectronic diode with a Group III nitride active layer.
10. An optoelectronic device according to claim 9 wherein said diode is selected from the group consisting of p-n homojunctions, p-n single and double heterojunctions, and p-n quantum junction well structures, and said silicon carbide substrate has a polytype selected from the group consisting of the 3C, 4H, 6H, and 15R polytypes.
11. An optoelectronic device according to any one of claims 3 and 9 wherein said Group III nitride active layer is selected from the group consisting of gallium nitride and indium gallium nitride.
12, An optoelectronic device according to Claim 3 or 9 comprising a light emitting diode.
13. A pixel that incorporates a light emitting diode according to Claim 12.
14. A display that incorporates a plurality of pixels according to Claim 13.
15. An optoelectronic device according to any one of Claims 3 and 9 comprising a laser diode.
16. A method of producing a Group III nitride optoelectronic device on a silicon carbide substrate comprising:
forming a predetermined pattern of grooves on the surface of a silicon carbide substrate that has otherwise been prepared for crystal growth thereon;
forming a buffer layer selected from the group consisting of gallium nitride and indium gallium nitride on the patterned surface of the silicon carbide substrate so that the buffer layer grows stress-absorbing discontinuities in the crystal structure of the buffer layer that track the predetermined pattern in the surface of the silicon carbide substrate; and forming an optoelectronic device with a Group III nitride active layer on the buffer layer.
forming a predetermined pattern of grooves on the surface of a silicon carbide substrate that has otherwise been prepared for crystal growth thereon;
forming a buffer layer selected from the group consisting of gallium nitride and indium gallium nitride on the patterned surface of the silicon carbide substrate so that the buffer layer grows stress-absorbing discontinuities in the crystal structure of the buffer layer that track the predetermined pattern in the surface of the silicon carbide substrate; and forming an optoelectronic device with a Group III nitride active layer on the buffer layer.
17. A method according to Claim 16 wherein the step of forming the grooves comprises masking the surface of the silicon carbide substrate and thereafter etching the surface to produce the pattern.
18. A method according to Claim 16 wherein the step of forming an optoelectronic device with a Group III nitride active layer comprises forming a device with an active layer selected from the group consisting of gallium nitride and indium gallium nitride.
19. A method of producing a Group III nitride optoelectronic device on a silicon carbide substrate comprising:
forming a predetermined pattern of mesa structures on the surface of the silicon carbide substrate from a material that is resistive to the growth of a buffer material;
forming a conductively doped buffer layer on the exposed surface of the silicon carbide substrate; and;
forming an optoelectronic device with a Group III nitride active layer on the buffer layer.
forming a predetermined pattern of mesa structures on the surface of the silicon carbide substrate from a material that is resistive to the growth of a buffer material;
forming a conductively doped buffer layer on the exposed surface of the silicon carbide substrate; and;
forming an optoelectronic device with a Group III nitride active layer on the buffer layer.
20. A method according to claim 19 wherein said material that is resistive to the growth of a buffer material is selected from the group consisting of silicon dioxide, silicon nitride, and aluminum oxide.
21. A method according to claim 19 wherein said buffer material is selected from the group consisting of gallium nitride and indium gallium nitride.
22. A method according to Claim 19 wherein the step of forming an optoelectronic device with a Group III nitride active layer comprises forming a device with an active layer selected from the group consisting of gallium nitride and indium gallium nitride.
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US08/944,547 | 1997-10-07 | ||
PCT/US1998/021160 WO1999018617A1 (en) | 1997-10-07 | 1998-10-06 | Group iii nitride photonic devices on silicon carbide substrates with conductive buffer interlayer structure |
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CA002305203A Expired - Fee Related CA2305203C (en) | 1997-10-07 | 1998-10-06 | Group iii nitride photonic devices on silicon carbide substrates with conductive buffer interlayer structure |
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US (5) | US6201262B1 (en) |
EP (1) | EP1027736A1 (en) |
JP (2) | JP4061019B2 (en) |
KR (1) | KR100592897B1 (en) |
CN (1) | CN1185719C (en) |
AU (1) | AU9689098A (en) |
CA (1) | CA2305203C (en) |
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US6825501B2 (en) * | 1997-08-29 | 2004-11-30 | Cree, Inc. | Robust Group III light emitting diode for high reliability in standard packaging applications |
US6201262B1 (en) * | 1997-10-07 | 2001-03-13 | Cree, Inc. | Group III nitride photonic devices on silicon carbide substrates with conductive buffer interlay structure |
US6459100B1 (en) * | 1998-09-16 | 2002-10-01 | Cree, Inc. | Vertical geometry ingan LED |
-
1997
- 1997-10-07 US US08/944,547 patent/US6201262B1/en not_active Expired - Lifetime
-
1998
- 1998-10-06 JP JP2000515300A patent/JP4061019B2/en not_active Expired - Lifetime
- 1998-10-06 AU AU96890/98A patent/AU9689098A/en not_active Abandoned
- 1998-10-06 KR KR1020007003789A patent/KR100592897B1/en not_active IP Right Cessation
- 1998-10-06 WO PCT/US1998/021160 patent/WO1999018617A1/en active IP Right Grant
- 1998-10-06 CN CNB988110652A patent/CN1185719C/en not_active Expired - Lifetime
- 1998-10-06 CA CA002305203A patent/CA2305203C/en not_active Expired - Fee Related
- 1998-10-06 EP EP98950987A patent/EP1027736A1/en not_active Withdrawn
-
1999
- 1999-09-20 US US09/399,445 patent/US6187606B1/en not_active Expired - Lifetime
-
2000
- 2000-11-22 US US09/718,654 patent/US6373077B1/en not_active Expired - Lifetime
- 2000-11-22 US US09/718,958 patent/US6492193B1/en not_active Expired - Lifetime
-
2001
- 2001-09-28 US US09/966,789 patent/US6630690B2/en not_active Expired - Lifetime
-
2006
- 2006-12-26 JP JP2006349833A patent/JP4966645B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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WO1999018617A1 (en) | 1999-04-15 |
CA2305203A1 (en) | 1999-04-15 |
US6201262B1 (en) | 2001-03-13 |
EP1027736A1 (en) | 2000-08-16 |
JP2007180556A (en) | 2007-07-12 |
JP4966645B2 (en) | 2012-07-04 |
US6492193B1 (en) | 2002-12-10 |
US6187606B1 (en) | 2001-02-13 |
JP2001519603A (en) | 2001-10-23 |
JP4061019B2 (en) | 2008-03-12 |
US6630690B2 (en) | 2003-10-07 |
US20020008241A1 (en) | 2002-01-24 |
CN1185719C (en) | 2005-01-19 |
KR100592897B1 (en) | 2006-06-23 |
AU9689098A (en) | 1999-04-27 |
US6373077B1 (en) | 2002-04-16 |
KR20010031003A (en) | 2001-04-16 |
CN1278949A (en) | 2001-01-03 |
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