CA2312646A1 - Hybrid micropackaging of microdevices - Google Patents

Hybrid micropackaging of microdevices Download PDF

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Publication number
CA2312646A1
CA2312646A1 CA002312646A CA2312646A CA2312646A1 CA 2312646 A1 CA2312646 A1 CA 2312646A1 CA 002312646 A CA002312646 A CA 002312646A CA 2312646 A CA2312646 A CA 2312646A CA 2312646 A1 CA2312646 A1 CA 2312646A1
Authority
CA
Canada
Prior art keywords
microdevices
hybrid
micropackaging
wafer
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002312646A
Other languages
French (fr)
Inventor
Hubert Jerominek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institut National dOptique
Original Assignee
Institut National dOptique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institut National dOptique filed Critical Institut National dOptique
Priority to CA002312646A priority Critical patent/CA2312646A1/en
Priority to US09/888,713 priority patent/US6686653B2/en
Priority claimed from US09/888,713 external-priority patent/US6686653B2/en
Priority to PCT/CA2001/000939 priority patent/WO2002001633A1/en
Priority to EP01949152A priority patent/EP1295335B1/en
Priority to DE60103401T priority patent/DE60103401D1/en
Priority to CA002410430A priority patent/CA2410430C/en
Priority to AU2001270396A priority patent/AU2001270396A1/en
Publication of CA2312646A1 publication Critical patent/CA2312646A1/en
Priority to US10/304,172 priority patent/US7077969B2/en
Abandoned legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0077—Other packages not provided for in groups B81B7/0035 - B81B7/0074
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Description

Hybrid Micropackaging of Microdevices A new approach to vacuum packaging of various microdevices, including bolometric FPAs, is being presented. This new, very small-size package structure consists of a central piece of machined ceramic or metal to which a small size window made of glass; ZnSe, Si or (3e and a microdevice in a die form are being attached using, for example, a soldering technique. The central part is equipped with a microchamber and a pump-out opening.
When the process of attaching the die and the window is completed, the air is pumped out from the microchamber via the opening and the opening is subsequently plugged.
Physical vapor deposition of the plugging material is suggested. Each die can be packaged separately and each package can be equipped with a dedicated application oriented window. Machinable ceramic materfals, such as Macor, are suggested for the package central part. The die is attached to the central part via a miniature spacer structure which can be produced by machining, electroplating or thin film deposition. This spacer is covered with the solder material.
In a different embodiment, the central package parts are machined in a ceramic wafer.
Then several possibly different windows are attached to the wafer.
Subsequently, the individual dies are attached to this wafer vis-~-vis the windows and the wafer, serving as a tray for the windows and the dies, is sawed into individual packaged devices.
Again, in a different embodiment, the central package parts are machined in a ceramic wafer and then the windows are attached to the ceramic wafer. The ceramic wafer is then attached to a semiconductor wafer in which the individual microdevices or dies have been previously produced. The semiconductor wafer is not sawed but it is in one piece. After attaching of the ceramic wafer to the semiconductor wafer, the vacuum pumping and the sealing operation is being performed on all devices. Then, the semiconductor and the ceramic wafers are sawed into separate individually vacuum packaged devices.
In each of the described embodiments, the semiconductor die is equipped with standard bonding pads or through-holes connected to bonding pads placed on the opposite surface of the die. In the first case, after completion of the packaging process, the packaged devices are connected to external electronics, typically using a standard wire bonding technique. In the case of the through-hole, the packaged device can be directly soldered to external electronics. Instead of producing the conducting through-holes in the semiconductor die, they can be produced in the ceramic central piece of the package.
These metallzed through-holes have to be connected by soldering or other methods to the bonding pads of the semiconductor die.
In each of the described embodiments, if a thermo-electric cooler is being used, it is placed outside the package attached directly to the packaged microdevice.
The hybrid micropackaging method and stnrctures are presented in the enclosed Figures.

Claims
CA002312646A 2000-06-28 2000-06-28 Hybrid micropackaging of microdevices Abandoned CA2312646A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
CA002312646A CA2312646A1 (en) 2000-06-28 2000-06-28 Hybrid micropackaging of microdevices
US09/888,713 US6686653B2 (en) 2000-06-28 2001-06-25 Miniature microdevice package and process for making thereof
PCT/CA2001/000939 WO2002001633A1 (en) 2000-06-28 2001-06-27 Miniature microdevice package and process for making thereof
EP01949152A EP1295335B1 (en) 2000-06-28 2001-06-27 Miniature microdevice package and process for making same
DE60103401T DE60103401D1 (en) 2000-06-28 2001-06-27 MINIATURE PACKAGING FOR MICRO DEVICES AND METHOD FOR THE PRODUCTION THEREOF
CA002410430A CA2410430C (en) 2000-06-28 2001-06-27 Miniature microdevice package and process for making thereof
AU2001270396A AU2001270396A1 (en) 2000-06-28 2001-06-27 Miniature microdevice package and process for making thereof
US10/304,172 US7077969B2 (en) 2000-06-28 2002-11-25 Miniature microdevice package and process for making thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US21443400P 2000-06-28 2000-06-28
CA002312646A CA2312646A1 (en) 2000-06-28 2000-06-28 Hybrid micropackaging of microdevices
US09/888,713 US6686653B2 (en) 2000-06-28 2001-06-25 Miniature microdevice package and process for making thereof
US10/304,172 US7077969B2 (en) 2000-06-28 2002-11-25 Miniature microdevice package and process for making thereof

Publications (1)

Publication Number Publication Date
CA2312646A1 true CA2312646A1 (en) 2001-12-28

Family

ID=29407855

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002312646A Abandoned CA2312646A1 (en) 2000-06-28 2000-06-28 Hybrid micropackaging of microdevices

Country Status (5)

Country Link
US (1) US7077969B2 (en)
EP (1) EP1295335B1 (en)
AU (1) AU2001270396A1 (en)
CA (1) CA2312646A1 (en)
WO (1) WO2002001633A1 (en)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN112701211A (en) * 2020-12-29 2021-04-23 上海烨映微电子科技股份有限公司 Infrared thermopile packaging structure and method

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WO2003093167A1 (en) * 2002-04-29 2003-11-13 Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung Device for protecting a chip and method for operating a chip
US7276798B2 (en) * 2002-05-23 2007-10-02 Honeywell International Inc. Integral topside vacuum package
FR2841380A1 (en) * 2002-06-25 2003-12-26 Commissariat Energie Atomique Encapsulation of an object under a controlled atmosphere in a cavity provided with a vent that is stopped with a porous material prior to final sealing
US7274094B2 (en) * 2002-08-28 2007-09-25 Micron Technology, Inc. Leadless packaging for image sensor devices
US6872319B2 (en) * 2002-09-30 2005-03-29 Rockwell Scientific Licensing, Llc Process for high yield fabrication of MEMS devices
JP4342174B2 (en) 2002-12-27 2009-10-14 新光電気工業株式会社 Electronic device and manufacturing method thereof
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EP1796707B1 (en) * 2004-09-07 2011-12-28 The Burnham Institute Peptides that selectively home to heart vasculature and related conjugates and methods
FR2879184B1 (en) * 2004-12-15 2007-03-09 Commissariat Energie Atomique DEVICE AND METHOD FOR HERMETICALLY CLOSING A CAVITY OF AN ELECTRONIC COMPOUND.
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KR20080048492A (en) * 2005-08-24 2008-06-02 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Light emitting diodes and lasers diodes with color converters
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Publication number Priority date Publication date Assignee Title
CN112701211A (en) * 2020-12-29 2021-04-23 上海烨映微电子科技股份有限公司 Infrared thermopile packaging structure and method
CN112701211B (en) * 2020-12-29 2023-04-28 上海烨映微电子科技股份有限公司 Infrared thermopile packaging structure and method

Also Published As

Publication number Publication date
US7077969B2 (en) 2006-07-18
EP1295335A1 (en) 2003-03-26
EP1295335B1 (en) 2004-05-19
US20030111441A1 (en) 2003-06-19
AU2001270396A1 (en) 2002-01-08
WO2002001633A1 (en) 2002-01-03

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