CA2313583C - Integrated pc card host controller for the detection and operation of a plurality of expansion cards - Google Patents
Integrated pc card host controller for the detection and operation of a plurality of expansion cards Download PDFInfo
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- CA2313583C CA2313583C CA002313583A CA2313583A CA2313583C CA 2313583 C CA2313583 C CA 2313583C CA 002313583 A CA002313583 A CA 002313583A CA 2313583 A CA2313583 A CA 2313583A CA 2313583 C CA2313583 C CA 2313583C
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S439/00—Electrical connectors
- Y10S439/945—Adapter for pcb or cartridge
Abstract
An integrated controller for the detection and operation of both PC Cards, smart cards and passive smart card adapter cards. In one aspect, the invention detects the presence of standard expansion cards or passive smart card adapters 18 by utilizing the reserved detection and voltage selection signal area defined by the PC Card specification. In another aspect, the invention provides an integrated controller that includes logic to operate either a standard expansion card or a passive smart card adapter by reassigning certain PC Card signal lines to operate a standard expansion card or a passive smart card adapter, thereby eliminating the need to provide pins in addition to those defined by the PC Card specification.
Description
3 The present invention relates to an integrated controller for the detecting and 4 operating one or more expansion cards. More specifically, the present invention relates to an integrated controller for detecting and controlling PC Cards (16-bit 6 PCMCIA cards and 32 bit-CardBus cards), and smart cards. Particular utility of the 7 present invention is to provide an integrated controller for mobile computing devices, 8 e.g., laptop computers, etc, although other utilities are contemplated herein.
9 The need for security and enhanced privacy is increasing as electronic forms of identification replace face-to-face and paper-based ones. The emergence of the 11 global Internet, and the expansion of the corporate network to include access by 12 customers and suppliers from outside the firewall, have accelerated the demand for 13 solutions based on public-key technology. A few examples of the kinds of services 14 that public key technologies enable are secure channel communications over a public network, digital signatures to ensure image integrity and confidentiality, and 16 authentication of a client to a server (and visa-versa).
17 Smart cards are a key component of the public-key infrastructure that 18 Microsoft is integrating into the Windows platform because smart cards enhance 19 software-only solutions such as client authentication, logon, and secure, e-mail. Smart cards are essentially a convergence point for public key certificates and associated 21 keys because they provide tamper-resistant storage for protecting private keys and 22 other forms of personal information; isolate security-critical computations involving 23 authentication, digital signatures, and key exchange from other parts of the system 24 that do not have a "need to know"; and enable portability of credentials and other private information between computers at work, home, or on the road.
26 It is estimated that the smart card will become an integral part of the Windows 27 platform because smart cards will enable new breeds of applications in the same 28 manner that the mouse and CD-ROM did when they were first integrated with the 29 Personal Computer (PC). Incompatibility among applications, cards, and readers has been a major reason for the slow adoption of smart cards outside of Europe.
31 Interoperability among different vendors' products is a necessary requirement to 32 enable broad consumer acceptance of smart cards, and for corporations to deploy 1 smart cards for use within the enterprise.
2 ISO 7816, EMV, and GSM
3 In order to promote interoperability among smart cards and readers, the 4 International Standards Organization (ISO) developed the ISO 7816 standards for integrated circuit cards with contacts. These specifications focused on interoperability 6 at the physical, electrical, and data-link protocol levels. In 1996, Europay, 7 MasterCard, and VISA (EMV) defined an industry-specific smart card specification 8 that adopted the ISO 7816 standards and defined some additional data types and 9 encoding rules for use by the financial services industry. The European telecommunications industry also embraced the ISO 7816 standards for their Global 11 System for Mobile communications (GSM) smart card specification to enable 12 identification and authentication of mobile phone users.
13 While all of these specifications (ISO 7816, EMV, and GSM) were a step in 14 the right direction, each was either too low-level or application-specific to gain broad industry support. Application interoperability issues such as device-independent APIs, 16 developer tools, and resource sharing were not addressed by any of these 17 specifications.
18 PC/SC Workgroup 19 The PC/SC (Personal Computer/Smart Card) Workgroup was formed in May 1996 in partnership with major PC and smart card companies: Groupe Bull, Hewlett-21 Packard, Microsoft, Schlumberger, and Siemens Nixdorf. The main focus of the 22 workgroup has been to develop specifications that solve the previously mentioned 23 interoperability problems. T he PC/SC specifications are based on the ISO
24 standards and are compatible with both the EMV and GSM industry-specific specifications. By virtue of the companies involved in the PC/SC Workgroup, there is 26 broad industry support for the specifications and a strong desire to move them onto an 27 independent-standards tract in the future.
28 Since its founding and initial publication of the specifications, additional 29 members have joined the PC/SC Workgroup. New members include Gemplus, IBM, Sun Microsystems, Toshiba, and Verifone.
1 Microsoft's Approach 2 Microsoft's approach consists of the following:
3 = A standard model for interfacing smart card readers and cards with PCs 4 = Device-independent APIs for enabling smart card-aware applications = Faniiliar tools for software development 6 = Integration with Windows and Windows NT platforms 7 Having a standard model for how readers and cards interface with the PC
8 enforces interoperability among cards and readers from different manufacturers.
9 Device-independent APIs serves to insulate application developers from differences between current and future implementations. Device-independence also preserves 11 software development costs by avoiding application obsolescence due to underlying 12 hardware changes.
13 The most popular method currently being used to interface a smart card with a 14 notebook computer is to use a PCMCIA Type II smart card reader/writer (Figure 1).
PCMCIA smart card readers are currently available from companies such as Gemplus, 16 SCM Microsystems and Tritheim Technologies, to name a few. The end user cost for 17 these smart card readers is typically around $150 US. The cost of the reader is a 18 major portion to the cost of the overall security solution. The adapter card 104 in 19 Figure 1 depicts the major functional blocks of a conventional smart card reader. The PCIC Host Interface block of the smart card reader provides the electrical interface to 21 the PC Card connector (106 , which in turn connects to the PC Card controller 102.
22 Additional logic is provided to control the interaction between the smart card and the 23 software application. However, as noted above, this solution carries a significant per 24 unit cost, and thus, is an unattractive alternative to large-scale migration to smart card compatibility.
26 Thus, there exists a need to provide an integrated host controller that provides 27 PC Card, smart card, and Passive smart card adapter operability. Moreover, there 28 exists a need to provide an integrated controller that can replace existing 29 motherboard-mounted PC Card host controllers, without having to retool or redesign the motherboard.
1 Accordingly, one object of the present invention is to provide an integrated PC
2 Card and Smart card controller suitable to replace conventional PC Card controllers 3 for integration into current PC motherboard technology.
4 It is another object to provide a controller as above that is simultaneously fully compatible with PC Card specifications.
6 It is still another object to provide a Smart card controller, as above, that has 7 an identical pinout arrangement as existing PC Card controllers, thereby permitting 8 the controller to be directly integrated onto a PC motherboard without redesigning 9 and/or retooling costs.
It is another object of the present invention to provide logic and methodology 11 to detect the presence of a smart card or a Passive smart card adapter utilizing existing 12 PC Card specified signals.
13 In one aspect, the present invention provides a method of detecting the 14 presence of an expansion card using conventional PC Card specification signal lines, during the initial card detection sequence. The method comprising the steps of 16 determining the signal state of a first and second card detection signal lines;
17 determining the signal state of a first and second voltage select signal lines;
18 determining if said first and/or second card detection signal lines, or said first and/or 19 second voltage select signal lines, comprise a signal state that is reserve,d by a PC
Card signal specification; and determining the signal state of a predetermined unused 21 PC Card signal line, relative to said reserved signal state. During the card detection 22 sequence the status change signal (STSCHG) is used to detect a smart card or a smart 23 card adapter. After the detection sequence is completed the STSCHG signal has the 24 original uses based on the PC Card specification for signal definition.
Also, in the preferred embodiment, this process determines the presence of a smart card or a 26 Passive smart card adapter by determining whether said first card detection signal and 27 said second voltage select signals are tied together.
28 In logic form, the present invention provides a device to detect the presence of 29 an expansion card using conventional PC Card specification signal lines, comprising a state machine including a lookup table and a plurality of logic sets, each said logic 31 sets operable to interface with a certain predefined expansion card type, said state 1 machine accepting as input signals a plurality of predetermined card detection and 2 voltage selection signals, and an additional signal, and coupling an appropriate one of 3 said logic sets to an appropriate one of said expansion cards based on a match 4 between said input signals and said lookup table.
In another aspect, the present invention provides an integrated circuit for the 6 detection and operation of a plurality of expansion cards, comprising, a first logic set 7 for detecting and operating a plurality of expansion card types, said first logic set 8 having predetermined signal lines and a pinout arrangement defined by PC
Card 9 specifications, and a second logic set for detecting and operating a smart card, wherein said first and second logic being incorporated into a single controller without 11 requiring additional pinouts. In the preferred embodiment, the second logic set is 12 adapted to reassign certain ones of said predetermined signal lines to detect and 13 operate said smart card , so that additional pins are not required.
14 It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to preferred 16 embodiments and methods of use, the present invention is not intended to be limited 17 to these preferred embodiments and methods of use. Rather, the present invention is 18 of broad scope and is intended to be limited as only set forth in the accompanying 19 claims.
Other features and advantages of the present invention will become apparent 21 as the following Detailed Description proceeds, and upon reference to the Drawings, 22 wherein like numerals depict like parts, and wherein:
23 Figure 1 depicts a block diagram of a conventional solution to incorporate 24 smart card operability for PC applications;
Figure 2 is a system-level block diagram of the integrated smart card reader of 26 the present invention;
27 Figure 3 is a detailed block diagram of the integrated Smart card reader of the 28 present invention;
29 Figure 4 is a state machine block diagram of the integrated Smart card reader of the present invention;
9 The need for security and enhanced privacy is increasing as electronic forms of identification replace face-to-face and paper-based ones. The emergence of the 11 global Internet, and the expansion of the corporate network to include access by 12 customers and suppliers from outside the firewall, have accelerated the demand for 13 solutions based on public-key technology. A few examples of the kinds of services 14 that public key technologies enable are secure channel communications over a public network, digital signatures to ensure image integrity and confidentiality, and 16 authentication of a client to a server (and visa-versa).
17 Smart cards are a key component of the public-key infrastructure that 18 Microsoft is integrating into the Windows platform because smart cards enhance 19 software-only solutions such as client authentication, logon, and secure, e-mail. Smart cards are essentially a convergence point for public key certificates and associated 21 keys because they provide tamper-resistant storage for protecting private keys and 22 other forms of personal information; isolate security-critical computations involving 23 authentication, digital signatures, and key exchange from other parts of the system 24 that do not have a "need to know"; and enable portability of credentials and other private information between computers at work, home, or on the road.
26 It is estimated that the smart card will become an integral part of the Windows 27 platform because smart cards will enable new breeds of applications in the same 28 manner that the mouse and CD-ROM did when they were first integrated with the 29 Personal Computer (PC). Incompatibility among applications, cards, and readers has been a major reason for the slow adoption of smart cards outside of Europe.
31 Interoperability among different vendors' products is a necessary requirement to 32 enable broad consumer acceptance of smart cards, and for corporations to deploy 1 smart cards for use within the enterprise.
2 ISO 7816, EMV, and GSM
3 In order to promote interoperability among smart cards and readers, the 4 International Standards Organization (ISO) developed the ISO 7816 standards for integrated circuit cards with contacts. These specifications focused on interoperability 6 at the physical, electrical, and data-link protocol levels. In 1996, Europay, 7 MasterCard, and VISA (EMV) defined an industry-specific smart card specification 8 that adopted the ISO 7816 standards and defined some additional data types and 9 encoding rules for use by the financial services industry. The European telecommunications industry also embraced the ISO 7816 standards for their Global 11 System for Mobile communications (GSM) smart card specification to enable 12 identification and authentication of mobile phone users.
13 While all of these specifications (ISO 7816, EMV, and GSM) were a step in 14 the right direction, each was either too low-level or application-specific to gain broad industry support. Application interoperability issues such as device-independent APIs, 16 developer tools, and resource sharing were not addressed by any of these 17 specifications.
18 PC/SC Workgroup 19 The PC/SC (Personal Computer/Smart Card) Workgroup was formed in May 1996 in partnership with major PC and smart card companies: Groupe Bull, Hewlett-21 Packard, Microsoft, Schlumberger, and Siemens Nixdorf. The main focus of the 22 workgroup has been to develop specifications that solve the previously mentioned 23 interoperability problems. T he PC/SC specifications are based on the ISO
24 standards and are compatible with both the EMV and GSM industry-specific specifications. By virtue of the companies involved in the PC/SC Workgroup, there is 26 broad industry support for the specifications and a strong desire to move them onto an 27 independent-standards tract in the future.
28 Since its founding and initial publication of the specifications, additional 29 members have joined the PC/SC Workgroup. New members include Gemplus, IBM, Sun Microsystems, Toshiba, and Verifone.
1 Microsoft's Approach 2 Microsoft's approach consists of the following:
3 = A standard model for interfacing smart card readers and cards with PCs 4 = Device-independent APIs for enabling smart card-aware applications = Faniiliar tools for software development 6 = Integration with Windows and Windows NT platforms 7 Having a standard model for how readers and cards interface with the PC
8 enforces interoperability among cards and readers from different manufacturers.
9 Device-independent APIs serves to insulate application developers from differences between current and future implementations. Device-independence also preserves 11 software development costs by avoiding application obsolescence due to underlying 12 hardware changes.
13 The most popular method currently being used to interface a smart card with a 14 notebook computer is to use a PCMCIA Type II smart card reader/writer (Figure 1).
PCMCIA smart card readers are currently available from companies such as Gemplus, 16 SCM Microsystems and Tritheim Technologies, to name a few. The end user cost for 17 these smart card readers is typically around $150 US. The cost of the reader is a 18 major portion to the cost of the overall security solution. The adapter card 104 in 19 Figure 1 depicts the major functional blocks of a conventional smart card reader. The PCIC Host Interface block of the smart card reader provides the electrical interface to 21 the PC Card connector (106 , which in turn connects to the PC Card controller 102.
22 Additional logic is provided to control the interaction between the smart card and the 23 software application. However, as noted above, this solution carries a significant per 24 unit cost, and thus, is an unattractive alternative to large-scale migration to smart card compatibility.
26 Thus, there exists a need to provide an integrated host controller that provides 27 PC Card, smart card, and Passive smart card adapter operability. Moreover, there 28 exists a need to provide an integrated controller that can replace existing 29 motherboard-mounted PC Card host controllers, without having to retool or redesign the motherboard.
1 Accordingly, one object of the present invention is to provide an integrated PC
2 Card and Smart card controller suitable to replace conventional PC Card controllers 3 for integration into current PC motherboard technology.
4 It is another object to provide a controller as above that is simultaneously fully compatible with PC Card specifications.
6 It is still another object to provide a Smart card controller, as above, that has 7 an identical pinout arrangement as existing PC Card controllers, thereby permitting 8 the controller to be directly integrated onto a PC motherboard without redesigning 9 and/or retooling costs.
It is another object of the present invention to provide logic and methodology 11 to detect the presence of a smart card or a Passive smart card adapter utilizing existing 12 PC Card specified signals.
13 In one aspect, the present invention provides a method of detecting the 14 presence of an expansion card using conventional PC Card specification signal lines, during the initial card detection sequence. The method comprising the steps of 16 determining the signal state of a first and second card detection signal lines;
17 determining the signal state of a first and second voltage select signal lines;
18 determining if said first and/or second card detection signal lines, or said first and/or 19 second voltage select signal lines, comprise a signal state that is reserve,d by a PC
Card signal specification; and determining the signal state of a predetermined unused 21 PC Card signal line, relative to said reserved signal state. During the card detection 22 sequence the status change signal (STSCHG) is used to detect a smart card or a smart 23 card adapter. After the detection sequence is completed the STSCHG signal has the 24 original uses based on the PC Card specification for signal definition.
Also, in the preferred embodiment, this process determines the presence of a smart card or a 26 Passive smart card adapter by determining whether said first card detection signal and 27 said second voltage select signals are tied together.
28 In logic form, the present invention provides a device to detect the presence of 29 an expansion card using conventional PC Card specification signal lines, comprising a state machine including a lookup table and a plurality of logic sets, each said logic 31 sets operable to interface with a certain predefined expansion card type, said state 1 machine accepting as input signals a plurality of predetermined card detection and 2 voltage selection signals, and an additional signal, and coupling an appropriate one of 3 said logic sets to an appropriate one of said expansion cards based on a match 4 between said input signals and said lookup table.
In another aspect, the present invention provides an integrated circuit for the 6 detection and operation of a plurality of expansion cards, comprising, a first logic set 7 for detecting and operating a plurality of expansion card types, said first logic set 8 having predetermined signal lines and a pinout arrangement defined by PC
Card 9 specifications, and a second logic set for detecting and operating a smart card, wherein said first and second logic being incorporated into a single controller without 11 requiring additional pinouts. In the preferred embodiment, the second logic set is 12 adapted to reassign certain ones of said predetermined signal lines to detect and 13 operate said smart card , so that additional pins are not required.
14 It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to preferred 16 embodiments and methods of use, the present invention is not intended to be limited 17 to these preferred embodiments and methods of use. Rather, the present invention is 18 of broad scope and is intended to be limited as only set forth in the accompanying 19 claims.
Other features and advantages of the present invention will become apparent 21 as the following Detailed Description proceeds, and upon reference to the Drawings, 22 wherein like numerals depict like parts, and wherein:
23 Figure 1 depicts a block diagram of a conventional solution to incorporate 24 smart card operability for PC applications;
Figure 2 is a system-level block diagram of the integrated smart card reader of 26 the present invention;
27 Figure 3 is a detailed block diagram of the integrated Smart card reader of the 28 present invention;
29 Figure 4 is a state machine block diagram of the integrated Smart card reader of the present invention;
1 Figure 5 is a table of conventional PC Card detection and voltage sensing pin 2 arrangements, and an example of the use of a pin arrangement for smart card 3 detection employed by the controller of the present invention;
4 Figure 6 is a flowchart of an exemplary smart card and passive smart card adapter detection scheme of the present invention; and 6 Figures7A and 7B depict tables showing conventional PCMCIA assigned 7 functional pins and their use for Smart Card interface and detection, respectively.
4 Figure 6 is a flowchart of an exemplary smart card and passive smart card adapter detection scheme of the present invention; and 6 Figures7A and 7B depict tables showing conventional PCMCIA assigned 7 functional pins and their use for Smart Card interface and detection, respectively.
8 Figure 2 depicts a system-level block diagram of how the passive smart card 9 adapter and a smart card interface'with a host controller. The controller 10 is integrated into a PC platform, for example, laptop PC. As an example, the PC
may be 11 configured as shown, with the controller 10 operating to detect and control one or 12 more expansion device cards that are inserted into Socket A 12 and/or Socket B 14. It 13 will be understood that the controller 10 of present invention is adapted with the 14 appropriate logic to drive PC Cards as well as smart cards. The PC system typically includes a processor 26 and a data bus 20. "North Bridge" logic 24 provides 16 communication between the processor 26 and the bus 20. The controller 10, of the 17 present invention is likewise adapted to communicate with the bus 20. In this 18 example, the bus 20 is a PCI bus, however, any bus technology can be incorporated 19 into the controller's logic. To complete the picture, "South Bridge" logic is provided for external bus communications, for example, legacy devices (ISA bus architecture), 21 etc. South Bridge and North Bridge logic are well known in the art. Power IC chip 22 28 supplies the correct voltages (as determined by the card type inserted into Socket A
23 or B) to the pins of the PC Card connector. Once the type of card is detected (based 24 on the PC Card definitional table of Figure 5, discussed below), chip 28 supplies the appropriate voltage for that card type.
26 In one embodiment, the present invention provides a passive smartcard 27 adapter 18 which is configured to be inserted into either Socket A 12 or Socket B 14, 28 which are in turn configured as either PC Card type I/11/III--type socket interface. The 29 passive adapter 18 of this embodiment includes appropriate connector 84 and passive circuit 86. The smart card 16 inserted into the passive smart card adapter 18 also 31 includes physical contacts 88 to interface with the physical connector 84 of the 1 adapter. Pinout arrangements 84 and 88 of the adapter and smart card are dictated by 2 the smart card specification, for example PC/SC compliant Smart card specification 3 that meets ISO 7816 electrical specifications and T = 0, T = 1 protocols. In this 4 embodiment the use of an adapter 18 permits smart card readability and operability without retooling the PC case to include a specific smart card socket.
Alternatively, 6 the PC can include a smart card slot 14' as shown in Figure 2. In this alternative 7 embodiment, the logic 86 and connector 84 are, of course, provided internally within 8 socket 14.
9 Referring now to Figure 3,'a more detailed block diagram of the integrated controller 10 is depicted, showing those logic portions directed to smart card detection 11 and operability. In this example, the controller 10 includes smart card sensing logic 12 30A and 30B, Smart card multiplexer (MUX) logic 32A and 32B, Smart card reader 13 logic 34A and 34B and interface logic 36A and 36B.
14 ,It should be noted at the outset that Figure 3 depicts only the logic associated with smart card and Passive smart card adapter detection and operability, and it 16 should be understood that controller 10 includes additional logic (not shown) to 17 permit detection and operation of conventional PC Card's. Conventional PC
Card 18 controllers detect the type of card inserted into a slot using a set of card detection 19 pins, CD 1 and CD2, and a set of voltage sense pins VS 1 and VS2. Tho coupling combinations between these pins (with reference to ground) indicate to the 21 appropriate logic which type of card has been inserted into the socket. For example, 22 as shown in the table of Figure 5, the coupling combination of CD1, CD2, VSI and 23 VS2 determine whether the PC Card inserted is a 16-bit PCMCIA card or a 32-bit 24 CardBus card. Moreover, as is shown in the table, this combination also determines the driving voltage for the particular type of card. For example, 3.3 V, 5 V, X.X V
26 and Y.Y V. In the last two rows of the table of Figure 5, it is to be noted that the 27 listed combinations of CD1, CD2, VS1 and VS2 are reserved in the PC Card 28 specification. The present invention utilizes one of these reserved combinations of 29 CD1, CD2, VSl and VS2, and additionally uses a status change signal, STSCHG, to indicate whether a smart card has been inserted into the slot (either directly, or via an 31 adapter). The status change signal is preferably used in the present invention since 1 this signal is not utilized during the detection process for conventional PC
Card 2 cards, and is only used once the card type is known.
3 Thus, in one sense, the smart card sensing logic 30A shown in Figure 3 can be 4 viewed as a state machine that determines the type of card inserted into a socket. To that end, and referring to Figure 4, a state machine representation of the card sensing 6 logic 30A of Figure 3 is depicted. As is shown, the card sensing logic 30A
accepts as 7 inputs CD1, CD2, VS1, VS2 and status change (labeled 40, 42, 44, 46 and 48, 8 respectively). In accordance with the reserved arrangement of CD1, CD2, VS1, 9 as shown in Figure 5, and the addition of the status change signal, the state machine 30A determines the appropriate logic 32 A for communicating with the given type of 11 card. For example, certain combinations of CDl, CD2, VS1, VS2 (as indicated in 12 Figure 5) will dictate that the card inserted into the socket is either a 16-bit PC card or 13 a 32-bit CardBus PC card. Accordingly, the state machine 30A will activate the 14 appropriate logic 50 or 52 for the given card type. It should also be noted that the particular voltage of the inserted card is also determined using the combination of 16 these four pins. Extending the capabilities of conventional PC Card controllers, the 17 present invention also monitors the STSCHG pin to determine if a smart card or a 18 passive smart card adapter has been inserted into the socket, and likewise activates the 19 appropriate logic 54 to communicate with the smart card, for example, Jogic 32A as shown in Figure 3. To determine the states of CD1, CD2, VS1, VS2 and STSCHG, 21 the card sensing logic 30A can produce, for example, a pulse train signal on selected 22 ones of these pinouts, and by monitoring the signal on one or more of the other pins 23 (with respect to ground), it can then be determined the card type inserted into the 24 socket.
The smart card sensing logic 30A and 30B operate to detect both a smart card 26 or a passive smart card adapter and PC Cards, based on the Table in Figure 5. The pin 27 assignments shown in Figure 5 are designated by the PC Card specification, and are 28 conventional pin assignments for these signal lines. The identity of the card is 29 determined by the values of the voltages of columns 1-4, i.e., CD2, CD1, VS2 and VS 1. Both smart card and passive smart card adapter detection operates by utilizing 31 the reserved combinations of these pins, plus the use of an additional pin, for 1 example, STSCHG signal line. The concept is summarized in the Table of Figure 7B.
2 This table shows the pins used to detect PC Cards, smart cards and Passive smart card 3 adapter cards. The signal column for a smart card or passive smart card adapter 4 detection includes one of the reserved areas for CD1, CD2, VS1 and VS2, as shown in the last two rows of Table of Figure 5. It should be noted that although the figures 6 depict the use of signal line STSCHG (which is provided by the conventional PC Card 7 specification), the present invention, generally, could use any pin in the PC Card 8 specification that is unused during the card detection sequence. In other words, from 9 a timing perspective, certain signal lines in the PC Card specification remain unused during the card detection process. The present invention utilizes one (or more) of 11 these signal lines, in conjunction with the reserved combination of CD 1, CD2, VS 1, 12 and VS2, to effectuate smart card or passive smart card adapter detection.
Thus, the 13 figures represent only one of many examples for the use of an additional signal pin 14 that could be used for smart card detection.
A flow chart 60 of the card-type detection process is depicted in Figure 6.
16 For clarity, the corresponding reference numerals of the logic to detect and operate PC
17 Card, smart card and passive smart card adapter cards (as shown in Figures 2 and 3) 18 are omitted. Initially, the detection logic seeks the presence of CDI, CD2, VS1, VS2, 19 and STSCHG 62. If not present, or otherwise unavailable, it is assumed the no card has been inserted into a socket, and thus the card detection signals (CD 1 and CD2) are 21 blocked 64. Once a card is inserted, the detection logic monitors the falling edge of 22 CD 1 or CD2 66. This is dictated by the PC Card specification for determining the 23 presence of a card. Once a card is detected, the detection logic of the present 24 invention toggles CD1, CD2, VS1, VS2, and STSCHG to determine the type of card inserted 68. Toggling, as cited above, can be in the form of a pulse train signal, or 26 other toggling signal. The detection logic proceeds by polling CD1, CD2, VS1, VS2, 27 and STSCHG in the following manner. First, the logic determines if VS 1 and 28 are tied to ground 70. If not, it is known that a 16-Bit PCMCIA Card or 32-bit 29 CardBus card is inserted 72, as indicated by the table of Figure 5. If yes, the logic determines if VS2 and CD1 are tied together 74. If this is not the case, again it is 31 known that a 16-Bit Card or 32-bit CardBus card is inserted 76, as indicated by the 1 table of Figure 5. If it is determined that CD 1 and STSCHG are tied together 78, then 2 it is determined that a smart card or a passive smart card adapter is present. Either the 3 passive smart card adapter is inserted into the socket, or a smart card is inserted 4 directly into a smart card socket 82.
Another feature of the present invention is to provide an integrated controller 6 circuit 10, which can be directly integrated with current PC Card controller logic.
7 Conventional PC Card controller logic is an IC package that is mounted directly on 8 the motherboard, which has 208 pins, and each of these pins is assigned by the PC
9 Card specification. Another feature is to provide a controller 10 that can directly replace conventional controllers, without having to reconfigure pin assignments, add 11 additional pin configurations, alter the motherboard, or change the tooling required.
12 To that end, and reterring to the table of Figure 7A, the controller 10 of present 13 invention includes both conventional, legacy interface card signals and smart card 14 signals. As is shown in this table, the same pins (leftmost column) used to interface with conventional 16 and 32 cards are likewise used to interface with the smart card.
16 Thus, no additional pins are required. Referring again to Figure 3, if a smart card is 17 detected into a socket, logic 30A or 30B communicates with and enables logic 34A or 18 34B, to enable smart card readability. Logic 34A and 34B enable the socket MUX
19 logic 32A or 32B, so that the socket (A or B) can communicate with thf, cardbus/PCI
controller logic 36A or 36B, which communicate with the PCI bus 20 (via PCI
21 interface 38). As should be understood, the smart card logic 30A, 30B, 34A
and 34B
22 of the present invention directly interfaces with the MUX logic 32A and 32B
and 23 communicates with bus interface controllers 36A and 36B using conventional PC
24 Card communication protocols. If a conventional card is inserted into a socket (socket A or B), then conventional logic (not shown) incorporated into the controller 26 10 activates MUX 32A and 32B and communicates with bus interface controllers 36A
27 and 36B using conventional PC Card communication protocols.
28 To facilitate direct integration with conventional PC Card logic sets, the 29 present invention controls a predetermined number of pre-assigned pins to effectuate smart card communication. For example, as shown in Figure 7A, pins 17, 51, 58, 47, 31 32, GND, 18, 16 and 40, as specified by the PC Card standard, are utilized by the I present invention to operate both smart cards and PC cards. Therefore, no extra pins 2 are required by the controller 10 to effectuate Smart card operability. In operation, 3 once the smart card has been detected (as described above with reference to Figures 3-4 6), logic 34A or 34B reassigns the operability of the PC Card pins noted in Figure 7A
to effectuate Smart card readability. The signal assignments, set forth under the smart 6 card Signal column of Figure 7A, are the required signals to read smart Cards.
7 The table and Figure 7A is included as a lookup table in the controller 10 of 8 the present invention to operate PC Cards. Likewise, the tables of Figure 5 and 9 Figure 7B are included as lookup tables in the controller 10 for the detection of PC
Cards and smart Cards. To this end, and view the logic sets 30A and 30B as a state 11 machine (shown in Figure 4), the state machine compares the input signals to the 12 lookup, tables of Figures 5 and 7B to couple the appropriate logic to the card.
13 Those skilled in the art will recognize that CD1, CD2, VSl and VS2 comprise 14 card detect and voltage select signals, respectively, as specified by the conventional PC Card signal specification. In the tables of Figures 5, 7A and 7B, and the flowchart 16 of Figure 6, the nomenclature used for these signal lines includes, for example, CD1#, 17 CD2#, VS I#, VS2#, etc., which are the formal names for these conventional signal 18 lines. However, it should be apparent that the use of CD1, CD2, VS1 and VS2 are 19 shorthand versions of these formal names, and may be used intercliangeably.
Thus, it is evident that there has been provided an integrated Smart card 21 controller and Smart card detection process that satisfies the aims and objectives 22 stated herein. It will be apparent to those skilled in the art that modifications are 23 possible. For example, although the present invention has been described with 24 reference to detection and operation of smart Cards, the present invention is equally adapted for the detection and operation of any type of expansion cards, in addition to 26 conventional PC Cards. Other modifications are possible. For example, it may be 27 desirable to include a software lock on the operability of the smart card logic shown 28 herein. Accordingly, the logic depicted in Figure 3 can include an enable bit, which 29 selectively turns on and off smart card detectability and operability. To that end, and referring to Figure 6, the smart card detection process may alternatively include the 31 step of determining if an enable bit is enabled, and if CDl and STSCHG are tied 1 together 84. If this is not the case, the smart card the logic will not_detect the presence 2 of a smart card. This feature of the present invention permits, for example, 3 manufacturers to offer smart card compatibility as an upgrade option, while still 4 integrating the core logic of the controller 10. Those skilled in the art will recognize additional modifications, and all such modifications are deemed within the scope of 6 the present invention, only as limited by the appended claims.
may be 11 configured as shown, with the controller 10 operating to detect and control one or 12 more expansion device cards that are inserted into Socket A 12 and/or Socket B 14. It 13 will be understood that the controller 10 of present invention is adapted with the 14 appropriate logic to drive PC Cards as well as smart cards. The PC system typically includes a processor 26 and a data bus 20. "North Bridge" logic 24 provides 16 communication between the processor 26 and the bus 20. The controller 10, of the 17 present invention is likewise adapted to communicate with the bus 20. In this 18 example, the bus 20 is a PCI bus, however, any bus technology can be incorporated 19 into the controller's logic. To complete the picture, "South Bridge" logic is provided for external bus communications, for example, legacy devices (ISA bus architecture), 21 etc. South Bridge and North Bridge logic are well known in the art. Power IC chip 22 28 supplies the correct voltages (as determined by the card type inserted into Socket A
23 or B) to the pins of the PC Card connector. Once the type of card is detected (based 24 on the PC Card definitional table of Figure 5, discussed below), chip 28 supplies the appropriate voltage for that card type.
26 In one embodiment, the present invention provides a passive smartcard 27 adapter 18 which is configured to be inserted into either Socket A 12 or Socket B 14, 28 which are in turn configured as either PC Card type I/11/III--type socket interface. The 29 passive adapter 18 of this embodiment includes appropriate connector 84 and passive circuit 86. The smart card 16 inserted into the passive smart card adapter 18 also 31 includes physical contacts 88 to interface with the physical connector 84 of the 1 adapter. Pinout arrangements 84 and 88 of the adapter and smart card are dictated by 2 the smart card specification, for example PC/SC compliant Smart card specification 3 that meets ISO 7816 electrical specifications and T = 0, T = 1 protocols. In this 4 embodiment the use of an adapter 18 permits smart card readability and operability without retooling the PC case to include a specific smart card socket.
Alternatively, 6 the PC can include a smart card slot 14' as shown in Figure 2. In this alternative 7 embodiment, the logic 86 and connector 84 are, of course, provided internally within 8 socket 14.
9 Referring now to Figure 3,'a more detailed block diagram of the integrated controller 10 is depicted, showing those logic portions directed to smart card detection 11 and operability. In this example, the controller 10 includes smart card sensing logic 12 30A and 30B, Smart card multiplexer (MUX) logic 32A and 32B, Smart card reader 13 logic 34A and 34B and interface logic 36A and 36B.
14 ,It should be noted at the outset that Figure 3 depicts only the logic associated with smart card and Passive smart card adapter detection and operability, and it 16 should be understood that controller 10 includes additional logic (not shown) to 17 permit detection and operation of conventional PC Card's. Conventional PC
Card 18 controllers detect the type of card inserted into a slot using a set of card detection 19 pins, CD 1 and CD2, and a set of voltage sense pins VS 1 and VS2. Tho coupling combinations between these pins (with reference to ground) indicate to the 21 appropriate logic which type of card has been inserted into the socket. For example, 22 as shown in the table of Figure 5, the coupling combination of CD1, CD2, VSI and 23 VS2 determine whether the PC Card inserted is a 16-bit PCMCIA card or a 32-bit 24 CardBus card. Moreover, as is shown in the table, this combination also determines the driving voltage for the particular type of card. For example, 3.3 V, 5 V, X.X V
26 and Y.Y V. In the last two rows of the table of Figure 5, it is to be noted that the 27 listed combinations of CD1, CD2, VS1 and VS2 are reserved in the PC Card 28 specification. The present invention utilizes one of these reserved combinations of 29 CD1, CD2, VSl and VS2, and additionally uses a status change signal, STSCHG, to indicate whether a smart card has been inserted into the slot (either directly, or via an 31 adapter). The status change signal is preferably used in the present invention since 1 this signal is not utilized during the detection process for conventional PC
Card 2 cards, and is only used once the card type is known.
3 Thus, in one sense, the smart card sensing logic 30A shown in Figure 3 can be 4 viewed as a state machine that determines the type of card inserted into a socket. To that end, and referring to Figure 4, a state machine representation of the card sensing 6 logic 30A of Figure 3 is depicted. As is shown, the card sensing logic 30A
accepts as 7 inputs CD1, CD2, VS1, VS2 and status change (labeled 40, 42, 44, 46 and 48, 8 respectively). In accordance with the reserved arrangement of CD1, CD2, VS1, 9 as shown in Figure 5, and the addition of the status change signal, the state machine 30A determines the appropriate logic 32 A for communicating with the given type of 11 card. For example, certain combinations of CDl, CD2, VS1, VS2 (as indicated in 12 Figure 5) will dictate that the card inserted into the socket is either a 16-bit PC card or 13 a 32-bit CardBus PC card. Accordingly, the state machine 30A will activate the 14 appropriate logic 50 or 52 for the given card type. It should also be noted that the particular voltage of the inserted card is also determined using the combination of 16 these four pins. Extending the capabilities of conventional PC Card controllers, the 17 present invention also monitors the STSCHG pin to determine if a smart card or a 18 passive smart card adapter has been inserted into the socket, and likewise activates the 19 appropriate logic 54 to communicate with the smart card, for example, Jogic 32A as shown in Figure 3. To determine the states of CD1, CD2, VS1, VS2 and STSCHG, 21 the card sensing logic 30A can produce, for example, a pulse train signal on selected 22 ones of these pinouts, and by monitoring the signal on one or more of the other pins 23 (with respect to ground), it can then be determined the card type inserted into the 24 socket.
The smart card sensing logic 30A and 30B operate to detect both a smart card 26 or a passive smart card adapter and PC Cards, based on the Table in Figure 5. The pin 27 assignments shown in Figure 5 are designated by the PC Card specification, and are 28 conventional pin assignments for these signal lines. The identity of the card is 29 determined by the values of the voltages of columns 1-4, i.e., CD2, CD1, VS2 and VS 1. Both smart card and passive smart card adapter detection operates by utilizing 31 the reserved combinations of these pins, plus the use of an additional pin, for 1 example, STSCHG signal line. The concept is summarized in the Table of Figure 7B.
2 This table shows the pins used to detect PC Cards, smart cards and Passive smart card 3 adapter cards. The signal column for a smart card or passive smart card adapter 4 detection includes one of the reserved areas for CD1, CD2, VS1 and VS2, as shown in the last two rows of Table of Figure 5. It should be noted that although the figures 6 depict the use of signal line STSCHG (which is provided by the conventional PC Card 7 specification), the present invention, generally, could use any pin in the PC Card 8 specification that is unused during the card detection sequence. In other words, from 9 a timing perspective, certain signal lines in the PC Card specification remain unused during the card detection process. The present invention utilizes one (or more) of 11 these signal lines, in conjunction with the reserved combination of CD 1, CD2, VS 1, 12 and VS2, to effectuate smart card or passive smart card adapter detection.
Thus, the 13 figures represent only one of many examples for the use of an additional signal pin 14 that could be used for smart card detection.
A flow chart 60 of the card-type detection process is depicted in Figure 6.
16 For clarity, the corresponding reference numerals of the logic to detect and operate PC
17 Card, smart card and passive smart card adapter cards (as shown in Figures 2 and 3) 18 are omitted. Initially, the detection logic seeks the presence of CDI, CD2, VS1, VS2, 19 and STSCHG 62. If not present, or otherwise unavailable, it is assumed the no card has been inserted into a socket, and thus the card detection signals (CD 1 and CD2) are 21 blocked 64. Once a card is inserted, the detection logic monitors the falling edge of 22 CD 1 or CD2 66. This is dictated by the PC Card specification for determining the 23 presence of a card. Once a card is detected, the detection logic of the present 24 invention toggles CD1, CD2, VS1, VS2, and STSCHG to determine the type of card inserted 68. Toggling, as cited above, can be in the form of a pulse train signal, or 26 other toggling signal. The detection logic proceeds by polling CD1, CD2, VS1, VS2, 27 and STSCHG in the following manner. First, the logic determines if VS 1 and 28 are tied to ground 70. If not, it is known that a 16-Bit PCMCIA Card or 32-bit 29 CardBus card is inserted 72, as indicated by the table of Figure 5. If yes, the logic determines if VS2 and CD1 are tied together 74. If this is not the case, again it is 31 known that a 16-Bit Card or 32-bit CardBus card is inserted 76, as indicated by the 1 table of Figure 5. If it is determined that CD 1 and STSCHG are tied together 78, then 2 it is determined that a smart card or a passive smart card adapter is present. Either the 3 passive smart card adapter is inserted into the socket, or a smart card is inserted 4 directly into a smart card socket 82.
Another feature of the present invention is to provide an integrated controller 6 circuit 10, which can be directly integrated with current PC Card controller logic.
7 Conventional PC Card controller logic is an IC package that is mounted directly on 8 the motherboard, which has 208 pins, and each of these pins is assigned by the PC
9 Card specification. Another feature is to provide a controller 10 that can directly replace conventional controllers, without having to reconfigure pin assignments, add 11 additional pin configurations, alter the motherboard, or change the tooling required.
12 To that end, and reterring to the table of Figure 7A, the controller 10 of present 13 invention includes both conventional, legacy interface card signals and smart card 14 signals. As is shown in this table, the same pins (leftmost column) used to interface with conventional 16 and 32 cards are likewise used to interface with the smart card.
16 Thus, no additional pins are required. Referring again to Figure 3, if a smart card is 17 detected into a socket, logic 30A or 30B communicates with and enables logic 34A or 18 34B, to enable smart card readability. Logic 34A and 34B enable the socket MUX
19 logic 32A or 32B, so that the socket (A or B) can communicate with thf, cardbus/PCI
controller logic 36A or 36B, which communicate with the PCI bus 20 (via PCI
21 interface 38). As should be understood, the smart card logic 30A, 30B, 34A
and 34B
22 of the present invention directly interfaces with the MUX logic 32A and 32B
and 23 communicates with bus interface controllers 36A and 36B using conventional PC
24 Card communication protocols. If a conventional card is inserted into a socket (socket A or B), then conventional logic (not shown) incorporated into the controller 26 10 activates MUX 32A and 32B and communicates with bus interface controllers 36A
27 and 36B using conventional PC Card communication protocols.
28 To facilitate direct integration with conventional PC Card logic sets, the 29 present invention controls a predetermined number of pre-assigned pins to effectuate smart card communication. For example, as shown in Figure 7A, pins 17, 51, 58, 47, 31 32, GND, 18, 16 and 40, as specified by the PC Card standard, are utilized by the I present invention to operate both smart cards and PC cards. Therefore, no extra pins 2 are required by the controller 10 to effectuate Smart card operability. In operation, 3 once the smart card has been detected (as described above with reference to Figures 3-4 6), logic 34A or 34B reassigns the operability of the PC Card pins noted in Figure 7A
to effectuate Smart card readability. The signal assignments, set forth under the smart 6 card Signal column of Figure 7A, are the required signals to read smart Cards.
7 The table and Figure 7A is included as a lookup table in the controller 10 of 8 the present invention to operate PC Cards. Likewise, the tables of Figure 5 and 9 Figure 7B are included as lookup tables in the controller 10 for the detection of PC
Cards and smart Cards. To this end, and view the logic sets 30A and 30B as a state 11 machine (shown in Figure 4), the state machine compares the input signals to the 12 lookup, tables of Figures 5 and 7B to couple the appropriate logic to the card.
13 Those skilled in the art will recognize that CD1, CD2, VSl and VS2 comprise 14 card detect and voltage select signals, respectively, as specified by the conventional PC Card signal specification. In the tables of Figures 5, 7A and 7B, and the flowchart 16 of Figure 6, the nomenclature used for these signal lines includes, for example, CD1#, 17 CD2#, VS I#, VS2#, etc., which are the formal names for these conventional signal 18 lines. However, it should be apparent that the use of CD1, CD2, VS1 and VS2 are 19 shorthand versions of these formal names, and may be used intercliangeably.
Thus, it is evident that there has been provided an integrated Smart card 21 controller and Smart card detection process that satisfies the aims and objectives 22 stated herein. It will be apparent to those skilled in the art that modifications are 23 possible. For example, although the present invention has been described with 24 reference to detection and operation of smart Cards, the present invention is equally adapted for the detection and operation of any type of expansion cards, in addition to 26 conventional PC Cards. Other modifications are possible. For example, it may be 27 desirable to include a software lock on the operability of the smart card logic shown 28 herein. Accordingly, the logic depicted in Figure 3 can include an enable bit, which 29 selectively turns on and off smart card detectability and operability. To that end, and referring to Figure 6, the smart card detection process may alternatively include the 31 step of determining if an enable bit is enabled, and if CDl and STSCHG are tied 1 together 84. If this is not the case, the smart card the logic will not_detect the presence 2 of a smart card. This feature of the present invention permits, for example, 3 manufacturers to offer smart card compatibility as an upgrade option, while still 4 integrating the core logic of the controller 10. Those skilled in the art will recognize additional modifications, and all such modifications are deemed within the scope of 6 the present invention, only as limited by the appended claims.
Claims (28)
1. A method of detecting the presence of an expansion card using conventional PC
Card specification signal lines, said method comprising the steps of:
determining the signal state of a first and second card detection signal lines;
determining the signal state of a first and second voltage select signal lines;
determining if said first and/or second card detection signal lines, or said first and/or second voltage select signal lines, comprise a signal state that is reserved by a PC
Card signal specification;
determining the signal state of a predetermined unused PC Card signal line that is unused during the detection of a PC Card; relative to said reserved signal state; and determining the presence of an expansion card that complies with the PC Card Specification and/or an expansion card that complies with a specification other than said PC Card Specification based on the signal states of said first and/or second card detection signal lines, and/or said first and/or said second voltage select signal lines, and/or said unused PC Card signal line.
Card specification signal lines, said method comprising the steps of:
determining the signal state of a first and second card detection signal lines;
determining the signal state of a first and second voltage select signal lines;
determining if said first and/or second card detection signal lines, or said first and/or second voltage select signal lines, comprise a signal state that is reserved by a PC
Card signal specification;
determining the signal state of a predetermined unused PC Card signal line that is unused during the detection of a PC Card; relative to said reserved signal state; and determining the presence of an expansion card that complies with the PC Card Specification and/or an expansion card that complies with a specification other than said PC Card Specification based on the signal states of said first and/or second card detection signal lines, and/or said first and/or said second voltage select signal lines, and/or said unused PC Card signal line.
2. A method as claimed in claim 1, further comprising the steps of:
determining the presence of a smart card by determining whether said first card detection signal line and said second voltage select signal line are tied together.
determining the presence of a smart card by determining whether said first card detection signal line and said second voltage select signal line are tied together.
3. A method as claimed in claim 1, wherein said steps of determining the signal states of said signal lines comprise polling said signal lines with a predetermined input signal and measuring an output signal.
4. A device to detect the presence of an expansion card using conventional PC
Card specification signal lines, comprising a state machine including a lookup table and a plurality of logic sets, each said logic sets operable to interface with a certain predefined expansion card type, said state machine accepting as input signals a plurality of predetermined card detection and voltage selection signals, and an additional signal that is unused during detection of a PC Card, and coupling an appropriate one of said logic sets to an appropriate one of said expansion cards based on a match between said input signals and said lookup table.
Card specification signal lines, comprising a state machine including a lookup table and a plurality of logic sets, each said logic sets operable to interface with a certain predefined expansion card type, said state machine accepting as input signals a plurality of predetermined card detection and voltage selection signals, and an additional signal that is unused during detection of a PC Card, and coupling an appropriate one of said logic sets to an appropriate one of said expansion cards based on a match between said input signals and said lookup table.
5. A device as claimed in claim 4, wherein said logic sets comprise a first logic set to operate a 16-Bit expansion card, a second logic set to operate a 32-Bit expansion card, and a third logic set to operate a Smart card.
6. A device as claimed in claim 4, wherein said lookup table comprises a plurality of assigned signal state definitions for said input signals, said signal state definitions include the interface type and operable voltage for a plurality of expansion cards.
7. A device as claimed in claim 4, wherein said additional signal is a status change (STSCHG) signal.
8. An integrated circuit for the detection and operation of a plurality of expansion cards, comprising, a first logic set for detecting and operating a plurality of expansion card types, said first logic set having predetermined signal lines and a pinout arrangement defined by PC Card specifications, and a second logic set for detecting and operating a smart card, wherein said first and second logic being incorporated into a single controller, and wherein said second logic set being adapted to reassign certain ones of said predetermined signal lines to detect and operate said smart card without requiring additional pinouts.
9. A system for the detection and operation of a Smart Card, comprising:
a socket for receiving a Smart Card; and an integrated controller comprising a first logic set for detecting said Smart Card, a second logic set enabled by said first logic set for operating said Smart Card, MUX
logic enabled by said first and second logic sets to provide communication between said Smart Card and a bus controller logic using conventional PC card communication protocols.
a socket for receiving a Smart Card; and an integrated controller comprising a first logic set for detecting said Smart Card, a second logic set enabled by said first logic set for operating said Smart Card, MUX
logic enabled by said first and second logic sets to provide communication between said Smart Card and a bus controller logic using conventional PC card communication protocols.
10. A system as claimed in claim 9, further comprising:
a second socket for receiving a PC Card;
said integrated controller further comprising logic to detect and operate said PC
Card, said logic enabling said MUX logic to provide communication between said PC
Card and said bus controller logic using said conventional PC Card communication protocols.
a second socket for receiving a PC Card;
said integrated controller further comprising logic to detect and operate said PC
Card, said logic enabling said MUX logic to provide communication between said PC
Card and said bus controller logic using said conventional PC Card communication protocols.
11. A system as claimed in claim 9, said integrated controller further comprising a bus interface to permit said bus controller logic to communicate with a bus.
12. A system as claimed in claim 11, wherein said bus comprises a PCI bus and said bus controller logic comprises PCI bus and conventional PC card communication protocols.
13. A system as claimed in claim 10, wherein said PC Card is selected from the group of a CardBus Card or a PCMCIA card.
14. A method for detecting and operating a plurality of expansion cards, comprising the steps of:
detecting that a card is inserted into a card socket;
determining the type of card using conventional PC Card signal lines;
enabling Smart Card reader logic or conventional PC Card reader logic when the type of card is determined; and enabling MUX logic to provide communication between said card and bus controller logic using conventional PC Card communication protocols.
detecting that a card is inserted into a card socket;
determining the type of card using conventional PC Card signal lines;
enabling Smart Card reader logic or conventional PC Card reader logic when the type of card is determined; and enabling MUX logic to provide communication between said card and bus controller logic using conventional PC Card communication protocols.
15. A method as claimed in claim 14, said step of determining the type of card further comprising the steps of:
determining the signal state of a first and second card detection signal lines;
determining the signal state of a first and second voltage select signal lines;
determining if said first and/or second card detection signal lines, or said first and/or second voltage select signal lines, comprise a signal state that is reserved by a PC
Card signal specification;
determining the signal state of a PC Card signal line that is unused during the detection of a PC Card; and determining the presence of an expansion card that complies with the PC Card Specification and/or an expansion card that complies with a specification other than said PC Card Specification based on the signal states of said first and/or second card detection signal lines, and/or said first and/or said second voltage select signal lines, and/or said unused PC Card signal line.
determining the signal state of a first and second card detection signal lines;
determining the signal state of a first and second voltage select signal lines;
determining if said first and/or second card detection signal lines, or said first and/or second voltage select signal lines, comprise a signal state that is reserved by a PC
Card signal specification;
determining the signal state of a PC Card signal line that is unused during the detection of a PC Card; and determining the presence of an expansion card that complies with the PC Card Specification and/or an expansion card that complies with a specification other than said PC Card Specification based on the signal states of said first and/or second card detection signal lines, and/or said first and/or said second voltage select signal lines, and/or said unused PC Card signal line.
16. A method as claimed in claim 14,further comprising the steps of interfacing said card to a bus using said bus controller logic to provide communication between said bus and said card.
17. A system for the detection and operation of a plurality of expansion cards, comprising:
a first socket for receiving a first expansion card that complies with the PC
Card Specification;
a second socket for receiving a second expansion card that complies with a specification other than said PC Card Specification;
an integrated controller comprising first logic sets for detecting and operating said first expansion card, second logic sets for detecting and operating said second expansion card, MUX logic enabled by said first and/or second logic sets to provide communication between said first and/or second expansion card and a bus controller logic using conventional PC card communication protocols.
a first socket for receiving a first expansion card that complies with the PC
Card Specification;
a second socket for receiving a second expansion card that complies with a specification other than said PC Card Specification;
an integrated controller comprising first logic sets for detecting and operating said first expansion card, second logic sets for detecting and operating said second expansion card, MUX logic enabled by said first and/or second logic sets to provide communication between said first and/or second expansion card and a bus controller logic using conventional PC card communication protocols.
18. A system as claimed in claim 17, wherein said first card comprising a CardBus card.
19. A system as claimed in claim 17,wherein said second card comprising a Smart Card.
20. A system as claimed in claim 17, said integrated controller further comprising a bus interface to permit said bus controller logic to communicate with a bus.
21. A system as claimed in claim 20, wherein said bus comprises a PCI bus and said bus controller logic comprises PCI bus and conventional PC card communication protocols.
22. A system as claimed in claim 17, wherein said second logic set detects said second card using convention PC Card signal lines.
23. An integrated controller for reading a plurality of expansion cards, comprising:
first logic sets for detecting and operating a first expansion card;
second logic sets for detecting and operating a second expansion card; and MUX logic enabled by said first and/or second logic sets to provide communication between said first and/or second expansion card and a bus controller logic using conventional PC card communication protocols.
first logic sets for detecting and operating a first expansion card;
second logic sets for detecting and operating a second expansion card; and MUX logic enabled by said first and/or second logic sets to provide communication between said first and/or second expansion card and a bus controller logic using conventional PC card communication protocols.
24. An integrated controller for reading a Smart Card, comprising:
a first logic set for detecting said Smart Card, a second logic set enabled by said first logic set for operating said Smart Card, MUX logic enabled by said first and second logic sets to provide communication between said Smart Card and a bus controller logic using conventional PC card communication protocols.
a first logic set for detecting said Smart Card, a second logic set enabled by said first logic set for operating said Smart Card, MUX logic enabled by said first and second logic sets to provide communication between said Smart Card and a bus controller logic using conventional PC card communication protocols.
25. A controller as claimed in claim 24, wherein said first logic set detects said Smart Card using conventional PC Card signal lines.
26. A controller as claimed in claim 24, further comprising PC Card logic to detect and operate a PC Card, said PC Card logic enabling said MUX logic to provide communication between said PC Card and said bus controller logic using said conventional PC Card communication protocols.
27. A controller as claimed in claim 24, further comprising a bus interface to permit said bus controller logic to communicate with a bus.
28. A system as claimed in claim 25, wherein said bus comprises a PCI bus and said bus controller logic comprises PCI bus and conventional PC card communication protocols.
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14754499P | 1999-08-05 | 1999-08-05 | |
| US60/147,544 | 1999-08-05 | ||
| US16124999P | 1999-10-25 | 1999-10-25 | |
| US60/161,249 | 1999-10-25 | ||
| US17494800P | 2000-01-07 | 2000-01-07 | |
| US60/174,948 | 2000-01-07 | ||
| US09/536,578 US6470284B1 (en) | 1999-08-05 | 2000-03-28 | Integrated PC card host controller for the detection and operation of a plurality of expansion cards |
| US09/536,578 | 2000-03-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2313583A1 CA2313583A1 (en) | 2001-02-05 |
| CA2313583C true CA2313583C (en) | 2008-02-05 |
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| CA002313583A Expired - Fee Related CA2313583C (en) | 1999-08-05 | 2000-07-05 | Integrated pc card host controller for the detection and operation of a plurality of expansion cards |
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| US (5) | US6470284B1 (en) |
| EP (1) | EP1074918B1 (en) |
| JP (1) | JP3667199B2 (en) |
| CN (1) | CN1220137C (en) |
| AT (1) | ATE308781T1 (en) |
| CA (1) | CA2313583C (en) |
| DE (1) | DE60023608T2 (en) |
| TW (1) | TW486623B (en) |
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- 2000-07-10 JP JP2000208128A patent/JP3667199B2/en not_active Expired - Fee Related
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-
2002
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-
2003
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| US20210374718A1 (en) * | 2018-09-04 | 2021-12-02 | Sony Corporation | Ic card, processing method, and information processing system |
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|---|---|
| EP1074918B1 (en) | 2005-11-02 |
| DE60023608D1 (en) | 2005-12-08 |
| US7191270B2 (en) | 2007-03-13 |
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| US6807597B2 (en) | 2004-10-19 |
| US7076589B2 (en) | 2006-07-11 |
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| US6470284B1 (en) | 2002-10-22 |
| ATE308781T1 (en) | 2005-11-15 |
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| US20060265538A1 (en) | 2006-11-23 |
| TW486623B (en) | 2002-05-11 |
| US20020152047A1 (en) | 2002-10-17 |
| CN1283818A (en) | 2001-02-14 |
| US20040073736A1 (en) | 2004-04-15 |
| EP1074918A3 (en) | 2003-11-12 |
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