CA2315456A1 - Schematic organization tool - Google Patents

Schematic organization tool Download PDF

Info

Publication number
CA2315456A1
CA2315456A1 CA002315456A CA2315456A CA2315456A1 CA 2315456 A1 CA2315456 A1 CA 2315456A1 CA 002315456 A CA002315456 A CA 002315456A CA 2315456 A CA2315456 A CA 2315456A CA 2315456 A1 CA2315456 A1 CA 2315456A1
Authority
CA
Canada
Prior art keywords
schematic
cell
components
project
high level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002315456A
Other languages
French (fr)
Other versions
CA2315456C (en
Inventor
Val Gont
Larry Lam
Alexei Ioudovski
Jason Abt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TechInsights Inc
Original Assignee
Semiconductor Insights Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Insights Inc filed Critical Semiconductor Insights Inc
Priority to CA002315456A priority Critical patent/CA2315456C/en
Priority to US09/920,734 priority patent/US6738957B2/en
Publication of CA2315456A1 publication Critical patent/CA2315456A1/en
Application granted granted Critical
Publication of CA2315456C publication Critical patent/CA2315456C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/31—Design entry, e.g. editors specifically adapted for circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/12—Symbolic schematics

Abstract

A process in a computer system for generating a high level schematic from a project schematic of basic components which comprises scanning the project schematic for a predetermined cell, wherein the cell is made up of a select group of components and their interconnections, and replacing the select group of components on every occurrence that it is found in the project schematic by a cell symbol having input and outputs to generate the high level schematic. The process may also be repeated for other predetermined cells which may be selected from a library or created by the user.
CA002315456A 2000-08-09 2000-08-09 Schematic organization tool Expired - Lifetime CA2315456C (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002315456A CA2315456C (en) 2000-08-09 2000-08-09 Schematic organization tool
US09/920,734 US6738957B2 (en) 2000-08-09 2001-08-03 Schematic organization tool

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002315456A CA2315456C (en) 2000-08-09 2000-08-09 Schematic organization tool

Publications (2)

Publication Number Publication Date
CA2315456A1 true CA2315456A1 (en) 2002-02-09
CA2315456C CA2315456C (en) 2009-10-13

Family

ID=4166860

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002315456A Expired - Lifetime CA2315456C (en) 2000-08-09 2000-08-09 Schematic organization tool

Country Status (2)

Country Link
US (1) US6738957B2 (en)
CA (1) CA2315456C (en)

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DE10151379C1 (en) * 2001-10-18 2003-04-24 Infineon Technologies Ag Manufacturing integrated semiconducting circuit involves implementing short, wide range wiring in same metallization plane, showing each different form on different layer type drawing
US7062427B2 (en) * 2001-12-27 2006-06-13 John Stephen Walther Batch editor for netlists described in a hardware description language
JP2004030308A (en) * 2002-06-26 2004-01-29 Nec Micro Systems Ltd Method for preparing layout of semiconductor integrated circuit
KR100459731B1 (en) * 2002-12-04 2004-12-03 삼성전자주식회사 Device and method for generating selective netlist having interconnection influence for the simulation of semiconductor integrated circuit
US7503021B2 (en) * 2002-12-17 2009-03-10 International Business Machines Corporation Integrated circuit diagnosing method, system, and program product
US6968518B2 (en) * 2003-01-21 2005-11-22 Infineon Technologies Ag Method of resolving missing graphical symbols in computer-aided integrated circuit design
US7096439B2 (en) * 2003-05-21 2006-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for performing intellectual property merge
US20050050485A1 (en) * 2003-08-25 2005-03-03 Keller S. Brandon Systems and methods for identifying data sources associated with a circuit design
US7146594B1 (en) * 2003-12-15 2006-12-05 Ugs Corp. System, method, and computer program product for schematic generation
US7188329B2 (en) * 2004-02-13 2007-03-06 Inventec Corporation Computer-assisted electronic component schematic linking method
US20060055704A1 (en) * 2004-09-10 2006-03-16 Kruk James L Empty space reduction for auto-generated drawings
US7131092B2 (en) * 2004-12-21 2006-10-31 Via Technologies, Inc. Clock gating circuit
US20070198588A1 (en) * 2005-10-17 2007-08-23 Siemens Corporate Research Inc Automatic Qualification of Plant Equipment
US7543262B2 (en) * 2005-12-06 2009-06-02 Cadence Design Systems, Inc. Analog layout module generator and method
US7831948B2 (en) * 2006-02-02 2010-11-09 The Boeing Company Method and system for automatically generating schematics
US7990375B2 (en) * 2006-04-03 2011-08-02 Cadence Design Systems, Inc. Virtual view schematic editor
US20070256037A1 (en) * 2006-04-26 2007-11-01 Zavadsky Vyacheslav L Net-list organization tools
US8214789B2 (en) * 2006-10-02 2012-07-03 The Boeing Company Method and system for keyboard managing and navigating among drawing objects
US20080172604A1 (en) * 2006-12-28 2008-07-17 International Business Machines Corporation Time reduction mechanism in schematic design entry page setup
US7937678B2 (en) * 2008-06-11 2011-05-03 Infineon Technologies Ag System and method for integrated circuit planar netlist interpretation
US8205183B1 (en) * 2009-09-18 2012-06-19 Altera Corporation Interactive configuration of connectivity in schematic diagram of integrated circuit design
CN102446230B (en) * 2010-10-11 2013-03-13 上海华虹Nec电子有限公司 Method for merging GDSII layout data
US8464191B2 (en) * 2011-07-21 2013-06-11 R3 Logic, Inc. System and method for identifying circuit components of an integrated circuit
US10354037B1 (en) * 2016-06-30 2019-07-16 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing an electronic design by manipulating a hierarchical structure of the electronic design
US10210299B1 (en) 2016-09-30 2019-02-19 Cadence Design Systems, Inc. Methods, systems, and computer program product for dynamically abstracting virtual hierarchies for an electronic design
US10192020B1 (en) 2016-09-30 2019-01-29 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing dynamic maneuvers within virtual hierarchies of an electronic design
US10282505B1 (en) 2016-09-30 2019-05-07 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing legal routing tracks across virtual hierarchies and legal placement patterns
IT201900000625A1 (en) * 2019-01-15 2020-07-15 Texa Spa METHOD OF DRAWING UP ELECTRICAL DIAGRAMS
CN113591426B (en) * 2021-08-04 2022-05-24 北京华大九天科技股份有限公司 Method for creating net mark in integrated circuit layout design

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Publication number Priority date Publication date Assignee Title
DE3587846T2 (en) 1984-12-26 1994-10-06 Hitachi Ltd Method and device for checking the geometry of multilayer patterns for integrated circuit structures.
US4835704A (en) 1986-12-29 1989-05-30 General Electric Company Adaptive lithography system to provide high density interconnect
US5210699A (en) 1989-12-18 1993-05-11 Siemens Components, Inc. Process for extracting logic from transistor and resistor data representations of circuits
US5384710A (en) 1990-03-13 1995-01-24 National Semiconductor Corporation Circuit level netlist generation
US5572437A (en) 1990-04-06 1996-11-05 Lsi Logic Corporation Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
GB2282480B (en) * 1990-07-05 1995-07-26 Olivetti Systems & Networks S Integrated circuit structure analysis
US5086477A (en) * 1990-08-07 1992-02-04 Northwest Technology Corp. Automated system for extracting design and layout information from an integrated circuit
JPH05198593A (en) 1992-01-22 1993-08-06 Hitachi Ltd Method of extracting parameter
US5629858A (en) 1994-10-31 1997-05-13 International Business Machines Corporation CMOS transistor network to gate level model extractor for simulation, verification and test generation
US5694481A (en) 1995-04-12 1997-12-02 Semiconductor Insights Inc. Automated design analysis system for generating circuit schematics from high magnification images of an integrated circuit
CA2216900C (en) 1996-10-01 2001-12-04 Semiconductor Insights Inc. Method to extract circuit information
US6499129B1 (en) 1998-07-22 2002-12-24 Circuit Semantics, Inc. Method of estimating performance of integrated circuit designs
JP2002157295A (en) * 2000-11-21 2002-05-31 Nec Microsystems Ltd Device and method for designing semiconductor circuit

Also Published As

Publication number Publication date
US6738957B2 (en) 2004-05-18
US20020023107A1 (en) 2002-02-21
CA2315456C (en) 2009-10-13

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Legal Events

Date Code Title Description
EEER Examination request
MKEX Expiry

Effective date: 20200810

MKEX Expiry

Effective date: 20200810