CA2319430A1 - A method for generating electrical conducting or semiconducting structures in two or three dimensions, a method for erasing the same structures and an electric field generator/modulator for use with the method for generating - Google Patents
A method for generating electrical conducting or semiconducting structures in two or three dimensions, a method for erasing the same structures and an electric field generator/modulator for use with the method for generating Download PDFInfo
- Publication number
- CA2319430A1 CA2319430A1 CA002319430A CA2319430A CA2319430A1 CA 2319430 A1 CA2319430 A1 CA 2319430A1 CA 002319430 A CA002319430 A CA 002319430A CA 2319430 A CA2319430 A CA 2319430A CA 2319430 A1 CA2319430 A1 CA 2319430A1
- Authority
- CA
- Canada
- Prior art keywords
- structures
- electric field
- matrix
- electrical conducting
- dimensions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title abstract 5
- 230000005684 electric field Effects 0.000 title abstract 4
- 239000000463 material Substances 0.000 abstract 7
- 239000011159 matrix material Substances 0.000 abstract 4
- 238000000059 patterning Methods 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/50—Forming devices by joining two substrates together, e.g. lamination techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
- H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
In a method for generating electrical conducting or semiconducting structures in three dimensions in a matrix which comprises two or more materials in spatially separated material structures, an electric field is applied to the separate material structure or the field-modulated spatially according to a protocol which represents a predetermined pattern of electrical conducting or semiconducting structures which are generated in the material structure in response to the field. The matrix composed by the material structures will hence comprise structures of this kind in three dimensions. In a method for global erasing an electric field is applied to the matrix until the materials in the matrix in response to the field in their entirety arrive in a non-conducting state. In an electric field generator/modulator (EFGM) which can be used for patterning and generating electrical conducting or semiconducting structures, two electrode means (E1;E2) comprise parallel strip electrodes (21;22) provided mutually spaced apart in parallel planes such that the electrodes (21, 22) form a matrix-like arrangement. The electrode means (E1;E2) are over cross-connection devices (24, 25) connected with a power supply (23). EFGM (20) is adapted for receiving a thin-film material between the electrode devices (E1, E2) in order to generate said structures.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NO980385A NO980385D0 (en) | 1998-01-28 | 1998-01-28 | Circuits generated by in situ conversion |
NO19980385 | 1998-01-28 | ||
NO982518A NO308149B1 (en) | 1998-06-02 | 1998-06-02 | Scalable, integrated data processing device |
NO19982518 | 1998-06-02 | ||
PCT/NO1999/000022 WO1999044229A1 (en) | 1998-01-28 | 1999-01-28 | A method for generating electrical conducting or semiconducting structures in two or three dimensions, a method for erasing the same structures and an electric field generator/modulator for use with the method for generating |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2319430A1 true CA2319430A1 (en) | 1999-09-02 |
CA2319430C CA2319430C (en) | 2004-05-11 |
Family
ID=26648814
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002319430A Expired - Fee Related CA2319430C (en) | 1998-01-28 | 1999-01-28 | A method for generating electrical conducting or semiconducting structures in two or three dimensions, a method for erasing the same structures and an electric field generator/modulator for use with the method for generating |
CA002319428A Expired - Fee Related CA2319428C (en) | 1998-01-28 | 1999-01-28 | A method for generation of electrical conducting or semiconducting structures in three dimensions and methods for erasure of the same structures |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002319428A Expired - Fee Related CA2319428C (en) | 1998-01-28 | 1999-01-28 | A method for generation of electrical conducting or semiconducting structures in three dimensions and methods for erasure of the same structures |
Country Status (12)
Country | Link |
---|---|
US (3) | US6432739B1 (en) |
EP (2) | EP1051745B1 (en) |
JP (2) | JP4272353B2 (en) |
KR (2) | KR100375864B1 (en) |
CN (2) | CN1171301C (en) |
AT (1) | ATE377842T1 (en) |
AU (2) | AU733522B2 (en) |
CA (2) | CA2319430C (en) |
DE (1) | DE69937485T2 (en) |
HK (2) | HK1035602A1 (en) |
RU (2) | RU2183882C2 (en) |
WO (2) | WO1999044229A1 (en) |
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