CA2399547A1 - Group iii nitride based fets and hemts with reduced trapping and method for producing the same - Google Patents

Group iii nitride based fets and hemts with reduced trapping and method for producing the same Download PDF

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Publication number
CA2399547A1
CA2399547A1 CA002399547A CA2399547A CA2399547A1 CA 2399547 A1 CA2399547 A1 CA 2399547A1 CA 002399547 A CA002399547 A CA 002399547A CA 2399547 A CA2399547 A CA 2399547A CA 2399547 A1 CA2399547 A1 CA 2399547A1
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layer
fet
barrier layer
transistor
electron source
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CA002399547A
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CA2399547C (en
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Yifeng Wu
Naiqian Zhang
Jian Xu
Lee Mccarthy
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University of California
Wolfspeed Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

New Group III nitride based field effect transistors (10) and high electron mobility transistors (30) are disclosed that provide enhanced high frequency response characteristics. The preferred transistors (10, 30) are made from GaN/AlGaN and have a dielectric layer (22, 44) on the surface of their barrier layer (18, 38). The dielectric layer (22, 44) has a high percentage of donor electrons (68) that neutralize traps (69) in the barrier layer (18, 38) such that the traps (69) cannot slow the high frequency response of the transistors (10, 30). A new method of manufacturing the transistors (10, 30) is also disclosed, with the new method using sputtering to deposit the dielectric layer (18, 38).

Claims (41)

1. A field effect transistor (FET), comprising:
a high resistivity, non-conducting layer (20);
a barrier layer (18) on said non-conducting layer (20);
respective source, drain and gate contacts (13,14,16) contacting said barrier layer (18), with part of the surface of said barrier layer (18) uncovered by said contacts (13, 14, 16) ; and an electron source layer (22) formed on the surface of said barrier layer (18) between said contacts (13,14,16) said electron source layer (22) having a high percentage of donor electrons (68).
2. The FET of claim 1, wherein said barrier layer (18) has positive charged surface traps (69) and wherein said donor electrons (68) neutralize said traps (69).
3. The FET of claim 2, wherein said donor electrons (68) have a higher energy state than said traps (69).
4. The FET of claim 1, wherein said electron source layer (22) is a layer of dielectric material.
5. The FET of claim 1, wherein said electron source layer (22) has a stable bond with said barrier layer (18) under stresses created by increase electron fields, voltage or temperature.
6. The FET of claim 1, wherein the surface of said barrier layer (22) is substantially free of damage.
7. The FET of claim 1, wherein the forming of said electron source layer (22) causes substantially no damage to the surface of said barrier layer (18).
8. The FET of claim 1, wherein said electron source layer (22) comprises silicon nitride.
9. The FET of claim 1, further comprising a substrate (11) of sapphire or silicon carbide, said substrate (11) being adjacent to said non-conducting layer (20), opposite said barrier layer (18).
10. The FET of claim 9, wherein said substrate (11) is formed of a 4H polytype of silicon carbide.
11. The FET of claim 9, further comprising a buffer layer (12) between said non-conducting layer (20) and said substrate (11).
12. The FET of claim 11, wherein said buffer layer (12) is made of Al x Ga1-x N, x being between 0 and 1.
13. The FET of claim 1, wherein said non-conducting layer (20) and said barrier layer (18) are made of Group III
nitride semiconductor materials.
14. The FET of claim 1, wherein said barrier layer (18) is made of Al x Ga1-x N.
15. The FET of claim 1, wherein said barrier layer (18) is made of AlGaN and said non-conducting layer (20) is made of GaN.
16. The FET of claim 1, wherein said source and drain contacts (13,14) comprise an alloy of titanium, aluminum, and nickel.
17. The FET of claim 1, wherein said gate (16) is selected from a group consisting of titanium, platinum, chromium, alloys of titanium and tungsten, and platinum silicide.
18. The FET of claim 1, wherein said barrier layer (38) has a wider energy bandgap than said non-conducting layer (34), said FET further comprising a 2 dimensional electron gas (2DEG) (42) between said barrier layer (38) and non-conducting layer (34).
19. A high electron mobility transistor (HEMT), comprising:
a high resistivity, non-conducting semiconductor layer (34);
a barrier layer (38) on said high resistivity layer (34), said barrier layer (38) having a wider bandgap than said high resistivity layer (34);
a two dimensional electron gas (42) between said barrier layer (38) and said high resistivity layer (34);
respective source, drain and gate contacts (13, 14, 16) contacting said barrier layer (38) , with part
20 of the surface of said barrier layer (38) uncovered by said contacts (13,14,16); and an electron source layer (44) formed on the surface of said barrier layer (38) between said contacts (13,14,16), said electron source layer (44) having a high percentage of donor electrons (68).

20. The HEMT of claim 19, wherein said barrier layer (38) has positive charged traps (69) and wherein said donor electrons (68) neutralize said traps (69).
21. The HEMT of claim 20, wherein donor electrons (68) have a higher energy state than said traps (69).
22. The HEMT of claim 19, wherein said electron source layer (44) is a dielectric layer.
23. The HEMT of claim 19, wherein said electron source layer (44) has a stable bond with said barrier layer (38) under stresses created by increases in electron field, voltage or temperature.
24. The HEMT of claim 19, wherein the surface of said barrier layer (38) is substantially free of damage.
25. The HEMT of claim 19, wherein said electron source layer (44) comprises silicon nitride.
26. The HEMT of claim 19, further comprising a substrate (11) of sapphire or silicon carbide, said substrate (11) adjacent to said high resistivity layer (34), opposite said barrier layer (38).
27. The HEMT of claim 25, further comprising a buffer layer (12) between said high resistivity layer (34) and said substrate (11).
28. The HEMT of claim 19, wherein said high resistivity layer (34) and said barrier layer (38) are made of Group III nitride semiconductor materials.
29. The HEMT of claim 19, wherein said source and drain contacts (13,14,16) comprise an alloy of titanium, aluminum, and nickel.
30. The HEMT of claim 19, wherein said gate (16) is selected from a group consisting of titanium, platinum, chromium, alloys of titanium and tungsten, and platinum silicide.
31. A method for manufacturing a transistor (101) with an electron source layer (108) on its surface, comprising:
placing said transistor in a sputtering chamber (126);
sputtering said electron source layer (108) on said transistor in said sputtering chamber (128);
cooling and venting said sputtering chamber (130);
and removing said transistor from said sputtering chamber (130).
32. The method of claim 31, wherein said electron source layer (108) is a dielectric layer with a high percentage of donor electrons (68).
33. The method of claim 31, further comprising forming said transistor (122) and cleaning said transistor (124) prior to placing said transistor in said sputtering chamber (126).
34. The method of claim 33, wherein said transistor (101) is grown by metal-organic chemical vapor deposition (MOCVD).
35. The method of claim 33, wherein said transistor (101) is cleaned by rinsing said transistor with NH4OH:H2O (1:4) for approximately 10 to 60 seconds.
36. The method of claim 31, further comprising opening windows in said electron source layer (132) for contacts on said transistor (101) after said transistor (101) is removed from said chamber (130).
37. The method of claim 36, wherein said windows are opened in said electron source layer by etching(132).
38. The method of claim 31, wherein said transistor (101) is a FET or a HEMT.
39. The method of claim 31, wherein said electron source layer (108) is silicon nitride and said layer (108) is deposited on said transistor (101) by pumping down the said chamber (103) to a predetermined pressure, bombarding a silicon source (106) with a source gas to clean its surface, changing the chamber conditions to sputter the silicon (106), and allowing the sputtered silicon to react with nitrogen to deposit a silicon nitride layer (108) on said transistor (101).
40. The method of claim 31, wherein the forming of said electron source layer (108) causes substantially no damage to the surface of said transistor (101).
41. The method of claim 31, wherein said transistor (101) is formed in a substantially hydrogen free environment.
CA2399547A 2000-02-04 2001-02-01 Group iii nitride based fets and hemts with reduced trapping and method for producing the same Expired - Lifetime CA2399547C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US18043500P 2000-02-04 2000-02-04
US60/180,435 2000-02-04
US09/771,800 US6586781B2 (en) 2000-02-04 2001-01-29 Group III nitride based FETs and HEMTs with reduced trapping and method for producing the same
US09/771,800 2001-01-29
PCT/US2001/003433 WO2001057929A1 (en) 2000-02-04 2001-02-01 Group iii nitride based fets and hemts with reduced trapping and method for producing the same

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CA2399547A1 true CA2399547A1 (en) 2001-08-09
CA2399547C CA2399547C (en) 2011-04-19

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US (1) US6586781B2 (en)
EP (1) EP1261988B1 (en)
JP (1) JP5313424B2 (en)
KR (1) KR100710654B1 (en)
CN (1) CN1260827C (en)
AT (1) ATE525751T1 (en)
AU (1) AU2001233253A1 (en)
CA (1) CA2399547C (en)
MY (1) MY130244A (en)
WO (1) WO2001057929A1 (en)

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