CA2404270A1 - Three dimensional device integration method and integrated device - Google Patents

Three dimensional device integration method and integrated device Download PDF

Info

Publication number
CA2404270A1
CA2404270A1 CA002404270A CA2404270A CA2404270A1 CA 2404270 A1 CA2404270 A1 CA 2404270A1 CA 002404270 A CA002404270 A CA 002404270A CA 2404270 A CA2404270 A CA 2404270A CA 2404270 A1 CA2404270 A1 CA 2404270A1
Authority
CA
Canada
Prior art keywords
recited
substrate
bonding
elements
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002404270A
Other languages
French (fr)
Other versions
CA2404270C (en
Inventor
Paul M. Enquist
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Bonding Technologies Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24123592&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CA2404270(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Individual filed Critical Individual
Publication of CA2404270A1 publication Critical patent/CA2404270A1/en
Application granted granted Critical
Publication of CA2404270C publication Critical patent/CA2404270C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/043—Mechanically stacked PV cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
    • H01L31/0465—PV modules composed of a plurality of thin film solar cells deposited on the same substrate comprising particular structures for the electrical interconnection of adjacent PV cells in the module
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Abstract

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device (14) having a substrate (20) to an element (10) and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semi-conductor device. Interconnections (51) may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices (165) to an element (163), and the element may have recesses (167) in which the semiconductor devices are disposed. A conductor array (78) having a plurality of contact structures may be formed on an exposed surface of the semiconductor device (77), vias may be formed through the semiconductor device to device regions, and interconnection (81, 82, 83) may be formed between said device regions and said contact structures.

Claims (88)

1. A method of forming an integrated device, comprising:
forming a first bonding material on a first semiconductor device having a first substrate;
forming a second bonding material on a first element having a second substrate;
directly bonding said first and second bonding materials;
removing a portion of said first substrate to expose a remaining portion of said first semiconductor device; and mounting said integrated device in a package.
2. A method as recited in claim 1 comprising:
connecting said package to said first semiconductor device from an exposed side of said remaining portion of said first semiconductor device.
3. A method as recited in claim 1, comprising:
bonding said first semiconductor device having said first substrate with top and bottom sides, an active area being formed in said top side;
removing said portion from said bottom side; and connecting said package to said first semiconductor device from said bottom side.
4. A method as recited in claim 3, comprising:
directly bonding a second element having a third substrate to said remaining portion of said first semiconductor device;
removing substantially all of said first element; and connecting said first semiconductor device to said package from said top side.
5. A method as recited in claim 3, comprising:
forming a plurality of levels of interconnect in said first semiconductor device; and forming connections to at least one of said levels of interconnect from an exposed remaining portion side; and interconnecting said connections with said package.
6. A method as recited in claim 5, wherein forming connections comprises:
forming a plurality of levels of interconnect from an exposed remaining portion side.
7. A method as recited in claim 3, comprising:
directly bonding a third substrate to said remaining portion of said first semiconductor device;
exposing portions of said first semiconductor device from said top side; and connecting said semiconductor device to said package from said top side through said third substrate.
8. A method as recited in claim 7, wherein said first semiconductor device comprises a plurality of levels of interconnect; said method comprising:
forming connections to at least one of said levels of interconnect from an exposed remaining portion side; and interconnecting said connections with said package.
9. A method as recited in claim 1, comprising:
forming a connection directly to a device element region of said first semiconductor device.
10. A method of forming an integrated device, comprising:
bonding a first thermal spreading substrate to a first semiconductor device having a device substrate;
removing a portion of said device substrate to expose a remaining portion of said first semiconductor device; and bonding a second thermal spreading substrate to said remaining portion of said first semiconductor.
11. A method as recited in claim 10, comprising:
forming a plurality of levels of interconnect in said first semiconductor device; and forming connections to at least one of said levels of interconnect using said first thermal spreading substrate.
12. A method as recited in claim 11, comprising:
forming connections to at least one of said levels of interconnect using an areal contacting method.
13. A method as recited in claim 11, comprising:
forming a connection directly to a device element region of said first semiconductor device.
14. A method as recited in claim 10, comprising:
forming a plurality of levels of interconnect in said first semiconductor device; and forming connections to at least one of said levels of interconnect using said second thermal spreading substrate.
15. A method as recited in claim 14, comprising:
forming connections to at least one of said levels of interconnect using an areal contacting method.
16. A method as recited in claim 10, comprising:
forming interconnect structures in said semiconductor device accessible from a side exposed by removing said portion before said step of removing said portion.
17. A method as recited in claim 10, comprising:
forming interconnect structures in said semiconductor device, accessible from a side exposed by removing said portion, using processing from a side opposite said side exposed by removing said portion.
18. A method of forming an integrated device, comprising:
directly bonding a first semiconductor device having a first substrate to an element;
and removing a portion of said first substrate to expose a remaining portion of said first semiconductor device after said bonding;
wherein said element comprises one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements.
19. A method as recited in claim 18, comprising:
removing a portion of said remaining portion to expose a portion of said element.
20. A method as recited in claim 19, comprising:
interconnecting said remaining portion of said first semiconductor device with said element.
21. A method of forming an integrated system, comprising:
directly bonding a first component of a system to a second component of a system;
and interconnecting said first and second components.
22. A method as recited in claim 21, comprising:
bonding said first component to a second component having a substrate;

removing at least a portion of said substrate from a side of said second component;
and interconnecting said first and second components from said side of said second component.
23. A method as recited in claim 21, comprising:
bonding one of a shielding member and an isolation member to at least one of said first and second components.
24. A method as recited in claim 21, comprising:
bonding an antenna to at least one of said first and second components; and connecting said antenna to at least one said first and second components.
25. A method as recited in claim 21, comprising bonding an optical device as said first component to an electrical device as said second component.
26. A method as recited in claim 21, comprising:
bonding a lower-speed higher-density first semiconductor device as said first component to a higher-speed lower-density second semiconductor device as said second component.
27. A method as recited in claim 26, comprising:
bonding said first and second semiconductor devices of different technologies.
28. A method as recited in claim 26, comprising:
bonding a silicon device as said first semiconductor device to at least one III-V device as said second semiconductor device.
29. A method as recited in claim 21, comprising:
bonding a microprocessor on a first substrate comprising said first component to a high density memory device comprising said second component.
30. A method as recited in claim 21, comprising:
bonding a first solar cell comprising said first component to a second solar cell comprising said second component.
31. A method as recited in claim 30, comprising:
bonding at least a third solar cell to an element formed by bonding said first and second solar cells.
32. A method as recited in claim 21, comprising:
forming a void in a surface of said first component;
bonding said surface of said first component to a surface of said second component.
33. A method of integrating devices, comprising:
attaching a plurality of first elements to a surface of a substrate to form a second element; and directly bonding said second element, from a side to which said plurality of first elements are attached, to a third element.
34. A method as recited in claim 33, wherein attaching comprises:
directly bonding each of said plurality of first elements to said surface of said substrate to form said second element.
35. A method as recited in claim 34, comprising:
removing at least a portion of said second element after bonding said second element to said third element.
36. A method as recited in claim 34, comprising:
directly bonding a plurality of first semiconductor devices to said surface of said substrate; and directly bonding said second element to a third element comprising a second semiconductor device.
37. A method as recited in claim 34, comprising:
interconnecting said first elements with said third element.
38. A method as recited in claim 34, comprising:
interconnecting said first elements using said second element; and interconnecting said first elements and said third element using at least one of said second and third elements.
39. A method as recited in claim 34, comprising:
forming recesses in said second element; and bonding said plurality of first elements to said second element in said recesses.
40. A method as recited in claim 39, comprising:
removing at least a portion of said second element after bonding said second element to said third element.
41. A method as recited in claim 39, comprising:
directly bonding a plurality of first semiconductor devices to said surface of said substrate; and directly bonding said second element to a third element comprising a second semiconductor device.
42. A method as recited in claim 39, comprising:
interconnecting said first elements with said third element.
43. A method as recited in claim 39, comprising:
interconnecting said first elements using said second element; and interconnecting said first elements and said third element using at least one of said second and third elements.
44. A method as recited in claim 34, comprising:
directly bonding first semiconductor devices, as said first elements, on substrates; and directly bonding said first semiconductor devices to, as said second element;
at least one of a substrate used for thermal spreading, impedance matching, RF
isolation, antenna, a second semiconductor device, and a matching network comprised of at least one of passive elements and conductive layer patterning.
45. A method as recited in claim 44, comprising:
removing at least a portion of said substrates on which said first semiconductor devices are bonded.
46. A method as recited in claim 44, comprising:
interconnecting said first semiconductor devices with said second element.
47. A method of forming an integrated device, comprising:
forming a first bonding material on a first semiconductor device having a first substrate;
forming a second bonding material on a second element having a second substrate;
directly bonding said first and second bonding materials;
forming a conductor array having a plurality of contact structures on an exposed surface of said first semiconductor device;
forming vias through said first semiconductor device to device regions; and forming interconnection between said device regions and said contact structures.
48. A method as recited in claim 47, comprising:
forming a pin grid array as said conductor array.
49. A method as recited in claim 48, comprising:
mating said pin grid array with conductive regions formed on one of a board, card, and substrate.
50. A method as recited in claim 47, comprising:
mating said conductor array with conductive regions formed on at least one of a board, card, and substrate.
51. An integrated device, comprising:
a first device portion comprised of a first device having a first substrate from which said first substrate has been removed;
a first bonding material formed on said first device portion;
a first element;
a second bonding material formed on said first element; and said first bonding material directly bonded to said second bonding material.
52. An integrated device as recited in claim 51, wherein:
said first device portion comprises a first solar cell portion comprised of a first solar cell having said first substrate from which said first substrate has been removed;
said first element comprises a second solar cell having a second substrate;
and said integrated device comprising interconnections formed connecting said first solar cell portion and said second solar cell from a side of said first solar cell portion from which said first substrate is removed.
53. An integrated device as recited in claim 52, comprising:
at least a third solar cell portion, formed by removing a third substrate from a third solar cell;
a third bonding material formed on said third solar cell portion;
a fourth bonding material formed on said side of said first solar cell portion;
interconnections connecting said first solar cell portion, said second solar cell and said third solar cell portion formed from a side of said third solar cell portion from which said third substrate is removed.
54. An integrated device as recited in claim 51, wherein:

said first device portion comprises a semiconductor device having active elements;
and said first element comprises one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements.
55. An integrated device as recited in claim 51, wherein:
said first device portion comprises a remaining portion, having a first side and an opposing second side, of a first wafer having a first substrate from which substantially all of said first substrate has been removed from said first side of said remaining portion; and said first element is directly bonded to said second side of said remaining portion.
56. An integrated defice as recited in claim 55, comprising:
an interconnection connected to said first device portion from said first side.
57. An integrated device as recited in claim 56, wherein said interconnection comprises a multilayer interconnection.
58. An integrated device as recited in claim 55, wherein:
said remaining portion comprises no more than 10 microns of said first substrate.
59. An integrated device as recited in claim 55, wherein:
said remaining portion comprises no more than 20 microns of said first substrate.
60. An integrated device as recited in claim 55, comprising:
a package connected to said first device portion from said first side.
61. An integrated device as recited in claim 51, wherein:
said first device portion comprises a remaining portion, having a first side and an opposing second side, of a first wafer having a first substrate from which said first substrate has been substantially removed from said first side of said remaining portion;
and said first element is directly bonded to said first side of said remaining portion.
62. An integrated device as recited in claim 61, comprising:
an interconnection connected to said first device portion from said first side.
63. An integrated device as recited in claim 62, wherein said interconnection comprises a multilayer interconnection.
64. An integrated device as recited in claim 63, comprising:
a package connected to said first device from said second side.
65. An integrated device as recited in claim 51, wherein:
said first device portion comprises one of an active area of a memory and an active area of a microprocessor; and said first element comprises one of a microprocessor device and a memory device, respectively; and said integrated device comprises interconnections formed between said first device portion and said first element.
66. An integrated device as recited in claim 51, comprising:
one of a shielding member and an isolation member directly bonded to at least one of said first device portion and said first element.
67. An integrated device as recited in claim 51, comprising:
an antenna directly bonded to at least one of said first device portion and said first element; and interconnections connecting said antenna to at least one said first device portion and said first element.
68. An integrated device as recited in claim 51, wherein:
said first device portion comprises an optical device; and said first element comprises one of an electrical device and circuit.
69. An integrated device as recited in claim 51, wherein:
said first element comprises a lower-speed higher-density first semiconductor device;
and said first device portion comprises a higher-speed lower-density second semiconductor device.
70. An integrated device as recited in claim 69, comprising:
said first and second semiconductor devices being different technologies.
71. An integrated device as recited in claim 51, wherein:
said first element comprises a silicon processor; and said first device portion comprises a III-V device.
72. An integrated device, comprising:
a plurality of first elements each directly bonded to a surface of substrate to from a second element; and a third element directly bonded to said second elements from a side on which said first elements are bonded to said surface.
73. A device as recited in claim 72, comprising:
interconnections formed between said third element and selected ones of said plurality of first elements.
74. A device as recited in claim 72, comprising:
interconnections formed between selected ones of said plurality of first elements.
75. A device as recited in claim 72, comprising:
recesses formed in said substrate; and said first elements being disposed in said recesses.
76. An integrated device, comprising:
a device portion containing semiconductor devices having opposing top and bottom sides;
a first substrate directly bonded to said top side of said device portion; and a second substrate directly bonded to said bottom side of said device portion.
77. A device as recited in claim 76, comprising:
interconnections formed to said device portion through each of said first and second substrates.
78. A device as recited in claim 76, comprising:
power and ground interconnections formed to said device portion through only one of said first and second substrates.
79. A device as recited in claim 78, comprising:
at least one of signal and clock interconnections formed to said device portion through only the other of said first and second substrates.
80. A device as recited in claim 76, wherein said device portion comprises a plurality of device portions directly bonded to each other.
81. An integrated device, comprising:
a plurality of first elements each directly bonded to a surface of a second element.
82. A device as recited in claim 81, wherein:
first elements comprise at least one of first semiconductor devices, first patterned conductors, first antenna elements, and first impedance matching elements with passive components; and said second element comprises at least one of second semiconductor devices, second patterned conductors, second antenna elements, and second impedance matching elements with passive components.
83. A device as recited in claim 82, wherein said first elements comprise at least one of said first semiconductor devices, first patterned conductors, first antenna elements, and first impedance matching elements with passive components from which a substrate was removed.
84. A device as recited in claim 83, comprising:
vias formed in said first elements; and conductive material formed in said vias interconnecting said first elements to said second element.
85. An integrated device, comprising:
a first bonding material disposed on a first semiconductor device having a first substrate and first conductive regions;
a second bonding material disposed on a first element having a second substrate and directly bonded to the first bonding material;
a conductive array disposed on an exposed surface of first element having a plurality of second conductive regions; and interconnection formed between said first and second conductive regions.
86. A device as recited in claim 85, wherein said conductive array comprises a pin grid array.
87. A device as recited in claim 86, comprising:
conducting regions formed on at least one of a board, card, and substrate mated with said second conductive regions.
88. A device as recited in claim 85, comprising:
conducting regions formed on at least one of a board, card, and substrate mated with said second conductive regions.
CA2404270A 2000-03-22 2001-03-22 Three dimensional device integration method and integrated device Expired - Fee Related CA2404270C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/532,886 2000-03-22
US09/532,886 US6500694B1 (en) 2000-03-22 2000-03-22 Three dimensional device integration method and integrated device
PCT/US2001/008617 WO2001071797A1 (en) 2000-03-22 2001-03-22 Three dimensional device integration method and integrated device

Publications (2)

Publication Number Publication Date
CA2404270A1 true CA2404270A1 (en) 2001-09-27
CA2404270C CA2404270C (en) 2011-02-22

Family

ID=24123592

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2404270A Expired - Fee Related CA2404270C (en) 2000-03-22 2001-03-22 Three dimensional device integration method and integrated device

Country Status (8)

Country Link
US (4) US6500694B1 (en)
EP (1) EP1277232A4 (en)
JP (4) JP2003528466A (en)
KR (1) KR100916376B1 (en)
AU (1) AU2001247536A1 (en)
CA (1) CA2404270C (en)
TW (1) TW480628B (en)
WO (1) WO2001071797A1 (en)

Families Citing this family (356)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8018058B2 (en) * 2004-06-21 2011-09-13 Besang Inc. Semiconductor memory device
US7470142B2 (en) * 2004-06-21 2008-12-30 Sang-Yun Lee Wafer bonding method
US20050280155A1 (en) * 2004-06-21 2005-12-22 Sang-Yun Lee Semiconductor bonding and layer transfer method
US8058142B2 (en) * 1996-11-04 2011-11-15 Besang Inc. Bonded semiconductor structure and method of making the same
FR2773261B1 (en) 1997-12-30 2000-01-28 Commissariat Energie Atomique METHOD FOR THE TRANSFER OF A THIN FILM COMPRISING A STEP OF CREATING INCLUSIONS
US20030135294A1 (en) * 1998-10-09 2003-07-17 Lam Peter Ar-Fu Sound generation IC chip set
DE19929567B4 (en) * 1999-06-21 2005-06-23 Deutsches Elektronen-Synchrotron Desy Detector module for X-ray detector system
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP2001326284A (en) * 2000-05-17 2001-11-22 Nec Corp Compound semiconductor integrated circuit and its manufacturing method
SG136795A1 (en) * 2000-09-14 2007-11-29 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
KR100394808B1 (en) * 2001-07-19 2003-08-14 삼성전자주식회사 Wafer level stack chip package and method for manufacturing the same
US7351660B2 (en) * 2001-09-28 2008-04-01 Hrl Laboratories, Llc Process for producing high performance interconnects
US7018575B2 (en) * 2001-09-28 2006-03-28 Hrl Laboratories, Llc Method for assembly of complementary-shaped receptacle site and device microstructures
US6974604B2 (en) * 2001-09-28 2005-12-13 Hrl Laboratories, Llc Method of self-latching for adhesion during self-assembly of electronic or optical components
US7253091B2 (en) * 2001-09-28 2007-08-07 Hrl Laboratories, Llc Process for assembling three-dimensional systems on a chip and structure thus obtained
US6812064B2 (en) * 2001-11-07 2004-11-02 Micron Technology, Inc. Ozone treatment of a ground semiconductor die to improve adhesive bonding to a substrate
US6777648B2 (en) * 2002-01-11 2004-08-17 Intel Corporation Method and system to manufacture stacked chip devices
US6908791B2 (en) * 2002-04-29 2005-06-21 Texas Instruments Incorporated MEMS device wafer-level package
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6946322B2 (en) * 2002-07-25 2005-09-20 Hrl Laboratories, Llc Large area printing method for integrating device and circuit components
US6875995B2 (en) * 2002-08-16 2005-04-05 Cree, Inc. Heterogeneous bandgap structures for semiconductor devices and manufacturing methods therefor
US6822326B2 (en) 2002-09-25 2004-11-23 Ziptronix Wafer bonding hermetic encapsulation
US7307003B2 (en) * 2002-12-31 2007-12-11 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure incorporating a processing handle member
US7064055B2 (en) * 2002-12-31 2006-06-20 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure having a seamless bonding interface
US20040124538A1 (en) * 2002-12-31 2004-07-01 Rafael Reif Multi-layer integrated semiconductor structure
US20100133695A1 (en) * 2003-01-12 2010-06-03 Sang-Yun Lee Electronic circuit with embedded memory
US6849951B1 (en) 2003-02-28 2005-02-01 Xilinx, Inc. Bypass capacitor solution for integrated circuit dice
US6917219B2 (en) * 2003-03-12 2005-07-12 Xilinx, Inc. Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice
US6756305B1 (en) 2003-04-01 2004-06-29 Xilinx, Inc. Stacked dice bonded with aluminum posts
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7109635B1 (en) * 2003-06-11 2006-09-19 Sawtek, Inc. Wafer level packaging of materials with different coefficients of thermal expansion
US8071438B2 (en) * 2003-06-24 2011-12-06 Besang Inc. Semiconductor circuit
US20100190334A1 (en) * 2003-06-24 2010-07-29 Sang-Yun Lee Three-dimensional semiconductor structure and method of manufacturing the same
US7068072B2 (en) 2003-06-30 2006-06-27 Xilinx, Inc. Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit
US7548205B2 (en) * 2003-07-15 2009-06-16 Farrokh Mohamadi Wafer scale antenna module with a backside connectivity
FR2857953B1 (en) * 2003-07-21 2006-01-13 Commissariat Energie Atomique STACKED STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME
US7223635B1 (en) 2003-07-25 2007-05-29 Hrl Laboratories, Llc Oriented self-location of microstructures with alignment structures
US7230512B1 (en) 2003-08-19 2007-06-12 Triquint, Inc. Wafer-level surface acoustic wave filter package with temperature-compensating characteristics
US7344903B2 (en) 2003-09-17 2008-03-18 Luminus Devices, Inc. Light emitting device processes
US7341880B2 (en) 2003-09-17 2008-03-11 Luminus Devices, Inc. Light emitting device processes
US7723208B2 (en) * 2003-09-24 2010-05-25 Intel Corporation Integrated re-combiner for electroosmotic pumps using porous frits
US7459790B2 (en) 2003-10-15 2008-12-02 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US20050104027A1 (en) * 2003-10-17 2005-05-19 Lazarev Pavel I. Three-dimensional integrated circuit with integrated heat sinks
FR2861497B1 (en) 2003-10-28 2006-02-10 Soitec Silicon On Insulator METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION
US6958548B2 (en) * 2003-11-19 2005-10-25 Freescale Semiconductor, Inc. Semiconductor device with magnetically permeable heat sink
FR2864336B1 (en) * 2003-12-23 2006-04-28 Commissariat Energie Atomique METHOD FOR SEALING TWO PLATES WITH FORMATION OF AN OHMIC CONTACT BETWEEN THEM
GB0330010D0 (en) 2003-12-24 2004-01-28 Cavendish Kinetics Ltd Method for containing a device and a corresponding device
KR101127888B1 (en) * 2004-02-06 2012-03-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing thin film integrated circuit, and element substrate
US7041576B2 (en) * 2004-05-28 2006-05-09 Freescale Semiconductor, Inc. Separately strained N-channel and P-channel transistors
US20050280088A1 (en) * 2004-06-18 2005-12-22 Min Byoung W Backside body contact
US7507638B2 (en) * 2004-06-30 2009-03-24 Freescale Semiconductor, Inc. Ultra-thin die and method of fabricating same
FR2872627B1 (en) * 2004-06-30 2006-08-18 Commissariat Energie Atomique MOLECULAR ADHESION ASSEMBLY OF TWO SUBSTRATES
US9466595B2 (en) * 2004-10-04 2016-10-11 Intel Corporation Fabrication of stacked die and structures formed thereby
US7158220B2 (en) * 2004-10-19 2007-01-02 Guobiao Zhang Three-dimensional memory system-on-a-chip
US6949008B1 (en) * 2004-10-19 2005-09-27 Agilent Technologies, Inc. System and method for planarizing a substrate surface having a non-planar surface topography
FR2877142B1 (en) * 2004-10-21 2007-05-11 Commissariat Energie Atomique METHOD OF TRANSFERRING AT LEAST ONE MICROMETRIC OR MILLIMETRIC SIZE OBJECT USING A POLYMER HANDLE
US7563691B2 (en) * 2004-10-29 2009-07-21 Hewlett-Packard Development Company, L.P. Method for plasma enhanced bonding and bonded structures formed by plasma enhanced bonding
US7633505B1 (en) 2004-11-17 2009-12-15 Nvidia Corporation Apparatus, system, and method for joint processing in graphics processing units
US7598958B1 (en) * 2004-11-17 2009-10-06 Nvidia Corporation Multi-chip graphics processing unit apparatus, system, and method
EP1851369A1 (en) 2005-01-26 2007-11-07 Apollo Diamond, Inc. Gallium nitride light emitting devices on diamond
US7355247B2 (en) * 2005-03-03 2008-04-08 Intel Corporation Silicon on diamond-like carbon devices
US20110143506A1 (en) * 2009-12-10 2011-06-16 Sang-Yun Lee Method for fabricating a semiconductor memory device
US8367524B2 (en) * 2005-03-29 2013-02-05 Sang-Yun Lee Three-dimensional integrated circuit structure
JP2007005620A (en) * 2005-06-24 2007-01-11 Dainippon Printing Co Ltd Organic thin film solar cell
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US7166520B1 (en) * 2005-08-08 2007-01-23 Silicon Genesis Corporation Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process
US20070032044A1 (en) * 2005-08-08 2007-02-08 Silicon Genesis Corporation Method and structure for fabricating devices using one or more films provided by a layer transfer process and etch back
US20070029043A1 (en) * 2005-08-08 2007-02-08 Silicon Genesis Corporation Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process
US7485968B2 (en) * 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7427554B2 (en) * 2005-08-12 2008-09-23 Silicon Genesis Corporation Manufacturing strained silicon substrates using a backing material
FR2889887B1 (en) * 2005-08-16 2007-11-09 Commissariat Energie Atomique METHOD FOR DEFERING A THIN LAYER ON A SUPPORT
JP4908801B2 (en) * 2005-08-16 2012-04-04 株式会社神戸製鋼所 Copper base material for electronic parts and electronic parts
FR2891281B1 (en) 2005-09-28 2007-12-28 Commissariat Energie Atomique METHOD FOR MANUFACTURING A THIN FILM ELEMENT
US8499824B2 (en) * 2005-10-04 2013-08-06 Elektronische Bauelemente Gesellschaft M.B.H. Heat sink
US20070145367A1 (en) * 2005-12-27 2007-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure
US7626257B2 (en) * 2006-01-18 2009-12-01 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7414316B2 (en) * 2006-03-01 2008-08-19 Freescale Semiconductor, Inc. Methods and apparatus for thermal isolation in vertically-integrated semiconductor devices
US7863157B2 (en) 2006-03-17 2011-01-04 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
CN101512721A (en) 2006-04-05 2009-08-19 硅源公司 Method and structure for fabricating solar cells using a layer transfer process
US20070279053A1 (en) * 2006-05-12 2007-12-06 Taylor William P Integrated current sensor
US8153513B2 (en) 2006-07-25 2012-04-10 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process
US8021981B2 (en) 2006-08-30 2011-09-20 Micron Technology, Inc. Redistribution layers for microfeature workpieces, and associated systems and methods
JP4913517B2 (en) * 2006-09-26 2012-04-11 株式会社ディスコ Wafer grinding method
FR2910179B1 (en) 2006-12-19 2009-03-13 Commissariat Energie Atomique METHOD FOR MANUFACTURING THIN LAYERS OF GaN BY IMPLANTATION AND RECYCLING OF A STARTING SUBSTRATE
US8110425B2 (en) 2007-03-20 2012-02-07 Luminus Devices, Inc. Laser liftoff structure and related methods
US7869225B2 (en) * 2007-04-30 2011-01-11 Freescale Semiconductor, Inc. Shielding structures for signal paths in electronic devices
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US20090050939A1 (en) * 2007-07-17 2009-02-26 Briere Michael A Iii-nitride device
US20090206275A1 (en) * 2007-10-03 2009-08-20 Silcon Genesis Corporation Accelerator particle beam apparatus and method for low contaminate processing
US8219738B2 (en) * 2007-12-03 2012-07-10 Spansion Llc Direct interconnection between processor and memory component
US7781238B2 (en) * 2007-12-06 2010-08-24 Robert Gideon Wodnicki Methods of making and using integrated and testable sensor array
FR2925221B1 (en) * 2007-12-17 2010-02-19 Commissariat Energie Atomique METHOD FOR TRANSFERRING A THIN LAYER
US7795073B2 (en) * 2008-02-01 2010-09-14 Hynix Semiconductor Inc. Method for manufacturing stack package using through-electrodes
US7989262B2 (en) * 2008-02-22 2011-08-02 Cavendish Kinetics, Ltd. Method of sealing a cavity
US8273603B2 (en) 2008-04-04 2012-09-25 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
US8017451B2 (en) * 2008-04-04 2011-09-13 The Charles Stark Draper Laboratory, Inc. Electronic modules and methods for forming the same
US7993950B2 (en) * 2008-04-30 2011-08-09 Cavendish Kinetics, Ltd. System and method of encapsulation
US8853830B2 (en) 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
KR101285976B1 (en) * 2008-07-02 2013-07-23 한양대학교 산학협력단 Energy generating device type of integrated chip using 3-Dimension LSI technology
US8017471B2 (en) 2008-08-06 2011-09-13 International Business Machines Corporation Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
US8030780B2 (en) 2008-10-16 2011-10-04 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
US20100109115A1 (en) * 2008-11-03 2010-05-06 Ure Michael J Virtual IC wafers and bonding of constitutent IC films
US7863097B2 (en) * 2008-11-07 2011-01-04 Raytheon Company Method of preparing detectors for oxide bonding to readout integrated chips
FR2938202B1 (en) * 2008-11-07 2010-12-31 Soitec Silicon On Insulator SURFACE TREATMENT FOR MOLECULAR ADHESION
CN102308346B (en) * 2008-12-03 2014-01-29 平面磁性有限公司 An integrated planar variable transformer
JP5985136B2 (en) 2009-03-19 2016-09-06 ソニー株式会社 SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE
US8754533B2 (en) 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US8362800B2 (en) 2010-10-13 2013-01-29 Monolithic 3D Inc. 3D semiconductor device including field repairable logics
US8378715B2 (en) 2009-04-14 2013-02-19 Monolithic 3D Inc. Method to construct systems
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US9711407B2 (en) 2009-04-14 2017-07-18 Monolithic 3D Inc. Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US8405420B2 (en) 2009-04-14 2013-03-26 Monolithic 3D Inc. System comprising a semiconductor device and structure
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US8427200B2 (en) 2009-04-14 2013-04-23 Monolithic 3D Inc. 3D semiconductor device
US8362482B2 (en) 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US7986042B2 (en) 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US8384426B2 (en) 2009-04-14 2013-02-26 Monolithic 3D Inc. Semiconductor device and structure
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8373439B2 (en) 2009-04-14 2013-02-12 Monolithic 3D Inc. 3D semiconductor device
US8691664B2 (en) * 2009-04-20 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Backside process for a substrate
US20100270668A1 (en) * 2009-04-28 2010-10-28 Wafer-Level Packaging Portfolio Llc Dual Interconnection in Stacked Memory and Controller Module
US8072056B2 (en) 2009-06-10 2011-12-06 Medtronic, Inc. Apparatus for restricting moisture ingress
FR2947098A1 (en) 2009-06-18 2010-12-24 Commissariat Energie Atomique METHOD OF TRANSFERRING A THIN LAYER TO A TARGET SUBSTRATE HAVING A THERMAL EXPANSION COEFFICIENT DIFFERENT FROM THAT OF THE THIN LAYER
US8172760B2 (en) 2009-06-18 2012-05-08 Medtronic, Inc. Medical device encapsulated within bonded dies
US8409366B2 (en) 2009-06-23 2013-04-02 Oki Data Corporation Separation method of nitride semiconductor layer, semiconductor device, manufacturing method thereof, semiconductor wafer, and manufacturing method thereof
JP5224470B2 (en) * 2009-07-31 2013-07-03 国立大学法人東北大学 Photoelectric conversion member
US8296578B1 (en) 2009-08-03 2012-10-23 Xilinx, Inc. Method and apparatus for communicating data between stacked integrated circuits
WO2011036278A1 (en) * 2009-09-24 2011-03-31 Option Layout of contact pads of a system in package, comprising circuit board and electronic integrated elements
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US8536023B2 (en) 2010-11-22 2013-09-17 Monolithic 3D Inc. Method of manufacturing a semiconductor device and structure
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US8476145B2 (en) 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US8294159B2 (en) 2009-10-12 2012-10-23 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8450804B2 (en) 2011-03-06 2013-05-28 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US8581349B1 (en) 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US20110156197A1 (en) * 2009-12-31 2011-06-30 Tivarus Cristian A Interwafer interconnects for stacked CMOS image sensors
US20110156195A1 (en) * 2009-12-31 2011-06-30 Tivarus Cristian A Interwafer interconnects for stacked CMOS image sensors
US8461035B1 (en) 2010-09-30 2013-06-11 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US8541819B1 (en) 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US8026521B1 (en) 2010-10-11 2011-09-27 Monolithic 3D Inc. Semiconductor device and structure
US8373230B1 (en) 2010-10-13 2013-02-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
KR101134819B1 (en) 2010-07-02 2012-04-13 이상윤 Method for fabricating semiconductor memory
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US8411444B2 (en) 2010-09-15 2013-04-02 International Business Machines Corporation Thermal interface material application for integrated circuit cooling
KR101696644B1 (en) * 2010-09-15 2017-01-16 삼성전자주식회사 Rf stacked module using three dimension vertical interconnection and arrangement method thereof
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US8163581B1 (en) 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US8114757B1 (en) 2010-10-11 2012-02-14 Monolithic 3D Inc. Semiconductor device and structure
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US8379458B1 (en) 2010-10-13 2013-02-19 Monolithic 3D Inc. Semiconductor device and structure
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US8666505B2 (en) 2010-10-26 2014-03-04 Medtronic, Inc. Wafer-scale package including power source
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US8424388B2 (en) 2011-01-28 2013-04-23 Medtronic, Inc. Implantable capacitive pressure sensor apparatus and methods regarding same
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US9029173B2 (en) 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8778737B2 (en) 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
US8748885B2 (en) 2012-02-10 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Soft material wafer bonding and method of bonding
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
KR101326355B1 (en) 2012-08-02 2013-11-11 숭실대학교산학협력단 Method of manufacturing integrated circuit for wireless communication and integrated circuit thereof
US8878344B2 (en) 2012-10-18 2014-11-04 Analog Devices, Inc. Compound semiconductor lateral PNP bipolar transistors
US8686428B1 (en) 2012-11-16 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US8574929B1 (en) 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US8921992B2 (en) 2013-03-14 2014-12-30 Raytheon Company Stacked wafer with coolant channels
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
CN104282688B (en) * 2013-07-01 2017-05-10 中芯国际集成电路制造(上海)有限公司 Integrated circuit and manufacturing method thereof
WO2015001662A1 (en) * 2013-07-05 2015-01-08 株式会社日立製作所 Semiconductor device and manufacturing method for same
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
KR102177702B1 (en) 2014-02-03 2020-11-11 삼성전자주식회사 Via Structures and Semiconductor Devices Having a Via plug
KR102206378B1 (en) * 2014-06-13 2021-01-22 인텔 코포레이션 Surface encapsulation for wafer bonding
FR3030881A1 (en) * 2014-12-22 2016-06-24 Commissariat Energie Atomique METHOD FOR MAKING AN INTEGRATED CIRCUIT IN THREE DIMENSIONS
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US9343499B1 (en) * 2015-04-23 2016-05-17 Omnivision Technologies, Inc. Integrated circuit stack with strengthened wafer bonding
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
KR102424402B1 (en) * 2015-08-13 2022-07-25 삼성전자주식회사 Semiconductor packages and methods for fabricating the same
US9859896B1 (en) 2015-09-11 2018-01-02 Xilinx, Inc. Distributed multi-die routing in a multi-chip module
CN108401468A (en) 2015-09-21 2018-08-14 莫诺利特斯3D有限公司 3D semiconductor devices and structure
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US9673220B1 (en) 2016-03-09 2017-06-06 Globalfoundries Inc. Chip structures with distributed wiring
US10354975B2 (en) 2016-05-16 2019-07-16 Raytheon Company Barrier layer for interconnects in 3D integrated device
KR102603279B1 (en) 2016-07-01 2023-11-17 인텔 코포레이션 Reduced back contact resistance for semiconductor devices with metallization on both sides
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US10168475B2 (en) 2017-01-18 2019-01-01 Juniper Networks, Inc. Atomic layer deposition bonding for heterogeneous integration of photonics and electronics
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US11256004B2 (en) * 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10403577B1 (en) 2018-05-03 2019-09-03 Invensas Corporation Dielets on flexible and stretchable packaging for microelectronics
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
KR20210009426A (en) 2018-06-13 2021-01-26 인벤사스 본딩 테크놀로지스 인코포레이티드 TV as a pad
US10566686B2 (en) * 2018-06-28 2020-02-18 Micron Technology, Inc. Stacked memory package incorporating millimeter wave antenna in die stack
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
CN109686736B (en) * 2018-12-25 2021-02-26 电子科技大学 N-type epitaxy based JCD integrated device and preparation method thereof
KR20200089970A (en) * 2019-01-18 2020-07-28 삼성전자주식회사 Integrated circuit chip, and integrated circuit package and display apparatus including integrated circuit chip
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
CN112133820A (en) * 2019-06-25 2020-12-25 中电海康集团有限公司 Method for preparing MRAM bottom electrode
WO2021236361A1 (en) 2020-05-19 2021-11-25 Invensas Bonding Technologies, Inc. Laterally unconfined structure
WO2022024361A1 (en) 2020-07-31 2022-02-03 三菱電機株式会社 Active phased array antenna
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11562984B1 (en) 2020-10-14 2023-01-24 Hrl Laboratories, Llc Integrated mechanical aids for high accuracy alignable-electrical contacts
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die

Family Cites Families (147)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US588010A (en) * 1897-08-10 Valve-registering device
US3587166A (en) 1965-02-26 1971-06-28 Texas Instruments Inc Insulated isolation techniques in integrated circuits
US3423823A (en) 1965-10-18 1969-01-28 Hewlett Packard Co Method for making thin diaphragms
US3488834A (en) 1965-10-20 1970-01-13 Texas Instruments Inc Microelectronic circuit formed in an insulating substrate and method of making same
DE1665794C3 (en) 1966-10-28 1974-06-12 Siemens Ag, 1000 Berlin Und 8000 Muenchen Method for producing a magnetic field-dependent resistor arrangement
US3579391A (en) 1967-01-05 1971-05-18 Trw Inc Method of producing dielectric isolation for monolithic circuit
NL158024B (en) 1967-05-13 1978-09-15 Philips Nv PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY APPLYING THE PROCEDURE.
US3508980A (en) 1967-07-26 1970-04-28 Motorola Inc Method of fabricating an integrated circuit structure with dielectric isolation
GB1206308A (en) 1967-11-22 1970-09-23 Sony Corp Method of making semiconductor wafer
GB1186340A (en) 1968-07-11 1970-04-02 Standard Telephones Cables Ltd Manufacture of Semiconductor Devices
NL6910274A (en) 1969-07-04 1971-01-06
US3888708A (en) 1972-02-17 1975-06-10 Kensall D Wise Method for forming regions of predetermined thickness in silicon
JPS54116888A (en) 1978-03-03 1979-09-11 Hitachi Ltd Manufacture of dielectric separate substrate
JPS54155770A (en) 1978-05-29 1979-12-08 Nec Corp Manufacture of semiconductor device
US4416054A (en) 1980-07-01 1983-11-22 Westinghouse Electric Corp. Method of batch-fabricating flip-chip bonded dual integrated circuit arrays
JPS60167439A (en) 1984-02-10 1985-08-30 Nec Corp Manufacture of complementary dielectric isolation substrate
JPS6130059A (en) 1984-07-20 1986-02-12 Nec Corp Manufacture of semiconductor device
US4617160A (en) 1984-11-23 1986-10-14 Irvine Sensors Corporation Method for fabricating modules comprising uniformly stacked, aligned circuit-carrying layers
US4754544A (en) 1985-01-30 1988-07-05 Energy Conversion Devices, Inc. Extremely lightweight, flexible semiconductor device arrays
US4649630A (en) 1985-04-01 1987-03-17 Motorola, Inc. Process for dielectrically isolated semiconductor structure
NL8501773A (en) 1985-06-20 1987-01-16 Philips Nv METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES
JPS6231138A (en) 1985-08-02 1987-02-10 Nec Corp Dielectric isolation semiconductor integrated circuit device
US4829018A (en) 1986-06-27 1989-05-09 Wahlstrom Sven E Multilevel integrated circuits employing fused oxide layers
NL8700033A (en) * 1987-01-09 1988-08-01 Philips Nv METHOD FOR MANUFACTURING A SEMICONDUCTOR SEMICONDUCTOR TYPE ON ISOLATOR
JPS63237408A (en) 1987-03-26 1988-10-03 Sumitomo Metal Mining Co Ltd Substrate for semiconductor device
JPS63246841A (en) 1987-04-02 1988-10-13 Toshiba Corp Dielectric isolating method of silicon crystal body
US5196375A (en) 1987-07-24 1993-03-23 Kabushiki Kaisha Toshiba Method for manufacturing bonded semiconductor body
US5121706A (en) 1987-10-16 1992-06-16 The Curators Of The University Of Missouri Apparatus for applying a composite insulative coating to a substrate
US4963505A (en) 1987-10-27 1990-10-16 Nippondenso Co., Ltd. Semiconductor device and method of manufacturing same
JPH01259546A (en) 1988-04-08 1989-10-17 Fujitsu Ltd Manufacture of semiconductor device
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
NL8801981A (en) 1988-08-09 1990-03-01 Philips Nv METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
US4962879A (en) 1988-12-19 1990-10-16 Duke University Method for bubble-free bonding of silicon wafers
JPH02177435A (en) 1988-12-28 1990-07-10 Sony Corp Manufacture of semiconductor substrate
US5070026A (en) 1989-06-26 1991-12-03 Spire Corporation Process of making a ferroelectric electronic component and product
JPH0344067A (en) 1989-07-11 1991-02-25 Nec Corp Laminating method of semiconductor substrate
US5071792A (en) 1990-11-05 1991-12-10 Harris Corporation Process for forming extremely thin integrated circuit dice
JP2750163B2 (en) 1989-08-10 1998-05-13 沖電気工業株式会社 Method of manufacturing dielectric separated semiconductor device
JPH03101128A (en) 1989-09-13 1991-04-25 Casio Comput Co Ltd Manufacture of semiconductor chip
GB2237929A (en) 1989-10-23 1991-05-15 Philips Electronic Associated A method of manufacturing a semiconductor device
US4978421A (en) 1989-11-13 1990-12-18 International Business Machines Corporation Monolithic silicon membrane device fabrication process
US5849627A (en) 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
US5387555A (en) 1992-09-03 1995-02-07 Harris Corporation Bonded wafer processing with metal silicidation
US5081061A (en) 1990-02-23 1992-01-14 Harris Corporation Manufacturing ultra-thin dielectrically isolated wafers
US5034343A (en) 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
US5024723A (en) 1990-05-07 1991-06-18 Goesele Ulrich M Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning
JPH07118505B2 (en) 1990-12-28 1995-12-18 信越半導体株式会社 Method for manufacturing dielectric isolation substrate
US5668057A (en) 1991-03-13 1997-09-16 Matsushita Electric Industrial Co., Ltd. Methods of manufacture for electronic components having high-frequency elements
US5747857A (en) 1991-03-13 1998-05-05 Matsushita Electric Industrial Co., Ltd. Electronic components having high-frequency elements and methods of manufacture therefor
US5162251A (en) 1991-03-18 1992-11-10 Hughes Danbury Optical Systems, Inc. Method for making thinned charge-coupled devices
DE4115046A1 (en) 1991-05-08 1992-11-12 Fraunhofer Ges Forschung DIRECT SUBSTRATE BONDING
US5270261A (en) * 1991-09-13 1993-12-14 International Business Machines Corporation Three dimensional multichip package methods of fabrication
US5266511A (en) 1991-10-02 1993-11-30 Fujitsu Limited Process for manufacturing three dimensional IC's
US5561303A (en) 1991-11-07 1996-10-01 Harris Corporation Silicon on diamond circuit structure
US5321301A (en) 1992-04-08 1994-06-14 Nec Corporation Semiconductor device
US5427638A (en) * 1992-06-04 1995-06-27 Alliedsignal Inc. Low temperature reaction bonding
JPH06291587A (en) 1992-07-08 1994-10-18 Matsushita Electric Ind Co Ltd Piezoelectric vibrator
DE69321430T2 (en) 1992-07-08 1999-04-29 Matsushita Electric Ind Co Ltd Optical waveguide and its manufacturing process
US5489554A (en) 1992-07-21 1996-02-06 Hughes Aircraft Company Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer
JP3192000B2 (en) 1992-08-25 2001-07-23 キヤノン株式会社 Semiconductor substrate and manufacturing method thereof
JPH06112451A (en) 1992-09-29 1994-04-22 Nagano Denshi Kogyo Kk Manufacture of soi substrate
US5324687A (en) 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
KR0137125B1 (en) 1992-11-16 1998-06-15 모리시타 요이찌 An optical wave guide device and a method for fabricating the same
US5503704A (en) 1993-01-06 1996-04-02 The Regents Of The University Of California Nitrogen based low temperature direct bonding
WO2004077537A1 (en) 1993-01-18 2004-09-10 Shinsuke Sakai Method of fabrication of semiconductor substrate
US5591678A (en) 1993-01-19 1997-01-07 He Holdings, Inc. Process of manufacturing a microelectric device using a removable support substrate and etch-stop
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JP2701709B2 (en) 1993-02-16 1998-01-21 株式会社デンソー Method and apparatus for directly joining two materials
US5349207A (en) 1993-02-22 1994-09-20 Texas Instruments Incorporated Silicon carbide wafer bonded to a silicon wafer
US5272104A (en) 1993-03-11 1993-12-21 Harris Corporation Bonded wafer process incorporating diamond insulator
US5354605A (en) 1993-04-02 1994-10-11 Alliedsignal Inc. Soft armor composite
US5516727A (en) 1993-04-19 1996-05-14 International Business Machines Corporation Method for encapsulating light emitting diodes
EP0695494B1 (en) 1993-04-23 2001-02-14 Irvine Sensors Corporation Electronic module comprising a stack of ic chips
DE69426789T2 (en) 1993-04-28 2001-08-02 Matsushita Electric Ind Co Ltd Surface acoustic wave device and manufacturing method therefor
US5647932A (en) 1993-05-18 1997-07-15 Matsushita Electric Industrial Co., Ltd. Method of processing a piezoelectric device
JP2771423B2 (en) 1993-05-20 1998-07-02 日本電気株式会社 Bipolar transistor
US5456539A (en) * 1993-05-25 1995-10-10 Duplex Printer, Inc. Printer with dual opposing printheads
US5441591A (en) 1993-06-07 1995-08-15 The United States Of America As Represented By The Secretary Of The Navy Silicon to sapphire bond
JPH06350371A (en) 1993-06-10 1994-12-22 Matsushita Electric Ind Co Ltd Manufacture of piezoelectric device
JP2856030B2 (en) 1993-06-29 1999-02-10 信越半導体株式会社 Method for manufacturing bonded wafer
JP3806151B2 (en) 1993-07-13 2006-08-09 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method for coupling first object to second object
EP1178530A2 (en) 1993-09-30 2002-02-06 Kopin Corporation Three-dimensional processor using transferred thin film circuits
JPH07193294A (en) 1993-11-01 1995-07-28 Matsushita Electric Ind Co Ltd Electronic component and its manufacture
JPH07161705A (en) * 1993-12-03 1995-06-23 Nec Corp Method of forming interlayer insulating film of multilayered wiring of semiconductor device
EP0657900B1 (en) 1993-12-06 1998-03-25 Matsushita Electric Industrial Co., Ltd. Hybrid magnetic structure and method for producing the same
US5460659A (en) * 1993-12-10 1995-10-24 Spectrolab, Inc. Concentrating photovoltaic module and fabrication method
DE4400985C1 (en) 1994-01-14 1995-05-11 Siemens Ag Method for producing a three-dimensional circuit arrangement
TW289837B (en) 1994-01-18 1996-11-01 Hwelett Packard Co
FR2715502B1 (en) 1994-01-26 1996-04-05 Commissariat Energie Atomique Structure having cavities and method for producing such a structure.
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5362659A (en) 1994-04-25 1994-11-08 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating vertical bipolar junction transistors in silicon bonded to an insulator
US5517754A (en) * 1994-06-02 1996-05-21 International Business Machines Corporation Fabrication processes for monolithic electronic modules
DE59510807D1 (en) 1994-07-05 2003-11-20 Infineon Technologies Ag METHOD FOR PRODUCING A THREE-DIMENSIONAL CIRCUIT ARRANGEMENT
JPH0822987A (en) * 1994-07-05 1996-01-23 Asahi Chem Ind Co Ltd Semiconductor device and its manufacture
US5880010A (en) 1994-07-12 1999-03-09 Sun Microsystems, Inc. Ultrathin electronics
DE4433833A1 (en) * 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Method for producing a three-dimensional integrated circuit while achieving high system yields
DE4433846C2 (en) 1994-09-22 1999-06-02 Fraunhofer Ges Forschung Method of making a vertical integrated circuit structure
DE4433845A1 (en) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Method of manufacturing a three-dimensional integrated circuit
IT1268123B1 (en) * 1994-10-13 1997-02-20 Sgs Thomson Microelectronics SLICE OF SEMICONDUCTOR MATERIAL FOR THE MANUFACTURE OF INTEGRATED DEVICES AND PROCEDURE FOR ITS MANUFACTURING.
WO1996013060A1 (en) * 1994-10-24 1996-05-02 Daimler-Benz Aktiengesellschaft Method for directly connecting flat bodies and articles produced according to said method from said flat bodies
US5841197A (en) 1994-11-18 1998-11-24 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US5534465A (en) 1995-01-10 1996-07-09 At&T Corp. Method for making multichip circuits using active semiconductor substrates
JPH08236695A (en) * 1995-02-24 1996-09-13 Kyocera Corp Three-dimensional integrated circuit device and fabrication therof
JPH08298260A (en) * 1995-02-28 1996-11-12 Hitachi Ltd Dielectric body, manufacture thereof, and semiconductor device
US5673478A (en) 1995-04-28 1997-10-07 Texas Instruments Incorporated Method of forming an electronic device having I/O reroute
JP2679681B2 (en) 1995-04-28 1997-11-19 日本電気株式会社 Semiconductor device, package for semiconductor device, and manufacturing method thereof
DE19516487C1 (en) * 1995-05-05 1996-07-25 Fraunhofer Ges Forschung Vertical integration process for microelectronic system
EP0742598B1 (en) 1995-05-08 2000-08-02 Matsushita Electric Industrial Co., Ltd. Method of manufacturing a composite substrate and a piezoelectric device using the substrate
JP3328102B2 (en) 1995-05-08 2002-09-24 松下電器産業株式会社 Surface acoustic wave device and method of manufacturing the same
US5915193A (en) 1995-05-18 1999-06-22 Tong; Qin-Yi Method for the cleaning and direct bonding of solids
JPH097908A (en) * 1995-06-15 1997-01-10 Hitachi Ltd Method of manufacturing semiconductor integrated circuit device
US5661901A (en) 1995-07-10 1997-09-02 Micron Technology, Inc. Method for mounting and electrically interconnecting semiconductor dice
US5759753A (en) 1995-07-19 1998-06-02 Matsushita Electric Industrial Co., Ltd. Piezoelectric device and method of manufacturing the same
US5691248A (en) 1995-07-26 1997-11-25 International Business Machines Corporation Methods for precise definition of integrated circuit chip edges
TW374211B (en) 1995-08-03 1999-11-11 Ibm Machine structures fabricated of multiple microstructure layers
US5652436A (en) 1995-08-14 1997-07-29 Kobe Steel Usa Inc. Smooth diamond based mesa structures
US5653019A (en) * 1995-08-31 1997-08-05 Regents Of The University Of California Repairable chip bonding/interconnect process
JPH0982588A (en) 1995-09-12 1997-03-28 Denso Corp Direct bonding method for nitride and direct bonded object
DE19543540C1 (en) 1995-11-22 1996-11-21 Siemens Ag Vertically integrated semiconductor component
US5567657A (en) 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
JP3250721B2 (en) 1995-12-12 2002-01-28 キヤノン株式会社 Method for manufacturing SOI substrate
DE69718693T2 (en) 1996-03-08 2003-11-27 Matsushita Electric Ind Co Ltd Electronic component and manufacturing process
JPH09252100A (en) 1996-03-18 1997-09-22 Shin Etsu Handotai Co Ltd Manufacture of bonded wafer and the wafer manufactured by the method
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JPH09330925A (en) * 1996-06-13 1997-12-22 Sony Corp Formation of low dielectric-constant silicon oxide insulating film and semiconductor device using it
US5760478A (en) 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits
US5783477A (en) 1996-09-20 1998-07-21 Hewlett-Packard Company Method for bonding compounds semiconductor wafers to create an ohmic interface
JPH10223636A (en) * 1997-02-12 1998-08-21 Nec Yamagata Ltd Manufacture of semiconductor integrated circuit device
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US5936280A (en) * 1997-04-21 1999-08-10 Advanced Micro Devices, Inc. Multilayer quadruple gate field effect transistor structure for use in integrated circuit devices
JPH10294995A (en) 1997-04-21 1998-11-04 Matsushita Electric Ind Co Ltd Dripproof ultrasonic wave transmitter
US6270202B1 (en) 1997-04-24 2001-08-07 Matsushita Electric Industrial Co., Ltd. Liquid jetting apparatus having a piezoelectric drive element directly bonded to a casing
US5877070A (en) 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
EP1018153A1 (en) 1997-08-29 2000-07-12 Sharon N. Farrens In situ plasma wafer bonding method
US5990472A (en) * 1997-09-29 1999-11-23 Mcnc Microelectronic radiation detectors for detecting and emitting radiation signals
US5966622A (en) * 1997-10-08 1999-10-12 Lucent Technologies Inc. Process for bonding crystalline substrates with different crystal lattices
US6274892B1 (en) * 1998-03-09 2001-08-14 Intersil Americas Inc. Devices formable by low temperature direct bonding
US5877516A (en) 1998-03-20 1999-03-02 The United States Of America As Represented By The Secretary Of The Army Bonding of silicon carbide directly to a semiconductor substrate by using silicon to silicon bonding
DE19813239C1 (en) 1998-03-26 1999-12-23 Fraunhofer Ges Forschung Wiring method for manufacturing a vertical integrated circuit structure and vertical integrated circuit structure
US6236141B1 (en) 1998-12-14 2001-05-22 Matsushita Electric Industrial Co., Ltd. Surface acoustic wave element
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
US6255899B1 (en) * 1999-09-01 2001-07-03 International Business Machines Corporation Method and apparatus for increasing interchip communications rates
US6984571B1 (en) * 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
GR1003602B (en) * 2000-02-29 2001-06-19 Αλεξανδρος Γεωργακιλας Procedure for the wafer scale intergration of gallium arsenide based optoelectronic devices with silicon based integrated circuits
US6563133B1 (en) 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US20020096760A1 (en) * 2001-01-24 2002-07-25 Gregory Simelgor Side access layer for semiconductor chip or stack thereof

Also Published As

Publication number Publication date
JP2012199556A (en) 2012-10-18
JP2003528466A (en) 2003-09-24
KR20020097203A (en) 2002-12-31
US20020164839A1 (en) 2002-11-07
US20030119279A1 (en) 2003-06-26
US20020064906A1 (en) 2002-05-30
JP2016178310A (en) 2016-10-06
KR100916376B1 (en) 2009-09-07
EP1277232A4 (en) 2003-07-23
JP6306076B2 (en) 2018-04-04
TW480628B (en) 2002-03-21
US7037755B2 (en) 2006-05-02
WO2001071797A1 (en) 2001-09-27
JP2015084421A (en) 2015-04-30
EP1277232A1 (en) 2003-01-22
US6500694B1 (en) 2002-12-31
US6864585B2 (en) 2005-03-08
US6627531B2 (en) 2003-09-30
CA2404270C (en) 2011-02-22
AU2001247536A1 (en) 2001-10-03

Similar Documents

Publication Publication Date Title
CA2404270A1 (en) Three dimensional device integration method and integrated device
US4670770A (en) Integrated circuit chip-and-substrate assembly
US6819001B2 (en) Interposer, interposer package and device assembly employing the same
US6271059B1 (en) Chip interconnection structure using stub terminals
US6962867B2 (en) Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof
US5495397A (en) Three dimensional package and architecture for high performance computer
KR100294747B1 (en) Method for forming vertically connected semiconductor parts
CN1314117C (en) System on a package fabricated on a semiconductor or dielectric wafer
EP0614220B1 (en) Multichip module and method of fabrication therefor
US5093708A (en) Multilayer integrated circuit module
EP0535479A1 (en) Multichip integrated circuit packages and systems
US5418687A (en) Wafer scale multi-chip module
CN1268245A (en) A system and method for packaging integrated circuits
JP2002515182A (en) System and method for packaging an integrated circuit
US7589414B2 (en) I/O Architecture for integrated circuit package
US8959759B2 (en) Method for assembling computer modules small in thickness
US5561593A (en) Z-interface-board
EP0154431B1 (en) Integrated circuit chip assembly
EP1902467B1 (en) Mmic having back-side multi-layer signal routing
US7193297B2 (en) Semiconductor device, method for manufacturing the same, circuit substrate and electronic device
CA1228179A (en) Packaging microminiature devices
JPH1167971A (en) Improved board-based integrated circuit package

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed

Effective date: 20150323