CA2430609A1 - System and method for providing a compatible signal to a medical device - Google Patents

System and method for providing a compatible signal to a medical device Download PDF

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Publication number
CA2430609A1
CA2430609A1 CA002430609A CA2430609A CA2430609A1 CA 2430609 A1 CA2430609 A1 CA 2430609A1 CA 002430609 A CA002430609 A CA 002430609A CA 2430609 A CA2430609 A CA 2430609A CA 2430609 A1 CA2430609 A1 CA 2430609A1
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Prior art keywords
signal
characteristic
output
input
signals
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CA002430609A
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French (fr)
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CA2430609C (en
Inventor
Robert D. Schell
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Bayer Healthcare LLC
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Bayer Healthcare LLC
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • G06F13/4072Drivers or receivers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/4045Coupling between buses using bus bridges where the bus bridge performs an extender function

Abstract

An interface system delivers an output signal having a first signal characteristic in re-sponse to first and second input signals having the first signal characteristic and a second, dif-ferent signal characteristic. The interface system includes a signal input for receiving a first signal having a first signal characteristic and a second signal having a second signal charac-teristic which is different from the first signal characteristic, a detector circuit for detecting whether the signal at the input is the first signal or the second signal, and a translator circuit for translating either of the first signal or the second signal into the output signal.

Description

INTERFACE SYSTEM
FIELD OF °TIIE INVENTION
This invention is directed generally to an improvement in a monitoring system, and more particularly, to a novel interface device for interconnecting two or more differ-ent monitoring devices with a processor, such as a personal computer (PC), laptop, hand-held system or the like.

While the invention may fmd other uses, the ensuing description refers specifi-cally to its use with blood glucose monitoring systems.
Those who have irregular blood glucose concentration levels are medically re-quired to regularly self monitor their blood glucose concentration level. An irregular blood glucose level can be brought on by a variety of reasons including illness such as diabetes. The purpose of monitoring the blood glucose concentration level is to deter-mine the blood glucose concentration level and then to take corrective action, if needed, based upon whether the level is too high or too low, to bring the level back within a nor-mal range. The failure to take corrective action can have serious implications. When blood glucose levels drop too low - a condition knov~ as hyi~oglycernia - a person can be-t 0 come nervous, shaky and confused. That person's judgment may become impaired and that person may eventually pass out. A person can. also become very ilI if their blood glucose level becomes too high - a condition known as hyperglycemia.
One method of monitoring a person's blood glucose level is with a portable, hand-held blood glucose testing device. The portable nature of these devices enables the 2 5 users to conveniently test their blood glucose levels wherever the user may be. The glu rose testing device includes a biosensor to harvest 'the blood for analysis.
One type of biosensor is the electrochemical biosensor. The electrochemical biosensor includes a reagent designed to react with glucose in the blood t~~ create an oxidation current at elec-trodes disposed within the electrochemical biosensor which is directly proportional to the 30 user's blood glucose concentration. Such a biosensor is described in ~(J.S.
Patent Nos.
5,120,420, 5,660,791, 5,759,364 and 5,798,031. Another type of sensor is an optical bio-sensor, which incorporates a reagent designed to produce a calorimetric reaction indica-tive of a user's blood glucose concentration level. T'he calorimetric reaction is then read by a spectrometer incorporated into the testing device. Surh an optical biosensor is de-scribed in U.S. Patent No. 5,194,393.
In order to check a person's blood glucose level, a drop of blood is obtained from the person's fingertip using a lancing device, and the blood is harvested using the biosen-sor. The biosensor, which is inserted into a testing unit or "aneter" is brought into contact with the blood drop. The biosensor draws the blood, via capillary action, inside the bio-sensor and the ensuing electrochemical reaction is measured by the test unit which then determines the concentration of glucose in the blood. Once the results of the test are dis-played on a display of the test unit, the biosensor is discar~.ed. Each new test requires a new biosensor.
The invention concerns an adapter which permits ~~ifferent types of monitoring devices to exchange signals with a processor, such as a personal computer (PC) or the like. This involves electronically differentiating between and automatically adapting to an open-collector signaling convention or an RS-232 (EIA-232) compatible signaling convention.
One existing blood glucose meter has an R.5-232 (EIA-232) compatible output port with a custom connector. A redesign of this met:er's electronics has been undertaken to reduce cost. However, the connector is molded into the case and a mold change is be-t 0 yond the proj ect scope. T herefore, the redesigned meter mast use the same connector as the earlier meter. Component and cost savings would, however, accrue if the RS-(EIA-232) compatible interface were replaced by an open-collector (OC) interface; how-ever, the existing I/O cable, used for coupling the meter to a PC, would not be compati-ble with this change. To simplify meter-to-computer interfacing for professionals that 2 5 will be seeing both meter types (i.e., OC and RS-232 (EIA-232)), it would be advanta-genus to develop a single cable that would automatically work with either meter. The invention provides an electronic circuit, to be implemented in a modified cable, for ac-complishing the above. If a stereo plug is wired in parallel with the plug, compatibility can be extended to other existing "open collector" output meters.
3 0 Existing cables are not compatible with both signaling conventions. The one prior interface device, "Basic CradleTM" can handle both signaling conventions, but not automatically through a shared connector. This is true in part because of the incompati-ble plug/connector design of some other ~C type meters.
The proposed invention will handle both signaling conventions automatically through a shared plug. It identifies the signal convention by monitoring for a negative marking voltage that is unique to the RS-232 (EIA-232) compatible interface of the ex fisting meter. It uses the detected interface type to automatically correct signal polarity and adjust the signal detection level for the serial data stream. The level-shifted and po larity-corrected data stream is then fed to another level translator to produce an RS-232 (EIA-232) compatible signal for the host computer. Like at least one existing cable, the interface is powered via signal pins of the host computer interface.
OBJECTS OF THE INVENTION
Accordingly, it is a general object of the invention to provide an adapter which permits different types of~ monitoring devices to exchange signals with a processor, such as a personal computer (f C) or the like.
SUMMAIZ~' OF THE INVENTION
Briefly, in accordance with the foregoing, an interface system for delivering an output signal having a said signal characteristic in response to first and second input sig-2 0 nals having said first signal characteristic and a second different signal characteristic, comprises a signal input f:or receiving a first signal having a: first signal characteristic and a second signal having a second signal characteristic which is different from said first signal characteristic, a detector circuit for detecting whether the signal at said input is said first signal or said second signal, and a translator circuit for translating either of said 2 5 first signal or said second signal into said output signal.
In accordance with another aspect of the invention, an interface method for deliv-ering an output signal having a given signal characteristic in response to first and second input signals having said first signal characteristic and a second, different signal charac-teristic, comprises receiving a first signal having a first signal characteristic and a second 3 0 signal having a second signal characteristic which is different from said first signal char-acteristic, detecting whether the signal at said input is said first signal or said second sig-nal, and translating either of said first signal or said second signal into said output signal.
In accordance with another aspect of the invention, an interface system for deliv-ering an output signal having a given signal characteristic in response to first and second input signals having said first signal characteristic arid a second, different signal charac-teristic, comprises means for receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from said first signal characteristic, means for detecting whether the signal at said input is said first signal or said second signal, and means for translating either of said first signal or said second signal into said output signal.
BRIEF DESCRIPTION ~F TH(E DRAWINGS
In the drawings:
FIG. 1 is a block diagram of a prior art cable device;
FIG. 2 is a somewhat more detailed schematic of the device of FIG. l;
FIG. 3 is a simplified schematic of an interface in acfrordance with the invention;
FIG. 4 is a second schematic, similar to FIG. 3, showing a meter interface of the invention; and FIG. 5 is a detailed schematic of the interface of FIGS. 3 and 4.
DETAILED DESCIZIPTI~N OF THE ILLT.1STRATED El9iIB~DIII~IENT
2 0 The present "Dex'TM" meter (a blood glucose monitoring device) has an I/O
port with a custom connector and uses RS-232 (EIA-232)-compatible signals. To save costs in a new meter design, called "Dex CURETM", it is necessary to use the same connector, but would be desirable to use an open collector (0C) interface built into a previously de-signed data acquisition ASIC, used in the prior "Elitc~TM" meter. The "OC"
meter output 2 5 is an open collector transistor with series resistor. The transistor's emitter is referenced to signal ground. The polarities of the two meter outputs (0C and RS-232 (EIA-232)) are also reversed. Accordingly, the present I/O cable is unsuitable for use with this new meter interface. It would be useful to have a common I/O cable or "interface"
for use with both the DexTM and Dex CURETM meters that would automatically adapt to the in 3 0 terface type (0C or RS-2 32 (EIA-232)) of the meter to which it is connected.
The (prior art) Basic CradleTM electronics had the ability to interface with either the RS-232 (EIA-232)-compatible interface of a DexTM meter or the open-collector logic level interface of an EliteTM meter. Different connectors 10, I2 were required for the two meters. After appropriate signal level translation and inversion of the DexTM
meter's output (at connector 10), the signals from the two connections were wire-ANDed 14.
The composite signal was then used to drive a signal level translator 16 feeding the host 5 computer's input 20. The Basic CradleTM circuit schematic is shown in FIGS.
Y and 2.
The interface 30 of the invention (see FIGS. 3-5) buffers the meter output and performs the necessary signal level translation to drive exclusive OR logic that the in-vention uses to feed a level translator used to drive: a host: computer's EIA-232D inter-face. The buffer input also has a pull-up to support an open-collector (OC) output meter style interface. Because the OC meter interface contains series resistance of up to 10 KS2, the buffer input voltage swing is never fully to ground arid is influenced by the strength of the pull-up. The pull-up should be strong enough to overcome anticipated leakage currents, but should be weak enough to allow adequate signal swing. In the block diagrams (FIGS. 3 and 4), a comparator 32 refi~renced to a voltage negatively offset from the pull-up voltage is used as a voltage level l:ranslator to detect OC
signal transi-tions and perform a voltage level translation. In practice, the comparator and reference functions might be implemented with a PNP transistor 70 (see FIG. 5).
The existing RS-232 (EIA-232) meter output is driven high in the spacing state.
Under low battery conditions, the magnitude of the; spacing output may be only 3 V to 2 0 4V. The transition level for the buffer should be less than the minimum spacing voltage in order to detect the transition. As illustrated in the block diagrams (FIGS.
3 and 4), this might be accomplished by regulating the pull-up voltage just below the 3V to 4V range of the minimum spacing voltage. An alternative, not diagrammed, is to use the output of the comparator 48 to modify the input threshold when an RS-232 (EIA-232) type or 2 5 ''DexTM" meter is detected. The interface buffer should withstand RS-232 (EIA-232) signal levels (~15 V maximum) without damage. The computer interface software should be tolerant of any break characters or chatter that rnay occur when connecting or disconnecting a "DexTM" meter.
Like the "Basic CradleTM," power for the interface of the invention is derived 3 0 form the host computer's DTR and TxD signals. Maximum loading of these pins should be consistent with the drive capabilities of an EIA.~-232 interface. Ideally, current re quired to operate the interface should be less than 1 nnA.
Although not shown, ESD (electrostatic discharge) protection is recommended for all exposed interface signals.
If an EliteTM meter compatible stereo plug 1 ~; (not shown in FIG. 4) is connected in parallel to the DexTM plug 10 (see also FIG. 6), the interface cable 80 can also be used for Bayer Corporation EliteTM and CatalystTM meters.
For the proposed cable interface 80 (see FIG,. 6), a single DexTM compatible con nector 10 must be shared for both (0C and RS-23:? (EIA-232)) signaling conventions.
As in the Basic CradleTM design, the host computer's TxD output 40 (FIGS. 3-5) can di rectly drive the shared RxD/DATA_IN meter input 42. The shared TxD/DATA-OUT
meter output connection requires unique handling for each interface type.
A distinguishing signal characteristic that the; proposed interface can use to iden-tify the type of meter interface connected is the marking voltage level. In the marking state, the DexTM style interface voltage goes negative, typically by SV to 15V. The open-collector interface is never driven to a negative voll:age. If the meter's signal output is appropriately rectified and used to charge a small capacitor 44, the capacitor voltage should go negative when the DexTM meter (RS-232 (EIA-'?32) output) is connected. A
large value bleed resistor 46 (see FIG. 5) shunting th.e capacitor 44 will discharge the ca-pacitor 44 if the DexTM meter is disconnected. The capacitor should be sized so as to not excessively load and distort the meter output. The RC time constant should be optimized 2 0 so that the capacitor voltage stays below a negative threshold during the normal spacing bits of DexTM data transmissions. The maximum discharge time should be limited so that the interface can recognize the switch from a DexTM to EliteTM style meter within a reasonable time period (several seconds). The capacitor 44 is monitored by a comparator 48 referenced to an appropriate threshold voltage (negative relative to that of the input 2 5 driven by capacitor 44 when the meter's output is maintained at a voltage greater than or equal to signal ground, as would be characteristic c~f the OC meter output).
The com-parator output will reflect the interface type. It can be used to control exclusive-OR logic 50 to appropriately invert the polarity of the meter output.
In operation, the rectified meter output signal. is used to negatively charge the ca 3 0 pacitor 44 whenever an RS-232 (EIA-232) compatible signal is present. The resistor 46 paralleling the capacitor is used to discharge it whenever the RS-232 (EIA-232) compati ble signal is removed. The comparator 48 is used to~ compare the capacitor voltage with a negative threshold voltage. The RC time constant is optimized to minimize distortion of the data signal, to maintain the capacitor voltage more; negative than the threshold voltage during spacing bits of an RS-232 (EIA-232.) data stream, and to allow the ca pacitor to discharge above the threshold voltage if an. RS-232 (EIA-232) marking voltage is not present for more than a few seconds.
The meter output is also fed to a voltage level translator 32 (70) to produce a common voltage swing for either type of meter output. A pull-up is used at the input to this level translator to handle the open-collector output of the EliteTM style interface. In FIG. 5, a voltage regulator 60 assures that the transition level for the level translator is within the signal swing for both the open-collector with pull-up and the RS-232 (EIA-232) signal swings. Alternatively, the output of the interface type detection comparator 48 can be used to adaptively adjust the transition level to match the presently connected interface type. The series resistance of the EIiteTM style interface requires a transition voltage that is set close to, but below, the pull-up voltage of the interface.
In a non-adaptive interface, this voltage must be less than the maximum 3V to 4V
positive swing of a DexTM meter under low battery conditions or RS-232 (EIA-232) transitions will not be recognized. In an adaptive system, the threshold voltage for an RS-232 (EIA-232) signal can be lowered closer to signal ground. The outputs of the level translator 32 and of the interface type detection comparator 48 are fed to the exclusive-CSR
logic 50. This 2 0 logic corrects for the signal polarity inversion inherent in the two interface types. The polarity-corrected signal then drives a level translator 52 that produces an RS-232 (EIA-232) compatible signal for the host computer.
Regarding the circuitry feeding comparator 48 in FIG. 5, in FIGS. 3 and 4, it was assumed that the comparator inputs could swing both positive and negative relative to 2 5 ground. This would have required a coparator needing both positive and negative sup plies. The implementation of FIG. 5 uses a low voltage comparator that can operate off of only the 3 V regulator used to power the level translates. For a single supply corn-parator to work, both inputs must be biased positive relative to ground.
Rather than a negative reference voltage, the reference input ("+") of com.parator 48 is supplied a volt-30 age slightly above ground by a resistive divider. This divider is supplied by a 3V regu-lator 60. A second resistive divider is also supplied by the 3 V regulator and creates a positive bias from the capacitor 44 voltage for the other comparator 48 input (-). This divider also provides the equivalent function of the bleed resistor 46 of FIGS. 3 and 4.
Instead of bleeding capacitor 44 to ground, the bleed is to -+-3V. When the negative Dex marking voltage is present, capacitor 44 is driven negative through a MMBD924LT1 di-ode 54. As the lower leg of the divider goes negative:, the comparator 4~
input driven by its center tap goes more negative than the reference input and the comparator state changes. A BAS40LT1 diode 56 clamps the comparator input near ground when the ca-pacitor voltage goes negative so that the comparator is not damaged by negative voltage swings (marking voltage can go as low as -15V, which the comparator would not survive without the diode). This diode will not bleed the capacitor of positive voltages. Other than the positive biasing tricks to allow a single supply cor~zparator to be used, the func-tionality is completely consistent with the other FIGS. 3 and 4.
The invention recognizes that the negative marking voltage produced by the RS-232 (EIA-232) compatible interface of the existing DexTM meter is a distinguishing sig-nal characteristic that can be used reliably to distinguish between interface types. It also recognizes that a rectifier and capacitor combination provide a simple method for detec-tion that rejects the spacing bits of an RS-232 (EIA-232) data stream and that this "fil-tered" signal can be used to control polarity correction and threshold setting for the input buffer.
While particular embodiments and applications oil the present invention have 2 0 been illustrated and described, it is to be understood that the invention is not limited to the precise construction and compositions discloseei herein and that various modifica tions, changes, and variations may be apparent from the foregoing descriptions without departing from the spirit and scope of the invention ass defined in the appended claims.

Claims (21)

1. An interface system for delivering an output signal having a said signal characteristic in response to first and second input signals having said first signal char-acteristic and a second signal characteristic different from said first signal characteristic, said interface system comprising:
a signal input for receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from said first sig-nal characteristic;
a detector circuit for detecting whether the signal at said input is said first signal or said second signal; and a translator circuit for translating either of said first signal or said second signal into said output signal.
2. The system of claim 1 wherein said first and second signals comprise out-put signals of a metering device and wherein said output signals comprises a signal com-patible with an input of a digital signal processor.
3. The system of claim 1 wherein said detector circuit is capable of recog-nizing a marking voltage characteristic of each of said first signal and said second signal.
4. The system of claim 3 wherein said detector circuit comprises a rectifier-capacitor circuit or a resistor-capacitor circuit.
5. The system of claim 1 wherein said translator includes a polarity setting circuit and a level setting circuit.
6. The system of claim 1 wherein said detector circuit includes a signal char-acteristic type detector circuit and a voltage level translator.
7. The system of claim 1 wherein said first signal is an RS-232 (EIA-232) output signal and said second signal is an open-collector output signal.
8. An interface method for delivering an output signal having a given signal characteristic in response to first and second input signals having said first signal char-acteristic and a second, signal characteristic different from said first signal characteristic, said method comprising:
receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from said first signal characteris-tic;
detecting whether the signal at said input is said first signal or said second signal;
and translating either of said first signal or said second signal into said output signal.
9. The method of claim 8 wherein said first and second signals comprise output signals of a metering device and wherein said output signals comprises a signal compatible with an input of a digital signal processor..
10. The method of claim 8 wherein said detecting includes recognizing a marking voltage characteristic of each of said first signal and said second signal.
11. The method of claim 10 wherein said detecting uses a rectifier-capacitor circuit or a resistor-capacitor circuit.
12. The method of claim 8 wherein said translating includes polarity setting and level setting.
13. The method of claim 8 wherein said detecting includes detecting said sig-nal characteristics and translating a voltage level of at least one of said first and second signals.
14. The method of claim 8 wherein said first signal is an RS-232 (EIA-232) output signal and said second signal is an open-collector output signal.
15. An interface system for delivering an output signal having a given signal characteristic in response to first and second input signals having said first signal char-acteristic and a second signal characteristic different from said first signal characteristic, said system comprising:
means for receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from said first signal char-acteristic;
means for detecting whether the signal at said input is said first signal or said sec-and signal; and means for translating either of said first signal or said second signal into said out-put signal.
16. The interface system of claim 8 wherein said first and second signals comprise output signals of a metering device and wherein said output signals comprise a signal compatible with an input of a digital signal processor.
17. The interface system of claim 8 wherein said means for detecting includes means for recognizing a marking voltage characteristic of each of said first signal and said second signal.
18. The interface system of claim 10 wherein said means for detecting uses a rectifier-capacitor circuit or a resistor-capacitor circuit.
19. The interface system of claim 8 wherein said means for translating in-cludes means for polarity setting and means for level setting.
20. The interface system of claim 8 wherein said means for detecting includes means for detecting said signal characteristics and means for translating a voltage level of at least one of said first and second signals.
21. The interface system of claim 8 wherein said first signal is an RS-232 (EIA-232) output signal and said second signal is an open-collector output signal.
CA2430609A 2002-06-04 2003-06-02 System and method for providing a compatible signal to a medical device Expired - Fee Related CA2430609C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38528502P 2002-06-04 2002-06-04
US60/385,295 2002-06-04

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