CA2437035A1 - Global interrupt and barrier networks - Google Patents
Global interrupt and barrier networks Download PDFInfo
- Publication number
- CA2437035A1 CA2437035A1 CA002437035A CA2437035A CA2437035A1 CA 2437035 A1 CA2437035 A1 CA 2437035A1 CA 002437035 A CA002437035 A CA 002437035A CA 2437035 A CA2437035 A CA 2437035A CA 2437035 A1 CA2437035 A1 CA 2437035A1
- Authority
- CA
- Canada
- Prior art keywords
- barrier
- global
- interrupt
- processing
- processing nodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000004888 barrier function Effects 0.000 title abstract 6
- 238000000034 method Methods 0.000 abstract 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/20—Modifications to facilitate cooling, ventilating, or heating
- H05K7/20709—Modifications to facilitate cooling, ventilating, or heating for server racks or cabinets; for data centers, e.g. 19-inch computer racks
- H05K7/20836—Thermal management, e.g. server temperature control
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04D—NON-POSITIVE-DISPLACEMENT PUMPS
- F04D25/00—Pumping installations or systems
- F04D25/16—Combinations of two or more pumps ; Producing two or more separate gas flows
- F04D25/166—Combinations of two or more pumps ; Producing two or more separate gas flows using fans
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04D—NON-POSITIVE-DISPLACEMENT PUMPS
- F04D27/00—Control, e.g. regulation, of pumps, pumping installations or pumping systems specially adapted for elastic fluids
- F04D27/004—Control, e.g. regulation, of pumps, pumping installations or pumping systems specially adapted for elastic fluids by varying driving speed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
- G09G5/008—Clock recovery
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F24—HEATING; RANGES; VENTILATING
- F24F—AIR-CONDITIONING; AIR-HUMIDIFICATION; VENTILATION; USE OF AIR CURRENTS FOR SCREENING
- F24F11/00—Control or safety arrangements
- F24F11/70—Control systems characterised by their outputs; Constructional details thereof
- F24F11/72—Control systems characterised by their outputs; Constructional details thereof for controlling the supply of treated air, e.g. its pressure
- F24F11/74—Control systems characterised by their outputs; Constructional details thereof for controlling the supply of treated air, e.g. its pressure for controlling air flow rate or air velocity
- F24F11/77—Control systems characterised by their outputs; Constructional details thereof for controlling the supply of treated air, e.g. its pressure for controlling air flow rate or air velocity by controlling the speed of ventilators
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B30/00—Energy efficient heating, ventilation or air conditioning [HVAC]
- Y02B30/70—Efficient control or regulation technologies, e.g. for control of refrigerant flow, motor or heating
Abstract
A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations perfomed by processing elements at selected processing nodes (12) of computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes (12) for communicating the global interrupt and barrier signals to the elements via low latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes (12) at times selected for otpimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US27112401P | 2001-02-24 | 2001-02-24 | |
US60/271,124 | 2001-02-24 | ||
PCT/US2002/005567 WO2002069095A2 (en) | 2001-02-24 | 2002-02-25 | Global interrupt and barrier networks |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2437035A1 true CA2437035A1 (en) | 2002-09-06 |
CA2437035C CA2437035C (en) | 2009-01-06 |
Family
ID=68499829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002437035A Expired - Fee Related CA2437035C (en) | 2001-02-24 | 2002-02-25 | Global interrupt and barrier networks |
Country Status (9)
Country | Link |
---|---|
US (1) | US7444385B2 (en) |
EP (1) | EP1381958A4 (en) |
JP (1) | JP4114480B2 (en) |
KR (1) | KR100586768B1 (en) |
CN (1) | CN1229739C (en) |
AU (1) | AU2002248494A1 (en) |
CA (1) | CA2437035C (en) |
IL (1) | IL157508A0 (en) |
WO (1) | WO2002069095A2 (en) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6957358B1 (en) | 2002-01-28 | 2005-10-18 | Cisco Systems, Inc. | Scaling dynamic clock distribution for large service provider networks |
US8626957B2 (en) | 2003-08-22 | 2014-01-07 | International Business Machines Corporation | Collective network for computer structures |
US20040153567A1 (en) * | 2003-01-31 | 2004-08-05 | Lichtenstein Walter D. | Scheduling data transfers using virtual nodes |
US20040151187A1 (en) * | 2003-01-31 | 2004-08-05 | Lichtenstein Walter D. | Scheduling data transfers for multiple use requests |
US7178059B2 (en) * | 2003-05-07 | 2007-02-13 | Egenera, Inc. | Disaster recovery for processing resources using configurable deployment platform |
US7186981B2 (en) * | 2003-07-29 | 2007-03-06 | Thermal Wave Imaging, Inc. | Method and apparatus for thermographic imaging using flash pulse truncation |
US20050188089A1 (en) * | 2004-02-24 | 2005-08-25 | Lichtenstein Walter D. | Managing reservations for resources |
US8001280B2 (en) * | 2004-07-19 | 2011-08-16 | International Business Machines Corporation | Collective network for computer structures |
CN100594463C (en) * | 2005-06-01 | 2010-03-17 | 特克拉科技股份公司 | A method and an apparatus for providing timing signals to a number of circuits, an integrated circuit and a node |
US7853639B2 (en) * | 2006-09-12 | 2010-12-14 | International Business Machines Corporation | Performing process migration with allreduce operations |
US7827385B2 (en) * | 2007-08-02 | 2010-11-02 | International Business Machines Corporation | Effecting a broadcast with an allreduce operation on a parallel computer |
US8370844B2 (en) * | 2007-09-12 | 2013-02-05 | International Business Machines Corporation | Mechanism for process migration on a massively parallel computer |
JP2009104300A (en) * | 2007-10-22 | 2009-05-14 | Denso Corp | Data processing apparatus and program |
MX2011004258A (en) | 2008-10-22 | 2011-06-01 | Merck Sharp & Dohme | Novel cyclic benzimidazole derivatives useful anti-diabetic agents. |
JP5557845B2 (en) | 2008-10-31 | 2014-07-23 | メルク・シャープ・アンド・ドーム・コーポレーション | Novel cyclic benzimidazole derivatives useful as antidiabetic agents |
US8321326B2 (en) | 2009-09-15 | 2012-11-27 | Auerbach Group Llc | Method and system for enhancing the efficiency of a digitally communicated data exchange |
US8571834B2 (en) * | 2010-01-08 | 2013-10-29 | International Business Machines Corporation | Opcode counting for performance measurement |
KR101262846B1 (en) * | 2009-12-15 | 2013-05-10 | 한국전자통신연구원 | Apparatus and method for measuring the performance of embedded devices |
EP2538784B1 (en) | 2010-02-25 | 2015-09-09 | Merck Sharp & Dohme Corp. | Benzimidazole derivatives useful anti-diabetic agents |
KR20150075120A (en) | 2011-02-25 | 2015-07-02 | 머크 샤프 앤드 돔 코포레이션 | Novel cyclic azabenzimidazole derivatives useful as anti-diabetic agents |
US8966457B2 (en) | 2011-11-15 | 2015-02-24 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
JP5974703B2 (en) | 2012-07-20 | 2016-08-23 | 富士通株式会社 | Information processing apparatus and barrier synchronization method |
RU2015106909A (en) | 2012-08-02 | 2016-09-27 | Мерк Шарп И Доум Корп. | ANTI-DIABETIC TRICYCLIC COMPOUNDS |
KR20150118158A (en) | 2013-02-22 | 2015-10-21 | 머크 샤프 앤드 돔 코포레이션 | Antidiabetic bicyclic compounds |
US9571329B2 (en) * | 2013-03-11 | 2017-02-14 | International Business Machines Corporation | Collective operation management in a parallel computer |
US9223728B2 (en) | 2013-03-12 | 2015-12-29 | International Business Machines Corporation | Servicing a globally broadcast interrupt signal in a multi-threaded computer |
EP2970119B1 (en) | 2013-03-14 | 2021-11-03 | Merck Sharp & Dohme Corp. | Novel indole derivatives useful as anti-diabetic agents |
US9405724B2 (en) * | 2013-06-28 | 2016-08-02 | Intel Corporation | Reconfigurable apparatus for hierarchical collective networks with bypass mode |
WO2015051496A1 (en) | 2013-10-08 | 2015-04-16 | Merck Sharp & Dohme Corp. | Antidiabetic tricyclic compounds |
EP3551176A4 (en) | 2016-12-06 | 2020-06-24 | Merck Sharp & Dohme Corp. | Antidiabetic heterocyclic compounds |
US10968232B2 (en) | 2016-12-20 | 2021-04-06 | Merck Sharp & Dohme Corp. | Antidiabetic spirochroman compounds |
KR101948163B1 (en) * | 2017-01-10 | 2019-02-14 | 충북대학교 산학협력단 | Method for implementing barrier based on PCI Express in interconnection network |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4860201A (en) | 1986-09-02 | 1989-08-22 | The Trustees Of Columbia University In The City Of New York | Binary tree parallel processor |
JP2708172B2 (en) | 1988-03-24 | 1998-02-04 | 株式会社東芝 | Parallel processing method |
US5365228A (en) * | 1991-03-29 | 1994-11-15 | International Business Machines Corporation | SYNC-NET- a barrier synchronization apparatus for multi-stage networks |
US6047122A (en) * | 1992-05-07 | 2000-04-04 | Tm Patents, L.P. | System for method for performing a context switch operation in a massively parallel computer system |
JPH06243113A (en) | 1993-02-19 | 1994-09-02 | Fujitsu Ltd | Calculation model mapping method for parallel computer |
US5434995A (en) * | 1993-12-10 | 1995-07-18 | Cray Research, Inc. | Barrier synchronization for distributed memory massively parallel processing systems |
JPH07234842A (en) * | 1994-02-22 | 1995-09-05 | Fujitsu Ltd | Parallel data processing system |
US5570364A (en) * | 1994-04-14 | 1996-10-29 | Lucent Technologies Inc. | Control for multimedia communication on local access table |
WO1995028686A1 (en) * | 1994-04-15 | 1995-10-26 | David Sarnoff Research Center, Inc. | Parallel processing computer containing a multiple instruction stream processing architecture |
US5671377A (en) * | 1994-07-19 | 1997-09-23 | David Sarnoff Research Center, Inc. | System for supplying streams of data to multiple users by distributing a data stream to multiple processors and enabling each user to manipulate supplied data stream |
US5682480A (en) * | 1994-08-15 | 1997-10-28 | Hitachi, Ltd. | Parallel computer system for performing barrier synchronization by transferring the synchronization packet through a path which bypasses the packet buffer in response to an interrupt |
US5721921A (en) * | 1995-05-25 | 1998-02-24 | Cray Research, Inc. | Barrier and eureka synchronization architecture for multiprocessors |
US6249881B1 (en) * | 1997-07-01 | 2001-06-19 | National Semiconductor Corporation | Method for enabling and servicing critical interrupts while running an interrupt based debug monitor |
US6615383B1 (en) * | 1998-05-29 | 2003-09-02 | Sun Microsystems, Inc. | System and method for message transmission between network nodes connected by parallel links |
-
2002
- 2002-02-25 IL IL15750802A patent/IL157508A0/en unknown
- 2002-02-25 JP JP2002568151A patent/JP4114480B2/en not_active Expired - Fee Related
- 2002-02-25 EP EP02717497A patent/EP1381958A4/en not_active Withdrawn
- 2002-02-25 CN CNB028054423A patent/CN1229739C/en not_active Expired - Fee Related
- 2002-02-25 WO PCT/US2002/005567 patent/WO2002069095A2/en active IP Right Grant
- 2002-02-25 KR KR1020037011111A patent/KR100586768B1/en not_active IP Right Cessation
- 2002-02-25 US US10/468,997 patent/US7444385B2/en not_active Expired - Fee Related
- 2002-02-25 CA CA002437035A patent/CA2437035C/en not_active Expired - Fee Related
- 2002-02-25 AU AU2002248494A patent/AU2002248494A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
EP1381958A4 (en) | 2007-05-09 |
WO2002069095A2 (en) | 2002-09-06 |
KR20040004539A (en) | 2004-01-13 |
US7444385B2 (en) | 2008-10-28 |
AU2002248494A1 (en) | 2002-09-12 |
CA2437035C (en) | 2009-01-06 |
US20040068599A1 (en) | 2004-04-08 |
CN1493036A (en) | 2004-04-28 |
JP2004529414A (en) | 2004-09-24 |
JP4114480B2 (en) | 2008-07-09 |
EP1381958A2 (en) | 2004-01-21 |
CN1229739C (en) | 2005-11-30 |
KR100586768B1 (en) | 2006-06-08 |
IL157508A0 (en) | 2004-03-28 |
WO2002069095A3 (en) | 2002-10-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed | ||
MKLA | Lapsed |
Effective date: 20110225 |