CA2446983A1 - Programmable logic device including programmable interface core and central processing unit - Google Patents

Programmable logic device including programmable interface core and central processing unit Download PDF

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Publication number
CA2446983A1
CA2446983A1 CA002446983A CA2446983A CA2446983A1 CA 2446983 A1 CA2446983 A1 CA 2446983A1 CA 002446983 A CA002446983 A CA 002446983A CA 2446983 A CA2446983 A CA 2446983A CA 2446983 A1 CA2446983 A1 CA 2446983A1
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Prior art keywords
programmable
programmable interface
devices
interface
logic device
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Granted
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CA002446983A
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French (fr)
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CA2446983C (en
Inventor
Khang Kim Dao
Glenn A. Baxter
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Xilinx Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Abstract

A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD
provides significant flexibility in providing features that can be parameterized based on the user's needs and/or associated design.
Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD. Finally, the functions of the processor local bus can be efficiently limited, thereby allowing the PLD to approach the performance level of an ASIC.

Claims (24)

1. A system comprising a programmable logic device having an embedded microprocessor, wherein the programmable logic device comprises:
a programmable interface coupled to the microprocessor, wherein the programmable interface includes a core designated by a user; and a first device for one of providing information to and receiving information from the microprocessor via the programmable interface.
2. The system of Claim 1, further including a plurality of devices, each device for one of providing information to the microprocessor via the programmable interface, receiving information from the microprocessor via the programmable interface, and communicating with another device via the programmable interface.
3. The system of Claim 2, wherein the programmable interface includes a crosspoint switch for coupling the plurality of devices.
4. The system of Claim 3, wherein the crosspoint switch includes address/control paths and data paths.
5. The system of Claim 4, wherein the address/control paths are formed from a first set of programmable resources and the data paths are formed from a second set of programmable resources.
6. The system of Claim 5, wherein the first and second sets of programmable resources are distinct.
7. The system of Claim 5, wherein the first and second set of programmable resources overlap on the programmable logic device.
8. The system of Claim 4, wherein the address/control paths are trimmable.
9. The system of Claim 4, wherein the data paths are trimmable.
10. The system of Claim 3, wherein the crosspoint switch is parameterizable.
11. The system of Claim 2, further including a peripheral bus coupled to the programmable interface.
12. The system of Claim 11, wherein a bridge module couples the peripheral bus to the programmable interface.
13. The system of Claim 12, wherein a first group of devices from the plurality of devices are coupled to the peripheral bus and coupled to the programmable interface via the bridge module.
14. The system of Claim 13, wherein a second group of devices from the plurality of devices are not connected to the programmable interface via the bridge module.
15. The system of Claim 13, wherein the first group of devices includes a plurality of cores designated by the user.
16. The system of Claim 15, wherein at least one core provides a master/slave functionality.
17. The system of Claim 15, wherein at least one core provides a master functionality.
18. The system of Claim 15, wherein at least one core provides a slave functionality.
19. The system of Claim 14, further including at least one memory device, wherein the at least one memory device is part of the second group of devices.
20. The system of Claim 19, wherein the at least one memory device is provided on the programmable logic device.
21. The system of Claim 14, further including an integrated circuit, wherein the integrated circuit is part of the second group of devices.
22. The system of Claim 21, wherein the integrated circuit includes a double data rate device.
23. The system of Claim 21, wherein the integrated circuit includes a memory device.
24. The system of Claim 11, further including a high speed bus interface coupled to the programmable interface and the peripheral bus, wherein the high speed bus interface provides communication to an off-chip device.
CA2446983A 2001-05-18 2002-04-17 Programmable logic device including programmable interface core and central processing unit Expired - Lifetime CA2446983C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/861,112 US7076595B1 (en) 2001-05-18 2001-05-18 Programmable logic device including programmable interface core and central processing unit
US09/861,112 2001-05-18
PCT/US2002/012234 WO2002095598A2 (en) 2001-05-18 2002-04-17 Programmable logic device including programmable interface core and central processing unit

Publications (2)

Publication Number Publication Date
CA2446983A1 true CA2446983A1 (en) 2002-11-28
CA2446983C CA2446983C (en) 2010-08-10

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CA2446983A Expired - Lifetime CA2446983C (en) 2001-05-18 2002-04-17 Programmable logic device including programmable interface core and central processing unit

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US (3) US7076595B1 (en)
EP (1) EP1402395B1 (en)
JP (1) JP3935847B2 (en)
CA (1) CA2446983C (en)
DE (1) DE60213601T2 (en)
WO (1) WO2002095598A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10365947B2 (en) 2014-07-28 2019-07-30 Hemett Packard Enterprise Development Lp Multi-core processor including a master core performing tasks involving operating system kernel-related features on behalf of slave cores

Families Citing this family (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724220B1 (en) 2000-10-26 2004-04-20 Cyress Semiconductor Corporation Programmable microcontroller architecture (mixed analog/digital)
US8176296B2 (en) 2000-10-26 2012-05-08 Cypress Semiconductor Corporation Programmable microcontroller architecture
US7076595B1 (en) * 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US6976239B1 (en) 2001-06-12 2005-12-13 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US20030033374A1 (en) * 2001-07-24 2003-02-13 Condor Engineering, Inc. Method and system for implementing a communications core on a single programmable device
US7145903B2 (en) * 2001-09-06 2006-12-05 Meshnetworks, Inc. Multi-master bus architecture for system-on-chip designs
US6857035B1 (en) 2001-09-13 2005-02-15 Altera Corporation Methods and apparatus for bus mastering and arbitration
US7420392B2 (en) * 2001-09-28 2008-09-02 Xilinx, Inc. Programmable gate array and embedded circuitry initialization and processing
US7676588B2 (en) * 2001-10-05 2010-03-09 International Business Machines Corporation Programmable network protocol handler architecture
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US6941538B2 (en) * 2002-02-22 2005-09-06 Xilinx, Inc. Method and system for integrating cores in FPGA-based system-on-chip (SoC)
US7085973B1 (en) 2002-07-09 2006-08-01 Xilinx, Inc. Testing address lines of a memory controller
US7755641B2 (en) * 2002-08-13 2010-07-13 Broadcom Corporation Method and system for decimating an indexed set of data elements
US7061485B2 (en) * 2002-10-31 2006-06-13 Hewlett-Packard Development Company, Lp. Method and system for producing a model from optical images
US6920627B2 (en) * 2002-12-13 2005-07-19 Xilinx, Inc. Reconfiguration of a programmable logic device using internal control
US7512103B1 (en) * 2003-06-19 2009-03-31 Rockwell Collins, In.C Virtual channel communications system
US7421014B2 (en) * 2003-09-11 2008-09-02 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
US7885320B1 (en) 2003-09-11 2011-02-08 Xilinx, Inc. MGT/FPGA clock management system
JP3966873B2 (en) * 2003-10-08 2007-08-29 株式会社東芝 Logic circuit device and operating voltage changing method
US20050097291A1 (en) * 2003-10-31 2005-05-05 Infineon Technologies North America Corp. Multiple data rate bus using return clock
US7340548B2 (en) * 2003-12-17 2008-03-04 Microsoft Corporation On-chip bus
US7209998B2 (en) * 2004-02-04 2007-04-24 Qualcomm Incorporated Scalable bus structure
JP2005250833A (en) * 2004-03-04 2005-09-15 Nec Electronics Corp Bus system and access control method
JP2006048530A (en) * 2004-08-06 2006-02-16 Fujitsu Ltd Bus switch circuit and bus switch system
US7225285B1 (en) * 2004-09-07 2007-05-29 Altera Corporation Assigning interrupts in multi-master systems
US7363473B2 (en) * 2004-09-10 2008-04-22 Intel Corporation System for dynamic service provisioning
US7284229B1 (en) 2004-10-01 2007-10-16 Xilinx, Inc. Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein
US7424655B1 (en) 2004-10-01 2008-09-09 Xilinx, Inc. Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
WO2006039711A1 (en) * 2004-10-01 2006-04-13 Lockheed Martin Corporation Service layer architecture for memory access system and method
US7353317B2 (en) * 2004-12-28 2008-04-01 Intel Corporation Method and apparatus for implementing heterogeneous interconnects
US7676782B2 (en) * 2004-12-29 2010-03-09 Dhabalendu Samanta Efficient method for mapping a logic design on field programmable gate arrays
JP4457025B2 (en) * 2005-02-17 2010-04-28 Ｏｋｉセミコンダクタ株式会社 Wireless integrated circuit
CN101133597A (en) * 2005-03-04 2008-02-27 皇家飞利浦电子股份有限公司 Electronic device and a method for arbitrating shared resources
US7856026B1 (en) * 2005-06-28 2010-12-21 Altera Corporation Configurable central memory buffered packet switch module for use in a PLD
US7426709B1 (en) * 2005-08-05 2008-09-16 Xilinx, Inc. Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system
WO2007029053A1 (en) * 2005-09-09 2007-03-15 Freescale Semiconductor, Inc. Interconnect and a method for designing an interconnect
US7412680B1 (en) * 2005-09-15 2008-08-12 Altera Corporation Method and apparatus for performing integrated global routing and buffer insertion
US7382154B2 (en) * 2005-10-03 2008-06-03 Honeywell International Inc. Reconfigurable network on a chip
JP2007122410A (en) * 2005-10-28 2007-05-17 Nec Electronics Corp Bus arbitration circuit and method
US7392032B2 (en) * 2005-12-30 2008-06-24 L3 Communications Corporation Modular ASIC with crosspoint switch
US7536669B1 (en) * 2006-08-30 2009-05-19 Xilinx, Inc. Generic DMA IP core interface for FPGA platform design
US7594207B2 (en) * 2006-09-13 2009-09-22 Cadence Design Systems, Inc. Computationally efficient design rule checking for circuit interconnect routing design
US8289966B1 (en) 2006-12-01 2012-10-16 Synopsys, Inc. Packet ingress/egress block and system and method for receiving, transmitting, and managing packetized data
US8706987B1 (en) 2006-12-01 2014-04-22 Synopsys, Inc. Structured block transfer module, system architecture, and method for transferring
US8127113B1 (en) 2006-12-01 2012-02-28 Synopsys, Inc. Generating hardware accelerators and processor offloads
US7734846B2 (en) * 2006-12-20 2010-06-08 L3 Communications Integrated Systems, L.P. Datapipe CPU register array
US7685332B2 (en) * 2006-12-20 2010-03-23 L3 Communications Integrated Systems, L.P. Datapipe CPU register array and methods of use
US8065356B2 (en) * 2006-12-20 2011-11-22 L3 Communications Integrated Systems, L.P. Datapipe synchronization device
US7655278B2 (en) * 2007-01-30 2010-02-02 Sabic Innovative Plastics Ip B.V. Composite-forming method, composites formed thereby, and printed circuit boards incorporating them
US8407658B2 (en) 2007-02-01 2013-03-26 International Business Machines Corporation Methods, systems, and computer program products for using direct memory access to initialize a programmable logic device
US7913022B1 (en) 2007-02-14 2011-03-22 Xilinx, Inc. Port interface modules (PIMs) in a multi-port memory controller (MPMC)
US7720636B1 (en) 2007-02-14 2010-05-18 Xilinx, Inc. Performance monitors (PMs) for measuring performance in a system and providing a record of transactions performed
US7711907B1 (en) * 2007-02-14 2010-05-04 Xilinx, Inc. Self aligning state machine
US8479124B1 (en) 2007-02-14 2013-07-02 Xilinx, Inc. Graphical user interface (GUI) including input files with information that determines representation of subsequent content displayed by the GUI
US7865695B2 (en) * 2007-04-19 2011-01-04 L3 Communications Integrated Systems, L.P. Reading and writing a memory element within a programmable processing element in a plurality of modes
US20080263322A1 (en) * 2007-04-19 2008-10-23 L3 Communications Integrated Systems, L.P. Mac architecture for pipelined accumulations
US7673274B2 (en) * 2007-04-19 2010-03-02 L3 Communications Integrated Systems, LP Datapipe interpolation device
US7394287B1 (en) * 2007-05-21 2008-07-01 Altera Corporation Programmable logic device having complex logic blocks with improved logic cell functionality
US8468287B2 (en) * 2007-08-22 2013-06-18 Nec Corporation Information processor and information processing method
US7830172B1 (en) * 2007-09-13 2010-11-09 Xilinx, Inc. Accessing user registers in an integrated circuit
US7810059B1 (en) 2007-10-11 2010-10-05 Xilinx, Inc. Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams
US7853916B1 (en) * 2007-10-11 2010-12-14 Xilinx, Inc. Methods of using one of a plurality of configuration bitstreams for an integrated circuit
US7865644B2 (en) * 2007-10-30 2011-01-04 International Business Machines Corporation Method and apparatus for attaching multiple slave devices to a single bus controller interface while supporting command pipelining
WO2009116171A1 (en) * 2008-03-21 2009-09-24 富士通株式会社 Information processing device, data transfer circuit, and method for controlling information processing device
US8006021B1 (en) * 2008-03-27 2011-08-23 Xilinx, Inc. Processor local bus bridge for an embedded processor block core in an integrated circuit
US8441298B1 (en) 2008-07-01 2013-05-14 Cypress Semiconductor Corporation Analog bus sharing using transmission gates
US7934046B2 (en) * 2008-07-02 2011-04-26 International Business Machines Corporation Access table lookup for bus bridge
DE102008037431B4 (en) 2008-10-10 2013-06-06 Lear Corporation Gmbh Method for dynamically configuring a signal conditioner
US9448964B2 (en) 2009-05-04 2016-09-20 Cypress Semiconductor Corporation Autonomous control in a programmable system
US8135884B1 (en) 2009-05-04 2012-03-13 Cypress Semiconductor Corporation Programmable interrupt routing system
US8179161B1 (en) 2009-05-05 2012-05-15 Cypress Semiconductor Corporation Programmable input/output circuit
US8487655B1 (en) 2009-05-05 2013-07-16 Cypress Semiconductor Corporation Combined analog architecture and functionality in a mixed-signal array
US9612987B2 (en) * 2009-05-09 2017-04-04 Cypress Semiconductor Corporation Dynamically reconfigurable analog routing circuits and methods for system on a chip
EP2282268B1 (en) * 2009-07-23 2012-11-21 STMicroelectronics Srl Interfacing device and method, for example for systems-on-chip
US8285912B2 (en) * 2009-08-07 2012-10-09 Arm Limited Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure
US20120210028A1 (en) * 2009-11-11 2012-08-16 Zte Corporation Service scheduling system and method, and control device
US20110179395A1 (en) * 2010-01-20 2011-07-21 Maxim Smirnov Distributed Pipeline Synthesis for High Level Electronic Design
US8656081B2 (en) * 2010-03-12 2014-02-18 The United States Of America As Represented By The Secretary Of The Navy System and method for coordinating control of an output device by multiple control consoles
US8667206B2 (en) * 2010-03-12 2014-03-04 The United States Of America As Represented By The Secretary Of The Navy Interface device for coordinating control of an output device by multiple control consoles
US8718967B2 (en) * 2010-05-28 2014-05-06 Advantest Corporation Flexible storage interface tester with variable parallelism and firmware upgradeability
JP2012128627A (en) * 2010-12-15 2012-07-05 Toshiba Corp Data transfer system
US9762246B2 (en) 2011-05-20 2017-09-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with a storage circuit having an oxide semiconductor
US8583844B2 (en) * 2011-05-31 2013-11-12 Lsi Corporation System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecture
US8793421B2 (en) 2011-10-31 2014-07-29 Apple Inc. Queue arbitration using non-stalling request indication
CN103136163B (en) * 2011-11-29 2015-06-24 中国航空工业集团公司第六三一研究所 Protocol processor chip capable of allocating and achieving FC-AE-ASM and FC-AV protocol
JP5975811B2 (en) * 2012-09-12 2016-08-23 レノボ・エンタープライズ・ソリューションズ（シンガポール）プライベート・リミテッド Integrity check of measured signal trace data
US9153292B2 (en) * 2013-03-07 2015-10-06 Xilinx, Inc. Integrated circuit devices having memory and methods of implementing memory in an integrated circuit device
US9665670B1 (en) * 2013-06-28 2017-05-30 Altera Corporation Emulation of synchronous pipeline registers in integrated circuits with asynchronous interconnection resources
US9674118B2 (en) * 2014-03-19 2017-06-06 xCelor LLC System and method for low-latency network data switching
JP6452719B2 (en) * 2014-04-03 2019-01-16 ホアウェイ・テクノロジーズ・カンパニー・リミテッド Field programmable gate array and communication method
US9558129B2 (en) 2014-06-10 2017-01-31 Xilinx, Inc. Circuits for and methods of enabling the access to data
US9846661B2 (en) * 2014-07-17 2017-12-19 Empire Technology Development Llc Utilization of solid state memory devices
US9806885B1 (en) * 2014-09-26 2017-10-31 Rockwell Collins, Inc. Dual use cryptographic system and method
US9798686B2 (en) * 2014-11-19 2017-10-24 Silicon Laboratories Inc. Slave side bus arbitration
US9880966B1 (en) * 2015-09-03 2018-01-30 Xilinx, Inc. Encapsulating metadata of a platform for application-specific tailoring and reuse of the platform in an integrated circuit
US10042692B1 (en) * 2015-09-29 2018-08-07 Xilinx, Inc. Circuit arrangement with transaction timeout detection
US9979693B2 (en) * 2016-01-28 2018-05-22 Fiber Logic Communications, Inc. IP allocation method for use in telecommunication network automatic construction
US10120831B1 (en) * 2016-12-02 2018-11-06 Xilinx, Inc. Circuit and method for handling write and read requests between a master circuit and a slave circuit in different clock domains
US10936597B2 (en) 2017-11-21 2021-03-02 Gto Llc Systems and methods for generating customized filtered-and-partitioned market-data feeds
US10852800B1 (en) * 2019-01-25 2020-12-01 Cadence Design Systems, Inc. Multi-modal power control
KR20210025403A (en) * 2019-08-27 2021-03-09 삼성전자주식회사 Apparatus and method for operating multi-fpga in wireless communication system
CN113227917A (en) * 2019-12-05 2021-08-06 Mzta科技中心有限公司 Modular PLC automatic configuration system
WO2021112708A1 (en) * 2019-12-05 2021-06-10 Общество С Ограниченной Ответственностью "Научно-Технический Центр Мзта" Controller with processor submodule
CN111766807A (en) * 2020-06-23 2020-10-13 济南浪潮高新科技投资发展有限公司 Hospital ward night shift inspection robot control system
WO2023229616A1 (en) * 2022-05-25 2023-11-30 Rakuten Symphony Uk Ltd Distributed firmware interfacing processors and intergrated circuits

Family Cites Families (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE34363E (en) 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4706216A (en) 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US5142625A (en) 1985-06-12 1992-08-25 Minolta Camera Kabushiki Kaisha One-chip microcomputer including a programmable logic array for interrupt control
US5072418A (en) 1989-05-04 1991-12-10 Texas Instruments Incorporated Series maxium/minimum function computing devices, systems and methods
US4855669A (en) 1987-10-07 1989-08-08 Xilinx, Inc. System for scan testing of logic circuit networks
US4878174A (en) 1987-11-03 1989-10-31 Lsi Logic Corporation Flexible ASIC microcomputer permitting the modular modification of dedicated functions and macroinstructions
US5111423A (en) * 1988-07-21 1992-05-05 Altera Corporation Programmable interface for computer system peripheral circuit card
JPH02235156A (en) 1989-03-08 1990-09-18 Canon Inc Information processor
US5274570A (en) 1989-05-22 1993-12-28 Mazda Motor Corporation Integrated circuit having metal substrate
US5109503A (en) * 1989-05-22 1992-04-28 Ge Fanuc Automation North America, Inc. Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
JPH03210649A (en) 1990-01-12 1991-09-13 Fujitsu Ltd Microcomputer and its bus cycle control method
US5550782A (en) 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5347181A (en) 1992-04-29 1994-09-13 Motorola, Inc. Interface control logic for embedding a microprocessor in a gate array
WO1993025968A1 (en) 1992-06-10 1993-12-23 Furtek Frederick C A modular computer based on reconfigurable logic
US5671355A (en) 1992-06-26 1997-09-23 Predacomm, Inc. Reconfigurable network interface apparatus and method
US5339262A (en) 1992-07-10 1994-08-16 Lsi Logic Corporation Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC
US5311114A (en) 1992-10-27 1994-05-10 Seeq Technology, Incorporated Apparatus and method for full-duplex ethernet communications
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
GB9303084D0 (en) 1993-02-16 1993-03-31 Inmos Ltd Programmable logic circuit
JPH0736858A (en) 1993-07-21 1995-02-07 Hitachi Ltd Signal processor
US5457410A (en) 1993-08-03 1995-10-10 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
WO1995004402A1 (en) 1993-08-03 1995-02-09 Xilinx, Inc. Microprocessor-based fpga
US5740404A (en) 1993-09-27 1998-04-14 Hitachi America Limited Digital signal processor with on-chip select decoder and wait state generator
US5500943A (en) 1993-11-02 1996-03-19 Motorola, Inc. Data processor with rename buffer and FIFO buffer for in-order instruction completion
EP0734573B1 (en) 1993-12-13 2002-04-03 Lattice Semiconductor Corporation Application specific modules in a programmable logic device
US5742179A (en) 1994-01-27 1998-04-21 Dyna Logic Corporation High speed programmable logic architecture
US5574942A (en) 1994-02-28 1996-11-12 Intel Corporation Hybrid execution unit for complex microprocessor
US5543640A (en) 1994-03-15 1996-08-06 National Semiconductor Corporation Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module
US5572717A (en) * 1994-04-06 1996-11-05 Altera Corporation Method and apparatus for assigning and analyzing timing specifications in a computer aided engineering program
US5600845A (en) 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5574930A (en) 1994-08-12 1996-11-12 University Of Hawaii Computer system and method using functional memory
US5732250A (en) 1994-09-15 1998-03-24 Intel Corporation Multi-function microprocessor wait state mechanism using external control line
US5742180A (en) 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US5892961A (en) 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US5737631A (en) 1995-04-05 1998-04-07 Xilinx Inc Reprogrammable instruction set accelerator
US5748979A (en) 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
US5752035A (en) 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
WO1996034346A1 (en) 1995-04-28 1996-10-31 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
GB9508931D0 (en) 1995-05-02 1995-06-21 Xilinx Inc Programmable switch for FPGA input/output signals
EP0780017A1 (en) 1995-07-10 1997-06-25 Xilinx, Inc. System comprising field programmable gate array and intelligent memory
US6175952B1 (en) 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US5933023A (en) 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
KR19990071991A (en) 1996-10-10 1999-09-27 파레 호세 마리아 인센서 Process for prototyping of mixed-signal applications and field programmable systems on chip for application of these processes
US6102964A (en) 1996-10-28 2000-08-15 Altera Corporation Fitting for incremental compilation of electronic designs
US5889788A (en) 1997-02-03 1999-03-30 Motorola, Inc. Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation
US6172990B1 (en) 1997-06-19 2001-01-09 Xaqti Corporation Media access control micro-RISC stream processor and method for implementing the same
US5874834A (en) 1997-03-04 1999-02-23 Xilinx, Inc. Field programmable gate array with distributed gate-array functionality
US6060903A (en) * 1997-05-06 2000-05-09 Altera Corporation Programmable logic device architecture incorporating a dedicated cross-bar switch
US5943490A (en) * 1997-05-30 1999-08-24 Quickturn Design Systems, Inc. Distributed logic analyzer for use in a hardware logic emulation system
US6011407A (en) 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US5970254A (en) 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US5995424A (en) 1997-07-16 1999-11-30 Tanisys Technology, Inc. Synchronous memory test system
US6020755A (en) 1997-09-26 2000-02-01 Lucent Technologies Inc. Hybrid programmable gate arrays
US6034542A (en) * 1997-10-14 2000-03-07 Xilinx, Inc. Bus structure for modularized chip with FPGA modules
US6279045B1 (en) 1997-12-29 2001-08-21 Kawasaki Steel Corporation Multimedia interface having a multimedia processor and a field programmable gate array
US6147890A (en) * 1997-12-30 2000-11-14 Kawasaki Steel Corporation FPGA with embedded content-addressable memory
US6096091A (en) 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6178541B1 (en) 1998-03-30 2001-01-23 Lsi Logic Corporation PLD/ASIC hybrid integrated circuit
US6163166A (en) 1998-05-27 2000-12-19 Altera Corporation Programmable logic device with selectable schmitt-triggered and threshold-triggered buffers
US6282627B1 (en) 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US6480989B2 (en) 1998-06-29 2002-11-12 Lsi Logic Corporation Integrated circuit design incorporating a power mesh
US6467009B1 (en) 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit
US6343207B1 (en) 1998-11-03 2002-01-29 Harris Corporation Field programmable radio frequency communications equipment including a configurable if circuit, and method therefor
US6154051A (en) 1998-11-05 2000-11-28 Vantis Corporation Tileable and compact layout for super variable grain blocks within FPGA device
US6181163B1 (en) 1999-01-21 2001-01-30 Vantis Corporation FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals
US6356987B1 (en) 1999-03-10 2002-03-12 Atmel Corporation Microprocessing device having programmable wait states
US6301696B1 (en) 1999-03-30 2001-10-09 Actel Corporation Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template
US6211697B1 (en) 1999-05-25 2001-04-03 Actel Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
US6272451B1 (en) 1999-07-16 2001-08-07 Atmel Corporation Software tool to allow field programmable system level devices
GB2352548B (en) * 1999-07-26 2001-06-06 Sun Microsystems Inc Method and apparatus for executing standard functions in a computer system
JP3512166B2 (en) 1999-11-26 2004-03-29 松下電器産業株式会社 How to set up a programmable logic device
US6519753B1 (en) 1999-11-30 2003-02-11 Quicklogic Corporation Programmable device with an embedded portion for receiving a standard circuit design
US6588006B1 (en) 1999-12-16 2003-07-01 Lsi Logic Corporation Programmable ASIC
US6434735B1 (en) 1999-12-16 2002-08-13 Lsi Logic Corporation Method for programming an FPGA and implementing an FPGA interconnect
US6539508B1 (en) 2000-03-15 2003-03-25 Xilinx, Inc. Methods and circuits for testing programmable logic
US6587995B1 (en) 2000-04-19 2003-07-01 Koninklijke Philips Electronics N.V. Enhanced programmable core model with integrated graphical debugging functionality
US6535043B2 (en) * 2000-05-26 2003-03-18 Lattice Semiconductor Corp Clock signal selection system, method of generating a clock signal and programmable clock manager including same
EP1307820B1 (en) * 2000-06-06 2014-07-23 Vitesse Semiconductor Corporation Crosspoint switch with switch matrix module
US6353331B1 (en) 2000-07-10 2002-03-05 Xilinx, Inc. Complex programmable logic device with lookup table
US6507942B1 (en) 2000-07-11 2003-01-14 Xilinx , Inc. Methods and circuits for testing a circuit fabrication process for device uniformity
US6693456B2 (en) * 2000-08-04 2004-02-17 Leopard Logic Inc. Interconnection network for a field programmable gate array
US6518787B1 (en) 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
US6611951B1 (en) 2000-11-30 2003-08-26 Lsi Logic Corporation Method for estimating cell porosity of hardmacs
US6522167B1 (en) 2001-01-09 2003-02-18 Xilinx, Inc. User configurable on-chip memory system
US6662285B1 (en) * 2001-01-09 2003-12-09 Xilinx, Inc. User configurable memory system having local and global memory blocks
US6532572B1 (en) 2001-03-14 2003-03-11 Lsi Logic Corporation Method for estimating porosity of hardmacs
US6675272B2 (en) * 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US6541991B1 (en) 2001-05-04 2003-04-01 Xilinx Inc. Interface apparatus and method for testing different sized ball grid array integrated circuits
US7076595B1 (en) * 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US6601227B1 (en) * 2001-06-27 2003-07-29 Xilinx, Inc. Method for making large-scale ASIC using pre-engineered long distance routing structure
US6510548B1 (en) * 2001-08-03 2003-01-21 Xilinx, Inc. Method for providing pre-designed modules for programmable logic devices
US6781407B2 (en) * 2002-01-09 2004-08-24 Xilinx, Inc. FPGA and embedded circuitry initialization and processing
US6798239B2 (en) * 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6886092B1 (en) * 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US6686769B1 (en) * 2001-12-14 2004-02-03 Altera Corporation Programmable I/O element circuit for high speed logic devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10365947B2 (en) 2014-07-28 2019-07-30 Hemett Packard Enterprise Development Lp Multi-core processor including a master core performing tasks involving operating system kernel-related features on behalf of slave cores

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