CA2504525C - Ground fault circuit interrupter with enhanced radio frequency interference suppression - Google Patents
Ground fault circuit interrupter with enhanced radio frequency interference suppression Download PDFInfo
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- CA2504525C CA2504525C CA2504525A CA2504525A CA2504525C CA 2504525 C CA2504525 C CA 2504525C CA 2504525 A CA2504525 A CA 2504525A CA 2504525 A CA2504525 A CA 2504525A CA 2504525 C CA2504525 C CA 2504525C
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- 230000001629 suppression Effects 0.000 title description 3
- 239000003990 capacitor Substances 0.000 claims abstract description 49
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 230000007935 neutral effect Effects 0.000 claims description 12
- 238000004804 winding Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims 4
- 238000001514 detection method Methods 0.000 abstract description 15
- 238000012360 testing method Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 238000001914 filtration Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 241000721662 Juniperus Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/26—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents
- H02H3/32—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors
- H02H3/33—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors using summation current transformers
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/005—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection avoiding undesired transient conditions
Abstract
A ground fault circuit interrupter device having a feedthrough capacitor for substantially reducing interference from radio frequency signals such as those emitted from cell phones. The ground fault circuit interrupter device includes a printed circuit board having a system ground terminal and a detection terminal for receiving a fault detection signal. A chip is provided having a ground pin connected to the system ground terminal and an input pin for receiving the fault detection signal. The feedthrough capacitor has a through conductor connected between the input pin and the detection terminal and a capacitor coupled between the through conductor and the system ground terminal.
Description
GROUND FAULT CIRCUIT INTERRUPTER WITH ENHANCED
RADIO FREQUENCY INTERFERENCE SUPPRESSION
This application claims the benefit of the filing date of a provisional application having serial number 60/561,413 which was filed on April 12, 2004.
BACKGROUND OF THE INVENTION
Field of the Invention This invention relates generally to ground fault circuit interrupters (GFCI's) and more specifically to a GFCI having reduced sensitivity to interference caused by radio frequency signals.
Description of the Related Art Present day GFCI circuits include by-pass capacitors, inductive chokes, and noise filters on signal lines and sensitive parts of the circuitry to the direct current (DC) Ground terminal to suppress interference caused by i-adio frequencies. While the components that are currently being used are adequate for radio frequency signals used in the past, they are not fully effective for signals in the spectrum of radio frequencies which are now being used. For example, cell phones use signals having frequencies which can interfere with the operation of a GFCI by not only causing nuisance tripping of the GFCI, but can also cause a GFCI to fail by subjecting one or more of the components in the GFCI to excessive stress. What is needed is GFCI circuitry for reducing interference caused by radio frequencies.
SUMMARY OF THE INVENTION
The present invention solves the above noted problems by providing a GFCI
device with a feedthrough capacitor to substantially suppress interference caused by radio frequency signals such as those generated by cell phones.
In one embodiment of the invention, the GFCI device includes a printed circuit board having a system ground terminal and a detection terminal for receiving a fault detection signal. A chip is provided having a ground pin connected to the system ground terminal and an input pin for receiving the fault detection signal. A
feedthrough capacitor is provided having a through conductor connected between the input pin and the detection terminal and a capacitor coupled between the through conductor and the system ground terminal. The feedthrough capacitor substantially reduces interference from radio frequency signals such as those emitted from cell phones.
In otlier embodiments, a feedthrough capacitor can be connected to other locations of the circuitry of GFCI device to further reduce interference from radio frequency signals. For example, the through conductor of the feedthrough capacitor can be connected to the input or output of a chip having ground fault interrupting functions, the gate terminal of a semiconductor switch, the power supply terminal of the printed circuit board holding the circuitry.
"hhe present invention provides one or more of the following advantages. The arrangement of the feedthrough capacitor reduces unwanted radio frequency signals by shunting or filtering the signals with respect to the system ground terminal GND thereby reducing interference from such signals. As a result, nuisance tripping of the GFCI may be reduced. In addition, the components of the GFCI may be subjected to less stress which would have been caused from such signals thereby improving the performance of the GFCI.
The foregoing has outlined, rather broadly, the preferred feature of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention and that such other structures do not depart from the spirit and scope of the invention in its broadest form.
RADIO FREQUENCY INTERFERENCE SUPPRESSION
This application claims the benefit of the filing date of a provisional application having serial number 60/561,413 which was filed on April 12, 2004.
BACKGROUND OF THE INVENTION
Field of the Invention This invention relates generally to ground fault circuit interrupters (GFCI's) and more specifically to a GFCI having reduced sensitivity to interference caused by radio frequency signals.
Description of the Related Art Present day GFCI circuits include by-pass capacitors, inductive chokes, and noise filters on signal lines and sensitive parts of the circuitry to the direct current (DC) Ground terminal to suppress interference caused by i-adio frequencies. While the components that are currently being used are adequate for radio frequency signals used in the past, they are not fully effective for signals in the spectrum of radio frequencies which are now being used. For example, cell phones use signals having frequencies which can interfere with the operation of a GFCI by not only causing nuisance tripping of the GFCI, but can also cause a GFCI to fail by subjecting one or more of the components in the GFCI to excessive stress. What is needed is GFCI circuitry for reducing interference caused by radio frequencies.
SUMMARY OF THE INVENTION
The present invention solves the above noted problems by providing a GFCI
device with a feedthrough capacitor to substantially suppress interference caused by radio frequency signals such as those generated by cell phones.
In one embodiment of the invention, the GFCI device includes a printed circuit board having a system ground terminal and a detection terminal for receiving a fault detection signal. A chip is provided having a ground pin connected to the system ground terminal and an input pin for receiving the fault detection signal. A
feedthrough capacitor is provided having a through conductor connected between the input pin and the detection terminal and a capacitor coupled between the through conductor and the system ground terminal. The feedthrough capacitor substantially reduces interference from radio frequency signals such as those emitted from cell phones.
In otlier embodiments, a feedthrough capacitor can be connected to other locations of the circuitry of GFCI device to further reduce interference from radio frequency signals. For example, the through conductor of the feedthrough capacitor can be connected to the input or output of a chip having ground fault interrupting functions, the gate terminal of a semiconductor switch, the power supply terminal of the printed circuit board holding the circuitry.
"hhe present invention provides one or more of the following advantages. The arrangement of the feedthrough capacitor reduces unwanted radio frequency signals by shunting or filtering the signals with respect to the system ground terminal GND thereby reducing interference from such signals. As a result, nuisance tripping of the GFCI may be reduced. In addition, the components of the GFCI may be subjected to less stress which would have been caused from such signals thereby improving the performance of the GFCI.
The foregoing has outlined, rather broadly, the preferred feature of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention and that such other structures do not depart from the spirit and scope of the invention in its broadest form.
BRIEF DESCRIPTION OF THE DRAWINGS
Other aspects, features and advantages of the present invention will become more fully apparent from the following detailed description, the appended claim, and the accompanying drawings in which similar elements are given similar reference numerals:
FIG. I is a schematic wiring diagram of a GFCI device according to an embodiment of the invention; and FIG. 2 is a schematic wiring diagram of a GFCI device according to another embodiment of the invention.
DETAILED DESCRIPTION OF THE INVEN7'ION
The present invention discloses GFCI circuitry having a feedthrough capacitor connected in close proximately to the circuitry at sensitive locations for substantially reducing interference from radio frequency signals such as those emitted from cell phones.
Referring to FIG. 1, there is shown a schematic wiring diagram of GFCI
circuitry 100 for detecting a predetermined fault condition such as a ground fault and disconnecting the input terminals from the output terminals in response thereto. The circuitry 100 has a feedthrough capacitor C 11 for substantially reducing interference from radio frequency signals such as those emitted from cell phones. The circuitry 100 includes a printed circuit board (not shown) with a direct current (DC) system ground terminal (GND) and a detection terminal (+VE) for receiving a fault detection signal from a differential transformer XF1. I'he system ground terminal GND is connected to the ground pin 4 of a chip IC-1 that performs fault detection functions. The feedthrough capacitor C11 has a through conductor connected between the input pin 3 of IC-1 and the detection terminal +VE and has a capacitor coupled between the through conductor and the system ground terminal GND. The input pin 3 is internally coupled to the non-inverting input of an operational amplifier (not shown) within IC-1 which is typically configured for handling a ground fault condition.
Other aspects, features and advantages of the present invention will become more fully apparent from the following detailed description, the appended claim, and the accompanying drawings in which similar elements are given similar reference numerals:
FIG. I is a schematic wiring diagram of a GFCI device according to an embodiment of the invention; and FIG. 2 is a schematic wiring diagram of a GFCI device according to another embodiment of the invention.
DETAILED DESCRIPTION OF THE INVEN7'ION
The present invention discloses GFCI circuitry having a feedthrough capacitor connected in close proximately to the circuitry at sensitive locations for substantially reducing interference from radio frequency signals such as those emitted from cell phones.
Referring to FIG. 1, there is shown a schematic wiring diagram of GFCI
circuitry 100 for detecting a predetermined fault condition such as a ground fault and disconnecting the input terminals from the output terminals in response thereto. The circuitry 100 has a feedthrough capacitor C 11 for substantially reducing interference from radio frequency signals such as those emitted from cell phones. The circuitry 100 includes a printed circuit board (not shown) with a direct current (DC) system ground terminal (GND) and a detection terminal (+VE) for receiving a fault detection signal from a differential transformer XF1. I'he system ground terminal GND is connected to the ground pin 4 of a chip IC-1 that performs fault detection functions. The feedthrough capacitor C11 has a through conductor connected between the input pin 3 of IC-1 and the detection terminal +VE and has a capacitor coupled between the through conductor and the system ground terminal GND. The input pin 3 is internally coupled to the non-inverting input of an operational amplifier (not shown) within IC-1 which is typically configured for handling a ground fault condition.
In one embodiment, the capacitor C 11 has attenuation characteristics that increase at 20dB per decade from its cutoff frequency to at least that frequency where it exhibits a minimum attenuation of 60dB and maintains this attenuation at higlier frequencies. "I'he cutoff frequency of the feedthrough capacitor can be selected from a band of frequencies in the 1 to 300,000 megahertz band of the radio spectrum. There are presently two frequency bands for cellular service centered on approximately 850 and 1850 MHz. The cutoff frequency of the feedthrough capacitor also can be selected from a range of frequencies in the 850 megahertz band, 1850 megahertz band or other bands for cell phone service. The frequency characteristics of the feedthrough capacitor C 11 along with the proximate placement of the capacitor to the circuitry at sensitive locations help reduce interference from radio frequency signals such as those emitted from cell phones.
The GFCI circuitry 100 includes a sensing circuit for detecting a predetermined condition such as a ground fault. The sensing circuit comprises a differential transformer XFI and a ground/neutral (G/N) transformer XF2 each of which can comprise a magnetic core having a coil winding with two ends. "I'he differential transformer XF I
is used for detecting a current imbalance on the line terminals 102, 104. The G/N
transformer XF2 is used for detecting a remote ground voltage that may be present on one of the load terminals 106, 108. The first end of the differential transformer XF 1 is connected to the input pin 2 of IC-1 through series resistor R3 and the second end of the transformer XF 1 is connected to input pin 3 of IC-1 through the through conductor of the feedthrough capacitor C 11. Filter capacitor C8 is placed in series with the second end of transformer XFI and the capacitor C1 I for filtering unwanted signals. Filter capacitor C7 is placed across pin 2 of IC-I and the first conductor of feedthrough capacitor C1 1 to filter unwanted signals. Filter capacitor C6 is placed across the through conductor of capacitor C11 and the system ground terminal GND for reducing unwanted signals. A zener diode Z1 is placed across the transformer XFl to limit any potential overvoltage surges across the transformer XF 1. It should be noted that input pin 2 is internally connected to the inverting input of an operational amplifier (not shown) in IC-1 and input pin 3 is internally connected to the non-inverting input of the operational amplifier.
The first end of the transformer XF2 is connected to the output pin 5 of IC- I and the second end of the transformer XF2 is connected to the system ground terminal GND through a filter capacitor C3 for filtering unwanted signals. It should be noted that pin 5 is the output from the internal sense amplifier (not shown) of IC-1. A filter capacitor C9 is placed across the first and second ends of the transformer XF2 for reducing unwanted signals.
Chip IC- I can be one of the integrated circuits typically used in ground fault circuits, for example LM-1851, manufactured by National Semiconductor or other well known semiconductor manufacturers. IC- I has an output pin I connected to the gate terminal of a semiconductor switch device SC 1 for trigging the switch in response to a fault detection signal received by IC- 1. A filter capacitor C2 is connected across pin 1 of IC-1 and the system ground terminal GND for reducing unwanted signals. A
filter capacitor C4 is connected across the power supply terminal VCC and the system ground terminal GND for reducing unwanted signals. A timing capacitor C5 is connected across pin 7 of IC-1 and the system ground terminal GND for setting the timing of IC-1.
Resistor R2 is connected across pins 6 and 8 of IC-1 for setting the sensitivity of IC-1.
The cathode of diode D1 is connected to the power supply terminal VCC and the anode of the diode is connected to the anode of switch SC 1 through resistor R1.
Diode D 1 performs a rectification function providing the power supply voltage at the VCC terminal for powering IC-1 and the other components. "I'he cathode terminal of the switch SC I is connected to the system ground terminal GND and the anode terminal is connected to the DC side of a full wave bridge comprising diodes D2-D5. A filter capacitor C 10 is connected across the anode and cathode terminals of switch SC 1 for reducing unwanted signals. Although the switch SCl is shown as a silicon controlled rectifier (SCR) other semiconductor or mechanical switches can be used.
Chip IC-1 is configured for detecting a current from the transformers in response to a ground fault and generating a signal causing a relay assembly to connect/disconnect power received at the input line terminals (102, 104) from any loads connected to the device via the output load terminals (106, 108). The relay assembly comprises a coil 112 and relay contacts 110, shown as a pair of switches SW2, SW3, to connect the line terminals 102, 104 to respective load terminals 106, 108. "I'he line terminals 102, 104 and load terminals 106, 108 are electrically isolated from each other unless connected by the switches SW2, SW3. A switch assembly comprising a switch SW 1 in series with current limiting resistor R4 is coupled between line terminal 102 and one end of the relay coil 112 (through jumper Jl being connected and providing an electrical path) tor manually generating a fault condition. A surge suppressor MV 1 is coupled across the AC
portion of the full wave bridge comprising diodes D2-D5 for absorbing extreme electrical energy levels that may be present at the linc terminals 102, 104. A fiiter capacitor C 1 is coupled across the surge suppressor MV I for filtering out unwanted signals.
The circuitry 100 includes test points and jumpers for various purposes such as testing the functionality of the circuitry. For example, test points TP1-TP9 are terminals which facilitate testing the circuitry of the GFCI 100 by providing a means for taking measurements, such as voltage levels, using test equipment such as a voltage meter.
Juniper elements or connectors are enlployed for providing a ineans of selecting certain features of the GFCI 100. For example, jumper element JP 1(for connection across terminals JP 1 A, JP 1 B) can be used to connect/disconnect an electrical path between the surge suppressor MV I and the line terminal 102. Likewise, jumper element JP2 (for connection across terminals JP2A, JP2B) and header terminal J 1 can be used to connect/disconnect an electrical path between relay coil 112 and the line terminal 102.
Although not shown, for proper operation, a connector is placed across the terminal J 1 for providing a complete electrical path between the line terminal 102 and the relay coil 112.
Further suppression of interference signals can be obtained by placing the first through conductor of the feedthrough capacitor C 1 I in close proximity to the input or output of an operational amplifier (not shown) which can be in chip IC-l, the gate terminal of semiconductor switch SCI, and the power supply terminal VCC on the printed circuit board. 'I'he layout and location of components on the printed circuit board is also important in reducing interference. The system ground terminal GND
should have a large conductor width and include a ground loop. "I'he distance between critical components should be kept to a minimum. In addition, filter capacitors should be positioned as close as possible to the circuitry 100.
In operation, with regard to unwanted radio frequency signals, the feedthough capacitor C I I shunts or filters the signals with respect to the system ground terminal GND thereby reducing interference from such signals. As a result, nuisance tripping of the GFCI is reduced. In addition, the components of the GFCI are subjected to less stress which would have been caused from such signals thereby improving the performance of the GFCI.
During a ground fault condition, a current provided by the differential transformer XF1, chip IC- I generates a voltage on pin l which triggers the gate terminal of switch SC I. The full wave bridge comprising diodes D2-D5 has a DC side which is connected to the anode of SC I. SC 1 is turned on, allowing current to flow through the DC side of the full wave bridge activating relay coil 112 causing the relay switches SW2, SW3 to open thereby removing power from the load terminals 106, 108. The relay coil 112 can also be activated when mechanical switch SW I is closed which causes a current imbalance on the line terminal conductors that is detected by the differential transformer XF1. The G/N transformer XF2 detects a remote ground voltage that may be present on one of the load terminals and provides a signal (current or voltage) to IC- I
upon detection of this remote ground which again activates relay coil 112. Thus, the sensing circuit engages a circuit interrupting portion of the GFCI device causing the device to be tripped.
In the tripped condition the line terminals and the load terminals are electrically isolated from each other.
Referring to FIG. 2, there is shown a feedthrough capacitor C11 connected to another embodiment of a GFCI circuit 200. The placement of the feedthrough capacitor C 11 in GFCI circuit 200 is similar to the placement of the feedthrough capacitor C 11 in GFCI circuit 100 of FIG. 1. Like GFCI 100, the input of the GFCI 200 is connected to line terminals (phase terminal 202 and neutral terminal 204) and load terminals (phase terminal 210 and neutral terminal 212). However, GFCI 200 is also connected to face terminals (phase terminal 206 and neutral terminal 208). In one embodiment, the GFCI is part of a wiring device such as a receptacle and the line terminals are connected to a cable providing a source of power, the load terminals are connected to another power cable which in turn is connected to a(oad, and the face terminals are provided on the face of the receptacle for receiving a plug with a cable as part of a load. In addition, to accommodate the face terminals, GFCI 200 has a relay coil 216 coupled to relay contacts 214 comprising a movable bridge assembly with face switches and load switches.
"I'he face switches SW2, SW3 are connected between the line terminals 202, 204 and the face terminals 206, 208. The load switches SW4, SW5 are connected between the line terminals 202, 204 and the load terminals 210, 212.
The operation of the GFCI circuit 200 is similar to the operation of the GFCI
circuit 100 of FIG. 1. For example, in response to a current or potential provided by the differential transformer XFI, chip IC- I generates a voltage on pin I turning on SCI and activating relay coil 216. The activation of relay coil 216 causes the relay face switches SW2, SW3 to remove power from the face terminals 206, 208 and the relay load switches SW4, SW5 to remove power from the load terminals 210, 212. Likewise, the G/N
transformer XF2 detects a fault condition and provides a current to IC-1 which activates relay coil 216 causing the movable bridge asseinbly 214 to remove power from the face terminals and the load terminals as described above. Test points TP 1-TP 10 and jumper elements JP1-JP4 provide various functions such as a means for testing the circuitry of the GFCI 200.
It should be noted that although the present invention is described in the context of a GFCI, the techniques of the present invention are equally applicable to other circuit interrupting devices and systems such as arc fault circuit interrupters (AFCI's), immersion detection circuit interrupters (IDCI's), appliance leakage circuit interrupters (ALCI's) and equipment leakage circuit interrupters (ELCI's). Exemplary values for the components of GFCI 100 and 200 of the present invcntion include: Resistors R1 (15K, 2W), R2-R3 (1/8W), R4 (15K), capacitors C1 (0.OluF, 400V), C2-C3 (0.OluF, 50V), C4 (luF, 50V), C5 (0.018uF, IOOV, 10%), C6 (100pF, 50V), C7 (0.0033uF, 50V), C8 (IOuF, 5.3V), C9 (100pF, 50V), CIO (680pF, 1000V), zener diode ZI (4.7V) and surge suppressor MV 1 is a metal oxide varistor (MOV) rated at 210V.
While there have been shown and described and pointed out the fundamental novel features of the invention as applied to the preferred embodiments, it will be understood that various omissions and substitutions and changes of the form and details of the method and apparatus illustrated and in the operation may be done by those skilled in the art, without departing fronl the spirit of the invention.
The GFCI circuitry 100 includes a sensing circuit for detecting a predetermined condition such as a ground fault. The sensing circuit comprises a differential transformer XFI and a ground/neutral (G/N) transformer XF2 each of which can comprise a magnetic core having a coil winding with two ends. "I'he differential transformer XF I
is used for detecting a current imbalance on the line terminals 102, 104. The G/N
transformer XF2 is used for detecting a remote ground voltage that may be present on one of the load terminals 106, 108. The first end of the differential transformer XF 1 is connected to the input pin 2 of IC-1 through series resistor R3 and the second end of the transformer XF 1 is connected to input pin 3 of IC-1 through the through conductor of the feedthrough capacitor C 11. Filter capacitor C8 is placed in series with the second end of transformer XFI and the capacitor C1 I for filtering unwanted signals. Filter capacitor C7 is placed across pin 2 of IC-I and the first conductor of feedthrough capacitor C1 1 to filter unwanted signals. Filter capacitor C6 is placed across the through conductor of capacitor C11 and the system ground terminal GND for reducing unwanted signals. A zener diode Z1 is placed across the transformer XFl to limit any potential overvoltage surges across the transformer XF 1. It should be noted that input pin 2 is internally connected to the inverting input of an operational amplifier (not shown) in IC-1 and input pin 3 is internally connected to the non-inverting input of the operational amplifier.
The first end of the transformer XF2 is connected to the output pin 5 of IC- I and the second end of the transformer XF2 is connected to the system ground terminal GND through a filter capacitor C3 for filtering unwanted signals. It should be noted that pin 5 is the output from the internal sense amplifier (not shown) of IC-1. A filter capacitor C9 is placed across the first and second ends of the transformer XF2 for reducing unwanted signals.
Chip IC- I can be one of the integrated circuits typically used in ground fault circuits, for example LM-1851, manufactured by National Semiconductor or other well known semiconductor manufacturers. IC- I has an output pin I connected to the gate terminal of a semiconductor switch device SC 1 for trigging the switch in response to a fault detection signal received by IC- 1. A filter capacitor C2 is connected across pin 1 of IC-1 and the system ground terminal GND for reducing unwanted signals. A
filter capacitor C4 is connected across the power supply terminal VCC and the system ground terminal GND for reducing unwanted signals. A timing capacitor C5 is connected across pin 7 of IC-1 and the system ground terminal GND for setting the timing of IC-1.
Resistor R2 is connected across pins 6 and 8 of IC-1 for setting the sensitivity of IC-1.
The cathode of diode D1 is connected to the power supply terminal VCC and the anode of the diode is connected to the anode of switch SC 1 through resistor R1.
Diode D 1 performs a rectification function providing the power supply voltage at the VCC terminal for powering IC-1 and the other components. "I'he cathode terminal of the switch SC I is connected to the system ground terminal GND and the anode terminal is connected to the DC side of a full wave bridge comprising diodes D2-D5. A filter capacitor C 10 is connected across the anode and cathode terminals of switch SC 1 for reducing unwanted signals. Although the switch SCl is shown as a silicon controlled rectifier (SCR) other semiconductor or mechanical switches can be used.
Chip IC-1 is configured for detecting a current from the transformers in response to a ground fault and generating a signal causing a relay assembly to connect/disconnect power received at the input line terminals (102, 104) from any loads connected to the device via the output load terminals (106, 108). The relay assembly comprises a coil 112 and relay contacts 110, shown as a pair of switches SW2, SW3, to connect the line terminals 102, 104 to respective load terminals 106, 108. "I'he line terminals 102, 104 and load terminals 106, 108 are electrically isolated from each other unless connected by the switches SW2, SW3. A switch assembly comprising a switch SW 1 in series with current limiting resistor R4 is coupled between line terminal 102 and one end of the relay coil 112 (through jumper Jl being connected and providing an electrical path) tor manually generating a fault condition. A surge suppressor MV 1 is coupled across the AC
portion of the full wave bridge comprising diodes D2-D5 for absorbing extreme electrical energy levels that may be present at the linc terminals 102, 104. A fiiter capacitor C 1 is coupled across the surge suppressor MV I for filtering out unwanted signals.
The circuitry 100 includes test points and jumpers for various purposes such as testing the functionality of the circuitry. For example, test points TP1-TP9 are terminals which facilitate testing the circuitry of the GFCI 100 by providing a means for taking measurements, such as voltage levels, using test equipment such as a voltage meter.
Juniper elements or connectors are enlployed for providing a ineans of selecting certain features of the GFCI 100. For example, jumper element JP 1(for connection across terminals JP 1 A, JP 1 B) can be used to connect/disconnect an electrical path between the surge suppressor MV I and the line terminal 102. Likewise, jumper element JP2 (for connection across terminals JP2A, JP2B) and header terminal J 1 can be used to connect/disconnect an electrical path between relay coil 112 and the line terminal 102.
Although not shown, for proper operation, a connector is placed across the terminal J 1 for providing a complete electrical path between the line terminal 102 and the relay coil 112.
Further suppression of interference signals can be obtained by placing the first through conductor of the feedthrough capacitor C 1 I in close proximity to the input or output of an operational amplifier (not shown) which can be in chip IC-l, the gate terminal of semiconductor switch SCI, and the power supply terminal VCC on the printed circuit board. 'I'he layout and location of components on the printed circuit board is also important in reducing interference. The system ground terminal GND
should have a large conductor width and include a ground loop. "I'he distance between critical components should be kept to a minimum. In addition, filter capacitors should be positioned as close as possible to the circuitry 100.
In operation, with regard to unwanted radio frequency signals, the feedthough capacitor C I I shunts or filters the signals with respect to the system ground terminal GND thereby reducing interference from such signals. As a result, nuisance tripping of the GFCI is reduced. In addition, the components of the GFCI are subjected to less stress which would have been caused from such signals thereby improving the performance of the GFCI.
During a ground fault condition, a current provided by the differential transformer XF1, chip IC- I generates a voltage on pin l which triggers the gate terminal of switch SC I. The full wave bridge comprising diodes D2-D5 has a DC side which is connected to the anode of SC I. SC 1 is turned on, allowing current to flow through the DC side of the full wave bridge activating relay coil 112 causing the relay switches SW2, SW3 to open thereby removing power from the load terminals 106, 108. The relay coil 112 can also be activated when mechanical switch SW I is closed which causes a current imbalance on the line terminal conductors that is detected by the differential transformer XF1. The G/N transformer XF2 detects a remote ground voltage that may be present on one of the load terminals and provides a signal (current or voltage) to IC- I
upon detection of this remote ground which again activates relay coil 112. Thus, the sensing circuit engages a circuit interrupting portion of the GFCI device causing the device to be tripped.
In the tripped condition the line terminals and the load terminals are electrically isolated from each other.
Referring to FIG. 2, there is shown a feedthrough capacitor C11 connected to another embodiment of a GFCI circuit 200. The placement of the feedthrough capacitor C 11 in GFCI circuit 200 is similar to the placement of the feedthrough capacitor C 11 in GFCI circuit 100 of FIG. 1. Like GFCI 100, the input of the GFCI 200 is connected to line terminals (phase terminal 202 and neutral terminal 204) and load terminals (phase terminal 210 and neutral terminal 212). However, GFCI 200 is also connected to face terminals (phase terminal 206 and neutral terminal 208). In one embodiment, the GFCI is part of a wiring device such as a receptacle and the line terminals are connected to a cable providing a source of power, the load terminals are connected to another power cable which in turn is connected to a(oad, and the face terminals are provided on the face of the receptacle for receiving a plug with a cable as part of a load. In addition, to accommodate the face terminals, GFCI 200 has a relay coil 216 coupled to relay contacts 214 comprising a movable bridge assembly with face switches and load switches.
"I'he face switches SW2, SW3 are connected between the line terminals 202, 204 and the face terminals 206, 208. The load switches SW4, SW5 are connected between the line terminals 202, 204 and the load terminals 210, 212.
The operation of the GFCI circuit 200 is similar to the operation of the GFCI
circuit 100 of FIG. 1. For example, in response to a current or potential provided by the differential transformer XFI, chip IC- I generates a voltage on pin I turning on SCI and activating relay coil 216. The activation of relay coil 216 causes the relay face switches SW2, SW3 to remove power from the face terminals 206, 208 and the relay load switches SW4, SW5 to remove power from the load terminals 210, 212. Likewise, the G/N
transformer XF2 detects a fault condition and provides a current to IC-1 which activates relay coil 216 causing the movable bridge asseinbly 214 to remove power from the face terminals and the load terminals as described above. Test points TP 1-TP 10 and jumper elements JP1-JP4 provide various functions such as a means for testing the circuitry of the GFCI 200.
It should be noted that although the present invention is described in the context of a GFCI, the techniques of the present invention are equally applicable to other circuit interrupting devices and systems such as arc fault circuit interrupters (AFCI's), immersion detection circuit interrupters (IDCI's), appliance leakage circuit interrupters (ALCI's) and equipment leakage circuit interrupters (ELCI's). Exemplary values for the components of GFCI 100 and 200 of the present invcntion include: Resistors R1 (15K, 2W), R2-R3 (1/8W), R4 (15K), capacitors C1 (0.OluF, 400V), C2-C3 (0.OluF, 50V), C4 (luF, 50V), C5 (0.018uF, IOOV, 10%), C6 (100pF, 50V), C7 (0.0033uF, 50V), C8 (IOuF, 5.3V), C9 (100pF, 50V), CIO (680pF, 1000V), zener diode ZI (4.7V) and surge suppressor MV 1 is a metal oxide varistor (MOV) rated at 210V.
While there have been shown and described and pointed out the fundamental novel features of the invention as applied to the preferred embodiments, it will be understood that various omissions and substitutions and changes of the form and details of the method and apparatus illustrated and in the operation may be done by those skilled in the art, without departing fronl the spirit of the invention.
Claims (14)
1. A circuit interrupting device comprising:
a housing;
a phase conductive path and a neutral conductive path each disposed at least partially within said housing between a line side and a load side, said phase conductive path terminating at a first connection capable of being electrically connected to a source of electricity, and a second connection capable of conducting electricity to at least one load;
a first transformer coupled to said phase conductive path and said neutral conductive path for detecting a phase to ground fault and generating a phase to ground fault signal;
a second transformer coupled to said phase and neutral conductive paths for generating a neutral to ground fault signal in the first transformer;
a circuit interrupting portion disposed within said housing and configured to cause electrical discontinuity in said phase conductive path;
said circuit interrupting device further comprising an integrated circuit chip having a ground pin connected to a system ground terminal and to the second transformer, a pair of input pins coupled to the first transformer, and an output pin coupled to the second transformer; and a feedthrough capacitor having (i) a through conductor disposed in the interior of the feedthrough capacitor, the through conductor connected between the first transformer and the input pin coupled thereto, and (ii) a capacitor coupled between said through conductor and said ground pin, wherein said feedthrough capacitor effectively reduces interference from radio frequency signals.
a housing;
a phase conductive path and a neutral conductive path each disposed at least partially within said housing between a line side and a load side, said phase conductive path terminating at a first connection capable of being electrically connected to a source of electricity, and a second connection capable of conducting electricity to at least one load;
a first transformer coupled to said phase conductive path and said neutral conductive path for detecting a phase to ground fault and generating a phase to ground fault signal;
a second transformer coupled to said phase and neutral conductive paths for generating a neutral to ground fault signal in the first transformer;
a circuit interrupting portion disposed within said housing and configured to cause electrical discontinuity in said phase conductive path;
said circuit interrupting device further comprising an integrated circuit chip having a ground pin connected to a system ground terminal and to the second transformer, a pair of input pins coupled to the first transformer, and an output pin coupled to the second transformer; and a feedthrough capacitor having (i) a through conductor disposed in the interior of the feedthrough capacitor, the through conductor connected between the first transformer and the input pin coupled thereto, and (ii) a capacitor coupled between said through conductor and said ground pin, wherein said feedthrough capacitor effectively reduces interference from radio frequency signals.
2. The circuit interrupting device of claim 1 wherein said input pins are connected to inputs of an operational amplifier.
3. The circuit interrupting device of claim 1 wherein the feedthrough capacitor has attenuation characteristics that increase at approximately 20 decibels per decade from its cutoff frequency.
4. The circuit interrupting device of claim 1 wherein the feedthrough capacitor has a cutoff frequency selected from a band of frequencies between 1 to 300,000 megahertz.
5. The circuit interrupting device of claim 1 wherein the feedthrough capacitor has a cutoff frequency selected from a range of frequencies in the radio band for cell phone service.
6. The circuit interrupting device of claim 1 wherein the feedthrough capacitor has a cutoff frequency selected from a range of frequencies in the 1850 megahertz band for cell phone service.
7. The circuit interrupting device of claim 1 wherein said phase conductive path further terminating in a third connection capable of conducting electricity to at least one user accessible load.
8. The circuit interrupting device of claim 1 wherein said neutral conductive path terminating at a first connection capable of being electrically connected to a source of electricity, a second connection capable of providing a neutral connection to said at least one load and a third connection capable of providing a neutral connection to said at least one user accessible load.
9. The circuit interrupting device of claim 1 wherein said first transformer generates a phase to ground fault signal in a secondary winding having a first end and a second end.
10. The circuit interrupting device of claim 1 wherein said circuit interrupting portion disposed within said housing is further configured to cause electrical discontinuity in said phase neutral conductive path between said line side and said load side.
11. The circuit interrupting device of claim 1 wherein said ground pin is connected to said system ground terminal and to a second end of a secondary winding of said second transformer.
12. The circuit interrupting device of claim 1 wherein said pair of input pins are coupled to a first end and a second end respectively of a secondary winding of said first transformer.
13. The circuit interrupting device of claim 1 wherein said output pin is coupled to a first end of a secondary winding of said second transformer.
14. The circuit interrupting device of claim 1 wherein said through conductor is connected between a second end of a secondary winding of said first transformer and the input pin.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US56141304P | 2004-04-12 | 2004-04-12 | |
| US60/561,413 | 2004-04-12 | ||
| US11/095,581 | 2005-04-01 | ||
| US11/095,581 US7375935B2 (en) | 2004-04-12 | 2005-04-01 | Ground fault circuit interrupter with enhanced radio frequency interference suppression |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2504525A1 CA2504525A1 (en) | 2005-10-12 |
| CA2504525C true CA2504525C (en) | 2012-10-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2504525A Active CA2504525C (en) | 2004-04-12 | 2005-04-12 | Ground fault circuit interrupter with enhanced radio frequency interference suppression |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US7375935B2 (en) |
| CA (1) | CA2504525C (en) |
| MX (1) | MXPA05003939A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7400477B2 (en) | 1998-08-24 | 2008-07-15 | Leviton Manufacturing Co., Inc. | Method of distribution of a circuit interrupting device with reset lockout and reverse wiring protection |
| ES2257152B1 (en) * | 2004-05-31 | 2007-07-01 | Laboratorios Almirall S.A. | COMBINATIONS THAT INCLUDE ANTIMUSCARINIC AGENTS AND BETA-ADRENERGIC AGONISTS. |
| CA2610229A1 (en) * | 2005-06-01 | 2006-12-07 | Leviton Manufacturing Co., Inc. | Circuit interrupting device having integrated enhanced rfi suppression |
| US7684162B2 (en) * | 2007-03-21 | 2010-03-23 | Magnetic Metals Corporation | Leakage current protection device |
| US8139328B2 (en) * | 2007-05-17 | 2012-03-20 | Levitron Manufacturing Company, Inc. | Fault circuit interrupting device with symmetrical inputs |
| US7889466B2 (en) * | 2008-05-02 | 2011-02-15 | Leviton Manufacturing Company, Inc. | Fault circuit interrupter with bi-directional sensing |
| US9774181B2 (en) | 2012-03-16 | 2017-09-26 | Hubbell Incorporated | Enhanced auto-monitoring circuit and method for an electrical device |
| US8830015B2 (en) | 2012-03-16 | 2014-09-09 | Hubbell Incorporated | Compact latching mechanism for switched electrical device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3845403A (en) * | 1972-12-27 | 1974-10-29 | Rca Corp | Amplifier for amplitude modulated waves with means for improving sideband response |
| US3961263A (en) * | 1974-06-03 | 1976-06-01 | Rca Corporation | Bandstart detector system for a television tuning system |
| DE2456088A1 (en) * | 1974-11-27 | 1976-08-12 | Siemens Ag | ELECTRIC DOUBLE RESTORING CAPACITOR |
| US4148003A (en) * | 1977-07-08 | 1979-04-03 | Globe-Union Inc. | Series feed-through capacitor |
| US5969921A (en) * | 1998-01-29 | 1999-10-19 | Eaton Corporation | Ground fault electrical switching apparatus for coordinating tripping with a downstream ground fault switch |
| US6424234B1 (en) * | 1998-09-18 | 2002-07-23 | Greatbatch-Sierra, Inc. | Electromagnetic interference (emi) filter and process for providing electromagnetic compatibility of an electronic device while in the presence of an electromagnetic emitter operating at the same frequency |
| US6807036B2 (en) * | 2001-04-26 | 2004-10-19 | Hubbell Incorporated | Digital fault interrupter with self-testing capabilities |
| US20030081370A1 (en) * | 2001-10-15 | 2003-05-01 | Haskell Donald K. | Apparatus and process for the control of electromagnetic fields on the surface of EMI filter capacitors |
-
2005
- 2005-04-01 US US11/095,581 patent/US7375935B2/en not_active Ceased
- 2005-04-12 CA CA2504525A patent/CA2504525C/en active Active
- 2005-04-12 MX MXPA05003939A patent/MXPA05003939A/en active IP Right Grant
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2010
- 2010-05-13 US US12/779,613 patent/USRE42866E1/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20060018061A1 (en) | 2006-01-26 |
| US7375935B2 (en) | 2008-05-20 |
| MXPA05003939A (en) | 2006-05-25 |
| CA2504525A1 (en) | 2005-10-12 |
| USRE42866E1 (en) | 2011-10-25 |
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