CA2543909A1 - High temperature electronic devices - Google Patents

High temperature electronic devices Download PDF

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Publication number
CA2543909A1
CA2543909A1 CA002543909A CA2543909A CA2543909A1 CA 2543909 A1 CA2543909 A1 CA 2543909A1 CA 002543909 A CA002543909 A CA 002543909A CA 2543909 A CA2543909 A CA 2543909A CA 2543909 A1 CA2543909 A1 CA 2543909A1
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Canada
Prior art keywords
electronic device
integrated circuit
circuit
fabricated
chip
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Granted
Application number
CA002543909A
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French (fr)
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CA2543909C (en
Inventor
Paul F. Rodney
James E. Masino
Christopher A. Golla
Roger L. Schultz
James J. Freeman
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Halliburton Energy Services Inc
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Individual
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Publication of CA2543909A1 publication Critical patent/CA2543909A1/en
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Publication of CA2543909C publication Critical patent/CA2543909C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • E—FIXED CONSTRUCTIONS
    • E21—EARTH DRILLING; MINING
    • E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
    • E21B47/00—Survey of boreholes or wells
    • E21B47/01—Devices for supporting measuring instruments on drill bits, pipes, rods or wirelines; Protecting measuring instruments in boreholes against heat, shock, pressure or the like
    • E21B47/017—Protecting measuring instruments
    • E21B47/0175—Cooling arrangements
    • E—FIXED CONSTRUCTIONS
    • E21—EARTH DRILLING; MINING
    • E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
    • E21B47/00—Survey of boreholes or wells
    • E—FIXED CONSTRUCTIONS
    • E21—EARTH DRILLING; MINING
    • E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
    • E21B47/00—Survey of boreholes or wells
    • E21B47/002—Survey of boreholes or wells by visual inspection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • E—FIXED CONSTRUCTIONS
    • E21—EARTH DRILLING; MINING
    • E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
    • E21B47/00—Survey of boreholes or wells
    • E21B47/01—Devices for supporting measuring instruments on drill bits, pipes, rods or wirelines; Protecting measuring instruments in boreholes against heat, shock, pressure or the like
    • E21B47/017—Protecting measuring instruments
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01V—GEOPHYSICS; GRAVITATIONAL MEASUREMENTS; DETECTING MASSES OR OBJECTS; TAGS
    • G01V1/00—Seismology; Seismic or acoustic prospecting or detecting
    • G01V1/40—Seismology; Seismic or acoustic prospecting or detecting specially adapted for well-logging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01V—GEOPHYSICS; GRAVITATIONAL MEASUREMENTS; DETECTING MASSES OR OBJECTS; TAGS
    • G01V8/00—Prospecting or detecting by optical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/11—Structural features, others than packages, for protecting a device against environmental influences
    • B81B2207/115—Protective layers applied directly to the device before packaging
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

In at least some embodiments, electronic devices suitable for use at temperatures in excess of 200 ~C may comprise an integrated circuit fabricated on a silicon carbide substrate, and a thick passivation layer. In other embodiments, electronic devices suitable for use at temperatures in excess of 200 ~C may comprise an integrated circuit formed from silicon located on a sapphire substrate, and a thick passivation layer. The electronic devices may be implemented in the context of hydrocarbon drilling and production operations.

Claims (61)

1. An electronic device operable at elevated temperatures, the device comprising:
an integrated circuit fabricated on a silicon carbide substrate; and a passivation layer thicker than about 2 microns.
2. The electronic device of claim 1 wherein the passivation layer comprises a nitride layer.
3. The electronic device of claim 1 further comprising guard rings around portions of the integrated circuit.
4. The electronic device of claim 1 further comprising a seal ring along the periphery of a die associated with the integrated circuit.
5. The electronic device of claim 4, wherein the seal ring's width is at least about twice the width of a cutting lane between dies.
6. The electronic device of claim 1 wherein the integrated circuit includes metal interconnects that limit current density to below a predetermined level when the integrated circuit operates in the elevated temperatures.
7. The electronic device of claim 6, wherein the predetermined level is about 10 4 A/cm2.
8. The electronic device of claim 1 wherein the integrated circuit is configured to operate at a clock frequency in excess of about 100 MHz.
9. The electronic device of claim 1 wherein the electronic device is disposed within a region having an environmental temperature greater than about 200 Celsius, wherein the electronic device is configured to continue operating while disposed in said region for an indefinitely extended time in excess of one week.
10. The electronic device of claim 1 wherein the integrated circuit comprises at least one circuit selected in the group consisting of an oscillator, a logic gate, an analog-to-digital converter, a digital-to-analog converter, a sample and hold circuit, a charge-coupled delay line, and an operational amplifier.
11. The electronic device of claim 10 wherein the at least one circuit is configured for use in a unit in the group consisting of an anti-fuse memory, a state machine, a floating poly-to-poly memory, a microprocessor, a micro electromechanical systems (MEMS), a tag sensor, a DC/DC
voltage converter, a digital memory, an analog memory, an on-chip transformer, an on-chip inductor, an on-chip capacitor, an on-chip resistor, an programmable logic device (PLD), a mixer, a switch and a charge pump.
12. The electronic device of claim 1 wherein the electronic device is configured for use in a drill bit, comprising:
a rotating base; and cutters mounted in the rotating base, wherein the electronic device is mounted near at least one of the cutters and configured to detect operating parameters of the drill bit.
13. The electronic device of claim 1 wherein the electronic device is configured for use within a multi-chip module and wherein a Peltier cooler disposed within the multi-chip module is configured to intermittently cool the electronic device.
14. The electronic device of claim 1 wherein the electronic device is configured for use in a hybrid circuit having dies that are limited to a size limit calculated to optimize cost of the hybrid circuit and wherein each die carries an integrated circuit that is a partitioned portion of a larger integrated circuit.
15. The electronic device of claim 1 wherein the electronic device is configured for use in a micro electromechanical system (MEMS) structure that operates as a sensor selected from the group consisting of accelerometers, pressure sensors, gyros, temperature sensors, and thermal arrays.
16. The electronic device of claim 1 wherein the electronic device is configured for use in a tag device that comprises:
a nonvolatile memory; and an on-chip antenna configurable to wirelessly transmit information stored in the nonvolatile memory.
17. An electronic device operable at elevated temperatures, the device comprising:
an integrated circuit fabricated on a sapphire substrate; and a passivation layer thicker than about 2 microns.
18. The electronic device of claim 17 wherein the passivation layer comprises a nitride layer.
19. The electronic device of claim 17 further comprising guard rings around portions of the integrated circuit.
20. The electronic device of claim 17 further comprising a seal ring that surrounds the integrated circuit.
21. The electronic device of claim 20, wherein the seal ring's width is greater than about twice the width of a cutting lane between dies.
22. The electronic device of claim 17 wherein the integrated circuit includes metal interconnects that limit current density to below a predetermined level when the integrated circuit operates in the elevated temperatures.
23. The electronic device of claim 22, wherein the predetermined level is about 10 4 A/cm2.
24. The electronic device of claim 17 wherein the integrated circuit is configured to operate at a clock frequency in excess of about 100 MHz.
25. The electronic device of claim 17 wherein the electronic device is disposed within a region having an environmental temperature greater than about 200 Celsius, wherein the electronic device is configured to continue operating while disposed in said region for an indefinitely extended time in excess of one week.
26. The electronic device of claim 17 wherein the integrated circuit comprises at least one circuit in the group consisting of an oscillator, a logic gate, an analog-to-digital converter, a
27 digital-to-analog converter, a sample and hold circuit, a charge-coupled delay line, and an operational amplifier.

27. The electronic device of claim 17 wherein the electronic device is configured for use in a unit in the group consisting of an anti-fuse memory, a state machine, a floating poly-to-poly memory, a microprocessor, a micro electromechanical systems (MEMS), a tag sensor, a DC/DC
voltage converter, a digital memory, an analog memory, an on-chip transformer, an on-chip inductor, an on-chip capacitor, an on-chip resistor, an programmable logic device (PLD), a mixer, a switch and a charge pump.
28. The electronic device of claim 17 wherein the electronic device is configured for use in a drill bit, comprising:
a rotating base; and cutters mounted in the rotating base, wherein the electronic device is mounted near at least one of the cutters and configured to detect operating parameters of the drill bit.
29. The electronic device of claim 17 wherein the electronic device is configured for use within a multi-chip module and wherein a Peltier cooler disposed within the multi-chip module is configured to intermittently cool the device.
30. The electronic device of claim 17 wherein the electronic device is configured for use in a hybrid circuit having dies that are limited to a size limit calculated to optimize cost of the hybrid circuit and wherein each die carries an integrated circuit that is a partitioned portion of a larger integrated circuit.
31. The electronic device of claim 17 wherein the electronic device is configured for use in a micro electromechanical system (MEMS) structure that operates as a sensor selected from the group consisting of accelerometers, pressure sensors, gyros, temperature sensors, and thermal arrays.
32. The electronic device of claim 17 wherein the electronic device is configured for use in a tag device that comprises:
a nonvolatile memory; and an on-chip antenna configurable to wirelessly transmit information stored in the nonvolatile memory.
33. A method, comprising:
forming an integrated circuit on a silicon carbide substrate; and depositing a passivation layer on the integrated circuit, wherein the passivation layer is at least about 2 microns thick.
34. The method of claim 33 wherein the integrated circuit comprises a circuit selected from the group consisting of an oscillator, a logic gate, an analog-to-digital converter, a sample and hold circuit, a charge couple delay line and an operational amplifier.
35. A method, comprising forming an integrated circuit on a sapphire substrate; and depositing a passivation layer on the integrated circuit, wherein the passivation layer is at least about 2 microns thick.
36. The method of claim 35 wherein the passivation layer is one of a nitride layer and an oxide layer.
37. A method of high-temperature circuit manufacture, the method comprising:
calculating fabrication costs for each of multiple chipsets that implement a circuit design in silicon on sapphire (SOS) or silicon carbide (SiC), said chipsets having one or more integrated circuit dies;
identifying a minimum cost chipset from said multiple chipsets; and fabricating the minimum cost chipset.
38. The method of claim 37, wherein said calculating includes:
partitioning an original circuit design into increasing numbers of chips; and determining a fabrication cost for the unpartitioned circuit design and for one or more partitioned circuit designs, wherein the minimum cost chipset is identified when the fabrication cost for a design with a greater number of chips exceeds the fabrication cost of a design with a smaller number of chips.
39. The method of claim 37, wherein the fabrication costs include a packaging cost for each chip in the chipset.
40. The method of claim 39, wherein the fabrication costs further include, for each die in the chipset, a wafer fabrication cost divided by an average number of defect-free die per wafer.
41. The method of claim 40, wherein said average number is an estimate based on a defect density and an active die area.
42. The method of claim 37, wherein said circuit designs are implemented in SOS alone.
43. The method of claim 37, wherein said circuit designs are implemented in SiC alone.
44. A tag device that comprises:
a sapphire substrate; and an antenna fabricated on the sapphire substrate and configurable to wirelessly transmit information.
45. The device of claim 44, further comprising:
a nonvolatile memory fabricated on the sapphire substrate.
46. The device of claim 44, further comprising:
a sensor fabricated on the sapphire substrate.
47. The device of claim 44, further comprising:
a transceiver module fabricated on the sapphire substrate, wherein the transceiver module is configured to detect commands transmitted to the tag device, and is further configured to respond to said commands via the antenna.
48. The device of claim 44, further comprising:
a power circuit fabricated on the sapphire substrate, wherein the power circuit is configured to power other device components with power extracted from a high-frequency electromagnetic signal.
49. A tag device that comprises:
a SiC substrate; and an antenna fabricated on the SiC substrate and configurable to wirelessly transmit information.
50. The device of claim 49, further comprising:
a nonvolatile memory fabricated on the SiG substrate.
51. The device of claim 49, further comprising:
a sensor fabricated on the SiC substrate.
52. The device of claim 49, further comprising:
a transceiver module fabricated on the SiC substrate, wherein the transceiver module is configured to detect commands transmitted to the tag device, and is further configured to respond to said commands via the antenna.
53. The device of claim 49, further comprising:
a power circuit fabricated on the SiC substrate, wherein the power circuit is configured to power other device components with power extracted from a high-frequency electromagnetic signal.
54. An electronic device that comprises:
a sapphire substrate; and a ring oscillator fabricated on the sapphire substrate.
55. The device of claim 54, wherein the ring oscillator is configured to produce an oscillating signal having a frequency indicative of an environmental parameter.
56. The device of claim 55, wherein the environmental parameter is temperature.
57. The device of claim 55, further comprising an antenna coupled to the ring oscillator and configured to transmit the oscillating signal.
58. An electronic device that comprises:
a SiC substrate; and a ring oscillator fabricated on the SiC substrate.
59. The device of claim 58, wherein the ring oscillator is configured to produce an oscillating signal having a frequency indicative of an environmental parameter.
60. The device of claim 59, wherein the environmental parameter is temperature.
61. The device of claim 59, further comprising an antenna coupled to the ring oscillator and configured to transmit the oscillating signal.
CA2543909A 2003-11-18 2004-11-18 High temperature electronic devices Expired - Fee Related CA2543909C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US52099203P 2003-11-18 2003-11-18
US52095003P 2003-11-18 2003-11-18
US60/520,992 2003-11-18
US60/520,950 2003-11-18
PCT/US2004/038793 WO2005050714A2 (en) 2003-11-18 2004-11-18 High temperature electronic devices

Publications (2)

Publication Number Publication Date
CA2543909A1 true CA2543909A1 (en) 2005-06-02
CA2543909C CA2543909C (en) 2012-01-31

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CA2543909A Expired - Fee Related CA2543909C (en) 2003-11-18 2004-11-18 High temperature electronic devices

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US (3) US7017662B2 (en)
EP (3) EP1687837A4 (en)
JP (1) JP4769729B2 (en)
CN (1) CN101095239B (en)
AU (2) AU2004311152B2 (en)
CA (1) CA2543909C (en)
GB (1) GB2425177B (en)
NO (2) NO341264B1 (en)
WO (4) WO2005050257A2 (en)

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AU2004311152B2 (en) 2010-03-04
AU2004291942C1 (en) 2010-04-08
US20050168224A1 (en) 2005-08-04
EP1700002A2 (en) 2006-09-13
GB2425177B (en) 2009-03-18
AU2004311152A1 (en) 2005-06-02
JP2007519228A (en) 2007-07-12
EP1700002B1 (en) 2017-07-05
WO2005050257A8 (en) 2005-08-11
WO2005050714A2 (en) 2005-06-02
GB0610533D0 (en) 2006-07-05
CA2543909C (en) 2012-01-31
WO2005050777A3 (en) 2006-08-10

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