CA2640317A1 - Cooperative writes over the address channel of a bus - Google Patents
Cooperative writes over the address channel of a bus Download PDFInfo
- Publication number
- CA2640317A1 CA2640317A1 CA002640317A CA2640317A CA2640317A1 CA 2640317 A1 CA2640317 A1 CA 2640317A1 CA 002640317 A CA002640317 A CA 002640317A CA 2640317 A CA2640317 A CA 2640317A CA 2640317 A1 CA2640317 A1 CA 2640317A1
- Authority
- CA
- Canada
- Prior art keywords
- payload
- channel
- bus
- receiving device
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
- G06F13/4273—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a clocked protocol
Abstract
A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
Claims (42)
1. A processing system, comprising:
a receiving device;
a bus having first, second and third channels; and a sending device configured to address the receiving device on the first channel, and read payload from the receiving device the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
a receiving device;
a bus having first, second and third channels; and a sending device configured to address the receiving device on the first channel, and read payload from the receiving device the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
2. The processing system of claim 1 wherein the sending device is further configured to concurrently write the first and second portions of the payload to the receiving device.
3. The processing system of claim 1 wherein the sending device is further configured to concurrently address the receiving device and write the second portion of the payload to the receiving device.
4. The processing system of claim 1 wherein the sending device is further configured write the first and second portions of the payload to a first address of the receiving device, the sending device being further configured to send a second address to the receiving device on the first channel concurrently with the writing of the second portion of the payload to the receiving device.
5. The processing system of claim 1 wherein the sending device comprises a first processing device and the receiving device comprises a bus interconnect, the processing system further comprising a second processing device, the bus interconnect being configured to connect the first and second processing devices to a shared resource, and wherein the first processing device is further configured to write the first and second portions of a payload to the bus interconnect in response to a snoop address from the second processing device.
6. The processing system of claim 1 wherein the bus comprises a fourth channel, the sending device being further configured to address the receiving device on the first channel for write operations and address the receiving device on the fourth channel for read operations, and wherein the sending device is further configured to write a third portion of the payload to the receiving device on the fourth channel.
7. The processing system of claim 6 wherein the sending device is further configured to concurrently write the first, second and third portions of the payload to the receiving device.
8. The processing system of claim 6 wherein the sending device is further configured write the first, second and third portions of the payload to a first address of the receiving device, the sending device being further configured to send a second address to the receiving device on the first channel concurrently with the writing of the second or third portion of the payload to the receiving device.
9. The processing system of claim 1 wherein the sending is further configured to provide a control signal to the receiving device indicating whether the first channel is currently being used to address the receiving device or write the first portion of the payload to the receiving device.
10. The processing system of claim 1 wherein the sending device is further configured to provide a control signal on each of the first and third channels to the receiving device, each of the control signals identifying the portion of the payload being sent on its corresponding channel.
11. A processing system, comprising:
a receiving device;
a bus having first, second and third channels;
means for addressing the receiving device on the first channel;
means for reading a payload from the receiving device on the second channel; and means for writing a first portion of the payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
a receiving device;
a bus having first, second and third channels;
means for addressing the receiving device on the first channel;
means for reading a payload from the receiving device on the second channel; and means for writing a first portion of the payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
12. A method of communicating between a sending device and a receiving device over a bus, the bus comprising first, second and third channel, the method comprising:
addressing a receiving device on the first channel, reading a payload from the receiving device on the second channel; and writing a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
addressing a receiving device on the first channel, reading a payload from the receiving device on the second channel; and writing a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
13. The method of claim 12 wherein the first and second portions of the payload are concurrently written to the receiving device.
14. The method of claim 12 wherein the receiving device is addressed concurrently with the writing of the second portion of the payload to the receiving device.
15. The method of claim 12 wherein the first and second portions of the payload a written to a first address of the receiving device, the addressing of the receiving device further comprising sending a second address to the receiving device on the first channel concurrently with the writing of the second portion of the payload to the receiving device.
16. The method of claim 12 wherein the sending device comprises a first processing device and the receiving device comprises a bus interconnect, the processing system further comprising a second processing device, the bus interconnect being configured to connect the first and second processing devices to a shared resource, and wherein the first and second portions of a payload are written to the bus interconnect in response to a snoop address from the second processing device.
17. The method of claim 12 wherein the bus further comprises a fourth channel, the addressing of the receiving device on the first channel being for write operations, the method further comprising addressing the receiving device on the fourth channel for read operations, and writing a third portion of the payload to the receiving device on the fourth channel.
18. The method of claim 17 wherein the sending device is further configured to concurrently write the first, second and third portions of the payload to the receiving device.
19. The method of claim 18 wherein the first second and third portions of the payload are written to a first address of the receiving device, the method further comprising sending a second address to the receiving device on the first channel concurrently with the writing of the second or third portion of the payload to the receiving device.
20. The method of claim 12 further comprising providing a control signal to the receiving device indicating whether the first channel is currently being used to address the receiving device or write the first portion of the payload to the receiving device.
21. The method of claim 12 further comprising a control signal on each of the first and third channels to the receiving device, each of the control signals identifying the portion of the payload being sent on its corresponding channel.
22. A bus mastering device, comprising:
a processor; and a bus interface configured to interface the processor to a bus having first, second and third channels, the bus interface being further configured to address a slave on the first channel, receive a payload from the slave on the second channel, and write a first portion of a payload to the slave on the first channel and a second portion of the payload to the slave on the third channel.
a processor; and a bus interface configured to interface the processor to a bus having first, second and third channels, the bus interface being further configured to address a slave on the first channel, receive a payload from the slave on the second channel, and write a first portion of a payload to the slave on the first channel and a second portion of the payload to the slave on the third channel.
23 23. The bus mastering device of claim 22 wherein the bus interface is further configured to concurrently write the first and second portions of the payload to the slave.
24. The bus mastering device of claim 22 wherein the bus interface is further configured to concurrently address the slave and write the second of the payload to the slave.
25. The bus mastering device of claim 22 wherein the bus interface is further configured write the first and second portions of the payload to a first address of the slave, the bus interface being further configured to send a second address to the slave on the first channel concurrently with the writing of the second portion of the payload to the slave.
26. The bus mastering device of claim 22 wherein the slave comprises a bus interconnect configured to connect the bus mastering device and a second bus mastering device to a shared resource, and wherein the bus mastering device is further configured to write the first and second portions of a payload to the bus interconnect in response to a snoop address from the second bus mastering device.
27. The bus mastering device of claim 22 wherein the bus further comprises a fourth channel, the bus interface being further configured to address the slave on the first channel for write operations and address the slave on the fourth channel for read operations, and wherein the bus interface is further configured to write a third portion of the payload to the slave on the fourth channel.
28. The bus mastering device of claim 27 wherein the bus interface is further configured to concurrently write the first, second and third potions of the payload to the slave.
29. The bus mastering device of claim 27 wherein the bus interface is further configured write the first, second and third portions of the payload to a first address of the slave, the bus interface being further configured to send a second address to the slave on the first channel concurrently with the writing of the second or third portion of the payload to the slave.
30. The bus mastering device of claim 22 wherein the bus interface is further configured to provide a control signal to the slave indicating whether the first channel is currently being used to address the slave or write the first portion of the payload to the slave.
31. The bus mastering device of claim 22 wherein the bus interface is further configured to provide a control signal on each of the first and third channels to the slave, each of the control signals identifying the portion of the payload being sent on its corresponding channel.
32. A bus mastering device, comprising:
a processor; and means for interfacing the processor to a bus having first, second and third channels, the means for interfacing the processor to the bus comprising means for addressing a slave on the first channel, means for receiving a payload from the slave on the second channel, and means for writing a first portion of a payload to the slave on the first channel and a second portion of the payload to the slave on the third channel.
a processor; and means for interfacing the processor to a bus having first, second and third channels, the means for interfacing the processor to the bus comprising means for addressing a slave on the first channel, means for receiving a payload from the slave on the second channel, and means for writing a first portion of a payload to the slave on the first channel and a second portion of the payload to the slave on the third channel.
33. A slave device, comprising:
memory; and a bus interface configured to interface the memory to a bus having first, second and third channels, the bus interface being configured to receive an address and a first portion of a payload from a bus mastering device on the first channel, send a payload to the bus mastering device on the second channel, and receive a second portion of the payload from the bus mastering device on the third.
memory; and a bus interface configured to interface the memory to a bus having first, second and third channels, the bus interface being configured to receive an address and a first portion of a payload from a bus mastering device on the first channel, send a payload to the bus mastering device on the second channel, and receive a second portion of the payload from the bus mastering device on the third.
34. The slave device of claim 33 wherein the bus interface is further configured to concurrently receive the first and second portions of the payload.
35. The slave device of claim 33 wherein the bus interface is further configured to concurrently receive the address and the second portion of the payload.
36. The slave device of claim 33 wherein the bus interface is further configured write the first and second portions of the payload to a first address in the memory, the bus interface being further configured to receive a second address on the first channel concurrently with the second portion of the payload.
37. The slave device of claim 33 wherein the bus further comprises a fourth channel, the bus interface being further configured to receive the address on the first channel for write operations and receive an address on the fourth channel for a read operation, and wherein the bus interface is further configured to receive a third portion of the payload from the bus mastering device on the fourth channel.
38. The slave device of claim 37 wherein the bus interface is further configured write the first, second and third portions of the payload.
39. The slave device of claim 37 wherein the bus interface is further configured write the first, second and third portions of the payload to a first address in the memory, the bus interface being further configured to receive a second address from the bus mastering device on the first channel concurrently with the receipt of the second or third portion of the payload.
40. The slave device of claim 33 wherein the bus interface is further configured to receive a control signal from the bus mastering device indicating whether the first channel is currently being used to send the address or the first portion of the payload.
41. The slave device of claim 33 wherein the bus interface is further configured to receive a control signal on each of the first and third channels from the bus mastering device, each of the control signals identifying the portion of the payload being sent on its corresponding channel.
42. A slave device, comprising:
memory; and means for interfacing the memory to a bus having first, second and third channels, the means for interfacing the memory to the bus comprising means for receiving an address and a first portion of a payload from a bus mastering device on the first channel, means for sending a payload to the bus mastering device on the second channel, and means for receive a second portion of the payload from the bus mastering device on the third channel.
memory; and means for interfacing the memory to a bus having first, second and third channels, the means for interfacing the memory to the bus comprising means for receiving an address and a first portion of a payload from a bus mastering device on the first channel, means for sending a payload to the bus mastering device on the second channel, and means for receive a second portion of the payload from the bus mastering device on the third channel.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US77652906P | 2006-02-24 | 2006-02-24 | |
| US60/776,529 | 2006-02-24 | ||
| US11/468,908 | 2006-08-31 | ||
| US11/468,908 US8107492B2 (en) | 2006-02-24 | 2006-08-31 | Cooperative writes over the address channel of a bus |
| PCT/US2007/062761 WO2007101134A1 (en) | 2006-02-24 | 2007-02-23 | Cooperative writes over the address channel of a bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2640317A1 true CA2640317A1 (en) | 2007-09-07 |
| CA2640317C CA2640317C (en) | 2012-01-31 |
Family
ID=38123722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2640317A Expired - Fee Related CA2640317C (en) | 2006-02-24 | 2007-02-23 | Cooperative writes over the address channel of a bus |
Country Status (11)
| Country | Link |
|---|---|
| US (2) | US8107492B2 (en) |
| EP (2) | EP2002345B1 (en) |
| JP (1) | JP5254044B2 (en) |
| KR (2) | KR20080097481A (en) |
| CN (1) | CN104199798B (en) |
| BR (1) | BRPI0708189A2 (en) |
| CA (1) | CA2640317C (en) |
| MX (1) | MX2008010822A (en) |
| RU (1) | RU2405195C2 (en) |
| TW (1) | TWI341468B (en) |
| WO (1) | WO2007101134A1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8107492B2 (en) | 2006-02-24 | 2012-01-31 | Qualcomm Incorporated | Cooperative writes over the address channel of a bus |
| US8108563B2 (en) | 2006-02-24 | 2012-01-31 | Qualcomm Incorporated | Auxiliary writes over address channel |
| WO2008013968A2 (en) | 2006-07-28 | 2008-01-31 | Vast Systems Technology Corporation | Virtual processor generation model for co-simulation |
| US8644305B2 (en) * | 2007-01-22 | 2014-02-04 | Synopsys Inc. | Method and system for modeling a bus for a system design incorporating one or more programmable processors |
| KR101178293B1 (en) | 2011-03-25 | 2012-08-29 | 마사미 후쿠시마 | Central processing unit and microcontroller |
| JP4862100B1 (en) * | 2011-03-25 | 2012-01-25 | 好一 北岸 | Central processing unit and microcomputer |
| US8516225B2 (en) | 2011-03-25 | 2013-08-20 | Koichi Kitagishi | Central processing unit and microcontroller |
| US9258244B1 (en) | 2013-05-01 | 2016-02-09 | Sandia Corporation | Protocol for communications in potentially noisy environments |
| KR102206313B1 (en) * | 2014-02-07 | 2021-01-22 | 삼성전자주식회사 | System interconnect and operating method of system interconnect |
| DE102018001574B4 (en) * | 2018-02-28 | 2019-09-05 | WAGO Verwaltungsgesellschaft mit beschränkter Haftung | Master-slave bus system and method for operating a bus system |
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-
2006
- 2006-08-31 US US11/468,908 patent/US8107492B2/en not_active Expired - Fee Related
-
2007
- 2007-02-23 CN CN201410424746.5A patent/CN104199798B/en not_active Expired - Fee Related
- 2007-02-23 EP EP07757444.0A patent/EP2002345B1/en active Active
- 2007-02-23 EP EP11158202.9A patent/EP2360599A3/en not_active Withdrawn
- 2007-02-23 BR BRPI0708189-8A patent/BRPI0708189A2/en not_active Application Discontinuation
- 2007-02-23 JP JP2008556569A patent/JP5254044B2/en not_active Expired - Fee Related
- 2007-02-23 KR KR1020087023216A patent/KR20080097481A/en not_active Application Discontinuation
- 2007-02-23 RU RU2008137971/08A patent/RU2405195C2/en not_active IP Right Cessation
- 2007-02-23 MX MX2008010822A patent/MX2008010822A/en active IP Right Grant
- 2007-02-23 CA CA2640317A patent/CA2640317C/en not_active Expired - Fee Related
- 2007-02-23 KR KR1020107027614A patent/KR101081301B1/en active IP Right Grant
- 2007-02-23 WO PCT/US2007/062761 patent/WO2007101134A1/en active Application Filing
- 2007-02-26 TW TW096106553A patent/TWI341468B/en not_active IP Right Cessation
-
2011
- 2011-12-20 US US13/330,734 patent/US8675679B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| RU2405195C2 (en) | 2010-11-27 |
| EP2360599A2 (en) | 2011-08-24 |
| JP5254044B2 (en) | 2013-08-07 |
| TW200809520A (en) | 2008-02-16 |
| EP2002345A1 (en) | 2008-12-17 |
| TWI341468B (en) | 2011-05-01 |
| US20070201506A1 (en) | 2007-08-30 |
| CA2640317C (en) | 2012-01-31 |
| RU2008137971A (en) | 2010-03-27 |
| KR101081301B1 (en) | 2011-11-08 |
| US8675679B2 (en) | 2014-03-18 |
| US20120096201A1 (en) | 2012-04-19 |
| WO2007101134A1 (en) | 2007-09-07 |
| BRPI0708189A2 (en) | 2012-06-12 |
| EP2002345B1 (en) | 2020-04-29 |
| US8107492B2 (en) | 2012-01-31 |
| JP2009528597A (en) | 2009-08-06 |
| KR20080097481A (en) | 2008-11-05 |
| CN104199798B (en) | 2017-04-12 |
| EP2360599A3 (en) | 2019-01-16 |
| MX2008010822A (en) | 2008-09-05 |
| CN104199798A (en) | 2014-12-10 |
| KR20100135332A (en) | 2010-12-24 |
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Legal Events
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| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20200224 |